68 	int reg;  in usb3_eye_config()  local
71 	reg = readl(MISC_REG_BASE + USB2_PHY0_CTRL);  in usb3_eye_config()
72 	reg &= ~USB2_PHY_MASK;  in usb3_eye_config()
73 	reg |= USB2_PHY_VREF; /* [7:4] -> (eye vref = 4%) */  in usb3_eye_config()
74 	reg |= USB2_PHY_PRE; /* [13:12] -> (pre electric = 3x) */  in usb3_eye_config()
75 	writel(reg, MISC_REG_BASE + USB2_PHY0_CTRL);  in usb3_eye_config()
79 	reg = readl(MISC_REG_BASE + USB2_PHY1_CTRL);  in usb3_eye_config()
80 	reg &= ~USB2_PHY_MASK;  in usb3_eye_config()
81 	reg |= USB2_PHY_VREF; /* [7:4] -> (eye vref = 4%) */  in usb3_eye_config()
82 	reg |= USB2_PHY_PRE; /* [13:12] -> (pre electric = 3x) */  in usb3_eye_config()
83 	writel(reg, MISC_REG_BASE + USB2_PHY1_CTRL);  in usb3_eye_config()
113 	unsigned int reg;  in phy_hiusb_init_ctrler()  local
115 	reg = readl(USB3_CTRL_CFG);  in phy_hiusb_init_ctrler()
116 	reg &= ~(USB3_VCC_SRST_REQ << usb3_offset);  in phy_hiusb_init_ctrler()
117 	writel(reg, USB3_CTRL_CFG);  in phy_hiusb_init_ctrler()
120 	reg = readl(xhci_base + REG_GUSB3PIPECTL0);  in phy_hiusb_init_ctrler()
121 	reg |= PCS_SSP_SOFT_RESET;  in phy_hiusb_init_ctrler()
122 	writel(reg, xhci_base + REG_GUSB3PIPECTL0);  in phy_hiusb_init_ctrler()
125 	reg = readl(xhci_base + REG_GCTL);  in phy_hiusb_init_ctrler()
126 	reg &= ~PORT_CAP_DIR;  in phy_hiusb_init_ctrler()
127 	reg |= PORT_SET_HOST; /* [13:12] 01: Host; 10: Device; 11: OTG */  in phy_hiusb_init_ctrler()
128 	writel(reg, xhci_base + REG_GCTL);  in phy_hiusb_init_ctrler()
131 	reg = readl(xhci_base + REG_GUSB3PIPECTL0);  in phy_hiusb_init_ctrler()
132 	reg &= ~PCS_SSP_SOFT_RESET;  in phy_hiusb_init_ctrler()
133 	reg &= ~PORT_DISABLE_SUSPEND; /* disable suspend */  in phy_hiusb_init_ctrler()
134 	writel(reg, xhci_base + REG_GUSB3PIPECTL0);  in phy_hiusb_init_ctrler()
137 	reg &= CLEAN_USB3_GTXTHRCFG;  in phy_hiusb_init_ctrler()
138 	reg |= USB_TXPKT_CNT_SEL;  in phy_hiusb_init_ctrler()
139 	reg |= USB_TXPKT_CNT;  in phy_hiusb_init_ctrler()
140 	reg |= USB_MAXTX_BURST_SIZE;  in phy_hiusb_init_ctrler()
141 	writel(reg, xhci_base + GTXTHRCFG);  in phy_hiusb_init_ctrler()
143 	writel(reg, xhci_base + GRXTHRCFG);  in phy_hiusb_init_ctrler()
150 	unsigned int reg;  in phy_hiusb_init_clk_ctrler()  local
152 	reg = readl(USB3_CTRL_CFG);  in phy_hiusb_init_clk_ctrler()
153 	reg |= (USB3_VCC_SRST_REQ << usb3_offset);  in phy_hiusb_init_clk_ctrler()
154 	writel(reg, USB3_CTRL_CFG);  in phy_hiusb_init_clk_ctrler()
158 	reg = readl(MISC_REG_BASE + USB_PORT0);  in phy_hiusb_init_clk_ctrler()
159 	reg |= P0_U3_PORT_DISABLE;  in phy_hiusb_init_clk_ctrler()
160 	writel(reg, MISC_REG_BASE + USB_PORT0);  in phy_hiusb_init_clk_ctrler()
163 	reg = readl(MISC_REG_BASE + USB_PORT1);  in phy_hiusb_init_clk_ctrler()
164 	reg |= P1_U3_PORT_DISABLE;  in phy_hiusb_init_clk_ctrler()
165 	writel(reg, MISC_REG_BASE + USB_PORT1);  in phy_hiusb_init_clk_ctrler()
168 	reg = readl(USB2_PHY_CFG);  in phy_hiusb_init_clk_ctrler()
169 	reg &= ~(USB2_PHY_PORT_TREQ << usb2_offset);  in phy_hiusb_init_clk_ctrler()
170 	writel(reg, USB2_PHY_CFG);  in phy_hiusb_init_clk_ctrler()
174 	reg = readl(USB3_CTRL_CFG);  in phy_hiusb_init_clk_ctrler()
175 	reg &= ~(USB3_UTMI_CKSEL << usb3_offset);  in phy_hiusb_init_clk_ctrler()
176 	writel(reg, USB3_CTRL_CFG);  in phy_hiusb_init_clk_ctrler()
180 	reg = readl(USB2_PHY_CFG);  in phy_hiusb_init_clk_ctrler()
181 	reg |= (USB2_PHY_CKEN << usb2_offset);  in phy_hiusb_init_clk_ctrler()
182 	writel(reg, USB2_PHY_CFG);  in phy_hiusb_init_clk_ctrler()
186 	reg = readl(USB2_PHY_CFG);  in phy_hiusb_init_clk_ctrler()
187 	reg &= ~(USB2_PHY_REQ << usb2_offset);  in phy_hiusb_init_clk_ctrler()
188 	writel(reg, USB2_PHY_CFG);  in phy_hiusb_init_clk_ctrler()
192 	reg = readl(USB3_COMBPHY_CFG);  in phy_hiusb_init_clk_ctrler()
195 		reg &= ~(COMBPHY_SRST_REQ);  in phy_hiusb_init_clk_ctrler()
197 		reg &= ~(COMBPHY_SRST_REQ >> usb3_offset);  in phy_hiusb_init_clk_ctrler()
199 	writel(reg, USB3_COMBPHY_CFG);  in phy_hiusb_init_clk_ctrler()
208 	unsigned int reg, cbp_mode;  in phy_hiusb_init()  local
232 	reg = readl(USB3_COMBPHY_CFG);  in phy_hiusb_init()
235 		reg = readl(USB3_CTRL_CFG);  in phy_hiusb_init()
236 		reg |= (USB3_0_PCLK_OCC_SEL | USB3_1_PCLK_OCC_SEL);  in phy_hiusb_init()
237 		writel(reg, USB3_CTRL_CFG);  in phy_hiusb_init()
241 		reg |= COMBPHY_SRST_REQ;  in phy_hiusb_init()
242 		reg |= COMBPHY_REF_CKEN;  in phy_hiusb_init()
243 		writel(reg, USB3_COMBPHY_CFG);  in phy_hiusb_init()
246 		reg = readl(USB3_CTRL_CFG);  in phy_hiusb_init()
247 		reg |= USB3_0_PCLK_OCC_SEL;  in phy_hiusb_init()
248 		writel(reg, USB3_CTRL_CFG);  in phy_hiusb_init()
251 		reg |= (COMBPHY_SRST_REQ >> usb3_offset);  in phy_hiusb_init()
252 		reg |= (COMBPHY_REF_CKEN >> usb3_offset);  in phy_hiusb_init()
253 		writel(reg, USB3_COMBPHY_CFG);  in phy_hiusb_init()
270 	unsigned int reg, cbp_mode;  in xhci_hcd_stop()  local
283 	reg = readl(USB3_COMBPHY_CFG);  in xhci_hcd_stop()
286 		reg |= COMBPHY_SRST_REQ;  in xhci_hcd_stop()
288 		reg |= (COMBPHY_SRST_REQ >> usb3_offset);  in xhci_hcd_stop()
290 	writel(reg, USB3_COMBPHY_CFG);  in xhci_hcd_stop()
293 	reg = readl(USB3_CTRL_CFG);  in xhci_hcd_stop()
294 	reg |= (USB3_VCC_SRST_REQ << usb3_offset);  in xhci_hcd_stop()
295 	writel(reg, USB3_CTRL_CFG);  in xhci_hcd_stop()