32 	struct udevice *sor;  member
717 				struct udevice *sor, int ena)  in tegra_dc_dp_set_assr()  argument
731 	tegra_dc_sor_set_internal_panel(sor, ena);  in tegra_dc_dp_set_assr()
736 				       struct udevice *sor,  in tegra_dp_set_link_bandwidth()  argument
739 	tegra_dc_sor_set_link_bandwidth(sor, link_bw);  in tegra_dp_set_link_bandwidth()
747 		struct udevice *sor)  in tegra_dp_set_lane_count()  argument
760 	tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);  in tegra_dp_set_lane_count()
919 	tegra_dc_sor_set_dp_linkctl(dp->sor, 1, tp, cfg);  in tegra_dp_tpg()
958 		ret = tegra_dc_dp_set_assr(dp, dp->sor, 1);  in tegra_dp_link_config()
963 	ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw);  in tegra_dp_link_config()
968 	ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor);  in tegra_dp_link_config()
973 	tegra_dc_sor_set_dp_linkctl(dp->sor, 1, training_pattern_none,  in tegra_dp_link_config()
1008 	struct udevice *sor = dp->sor;  in tegra_dp_lt_config()  local
1045 		tegra_dp_set_pe_vs_pc(sor, mask, pe_reg << shift,  in tegra_dp_lt_config()
1050 	tegra_dp_disable_tx_pu(dp->sor);  in tegra_dp_lt_config()
1192 	struct udevice *sor = dp->sor;  in tegra_dc_dp_full_link_training()  local
1196 	tegra_sor_precharge_lanes(sor, cfg);  in tegra_dc_dp_full_link_training()
1235 		struct udevice *sor)  in tegra_dc_dp_fast_link_training()  argument
1246 	tegra_dc_sor_set_lane_parm(sor, link_cfg);  in tegra_dc_dp_fast_link_training()
1251 	tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_1, link_cfg);  in tegra_dc_dp_fast_link_training()
1270 	tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena);  in tegra_dc_dp_fast_link_training()
1271 	tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_3, link_cfg);  in tegra_dc_dp_fast_link_training()
1287 	tegra_dc_sor_set_dp_linkctl(sor, 1, training_pattern_disabled,  in tegra_dc_dp_fast_link_training()
1292 		tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count);  in tegra_dc_dp_fast_link_training()
1307 		struct udevice *sor)  in tegra_dp_do_link_training()  argument
1314 		ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor);  in tegra_dp_do_link_training()
1322 			ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg);  in tegra_dp_do_link_training()
1339 	tegra_dc_sor_read_link_config(sor, &link_bw, &lane_count);  in tegra_dp_do_link_training()
1350 			struct udevice *sor,  in tegra_dc_dp_explore_link_cfg()  argument
1377 		(!tegra_dp_do_link_training(dp, &temp_cfg, timing, sor)))  in tegra_dc_dp_explore_link_cfg()
1450 		ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor);  in tegra_dc_dp_check_sink()
1453 		if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor,  in tegra_dc_dp_check_sink()
1459 		tegra_dc_sor_set_power_state(dp->sor, 1);  in tegra_dc_dp_check_sink()
1460 		tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing);  in tegra_dc_dp_check_sink()
1473 	struct udevice *sor;  in tegra_dp_enable()  local
1495 	ret = uclass_first_device(UCLASS_VIDEO_BRIDGE, &sor);  in tegra_dp_enable()
1496 	if (ret || !sor) {  in tegra_dp_enable()
1500 	priv->sor = sor;  in tegra_dp_enable()
1501 	ret = tegra_dc_sor_enable_dp(sor, link_cfg);  in tegra_dp_enable()
1505 	tegra_dc_sor_set_panel_power(sor, 1);  in tegra_dp_enable()
1533 	if (tegra_dc_dp_explore_link_cfg(priv, link_cfg, sor, timing)) {  in tegra_dp_enable()
1538 	tegra_dc_sor_set_power_state(sor, 1);  in tegra_dp_enable()
1539 	ret = tegra_dc_sor_attach(priv->dc_dev, sor, link_cfg, timing);  in tegra_dp_enable()
1554 	tegra_dc_sor_power_down_unused_lanes(sor, link_cfg);  in tegra_dp_enable()
1556 	ret = video_bridge_set_backlight(sor, 80);  in tegra_dp_enable()