1 // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // This module gets enough CPU information to optimize the
6 // atomicops module on x86.
7
8 #include <stdint.h>
9 #include <string.h>
10
11 #include "include/base/cef_atomicops.h"
12
13 // This file only makes sense with atomicops_internals_x86_gcc.h -- it
14 // depends on structs that are defined in that file. If atomicops.h
15 // doesn't sub-include that file, then we aren't needed, and shouldn't
16 // try to do anything.
17 #ifdef CEF_INCLUDE_BASE_INTERNAL_CEF_ATOMICOPS_X86_GCC_H_
18
19 // Inline cpuid instruction. In PIC compilations, %ebx contains the address
20 // of the global offset table. To avoid breaking such executables, this code
21 // must preserve that register's value across cpuid instructions.
22 #if defined(__i386__)
23 #define cpuid(a, b, c, d, inp) \
24 asm("mov %%ebx, %%edi\n" \
25 "cpuid\n" \
26 "xchg %%edi, %%ebx\n" \
27 : "=a"(a), "=D"(b), "=c"(c), "=d"(d) \
28 : "a"(inp))
29 #elif defined(__x86_64__)
30 #define cpuid(a, b, c, d, inp) \
31 asm("mov %%rbx, %%rdi\n" \
32 "cpuid\n" \
33 "xchg %%rdi, %%rbx\n" \
34 : "=a"(a), "=D"(b), "=c"(c), "=d"(d) \
35 : "a"(inp))
36 #endif
37
38 #if defined(cpuid) // initialize the struct only on x86
39
40 // Set the flags so that code will run correctly and conservatively, so even
41 // if we haven't been initialized yet, we're probably single threaded, and our
42 // default values should hopefully be pretty safe.
43 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
44 false, // bug can't exist before process spawns multiple threads
45 };
46
47 namespace {
48
49 // Initialize the AtomicOps_Internalx86CPUFeatures struct.
AtomicOps_Internalx86CPUFeaturesInit()50 void AtomicOps_Internalx86CPUFeaturesInit() {
51 uint32_t eax;
52 uint32_t ebx;
53 uint32_t ecx;
54 uint32_t edx;
55
56 // Get vendor string (issue CPUID with eax = 0)
57 cpuid(eax, ebx, ecx, edx, 0);
58 char vendor[13];
59 memcpy(vendor, &ebx, 4);
60 memcpy(vendor + 4, &edx, 4);
61 memcpy(vendor + 8, &ecx, 4);
62 vendor[12] = 0;
63
64 // get feature flags in ecx/edx, and family/model in eax
65 cpuid(eax, ebx, ecx, edx, 1);
66
67 int family = (eax >> 8) & 0xf; // family and model fields
68 int model = (eax >> 4) & 0xf;
69 if (family == 0xf) { // use extended family and model fields
70 family += (eax >> 20) & 0xff;
71 model += ((eax >> 16) & 0xf) << 4;
72 }
73
74 // Opteron Rev E has a bug in which on very rare occasions a locked
75 // instruction doesn't act as a read-acquire barrier if followed by a
76 // non-locked read-modify-write instruction. Rev F has this bug in
77 // pre-release versions, but not in versions released to customers,
78 // so we test only for Rev E, which is family 15, model 32..63 inclusive.
79 if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD
80 family == 15 && 32 <= model && model <= 63) {
81 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
82 } else {
83 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
84 }
85 }
86
87 class AtomicOpsx86Initializer {
88 public:
AtomicOpsx86Initializer()89 AtomicOpsx86Initializer() { AtomicOps_Internalx86CPUFeaturesInit(); }
90 };
91
92 // A global to get use initialized on startup via static initialization :/
93 AtomicOpsx86Initializer g_initer;
94
95 } // namespace
96
97 #endif // if x86
98
99 #endif // ifdef CEF_INCLUDE_BASE_CEF_ATOMICOPS_INTERNALS_X86_GCC_H_
100