1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 * Description: Control hieth regisiter header file 18 */ 19 20 21 #ifndef __HIETH_CTRL_H__ 22 #define __HIETH_CTRL_H__ 23 24 #include "hieth.h" 25 26 #ifdef HIETH_SFV300 27 28 /* ENDIAN */ 29 #define GLB_ENDIAN_MOD 0x1318 30 #define BITS_ENDIAN mk_bits(0, 2) 31 #define HIETH_BIG_ENDIAN 0 32 #define HIETH_LITTLE_ENDIAN 3 33 34 /* IRQs */ 35 #define GLB_RO_IRQ_STAT 0x1330 36 #define GLB_RW_IRQ_ENA 0x1334 37 #define GLB_RW_IRQ_RAW 0x1338 38 39 /* IRQs mask bits */ 40 #define BITS_IRQS_U mk_bits(0, 8) 41 #define BITS_VLAN_IRQS mk_bits(11, 1) 42 #define BITS_MDIO_IRQS mk_bits(13, 2) 43 #define BITS_IRQS_ENA_D mk_bits(17, 1) 44 #define BITS_IRQS_ENA_U mk_bits(18, 1) 45 #define BITS_IRQS_ENA_ALLPORT mk_bits(19, 1) 46 #define BITS_IRQS_D mk_bits(20, 8) 47 48 #define BITS_IRQS_MASK_U (0xFF) 49 #define BITS_IRQS_MASK_D (0xFF << 20) 50 51 /* IRQs bit name */ 52 #define HIETH_INT_RX_RDY_U bit(0) 53 #define HIETH_INT_RX_RDY_D bit(20) 54 #define HIETH_INT_TX_FIN_U bit(1) 55 #define HIETH_INT_TX_FIN_D bit(21) 56 #define HIETH_INT_LINK_CH_U bit(2) 57 #define HIETH_INT_LINK_CH_D bit(22) 58 #define HIETH_INT_SPEED_CH_U bit(3) 59 #define HIETH_INT_SPEED_CH_D bit(23) 60 #define HIETH_INT_DUPLEX_CH_U bit(4) 61 #define HIETH_INT_DUPLEX_CH_D bit(24) 62 #define HIETH_INT_STATE_CH_U bit(5) 63 #define HIETH_INT_STATE_CH_D bit(25) 64 #define HIETH_INT_TXQUE_RDY_U bit(6) 65 #define HIETH_INT_TXQUE_RDY_D bit(26) 66 #define HIETH_INT_MULTI_RXRDY_U bit(7) 67 #define HIETH_INT_MULTI_RXRDY_D bit(27) 68 69 #define HIETH_INT_MDIO_FINISH bit(12) 70 #define HIETH_INT_UNKNOW_VLANID bit(13) 71 #define HIETH_INT_UNKNOW_VLANM bit(14) 72 73 /* Tx/Rx Queue depth */ 74 #define U_GLB_QLEN_SET 0x0344 75 #define D_GLB_QLEN_SET 0x2344 76 #define BITS_TXQ_DEP mk_bits(0, 6) 77 #define BITS_RXQ_DEP mk_bits(8, 6) 78 79 /* Rx (read only) Queue-ID and LEN */ 80 #define U_GLB_RO_IQFRM_DES 0x0354 81 #define D_GLB_RO_IQFRM_DES 0x2354 82 /* bits of UD_GLB_RO_IQFRM_DES */ 83 #define BITS_RXPKG_LEN mk_bits(0, 11) 84 #define BITS_RXPKG_ID mk_bits(12, 6) 85 #define BITS_FRM_VLAN_VID mk_bits(18, 1) 86 #define BITS_FD_VID_VID mk_bits(19, 1) 87 #define BITS_FD_VLANID mk_bits(20, 12) 88 89 /* Rx ADDR */ 90 #define U_GLB_IQ_ADDR 0x0358 91 #define D_GLB_IQ_ADDR 0x2358 92 93 /* Tx ADDR and LEN */ 94 #define U_GLB_EQ_ADDR 0x0360 95 #define D_GLB_EQ_ADDR 0x2360 96 #define U_GLB_EQFRM_LEN 0x0364 97 #define D_GLB_EQFRM_LEN 0x2364 98 /* bits of UD_GLB_EQFRM_LEN */ 99 #define BITS_TXINQ_LEN mk_bits(0, 11) 100 101 /* Rx/Tx Queue ID */ 102 #define U_GLB_RO_QUEUE_ID 0x0368 103 #define D_GLB_RO_QUEUE_ID 0x2368 104 /* bits of UD_GLB_RO_QUEUE_ID */ 105 #define BITS_TXOUTQ_ID mk_bits(0, 6) 106 #define BITS_TXINQ_ID mk_bits(8, 6) 107 #define BITS_RXINQ_ID mk_bits(16, 6) 108 109 /* Rx/Tx Queue staus */ 110 #define U_GLB_RO_QUEUE_STAT 0x036C 111 #define D_GLB_RO_QUEUE_STAT 0x236C 112 /* bits of UD_GLB_RO_QUEUE_STAT */ 113 /* check this bit to see if we can add a Tx package */ 114 #define BITS_XMITQ_RDY mk_bits(24, 1) 115 /* check this bit to see if we can add a Rx addr */ 116 #define BITS_RECVQ_RDY mk_bits(25, 1) 117 /* counts in queue, include currently sending */ 118 #define BITS_XMITQ_CNT_INUSE mk_bits(0, 6) 119 /* counts in queue, include currently receving */ 120 #define BITS_RECVQ_CNT_RXOK mk_bits(8, 6) 121 122 #define is_recv_packet(ld) (hieth_readl(ld, GLB_RW_IRQ_RAW) & (ud_bit_name(HIETH_INT_RX_RDY))) 123 #define is_recv_packet_rx(ld) ((hieth_readl(ld, ud_reg_name(GLB_RO_QUEUE_STAT)) >> 8) & 0x3F) 124 #define hw_set_rxpkg_finish(ld) hieth_writel(ld, ud_bit_name(HIETH_INT_RX_RDY), GLB_RW_IRQ_RAW) 125 126 // ////////////////////////////////////////////////////////////////////////////////////////// 127 128 #define hw_get_rxpkg_id(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_IQFRM_DES), BITS_RXPKG_ID) 129 #define hw_get_rxpkg_len(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_IQFRM_DES), BITS_RXPKG_LEN) 130 131 #define hw_get_txqid(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_ID), BITS_TXINQ_ID) 132 #define hw_get_rxqid(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_ID), BITS_RXINQ_ID) 133 134 #define hw_xmitq_cnt_inuse(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), BITS_XMITQ_CNT_INUSE) 135 #define hw_recvq_cnt_rxok(ld) hieth_readl_bits(ld, ud_reg_name(GLB_RO_QUEUE_STAT), BITS_RECVQ_CNT_RXOK) 136 137 #define hw_recvq_setfd(ld, fd) hieth_writel(ld, (fd).frm_addr, ud_reg_name(GLB_IQ_ADDR)) 138 139 #endif 140 141 /* for each bits, set '1' enable the intterrupt, and '0' takes no effects */ 142 /* return last irq_enable status */ 143 u32 hieth_irq_enable(struct hieth_netdev_local *ld, u32 irqs); 144 u32 hieth_irq_disable(struct hieth_netdev_local *ld, u32 irqs); 145 /* return irqstatus */ 146 u32 hieth_read_irqstatus(struct hieth_netdev_local *ld); 147 u32 hieth_read_raw_irqstatus(struct hieth_netdev_local *ld); 148 /* return irqstatus after clean */ 149 u32 hieth_clear_irqstatus(struct hieth_netdev_local *ld, u32 irqs); 150 151 u32 hieth_set_endian_mode(struct hieth_netdev_local *ld, u32 mode); 152 void hw_xmitq_setfd(struct hieth_netdev_local *ld, struct hieth_frame_desc fd); 153 154 /* Tx/Rx queue operation */ 155 int hieth_set_hwq_depth(struct hieth_netdev_local *ld); 156 int hieth_get_hwq_xmit_depth(struct hieth_netdev_local *ld); 157 int hieth_get_hwq_recv_depth(struct hieth_netdev_local *ld); 158 159 #define hieth_invalid_txqfd_addr(addr) ((addr) & 0x3) 160 #define hieth_invalid_rxqfd_addr(addr) ((addr) & 0x3) 161 #define hieth_invalid_rxpkg_len(len) (!((len) >= 42 && (len) <= HIETH_MAX_FRAME_SIZE)) 162 163 #endif 164