1 /* 2 * platform.h 3 * 4 * Register and variable declaration of the chip. 5 * 6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 * 21 */ 22 23 #ifndef __HI_CHIP_REGS_H__ 24 #define __HI_CHIP_REGS_H__ 25 26 #define _HI3559A_V100 0x3559A100LL 27 #define _HI3559AV100_MASK 0xFFFFFFFFFFLL 28 29 /* -------------------------------------------------------------------- */ 30 /* Communication Register and flag used by bootrom */ 31 /* -------------------------------------------------------------------- */ 32 #define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1) 33 #define START_MAGIC 0x444f574e 34 #define SELF_BOOT_TYPE_USBDEV 0x2 35 #define CP_STEP1_ADDR 0x08040000 36 #define PCIE_SLAVE_BOOT_CTL_REG 0x0134 37 #define DDR_INIT_DOWNLOAD_OK_FLAG 0xDCDFF001 /* step1:Ddrinit Code Download Finished Flag: DCDFF001 */ 38 #define DDR_INIT_EXCUTE_OK_FLAG 0xDCEFF002 /* step2:Ddrinit Code Excute Finished Flag: DCEFF002 */ 39 #define UBOOT_DOWNLOAD_OK_FLAG 0xBCDFF003 /* step3:Boot Code Download Finished Flag: BCDFF003 */ 40 41 /* -------------------------------------------------------------------- */ 42 /* System Control */ 43 /* -------------------------------------------------------------------- */ 44 #define SYS_CTRL_REG_BASE 0x12020000 45 #define REG_BASE_SCTL SYS_CTRL_REG_BASE 46 #define REG_SC_CTRL 0x0000 47 #define REG_SC_SYSRES 0x0004 48 #define REG_PERISTAT 0x0030 49 #define REG_SYSSTAT 0x008c 50 #define get_spi_nor_addr_mode(_reg) (((_reg) >> 10) & 0x1) 51 #define get_spi_device_type(_reg) (((_reg) >> 9) & 0x1) 52 #define get_sys_boot_mode(_reg) (((_reg) >> 4) & 0x3) 53 #define BOOT_FROM_SPI 0 54 #define BOOT_FROM_NAND 1 55 #define BOOT_FROM_EMMC 2 56 #define BOOT_FROM_UFS 3 57 58 #define REG_SC_GEN0 0x0138 59 #define REG_SC_GEN1 0x013c 60 #define REG_SC_GEN2 0x0140 61 #define REG_SC_GEN3 0x0144 62 #define REG_SC_GEN4 0x0148 63 #define REG_SC_GEN9 0x0154 64 #define REG_SC_GEN20 0x0090 65 66 /* -------------------------------------------------------------------- */ 67 /* CPU SUBSYS */ 68 /* -------------------------------------------------------------------- */ 69 #define REG_CRG_CLUSTER0_CLK_RST 0x00cc /* CPU SUBSYS clock and reset control */ 70 #define CLUSTER0_GLB_SRST_REQ (0x1 << 21) 71 #define REG_PERI_CPU_RVBARADDR_A53UP 0x12030004 72 #define REG_PERI_CPU_RVBARADDR_SOC 0x1d830020 73 #define CLUSTER2_GLB_SRST_REQ (0x1 << 28) 74 #define CLUSTER2_GLB_CKEN (0x1 << 27) 75 76 /* -------------------------------------------------------------------- */ 77 /* CRG */ 78 /* -------------------------------------------------------------------- */ 79 #define CRG_REG_BASE 0x12010000 80 81 /* -------------------------------------------------------------------- */ 82 /* Peripheral Control REG */ 83 /* -------------------------------------------------------------------- */ 84 #define MISC_REG_BASE 0x12030000 85 86 /* -------------------------------------------------------------------- */ 87 /* IO configuration REG:mux and driver */ 88 /* -------------------------------------------------------------------- */ 89 #define IO_CONFIG_REG_BASE 0x1F000000 90 91 /* -------------------------------------------------------------------- */ 92 /* TIMER */ 93 /* -------------------------------------------------------------------- */ 94 #define TIMER0_REG_BASE 0x12000000 95 #define REG_TIMER_RELOAD 0x0 96 #define REG_TIMER_VALUE 0x4 97 #define REG_TIMER_CONTROL 0x8 98 #define CFG_TIMER_CLK 3000000 99 #define CFG_TIMERBASE TIMER0_REG_BASE 100 /* enable timer.32bit, periodic,mask irq, 1 divider. */ 101 #define CFG_TIMER_CTRL 0xC2 102 103 /* -------------------------------------------------------------------- */ 104 /* UART */ 105 /* -------------------------------------------------------------------- */ 106 #define UART0_REG_BASE 0x12100000 107 #define UART1_REG_BASE 0x12101000 108 #define UART2_REG_BASE 0x12102000 109 #define UART3_REG_BASE 0x12103000 110 111 /* -------------------------------------------------------------------- */ 112 /* DDRC */ 113 /* -------------------------------------------------------------------- */ 114 #define STACK_TRAINING 0x08009000 115 #define DDRC0_REG_BASE 0x12060000 116 #define DDR_MEM_BASE 0x40000000 117 #define REG_SC_DDRT0 0x0090 118 119 /* -------------------------------------------------------------------- */ 120 /* FMC */ 121 /* -------------------------------------------------------------------- */ 122 #define FMC_REG_BASE 0x10000000 123 #define FMC_MEM_BASE 0x14000000 124 125 /* FMC CRG register offset */ 126 #define REG_FMC_CRG 0x0170 127 128 #define fmc_clk_sel(_clk) (((_clk) & 0x7) << 2) 129 #define FMC_CLK_SEL_MASK (0x7 << 2) 130 #define get_fmc_clk_type(_reg) (((_reg) >> 2) & 0x7) 131 132 /* SDR/DDR clock */ 133 #define FMC_CLK_24M 0 134 #define FMC_CLK_75M 1 135 #define FMC_CLK_125M 2 136 #define FMC_CLK_150M 3 137 #define FMC_CLK_200M 4 138 /* Only DDR clock */ 139 #define FMC_CLK_250M 5 140 #define FMC_CLK_300M 6 141 #define FMC_CLK_400M 7 142 143 #define FMC_CLK_ENABLE (0x1 << 1) 144 #define FMC_SOFT_RST_REQ (0x1 << 0) 145 146 /*--------------------------------------------------------------------- */ 147 /* EMMC / SD */ 148 /* -------------------------------------------------------------------- */ 149 #define REG_SDIO0_CRG (CRG_REG_BASE + 0x1ec) 150 151 /* eMMC CRG register offset */ 152 #define REG_EMMC_CRG (CRG_REG_BASE + 0x1a8) 153 #define mmc_clk_sel(_clk) (((_clk) & 0x7) << 24) 154 #define MMC_CLK_SEL_MASK (0x7 << 24) 155 #define get_mmc_clk_type(_reg) (((_reg) >> 24) & 0x7) 156 157 /* SDIO0 REG */ 158 #define SDIO0_BASE_REG 0x10100000 159 160 /* SDIO1 REG */ 161 #define SDIO1_BASE_REG 0x10110000 162 163 /* EMMC REG */ 164 #define EMMC_BASE_REG 0x100F0000 165 #define EMMC_PHY_BASE 0x10290000 166 167 #define NF_BOOTBW_MASK (1 << 10) 168 #define REG_BASE_PERI_CTRL REG_BASE_SCTL 169 #define REG_BASE_IO_CONFIG IO_CONFIG_REG_BASE 170 171 #define MMC_IOMUX_START_ADDR 0xF8 172 #define MMC_IOMUX_END_ADDR 0x13C 173 #define MMC_IOMUX_CTRL_MASK (1<<0 | 1<<1) 174 #define MMC_IOMUX_CTRL (1<<1) 175 176 /* -------------------------------------------------------------------- */ 177 /* UFS */ 178 /* -------------------------------------------------------------------- */ 179 #define PERI_CRG96 0x180 /* UFS/eMMC clock and reset control */ 180 #define BIT_UFS_AXI_SRST_REQ (0x1 << 11) 181 #define BIT_UFS_SRST_REQ (0x1 << 12) 182 #define BIT_UFS_CLK_EN (0x1 << 13) 183 184 #define MISC_CTRL17 0x44 185 #define UFS_EN 0x1 186 #define DA_UFS_REFCLK_OEN (0x1 << 3) 187 #define DA_UFS_RST_OEN (0x1 << 10) 188 #define EMMC_ISO_EN (0x1 << 16) 189 #define RG_EMMC_LHEN_IN (0x3f << 17) 190 #define MISC_CTRL18 0x48 191 #define MISC_CTRL36 0x0090 192 #define MISC_CTRL37 0x0094 193 194 #define BIT_UFS_PAD_RESET (0x1 << 15) 195 #define BIT_DA_UFS_RESET_DS2 (0x1 << 14) 196 #define BIT_DA_UFS_RESET_DS1 (0x1 << 13) 197 #define BIT_DA_UFS_RESET_DS0 (0x1 << 12) 198 #define BIT_DA_UFS_RESET_SL (0x1 << 11) 199 #define BIT_DA_UFS_RESET_OEN (0x1 << 10) 200 #define BIT_DA_UFS_RESET_PS (0x1 << 9) 201 #define BIT_DA_UFS_RESET_PE (0x1 << 8) 202 #define BIT_DA_UFS_REFCLK_DS2 (0x1 << 7) 203 #define BIT_DA_UFS_REFCLK_DS1 (0x1 << 6) 204 #define BIT_DA_UFS_REFCLK_DS0 (0x1 << 5) 205 #define BIT_DA_UFS_REFCLK_SL (0x1 << 4) 206 #define BIT_DA_UFS_REFCLK_OEN (0x1 << 3) 207 #define BIT_DA_UFS_REFCLK_PS (0x1 << 2) 208 #define BIT_DA_UFS_REFCLK_PE (0x1 << 1) 209 #define BIT_UFS_ENABLE (0x1 << 0) 210 211 #define MASK_DA_UFS_RESET_DS (0x7 << 12) 212 #define MASK_DA_UFS_REFCLK_DS (0x7 << 5) 213 214 /*--------------------------------------------------------------------- */ 215 /* HIGMAC */ 216 /* -------------------------------------------------------------------- */ 217 #define HIGMAC0_IOBASE 0x101C0000 218 #define HIGMAC1_IOBASE 0x101E0000 219 /* Ethernet CRG register offset */ 220 #define REG_ETH_CRG 0x174 221 /* Ethernet MAC CRG register bit map */ 222 #define BIT_GSF_PUB_CLK_EN 0 223 #define BIT_GMAC0_RST BIT(0) 224 #define BIT_GMAC0_CLK_EN BIT(1) 225 #define BIT_GMAC1_RST BIT(2) 226 #define BIT_GMAC1_CLK_EN BIT(3) 227 #define BIT_MACIF0_RST BIT(4) 228 #define BIT_GMACIF0_CLK_EN BIT(5) 229 #define BIT_MACIF1_RST BIT(6) 230 #define BIT_GMACIF1_CLK_EN BIT(7) 231 #define BIT_RMII0_CLKSEL_PAD BIT(8) 232 #define BIT_RMII1_CLKSEL_PAD BIT(9) 233 #define BIT_EXT_PHY0_CLK_SELECT BIT(12) 234 #define BIT_EXT_PHY1_CLK_SELECT BIT(13) 235 #define BIT_EXT_PHY0_RST BIT(14) 236 #define BIT_EXT_PHY1_RST BIT(15) 237 238 #define PHY0_CLK_25M 0 239 #define PHY0_CLK_50M BIT_EXT_PHY0_CLK_SELECT 240 #define PHY1_CLK_25M 0 241 #define PHY1_CLK_50M BIT_EXT_PHY1_CLK_SELECT 242 243 #define HIGMAC_MACIF0_CTRL (HIGMAC0_IOBASE + 0x300c) 244 #define HIGMAC_MACIF1_CTRL (HIGMAC1_IOBASE + 0x300c) 245 #define HIGMAC_DUAL_MAC_CRF_ACK_TH (HIGMAC0_IOBASE + 0x3004) 246 247 /* -------------------------------------------------------------------- */ 248 /* USB */ 249 /* -------------------------------------------------------------------- */ 250 #define USB3_CTRL_REG_BASE 0x12300000 251 #define USB3_CTRL_REG_BASE_1 0x12310000 252 253 /* USB CRG register offset and config */ 254 #define PERI_CRG97 0x184 255 #define USB2_PHY_CKEN (0x1<<4) 256 #define USB2_PHY_PORT_TREQ (0x1<<2) 257 #define USB2_PHY_REQ (0x1<<0) 258 259 #define PERI_CRG98 0x188 260 #define COMBPHY_REF_CKEN (0x1<<24) 261 #define COMBPHY_SRST_REQ (0x1<<16) 262 263 #define PERI_CRG100 0x190 264 #define USB3_VCC_SRST_REQ (0x1<<0) 265 #define USB3_UTMI_CKSEL (0x1<<13) 266 #define USB3_1_PCLK_OCC_SEL (0x1<<14) 267 #define USB3_0_PCLK_OCC_SEL (0x1<<30) 268 269 #define USB2_PHY_CFG (CRG_REG_BASE + PERI_CRG97) 270 #define USB3_COMBPHY_CFG (CRG_REG_BASE + PERI_CRG98) 271 #define USB3_CTRL_CFG (CRG_REG_BASE + PERI_CRG100) 272 273 /* USB CTRL register offset and config */ 274 #define GTXTHRCFG 0xc108 275 #define GRXTHRCFG 0xc10c 276 #define REG_GCTL 0xc110 277 278 #define USB_TXPKT_CNT_SEL (0x1<<29) 279 #define USB_TXPKT_CNT (0x11<<24) 280 #define USB_MAXTX_BURST_SIZE (0x1<<20) 281 #define CLEAN_USB3_GTXTHRCFG 0x0 282 283 #define REG_GUSB3PIPECTL0 0xc2c0 284 #define PCS_SSP_SOFT_RESET (0x1 << 31) 285 286 /* USB EYE diagram para offset and config */ 287 #define USB3_COMB_PHY 0x14 288 #define P0_TX_SWING_COMP_CFG 0xd13 289 #define P0_TX_SWING_COMP_RCFG 0xd53 290 #define P0_TX_SWING_COMP_VAL 0xd13 291 292 #define P0_TX_TERMINATION_TRIM_CFG 0x14 293 #define P0_TX_TERMINATION_TRIM_RCFG 0x54 294 #define P0_TX_TERMINATION_TRIM_VAL 0x14 295 296 #define P1_TX_SWING_COMP_CFG 0xd33 297 #define P1_TX_SWING_COMP_RCFG 0xd73 298 #define P1_TX_SWING_COMP_VAL 0xd33 299 300 #define P1_TX_TERMINATION_TRIM_CFG 0x34 301 #define P1_TX_TERMINATION_TRIM_RCFG 0x74 302 #define P1_TX_TERMINATION_TRIM_VAL 0x34 303 304 #define USB2_PHY0_CTRL 0x24 305 #define USB2_PHY1_CTRL 0x30 306 #define USB2_PHY_VREF (0x5 << 4) 307 #define USB2_PHY_PRE (0x3 << 12) 308 309 /* -------------------------------------------------------------------- */ 310 /* HW DECOMPRESS */ 311 /* -------------------------------------------------------------------- */ 312 #define GZIP_REG_BASE 0x11330000 313 #define HW_DEC_INTR 86 314 /* -------------------------------------------------------------------- */ 315 /* PCIE */ 316 /* -------------------------------------------------------------------- */ 317 #define SYS_SATA 0x8c 318 #define PCIE_MODE 12 319 320 #define PERI_CRG98 0x188 321 #define PHY0_SRS_REQ 0 322 #define PHY0_SRS_REQ_SEL 1 323 #define PHY1_SRS_REQ 16 324 #define PHY1_SRS_REQ_SEL 17 325 326 #define MISC_CTRL5 0x14 327 328 /* --------------------------------------------------------- */ 329 #define NUM_0 0 330 #define NUM_1 1 331 #define NUM_2 2 332 #define NUM_3 3 333 #define NUM_4 4 334 #define NUM_5 5 335 #define NUM_6 6 336 #define NUM_7 7 337 #define NUM_8 8 338 #define NUM_9 9 339 #define NUM_10 10 340 341 #define BIT_16 16 342 #define BIT_20 20 343 #define BIT_24 24 344 #define BIT_28 28 345 346 #endif /* End of __HI_CHIP_REGS_H__ */ 347