1 /**************************************************************************//**
2 * @file gr551xx.h
3 * @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File for
4 * Device gr551xx
5 * @version V1.00
6 * @date 12. June 2018
7 ******************************************************************************/
8 /*
9 * Copyright (c) 2016-2018, Shenzhen Huiding Technology Co., Ltd
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 /** @addtogroup Device_Included
27 * @{
28 */
29
30 /** @addtogroup GR551xx
31 * @{
32 */
33
34 #ifndef __GR551xx_H__
35 #define __GR551xx_H__
36
37 #include <stdint.h>
38 #include "system_gr55xx.h" /* System Header */
39 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 #if defined (__CC_ARM)
46 #pragma push
47 #pragma anon_unions
48 #elif defined (__ICCARM__)
49 #pragma language=extended
50 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
51 #pragma clang diagnostic push
52 #pragma clang diagnostic ignored "-Wc11-extensions"
53 #pragma clang diagnostic ignored "-Wreserved-id-macro"
54 #elif defined (__GNUC__)
55 /* anonymous unions are enabled by default */
56 #elif defined (__TMS470__)
57 /* anonymous unions are enabled by default */
58 #elif defined (__TASKING__)
59 #pragma warning 586
60 #elif defined (__CSMC__)
61 /* anonymous unions are enabled by default */
62 #else
63 #warning Not supported compiler type
64 #endif
65
66
67 /* ================================================================================================================= */
68 /* ================ Device Specific Peripheral Section ================ */
69 /* ================================================================================================================= */
70
71 /** @addtogroup Peripheral_registers_structures
72 * @{
73 */
74
75 /**
76 * @brief AES
77 */
78 typedef struct _aes_regs {
79 __IOM uint32_t CTRL; /**< AES_REG_CTRL, Address offset: 0x00 */
80 __IOM uint32_t CONFIG; /**< AES_REG_CONFIG, Address offset: 0x04 */
81 __IM uint32_t STATUS; /**< AES_REG_STATUS, Address offset: 0x08 */
82 __IOM uint32_t INTERRUPT; /**< AES_REG_INTERRUPT, Address offset: 0x0C */
83 __IOM uint32_t TRAN_SIZE; /**< AES_REG_TRAN_SIZE, Address offset: 0x10 */
84 __IOM uint32_t RSTART_ADDR; /**< AES_REG_RSTART_ADDR, Address offset: 0x14 */
85 __IOM uint32_t WSTART_ADDR; /**< AES_REG_WSTART_ADDR, Address offset: 0x18 */
86 __IOM uint32_t KEY_ADDR; /**< AES_REG_KEY_ADDR, Address offset: 0x1C */
87 __IM uint32_t DATA_OUT[4]; /**< AES_REG_DATA_OUT, Address offset: 0x20 */
88 __OM uint32_t KEY[8]; /**< AES_REG_KEY, Address offset: 0x30 */
89 __IOM uint32_t SEED_IN; /**< AES_REG_SEED_IN, Address offset: 0x50 */
90 __IOM uint32_t SEED_OUT; /**< AES_REG_SEED_OUT, Address offset: 0x54 */
91 __IOM uint32_t SEED_IMASK; /**< AES_REG_SEED_IMASK, Address offset: 0x58 */
92 __IOM uint32_t SEED_OSBOX; /**< AES_REG_SEED_OSBOX, Address offset: 0x5C */
93 __OM uint32_t VECTOR_INIT[4]; /**< AES_REG_VECTOR_INIT, Address offset: 0x60 */
94 __OM uint32_t DATA_IN[4]; /**< AES_REG_DATA_IN, Address offset: 0x70 */
95 __OM uint32_t KPORT_MASK; /**< AES_REG_KPORT_MASK, Address offset: 0x80 */
96 } aes_regs_t;
97
98 /**
99 * @brief AON
100 */
101 typedef struct _aon_regs {
102 __IOM uint32_t SOFTWARE_0; /**< AON_REG_SOFTWARE_0, Address offset: 0x00 */
103 __IOM uint32_t PWR_RET01; /**< AON_REG_PWR_RET01, Address offset: 0x04 */
104 __IOM uint32_t SNSADC_CFG; /**< AON_REG_SNSADC_CFG, Address offset: 0x08 */
105 __IOM uint32_t RF_REG_0; /**< AON_REG_RF_REG_0, Address offset: 0x0C */
106 __IOM uint32_t RF_REG_1; /**< AON_REG_RF_REG_1, Address offset: 0x10 */
107 __IOM uint32_t RF_REG_2; /**< AON_REG_RF_REG_2, Address offset: 0x14 */
108 __IOM uint32_t CALENDAR_TIMER_CTL; /**< AON_REG_CALENDAR_TIMER_CTL, Address offset: 0x18 */
109 __IOM uint32_t MEM_STD_OVR; /**< AON_REG_MEM_STD_OVR, Address offset: 0x1C */
110 __IOM uint32_t RF_REG_3; /**< AON_REG_RF_REG_3, Address offset: 0x20 */
111 __IOM uint32_t RF_REG_4; /**< AON_REG_RF_REG_4, Address offset: 0x24 */
112 __IOM uint32_t RF_REG_5; /**< AON_REG_RF_REG_5, Address offset: 0x28 */
113 __IOM uint32_t RF_REG_6; /**< AON_REG_RF_REG_6, Address offset: 0x2C */
114 __IOM uint32_t RF_REG_7; /**< AON_REG_RF_REG_7, Address offset: 0x30 */
115 __IOM uint32_t RF_REG_8; /**< AON_REG_RF_REG_8, Address offset: 0x34 */
116 __IOM uint32_t RF_REG_9; /**< AON_REG_RF_REG_9, Address offset: 0x38 */
117 __IOM uint32_t MSIO_PAD_CFG_0; /**< AON_REG_MSIO_PAD_CFG_0, Address offset: 0x3C */
118 __IOM uint32_t MSIO_PAD_CFG_1; /**< AON_REG_MSIO_PAD_CFG_1, Address offset: 0x40 */
119 __IOM uint32_t SLP_EVENT; /**< AON_REG_SLP_EVENT, Address offset: 0x44 */
120 __IOM uint32_t WARM_BOOT_TIME; /**< AON_REG_WARM_BOOT_TIME, Address offset: 0x48 */
121 __IOM uint32_t RF_REG_10; /**< AON_REG_RF_REG_10, Address offset: 0x4C */
122 __IOM uint32_t AON_PAD_CTL0; /**< AON_REG_AON_PAD_CTL0, Address offset: 0x50 */
123 __IOM uint32_t MEM_N_SLP_CTL; /**< AON_REG_MEM_N_SLP_CTL, Address offset: 0x54 */
124 __IOM uint32_t EXT_WKUP_CTL; /**< AON_REG_EXT_WKUP_CTL, Address offset: 0x58 */
125 __IOM uint32_t AON_PAD_CTL1; /**< AON_REG_AON_PAD_CTL1, Address offset: 0x5C */
126 __IOM uint32_t SOFTWARE_1; /**< AON_REG_SOFTWARE_1, Address offset: 0x60 */
127 __IOM uint32_t MEM_PWR_SLP; /**< AON_REG_MEM_PWR_SLP, Address offset: 0x64 */
128 __IOM uint32_t MEM_PWR_WKUP; /**< AON_REG_MEM_PWR_WKUP, Address offset: 0x68 */
129 __IOM uint32_t PWR_RET27; /**< AON_REG_PWR_RET27, Address offset: 0x6C */
130 __IOM uint32_t PWR_RET28; /**< AON_REG_PWR_RET28, Address offset: 0x70 */
131 __IOM uint32_t PWR_RET29; /**< AON_REG_PWR_RET29, Address offset: 0x74 */
132 __IOM uint32_t SOFTWARE_2; /**< AON_REG_SOFTWARE_2, Address offset: 0x78 */
133 __IOM uint32_t PWR_RET31; /**< AON_REG_PWR_RET31, Address offset: 0x7C */
134 __IOM uint32_t PSC_CMD; /**< AON_REG_PSC_CMD, Address offset: 0x80 */
135 __IOM uint32_t PSC_CMD_OPC; /**< AON_REG_PSC_CMD_OPC, Address offset: 0x84 */
136 __IM uint32_t MCU_RELEASE; /**< AON_REG_MCU_RELEASE, Address offset: 0x88 */
137 __IM uint32_t RESERVED0; /**< Reserved, Address offset: 0x8C */
138 __IOM uint32_t TIMER_VALUE; /**< AON_REG_TIMER_VALUE, Address offset: 0x90 */
139 __IM uint32_t TIMER_VAL; /**< AON_REG_TIMER_VAL, Address offset: 0x94 */
140 __IM uint32_t RESERVED1[13]; /**< Reserved, Address offset: 0x98 */
141 __IOM uint32_t FPGA_CTRL; /**< AON_REG_FPGA_CTRL, Address offset: 0xCC */
142 __IM uint32_t RESERVED2[5]; /**< Reserved, Address offset: 0xD0 */
143 __IOM uint32_t ST_CALIB; /**< AON_REG_ST_CALIB_REG, Address offset: 0xE4 */
144 } aon_regs_t;
145
146 /**
147 * @brief DMA
148 */
149 #define DMA_REG(name) __IOM uint32_t name; __IOM uint32_t __pad_##name
150 /* DMA/Channel_x_Registers Registers */
151 typedef struct {
152 DMA_REG(SAR); /**< Source Address, Address offset: 0x00 */
153 DMA_REG(DAR); /**< Destination Address, Address offset: 0x08 */
154 DMA_REG(LLP); /**< Linked List Pointer, Address offset: 0x10 */
155 __IOM uint32_t CTL_LO; /**< Control Register Low, Address offset: 0x18 */
156 __IOM uint32_t CTL_HI; /**< Control Register High, Address offset: 0x1C */
157 DMA_REG(SSTAT); /**< Source Status, Address offset: 0x20 */
158 DMA_REG(DSTAT); /**< Destination Status, Address offset: 0x28 */
159 DMA_REG(SSTATAR); /**< Source Status Address, Address offset: 0x30 */
160 DMA_REG(DSTATAR); /**< Destination Status Address, Address offset: 0x38 */
161 __IOM uint32_t CFG_LO; /**< Configuration Register Low, Address offset: 0x40 */
162 __IOM uint32_t CFG_HI; /**< Configuration Register High, Address offset: 0x44 */
163 DMA_REG(SGR); /**< Source Gather, Address offset: 0x48 */
164 DMA_REG(DSR); /**< Destination Scatter, Address offset: 0x50 */
165 } DMA_CH_REGS;
166
167 /* DMA/Interrupt_Registers Registers */
168 typedef struct {
169 __IO uint32_t RAW_CH_EVT[10]; /**< Raw channel event, Address offset: 0x00 */
170 __I uint32_t STATUS_CH_EVT[10]; /**< Status channel event, Address offset: 0x28 */
171 __IO uint32_t MASK_CH_EVT[10]; /**< Mask channel event, Address offset: 0x50 */
172 __O uint32_t CLEAR_CH_EVT[10]; /**< Clear channel event, Address offset: 0x78 */
173 DMA_REG(STATUS_EVT); /**< Status event, Address offset: 0xA0 */
174 } DMA_INT_REGS;
175
176 /* DMA/Software_Handshake_Registers Registers */
177 typedef struct {
178 DMA_REG(REQ_SRC); /**< Source Transaction Request, Address offset: 0x00 */
179 DMA_REG(REQ_DST); /**< Destination Transaction Request, Address offset: 0x08 */
180 DMA_REG(SGL_RQ_SRC); /**< Source Single Transaction Request, Address offset: 0x20 */
181 DMA_REG(SGL_RQ_DST); /**< Destination Single Transaction Request,Address offset: 0x28 */
182 DMA_REG(LST_SRC); /**< Source Last Transaction Request, Address offset: 0x30 */
183 DMA_REG(LST_DST); /**< Destination Last Transaction Request, Address offset: 0x38 */
184 } DMA_HS_REGS;
185
186 /* DMA/Miscellaneous_Registers Registers */
187 typedef struct {
188 DMA_REG(CFG); /**< DMA Configuration, Address offset: 0x00 */
189 DMA_REG(CH_EN); /**< DMA Channel Enable, Address offset: 0x08 */
190 DMA_REG(ID); /**< DMA ID, Address offset: 0x20 */
191 DMA_REG(TEST); /**< DMA Test, Address offset: 0x28 */
192 DMA_REG(LP_TIMEOUT); /**< DMA Low Power Timeout, Address offset: 0x30 */
193 DMA_REG(RESERVED); /**< Reserved, Address offset: 0x38 */
194 DMA_REG(COMP_PARAMS_6); /**< DMA Component Parameters 6, Address offset: 0x40 */
195 DMA_REG(COMP_PARAMS_5); /**< DMA Component Parameters 5, Address offset: 0x48 */
196 DMA_REG(COMP_PARAMS_4); /**< DMA Component Parameters 4, Address offset: 0x50 */
197 DMA_REG(COMP_PARAMS_3); /**< DMA Component Parameters 3, Address offset: 0x58 */
198 DMA_REG(COMP_PARAMS_2); /**< DMA Component Parameters 2, Address offset: 0x60 */
199 DMA_REG(COMP_PARAMS_1); /**< DMA Component Parameters 1, Address offset: 0x68 */
200 DMA_REG(COMPS_ID); /**< DMA Component ID, Address offset: 0x70 */
201 } DMA_MISC_REGS;
202
203 typedef struct _dma_regs {
204 DMA_CH_REGS CHANNEL[8]; /**< DMA_REG_CH register, Address offset: 0x000 */
205 DMA_INT_REGS EVENT; /**< DMA_REG_INT register, Address offset: 0x2C0 */
206 DMA_HS_REGS HANDSHAKE; /**< DMA_REG_HS register, Address offset: 0x368 */
207 DMA_MISC_REGS MISCELLANEOU; /**< DMA_REG_MISC register, Address offset: 0x3A8 */
208 } dma_regs_t;
209
210 /**
211 * @brief DUAL_TIM
212 */
213 typedef struct _dual_timer_regs {
214 __IOM uint32_t RELOAD; /**< DUAL_TIMER auto-reload register, Address offset: 0x00 */
215 __IM uint32_t VALUE; /**< DUAL_TIMER counter value register, Address offset: 0x04 */
216 __IOM uint32_t CTRL; /**< DUAL_TIMER control register, Address offset: 0x08 */
217 __OM uint32_t INTCLR; /**< DUAL_TIMER interrupt status clear register, Address offset: 0x0C */
218 __IM uint32_t RAW_INTSTAT; /**< DUAL_TIMER raw interrupt status register, Address offset: 0x10 */
219 __IM uint32_t INTSTAT; /**< DUAL_TIMER interrupt status register, Address offset: 0x14 */
220 __IOM uint32_t BG_LOAD; /**< DUAL_TIMER background-reload register, Address offset: 0x18 */
221 } dual_timer_regs_t;
222
223 /**
224 * @brief GPIO
225 */
226 typedef struct _gpio_regs {
227 __IOM uint32_t DATA; /**< GPIO_REG_DATA register, Address offset: 0x000 */
228 __IOM uint32_t DATAOUT; /**< GPIO_REG_DATAOUT register, Address offset: 0x004 */
229 __IM uint32_t RESERVED0[2]; /**< GPIO_REG_RESERVED register, Address offset: 0x008 */
230 __IOM uint32_t OUTENSET; /**< GPIO_REG_OUTENSET register, Address offset: 0x010 */
231 __IOM uint32_t OUTENCLR; /**< GPIO_REG_OUTENCLR register, Address offset: 0x014 */
232 __IOM uint32_t ALTFUNCSET; /**< GPIO_REG_ALTFUNCSET register, Address offset: 0x018 */
233 __IOM uint32_t ALTFUNCCLR; /**< GPIO_REG_ALTFUNCCLR register, Address offset: 0x01C */
234 __IOM uint32_t INTENSET; /**< GPIO_REG_INTENSET register, Address offset: 0x020 */
235 __IOM uint32_t INTENCLR; /**< GPIO_REG_INTENCLR register, Address offset: 0x024 */
236 __IOM uint32_t INTTYPESET; /**< GPIO_REG_INTTYPESET register, Address offset: 0x028 */
237 __IOM uint32_t INTTYPECLR; /**< GPIO_REG_INTTYPECLR register, Address offset: 0x02C */
238 __IOM uint32_t INTPOLSET; /**< GPIO_REG_INTPOLSET register, Address offset: 0x030 */
239 __IOM uint32_t INTPOLCLR; /**< GPIO_REG_INTPOLCLR register, Address offset: 0x034 */
240 __IOM uint32_t INTSTAT; /**< GPIO_REG_INTSTAT register, Address offset: 0x038 */
241 __IM uint32_t RESERVED1[241]; /**< GPIO_REG_RESERVED register, Address offset: 0x03C */
242 __IOM uint32_t MASKLOWBYTE[256]; /**< GPIO_REG_MASKLOWBYTE register, Address offset: 0x400 */
243 __IOM uint32_t MASKHIGHBYTE[256]; /**< GPIO_REG_MASKHIGHBYTE register, Address offset: 0x500 */
244 } gpio_regs_t;
245
246 /**
247 * @brief HMAC
248 */
249 typedef struct _hmac_regs {
250 __IOM uint32_t CTRL; /**< HMAC_REG_CTRL register, Adderss offset: 0x00 */
251 __IOM uint32_t CONFIG; /**< HMAC_REG_CONFIG register, Adderss offset: 0x04 */
252 __IM uint32_t STATUS; /**< HMAC_REG_STATUS register, Adderss offset: 0x08 */
253 __IOM uint32_t TRAN_SIZE; /**< HMAC_REG_TRAN_SIZE register, Adderss offset: 0x0C */
254 __IOM uint32_t INTERRUPT; /**< HMAC_REG_INTERRUPT register, Adderss offset: 0x10 */
255 __IOM uint32_t RSTART_ADDR; /**< HMAC_REG_RSTART_ADDR register, Adderss offset: 0x14 */
256 __IOM uint32_t WSTART_ADDR; /**< HMAC_REG_WSTART_ADDR register, Adderss offset: 0x18 */
257 __IM uint32_t REVERSED0; /**< HMAC_REG_REVERSED register, Adderss offset: 0x1C */
258 __IOM uint32_t USER_HASH[8]; /**< HMAC_REG_USER_HASH register, Adderss offset: 0x20 */
259 __IM uint32_t FIFO_OUT; /**< HMAC_REG_FIFO_OUT register, Adderss offset: 0x40 */
260 __OM uint32_t MESSAGE_FIFO; /**< HMAC_REG_MESSAGE_FIFO register, Adderss offset: 0x44 */
261 __OM uint32_t KEY[8]; /**< HMAC_REG_KEY register, Adderss offset: 0x48 */
262 __IOM uint32_t KEY_ADDR; /**< HMAC_REG_KEY_ADDR register, Adderss offset: 0x68 */
263 __OM uint32_t KPORT_MASK; /**< HMAC_REG_KPORT_MASK register, Adderss offset: 0x6C */
264 } hmac_regs_t;
265
266 /**
267 * @brief I2C
268 */
269 typedef struct _i2c_regs {
270 __IOM uint32_t CON; /**< I2C control, Address offset: 0x00 */
271 __IOM uint32_t TAR; /**< I2C target address, Address offset: 0x04 */
272 __IOM uint32_t SAR; /**< I2C slave address, Address offset: 0x08 */
273 __IOM uint32_t HS_MADDR; /**< I2C HS Master Mode Code address, Address offset: 0x0C */
274 __IOM uint32_t DATA_CMD; /**< I2C Rx/Tx Data Buffer and Command, Address offset: 0x10 */
275 __IOM uint32_t SS_SCL_HCNT; /**< Standard Speed I2C clock SCL High Count, Address offset: 0x14 */
276 __IOM uint32_t SS_SCL_LCNT; /**< Standard Speed I2C clock SCL Low Count, Address offset: 0x18 */
277 __IOM uint32_t FS_SCL_HCNT; /**< Fast Speed I2C clock SCL Low Count, Address offset: 0x1C */
278 __IOM uint32_t FS_SCL_LCNT; /**< Fast Speed I2C clock SCL Low Count, Address offset: 0x20 */
279 __IOM uint32_t HS_SCL_HCNT; /**< High Speed I2C clock SCL Low Count, Address offset: 0x24 */
280 __IOM uint32_t HS_SCL_LCNT; /**< High Speed I2C clock SCL Low Count, Address offset: 0x28 */
281 __IM uint32_t INTR_STAT; /**< I2C Interrupt Status, Address offset: 0x2C */
282 __IOM uint32_t INTR_MASK; /**< I2C Interrupt Mask, Address offset: 0x30 */
283 __IM uint32_t RAW_INTR_STAT; /**< I2C Raw Interrupt Status, Address offset: 0x34 */
284 __IOM uint32_t RX_TL; /**< I2C Receive FIFO Threshold, Address offset: 0x38 */
285 __IOM uint32_t TX_TL; /**< I2C Transmit FIFO Threshold, Address offset: 0x3C */
286 __IM uint32_t CLR_INTR; /**< Clear combined and Individual Interrupts, Address offset: 0x40 */
287 __IM uint32_t CLR_RX_UNDER; /**< Clear RX_UNDER Interrupt, Address offset: 0x44 */
288 __IM uint32_t CLR_RX_OVER; /**< Clear RX_OVER Interrupt, Address offset: 0x48 */
289 __IM uint32_t CLR_TX_OVER; /**< Clear TX_OVER Interrupt, Address offset: 0x4C */
290 __IM uint32_t CLR_RD_REQ; /**< Clear RQ_REQ Interrupt, Address offset: 0x50 */
291 __IM uint32_t CLR_TX_ABRT; /**< Clear TX_ABRT Interrupt, Address offset: 0x54 */
292 __IM uint32_t CLR_RX_DONE; /**< Clear RX_DONE Interrupt, Address offset: 0x58 */
293 __IM uint32_t CLR_ACTIVITY; /**< Clear ACTIVITY Interrupt, Address offset: 0x5C */
294 __IM uint32_t CLR_STOP_DET; /**< Clear STOP_DET Interrupt, Address offset: 0x60 */
295 __IM uint32_t CLR_START_DET; /**< Clear START_DET Interrupt, Address offset: 0x64 */
296 __IM uint32_t CLR_GEN_CALL; /**< Clear GEN_CALL Interrupt, Address offset: 0x68 */
297 __IOM uint32_t ENABLE; /**< I2C Enable, Address offset: 0x6C */
298 __IM uint32_t STATUS; /**< I2C Status, Address offset: 0x70 */
299 __IM uint32_t TXFLR; /**< Transmit FIFO Level Register, Address offset: 0x74 */
300 __IM uint32_t RXFLR; /**< Receive FIFO Level Register, Address offset: 0x78 */
301 __IOM uint32_t SDA_HOLD; /**< SDA Hold Time Length Reg, Address offset: 0x7C */
302 __IM uint32_t TX_ABRT_SOURCE; /**< I2C Transmit Abort Status Reg, Address offset: 0x80 */
303 __IOM uint32_t SLV_DATA_NACK_ONLY; /**< Generate SLV_DATA_NACK Register, Address offset: 0x84 */
304 __IOM uint32_t DMA_CR; /**< DMA Control Register, Address offset: 0x88 */
305 __IOM uint32_t DMA_TDLR; /**< DMA Transmit Data Level, Address offset: 0x8C */
306 __IOM uint32_t DMA_RDLR; /**< DMA Receive Data Level, Address offset: 0x90 */
307 __IOM uint32_t SDA_SETUP; /**< SDA Setup Register, Address offset: 0x94 */
308 __IOM uint32_t ACK_GENERAL_CALL; /**< ACK General Call Register, Address offset: 0x98 */
309 __IM uint32_t ENABLE_STATUS; /**< Enable Status Register, Address offset: 0x9C */
310 __IOM uint32_t FS_SPKLEN; /**< ISS and FS spike suppression limit, Address offset: 0xA0 */
311 __IOM uint32_t HS_SPKLEN; /**< HS spike suppression limit, Address offset: 0xA4 */
312 __IM uint32_t CLR_RESTART_DET; /**< Clear RESTART_DET Interrupt Register, Address offset: 0xA8 */
313 __IOM uint32_t SCL_STUCK_AT_LOW_TIMEOUT; /**< I2C SCL Stuck at Low Timeout, Address offset: 0xAC */
314 __IOM uint32_t SDA_STUCK_AT_LOW_TIMEOUT; /**< I2C SDA Stuck at Low Timeout, Address offset: 0xB0 */
315 __IM uint32_t CLR_SCL_STUCK_DET; /**< Clear SCL Stuck at Low Detect Interrupt, Address offset: 0xB4 */
316 __IM uint32_t DEVICE_ID; /**< I2C Device-ID Register, Address offset: 0xB8 */
317 __IOM uint32_t SMBUS_CLK_LOW_SEXT; /**< SMBus Slave Clock Extend Timeout Register, Address offset: 0xBC */
318 __IOM uint32_t SMBUS_CLK_LOW_MEXT; /**< SMBus Master Clock Extend Timeout Register, Address offset: 0xC0 */
319 __IOM uint32_t SMBUS_THIGH_MAX_IDLE_COUNT; /**< SMBus Master THigh MAX Bus-idle count, Address offset: 0xC4 */
320 __IM uint32_t SMBUS_INTSTAT; /**< SMBUS Interrupt Status Register, Address offset: 0xC8 */
321 __IOM uint32_t SMBUS_INTMASK; /**< SMBus Interrupt Mask Register, Address offset: 0xCC */
322 __IM uint32_t SMBUS_RAW_INTSTAT; /**< SMBus Raw Interrupt Status Register, Address offset: 0xD0 */
323 __OM uint32_t SMBUS_INTCLR; /**< SMBus Clear Interrupt Register, Address offset: 0xD4 */
324 __IOM uint32_t OPTIONAL_SAR; /**< I2C Optional Slave Address Register, Address offset: 0xD8 */
325 __IOM uint32_t SMBUS_UDID_LSB; /**< SMBUS ARP UDID LSB Register, Address offset: 0xDC */
326 __IM uint32_t RESERVED[5]; /**< I2C RESERVED register, Address offset: 0xE0 */
327 __IM uint32_t COMP_PARAM_1; /**< Component Parameter Register 1, Address offset: 0xF4 */
328 __IM uint32_t COMP_VERSION; /**< Component Version Register, Address offset: 0xF8 */
329 __IM uint32_t COMP_TYPE; /**< Component Type Register, Address offset: 0xFC */
330 } i2c_regs_t;
331
332 /**
333 * @brief I2S
334 */
335 typedef struct {
336 __IOM uint32_t DATA_L; /**< Left TX/RX buffer register, Address offset: 0x000 */
337 __IOM uint32_t DATA_R; /**< Right TX/RX buffer register, Address offset: 0x004 */
338 __IOM uint32_t RXEN; /**< RX enable, Address offset: 0x008 */
339 __IOM uint32_t TXEN; /**< TX enable, Address offset: 0x00C */
340 __IOM uint32_t RXSIZE; /**< RX data size, Address offset: 0x010 */
341 __IOM uint32_t TXSIZE; /**< TX data size, Address offset: 0x014 */
342 __IM uint32_t INTSTAT; /**< Interrupt status, Address offset: 0x018 */
343 __IOM uint32_t INTMASK; /**< Interrupt mask, Address offset: 0x01C */
344 __IM uint32_t RXOVR; /**< RX FIFO overflow flag, read to clear, Address offset: 0x020 */
345 __IM uint32_t TXOVR; /**< TX FIFO overflow flag, read to clear, Address offset: 0x024 */
346 __IOM uint32_t RXFIFO_TL; /**< RX FIFO threshold level, Address offset: 0x028 */
347 __IOM uint32_t TXFIFO_TL; /**< TX FIFO threshold level, Address offset: 0x02C */
348 __OM uint32_t RXFIFO_FLUSH; /**< RX FIFO flush, Address offset: 0x030 */
349 __OM uint32_t TXFIFO_FLUSH; /**< TX FIFO flush, Address offset: 0x034 */
350 __IM uint32_t RESERVED[2]; /**< Reversed, Address offset: 0x038 */
351 } I2S_CHANNEL_REGS;
352
353 typedef struct _i2s_regs {
354 __IOM uint32_t ENABLE; /**< I2S enable, Address offset: 0x000 */
355 __IOM uint32_t RBEN; /**< I2S receiver block enable, Address offset: 0x004 */
356 __IOM uint32_t TBEN; /**< I2S transmitter block enable, Address offset: 0x008 */
357 __IOM uint32_t CLKEN; /**< Clock enable, Address offset: 0x00C */
358 __IOM uint32_t CLKCONFIG; /**< Clock configuration, Address offset: 0x010 */
359 __OM uint32_t RXFIFO_RST; /**< Receiver block FIFO reset, Address offset: 0x014 */
360 __OM uint32_t TXFIFO_RST; /**< Transmitter block FIFO reset, Address offset: 0x018 */
361 __IM uint32_t RESERVED0; /**< Reversed, Address offset: 0x01C */
362 I2S_CHANNEL_REGS I2S_CHANNEL[4]; /**< I2S channels registers, Address offset: 0x020 */
363 __IM uint32_t RESERVED1[40]; /**< Reversed, Address offset: 0x120 */
364 __IM uint32_t RXDMA; /**< Receiver block DMA register, Address offset: 0x1C0 */
365 __OM uint32_t RXDMA_RST; /**< Receiver block DMA reset, Address offset: 0x1C4 */
366 __OM uint32_t TXDMA; /**< Transmitter block DMA register, Address offset: 0x1C8 */
367 __OM uint32_t TXDMA_RST; /**< Transmitter block DMA reset, Address offset: 0x1CC */
368 __IM uint32_t RESERVED2[8]; /**< Reversed, Address offset: 0x1D0 */
369 __IM uint32_t I2S_PARAM2; /**< I2S component parameter register 2, Address offset: 0x1F0 */
370 __IM uint32_t I2S_PARAM1; /**< I2S component parameter register 1, Address offset: 0x1F4 */
371 __IM uint32_t I2S_VERSION; /**< I2S component version, Address offset: 0x1F8 */
372 __IM uint32_t I2S_TYPE; /**< I2S component type, Address offset: 0x1FC */
373 } i2s_regs_t;
374
375 /**
376 * @brief ISO7816
377 */
378 typedef struct _iso7816_regs {
379 __OM uint32_t CTRL; /**< Control Register, Address offset: 0x0000 */
380 __IM uint32_t STAT; /**< Status Register, Address offset: 0x0004 */
381 __IOM uint32_t CLK_CFG; /**< Clock Configuration Register , Address offset: 0x0008 */
382 __IOM uint32_t RESERVED0[1]; /**< RESERVED, Address offset: 0x000C */
383 __IOM uint32_t TIMES_CFG; /**< Times Configuration Register , Address offset: 0x0010 */
384 __IOM uint32_t DATA_CFG; /**< Data Configuration Register , Address offset: 0x0014 */
385 __IM uint32_t ADDR; /**< Address Register , Address offset: 0x0018 */
386 __IOM uint32_t START_ADDR; /**< Start Address Register , Address offset: 0x001C */
387 __IOM uint32_t RX_END_ADDR; /**< RX End Address Register , Address offset: 0x0020 */
388 __IOM uint32_t TX_END_ADDR; /**< TX End Address Register , Address offset: 0x0024 */
389 } iso7816_regs_t;
390
391 /**
392 * @brief MCU_SUB
393 */
394 typedef struct _mcu_sub_regs {
395 __IM uint32_t SENSE_ADC_FIFO; /**< MCU_SUB_REG_SENSE_ADC_FIFO, Address offset: 0x000 */
396 __IM uint32_t RESERVED0[63]; /**< RESERVED, Address offset: 0x004 */
397 __IOM uint32_t SENSE_FF_THRESH; /**< MCU_SUB_REG_SENSE_FF_THRESH, Address offset: 0x100 */
398 __IM uint32_t SENSE_ADC_STAT; /**< MCU_SUB_REG_SENSE_ADC_STAT, Address offset: 0x104 */
399 __IM uint32_t RESERVED1[62]; /**< RESERVED, Address offset: 0x108 */
400 __IOM uint32_t COMM_TMR_DEEPSLPSTAT; /**< MCU_SUB_REG_COMM_TMR_DEEPSLPSTAT, Address offset: 0x200 */
401 __IM uint32_t RESERVED2; /**< RESERVED, Address offset: 0x204 */
402 __IOM uint32_t DPAD_RE_N_BUS; /**< MCU_SUB_REG_DPAD_RE_N_BUS, Address offset: 0x208 */
403 __IM uint32_t RESERVED3; /**< RESERVED, Address offset: 0x20C */
404 __IOM uint32_t DPAD_RTYP_BUS; /**< MCU_SUB_REG_DPAD_RTYP_BUS, Address offset: 0x210 */
405 __IM uint32_t RESERVED4; /**< RESERVED, Address offset: 0x214 */
406 __IOM uint32_t DPAD_IE_N_BUS; /**< MCU_SUB_REG_DPAD_IE_N_BUS, Address offset: 0x218 */
407 __IM uint32_t RESERVED5; /**< RESERVED, Address offset: 0x21C */
408 __IOM uint32_t MSIO_REG0; /**< MCU_SUB_REG_MSIO_REG, Address offset: 0x220 */
409 __IOM uint32_t BLE_FERP_CTL; /**< MCU_SUB_REG_BLE_FERP_CTL, Address offset: 0x224 */
410 __IOM uint32_t DMA_ACC_SEL; /**< MCU_SUB_REG_DMA_ACC_SEL, Address offset: 0x228 */
411 __IOM uint32_t SECURITY_RESET; /**< MCU_SUB_REG_SECURITY_RESET, Address offset: 0x22C */
412 __IOM uint32_t PMU_ID; /**< MCU_SUB_REG_PMU_ID, Address offset: 0x230 */
413 __IOM uint32_t PWR_AVG_CTL; /**< MCU_SUB_REG_PWR_AVG_CTL_REG, Address offset: 0x234 */
414 __IOM uint32_t CLK_CAL_CTL[2]; /**< MCU_SUB_REG_CLK_CAL_CTL_REG0~1, Address offset: 0x238 */
415 __IOM uint32_t DPAD_MUX_CTL0_7; /**< MCU_SUB_REG_DPAD_MUX_CTL_00_07, Address offset: 0x240 */
416 __IOM uint32_t DPAD_MUX_CTL8_15; /**< MCU_SUB_REG_DPAD_MUX_CTL_08_15, Address offset: 0x244 */
417 __IOM uint32_t DPAD_MUX_CTL16_23; /**< MCU_SUB_REG_DPAD_MUX_CTL_16_23, Address offset: 0x248 */
418 __IOM uint32_t DPAD_MUX_CTL24_31; /**< MCU_SUB_REG_DPAD_MUX_CTL_24_31, Address offset: 0x24C */
419 __IM uint32_t RESERVED6; /**< RESERVED, Address offset: 0x250 */
420 __IOM uint32_t EFUSE_PWR_DELTA[2]; /**< MCU_SUB_REG_EFUSE_PWR_DELTA0~1, Address offset: 0x254 */
421 __IM uint32_t RESERVED7; /**< RESERVED, Address offset: 0x250 */
422 __IOM uint32_t EFUSE_PWR_CTRL[2]; /**< MCU_SUB_REG_EFUSE_PWR_CTRL0~1, Address offset: 0x260 */
423 __IOM uint32_t I2S_CLK_CFG; /**< MCU_SUB_REG_I2S_CLK_CFG, Address offset: 0x268 */
424 __IM uint32_t RESERVED8[5]; /**< RESERVED, Address offset: 0x26C */
425 __IOM uint32_t MCU_SUB_REG; /**< MCU_SUB_REG_MCU_SUB_REG, Address offset: 0x280 */
426 __IM uint32_t RESERVED9[3]; /**< RESERVED, Address offset: 0x284 */
427 __IOM uint32_t AON_PAD_MUX_CTL; /**< MCU_SUB_REG_AON_PAD_MUX_CTL, Address offset: 0x290 */
428 __IOM uint32_t MSIO_PAD_MUX_CTL; /**< MCU_SUB_REG_MSIO_PAD_MUX_CTL, Address offset: 0x294 */
429 __IM uint32_t RESERVED10[2]; /**< RESERVED, Address offset: 0x298 */
430 __IOM uint32_t MCU_SUBSYS_CG_CTRL[3]; /**< MCU_SUB_REG_MCU_SUBSYS_CG_CTRL0~2, Address offset: 0x2A0 */
431 __IOM uint32_t MCU_PERIPH_CG; /**< MCU_SUB_REG_MCU_PERIPH_CG, Address offset: 0x2AC */
432 __IOM uint32_t MCU_SUBSYS_CLK_CTRL; /**< MCU_SUB_REG_MCU_SUBSYS_CLK_CTRL, Address offset: 0x2B0 */
433 __IM uint32_t RESERVED11[3]; /**< RESERVED, Address offset: 0x2B4 */
434 __IOM uint32_t BLE_DSLEEP_CORR_EN; /**< MCU_SUB_REG_BLE_DSLEEP_CORR_EN, Address offset: 0x2C0 */
435 __IOM uint32_t BLE_DSLEEP_HW_TIM_CORR; /**< MCU_SUB_REG_BLE_DSLEEP_HW_TIM_CORR,Address offset: 0x2C4 */
436 } mcu_sub_regs_t;
437
438 /**
439 * @brief PKC
440 */
441 typedef struct _pkc_regs {
442 __IOM uint32_t CTRL; /**< PKC_REG_CTRL, Address offset: 0x00 */
443 __IOM uint32_t CONFIG0; /**< PKC_REG_CONFIG0, Address offset: 0x04 */
444 __IOM uint32_t CONFIG1; /**< PKC_REG_CONFIG1, Address offset: 0x08 */
445 __IOM uint32_t CONFIG2; /**< PKC_REG_CONFIG2, Address offset: 0x0C */
446 __IOM uint32_t CONFIG3; /**< PKC_REG_CONFIG3, Address offset: 0x10 */
447 __IOM uint32_t CONFIG4; /**< PKC_REG_CONFIG4, Address offset: 0x14 */
448 __IOM uint32_t CONFIG5; /**< PKC_REG_CONFIG5, Address offset: 0x18 */
449 __IOM uint32_t CONFIG6; /**< PKC_REG_CONFIG6, Address offset: 0x1C */
450 __IOM uint32_t CONFIG7; /**< PKC_REG_CONFIG7, Address offset: 0x20 */
451 __IOM uint32_t CONFIG8; /**< PKC_REG_CONFIG8, Address offset: 0x24 */
452 __IOM uint32_t CONFIG9; /**< PKC_REG_CONFIG9, Address offset: 0x28 */
453 __IOM uint32_t CONFIG10; /**< PKC_REG_CONFIG10, Address offset: 0x2C */
454 __IOM uint32_t CONFIG11; /**< PKC_REG_CONFIG11, Address offset: 0x30 */
455 __IOM uint32_t CONFIG12; /**< PKC_REG_CONFIG12, Address offset: 0x34 */
456 __IOM uint32_t CONFIG13; /**< PKC_REG_CONFIG13, Address offset: 0x38 */
457 __IM uint32_t REVERSED0; /**< PKC_REG_REVERSED, Address offset: 0x3C */
458 __IOM uint32_t SW_CTRL; /**< PKC_REG_SW_CTRL, Address offset: 0x40 */
459 __IOM uint32_t SW_CONFIG0; /**< PKC_REG_SW_CONFIG, Address offset: 0x44 */
460 __IOM uint32_t SW_CONFIG1; /**< PKC_REG_SW_CONFIG, Address offset: 0x48 */
461 __IOM uint32_t SW_CONFIG2; /**< PKC_REG_SW_CONFIG, Address offset: 0x4C */
462 __IOM uint32_t SW_CONFIG3; /**< PKC_REG_SW_CONFIG, Address offset: 0x50 */
463 __IOM uint32_t SW_CONFIG4; /**< PKC_REG_SW_CONFIG, Address offset: 0x54 */
464 __IOM uint32_t SW_CONFIG5; /**< PKC_REG_SW_CONFIG, Address offset: 0x58 */
465 __IOM uint32_t SW_CONFIG6; /**< PKC_REG_SW_CONFIG, Address offset: 0x5C */
466 __IOM uint32_t SW_CONFIG7; /**< PKC_REG_SW_CONFIG, Address offset: 0x60 */
467 __IM uint32_t SW_CONFIG8; /**< PKC_REG_SW_CONFIG, Address offset: 0x64 */
468 __IOM uint32_t SW_CONFIG9; /**< PKC_REG_SW_CONFIG, Address offset: 0x68 */
469 __IOM uint32_t SW_CONFIG10; /**< PKC_REG_SW_CONFIG, Address offset: 0x6C */
470 __IOM uint32_t SW_CONFIG11; /**< PKC_REG_SW_CONFIG, Address offset: 0x70 */
471 __IOM uint32_t SW_CONFIG12; /**< PKC_REG_SW_CONFIG, Address offset: 0x74 */
472 __IOM uint32_t SW_CONFIG13; /**< PKC_REG_SW_CONFIG, Address offset: 0x78 */
473 __IM uint32_t REVERSED1; /**< PKC_REG_REVERSED, Address offset: 0x7C */
474 __IOM uint32_t INTSTAT; /**< PKC_REG_INT_STATUS, Address offset: 0x80 */
475 __IOM uint32_t INTEN; /**< PKC_REG_INT_ENABLE, Address offset: 0x84 */
476 __IM uint32_t WORKSTAT; /**< PKC_REG_WORK_STATUS, Address offset: 0x88 */
477 __IM uint32_t REVERSED2; /**< PKC_REG_REVERSED, Address offset: 0x8C */
478 __IOM uint32_t DUMMY0; /**< PKC_REG_DUMMY0, Address offset: 0x90 */
479 __IOM uint32_t DUMMY1; /**< PKC_REG_DUMMY1, Address offset: 0x94 */
480 __IOM uint32_t DUMMY2; /**< PKC_REG_DUMMY2, Address offset: 0x98 */
481 } pkc_regs_t;
482
483 /**
484 * @brief PWM
485 */
486 typedef struct _pwm_regs {
487 __IOM uint32_t MODE; /**< PWM_REG_MODE, Address, offset: 0x00 */
488 __IOM uint32_t UPDATE; /**< PWM_REG_UPDATE, Address, offset: 0x04 */
489 __IOM uint32_t PRD; /**< PWM_REG_PRD, Address, offset: 0x08 */
490 __IOM uint32_t CMPA0; /**< PWM_REG_CMPA0, Address, offset: 0x0C */
491 __IOM uint32_t CMPA1; /**< PWM_REG_CMPA1, Address, offset: 0x10 */
492 __IOM uint32_t CMPB0; /**< PWM_REG_CMPB0, Address, offset: 0x14 */
493 __IOM uint32_t CMPB1; /**< PWM_REG_CMPB1, Address, offset: 0x18 */
494 __IOM uint32_t CMPC0; /**< PWM_REG_CMPC0, Address, offset: 0x1C */
495 __IOM uint32_t CMPC1; /**< PWM_REG_CMPC1, Address, offset: 0x20 */
496 __IOM uint32_t AQCTRL; /**< PWM_REG_AQCTRL, Address, offset: 0x24 */
497 __IOM uint32_t BRPRD; /**< PWM_REG_BRPRD, Address, offset: 0x28 */
498 __IOM uint32_t HOLD; /**< PWM_REG_HOLD, Address, offset: 0x2C */
499 } pwm_regs_t;
500
501 /**
502 * @brief SSI
503 */
504 typedef struct _ssi_regs {
505 __IOM uint32_t CTRL0; /**< SSI_REG_CTRL0, Address offset: 0x00 */
506 __IOM uint32_t CTRL1; /**< SSI_REG_CTRL1, Address offset: 0x04 */
507 __IOM uint32_t SSI_EN; /**< SSI_REG_SSI_EN, Address offset: 0x08 */
508 __IOM uint32_t MWC; /**< SSI_REG_MWC, Address offset: 0x0C */
509 __IOM uint32_t SE; /**< SSI_REG_SE, Address offset: 0x10 */
510 __IOM uint32_t BAUD; /**< SSI_REG_BAUD, Address offset: 0x14 */
511 __IOM uint32_t TX_FTL; /**< SSI_REG_TX_FTL, Address offset: 0x18 */
512 __IOM uint32_t RX_FTL; /**< SSI_REG_RX_FTL, Address offset: 0x1C */
513 __IM uint32_t TX_FL; /**< SSI_REG_TX_FL, Address offset: 0x20 */
514 __IM uint32_t RX_FL; /**< SSI_REG_RX_FL, Address offset: 0x24 */
515 __IM uint32_t STAT; /**< SSI_REG_STAT, Address offset: 0x28 */
516 __IOM uint32_t INTMASK; /**< SSI_REG_INT_MASK, Address offset: 0x2C */
517 __IM uint32_t INTSTAT; /**< SSI_REG_INT_STAT, Address offset: 0x30 */
518 __IM uint32_t RAW_INTSTAT; /**< SSI_REG_RAW_INT_STAT, Address offset: 0x34 */
519 __IM uint32_t TXOIC; /**< SSI_REG_TXOIC, Address offset: 0x38 */
520 __IM uint32_t RXOIC; /**< SSI_REG_RXOIC, Address offset: 0x3C */
521 __IM uint32_t RXUIC; /**< SSI_REG_RXUIC, Address offset: 0x40 */
522 __IM uint32_t MSTIC; /**< SSI_REG_MSTIC, Address offset: 0x44 */
523 __IM uint32_t INTCLR; /**< SSI_REG_INT_CLR, Address offset: 0x48 */
524 __IOM uint32_t DMAC; /**< SSI_REG_DMAC, Address offset: 0x4C */
525 __IOM uint32_t DMA_TDL; /**< SSI_REG_DMA_TDL, Address offset: 0x50 */
526 __IOM uint32_t DMA_RDL; /**< SSI_REG_DMA_RDL, Address offset: 0x54 */
527 __IM uint32_t ID; /**< SSI_REG_ID, Address offset: 0x58 */
528 __IM uint32_t VERSION_ID; /**< SSI_REG_VERSION_ID, Address offset: 0x5C */
529 __IOM uint32_t DATA; /**< SSI_REG_DATA, Address offset: 0x60 */
530 __IM uint32_t REVERSED[35]; /**< SSI_REG_REVERSED, Address offset: 0x64 */
531 __IOM uint32_t RX_SAMPLE_DLY; /**< SSI_REG_RX_SAMPLE_DLY, Address offset: 0xF0 */
532 __IOM uint32_t SPI_CTRL0; /**< SSI_REG_SPI_CTRL0, Address offset: 0xF4 */
533 } ssi_regs_t;
534
535 /**
536 * @brief TIM
537 */
538 typedef struct _timer_regs {
539 __IOM uint32_t CTRL; /**< TIMER control register, Address offset: 0x00 */
540 __IOM uint32_t VALUE; /**< TIMER counter value register, Address offset: 0x04 */
541 __IOM uint32_t RELOAD; /**< TIMER auto-reload register, Address offset: 0x08 */
542 __IOM uint32_t INTSTAT; /**< TIMER interrupt status register, Address offset: 0x0C */
543 } timer_regs_t;
544
545 /**
546 * @brief UART
547 */
548 typedef struct _uart_regs {
549 union {
550 __IOM uint32_t RBR;
551 __IOM uint32_t DLL;
552 __IOM uint32_t THR;
553 } RBR_DLL_THR; /**< UART_REG_RBR_DLL_THR, Address offset: 0x00 */
554 union {
555 __IOM uint32_t DLH;
556 __IOM uint32_t IER;
557 } DLH_IER; /**< UART_REG_DLH_IER, Address offset: 0x04 */
558 union {
559 __IOM uint32_t FCR;
560 __IOM uint32_t IIR;
561 } FCR_IIR; /**< UART_REG_FCR_IIR, Address offset: 0x08 */
562 __IOM uint32_t LCR; /**< UART_REG_LCR, Address offset: 0x0C */
563 __IOM uint32_t MCR; /**< UART_REG_MCR, Address offset: 0x10 */
564 __IOM uint32_t LSR; /**< UART_REG_LSR, Address offset: 0x14 */
565 __IOM uint32_t MSR; /**< UART_REG_MSR, Address offset: 0x18 */
566 __IOM uint32_t SCRATCHPAD; /**< UART_REG_SCRATCHPAD, Address offset: 0x1C */
567 __IOM uint32_t LPDLL; /**< UART_REG_LPDLL, Address offset: 0x20 */
568 __IOM uint32_t LPDLH; /**< UART_REG_LPDLH, Address offset: 0x24 */
569 __IOM uint32_t REVERSED0[2]; /**< REVERSED, Address offset: 0x28 */
570 union {
571 __IOM uint32_t SRBR[16];
572 __IOM uint32_t STHR[16];
573 } SRBR_STHR; /**< UART_REG_SRBR_STHR, Address offset: 0x30 */
574 __IOM uint32_t FAR; /**< UART_REG_FAR, Address offset: 0x70 */
575 __IOM uint32_t TFR; /**< UART_REG_TFR, Address offset: 0x74 */
576 __IOM uint32_t TFW; /**< UART_REG_TFW, Address offset: 0x78 */
577 __IOM uint32_t USR; /**< UART_REG_USR, Address offset: 0x7C */
578 __IOM uint32_t TFL; /**< UART_REG_TFL, Address offset: 0x80 */
579 __IOM uint32_t RFL; /**< UART_REG_RFL, Address offset: 0x84 */
580 __IOM uint32_t SRR; /**< UART_REG_SRR, Address offset: 0x88 */
581 __IOM uint32_t SRTS; /**< UART_REG_SRTS, Address offset: 0x8C */
582 __IOM uint32_t SBCR; /**< UART_REG_SBCR, Address offset: 0x90 */
583 __IOM uint32_t SDMAM; /**< UART_REG_SDMAM, Address offset: 0x94 */
584 __IOM uint32_t SFE; /**< UART_REG_SFE, Address offset: 0x98 */
585 __IOM uint32_t SRT; /**< UART_REG_SRT, Address offset: 0x9C */
586 __IOM uint32_t STET; /**< UART_REG_STET, Address offset: 0xA0 */
587 __IOM uint32_t HTX; /**< UART_REG_HTX, Address offset: 0xA4 */
588 __IOM uint32_t DMASA; /**< UART_REG_DMASA, Address offset: 0xA8 */
589 __IOM uint32_t TCR; /**< UART_REG_TCR, Address offset: 0xAC */
590 __IOM uint32_t DE_EN; /**< UART_REG_DE_EN, Address offset: 0xB0 */
591 __IOM uint32_t RE_EN; /**< UART_REG_RE_EN, Address offset: 0xB4 */
592 __IOM uint32_t DET; /**< UART_REG_DET, Address offset: 0xB8 */
593 __IOM uint32_t TAT; /**< UART_REG_TAT, Address offset: 0xBC */
594 __IOM uint32_t DLF; /**< UART_REG_DLF, Address offset: 0xC0 */
595 __IOM uint32_t RAR; /**< UART_REG_RAR, Address offset: 0xC4 */
596 __IOM uint32_t TAR; /**< UART_REG_TAR, Address offset: 0xC8 */
597 __IOM uint32_t LCR_EXT; /**< UART_REG_LCR_EXT, Address offset: 0xCC */
598 __IOM uint32_t REVERSED1[9]; /**< REVERSED, Address offset: 0xD0 */
599 __IOM uint32_t CPR; /**< UART_REG_CPR, Address offset: 0xF4 */
600 __IOM uint32_t UCV; /**< UART_REG_UCV, Address offset: 0xF8 */
601 __IOM uint32_t CTR; /**< UART_REG_CTR, Address offset: 0xFC */
602 } uart_regs_t;
603
604 /**
605 * @brief WDT
606 */
607 typedef struct _wdt_regs {
608 __IOM uint32_t LOAD; /**< WDT_REG_LOAD, Address offset: 0x000 */
609 __IOM uint32_t VALUE; /**< WDT_REG_VALUE, Address offset: 0x004 */
610 __IOM uint32_t CTRL; /**< WDT_REG_CONTROL, Address offset: 0x008 */
611 __IOM uint32_t INTCLR; /**< WDT_REG_INTCLR, Address offset: 0x00C */
612 __IOM uint32_t RIS; /**< WDT_REG_RIS, Address offset: 0x010 */
613 __IOM uint32_t MIS; /**< WDT_REG_MIS, Address offset: 0x014 */
614 __IOM uint32_t REVERSED[762]; /**< REVERSED, Address offset: 0x018 */
615 __IOM uint32_t LOCK; /**< WDT_REG_LOCK, Address offset: 0xC00 */
616 } wdt_regs_t;
617
618 /**
619 * @brief XQSPI
620 */
621 /* XQSPI/Cache Registers */
622 typedef struct {
623 __IOM uint32_t CTRL0; /**< Cache Control 0 Register, Address offset: 0x00 */
624 __IOM uint32_t CTRL1; /**< Cache Control 1 Register, Address offset: 0x04 */
625 __IM uint32_t HIT_COUNT; /**< Cache hits count, Address offset: 0x08 */
626 __IM uint32_t MISS_COUNT; /**< Cache miss count, Address offset: 0x0C */
627 __IM uint32_t STAT; /**< Status Register, Address offset: 0x10 */
628 __IOM uint32_t BUF_FIRST_ADDR; /**< Preload start address, Address offset: 0x14 */
629 __IOM uint32_t BUF_LAST_ADDR; /**< Preload last address, Address offset: 0x18 */
630 } CACHE_REGS;
631
632 /* XQSPI/QSPI Registers */
633 typedef struct {
634 __OM uint32_t TX_DATA; /**< Serial Data Transmit, Address offset: 0x00 */
635 __IM uint32_t RX_DATA; /**< Serial Data Receive, Address offset: 0x04 */
636 __IM uint32_t RESERVED0; /**< RESERVED, Address offset: 0x08 */
637 __IOM uint32_t CTRL; /**< Control, Address offset: 0x0C */
638 __IOM uint32_t AUX_CTRL; /**< Auxiliary Control, Address offset: 0x10 */
639 __IM uint32_t STAT; /**< Status Control, Address offset: 0x14 */
640 __IOM uint32_t SLAVE_SEL; /**< Slave Select, Address offset: 0x18 */
641 __IOM uint32_t SLAVE_SEL_POL; /**< Slave Select Polarity, Address offset: 0x1C */
642 __IOM uint32_t INTEN; /**< Interrupt Enable, Address offset: 0x20 */
643 __IM uint32_t INTSTAT; /**< Interrupt Status, Address offset: 0x24 */
644 __OM uint32_t INTCLR; /**< Interrupt Clear, Address offset: 0x28 */
645 __IM uint32_t TX_FIFO_LVL; /**< TX FIFO Level, Address offset: 0x2C */
646 __IM uint32_t RX_FIFO_LVL; /**< RX FIFO Level, Address offset: 0x30 */
647 __IM uint32_t RESERVED1; /**< RESERVED, Address offset: 0x34 */
648 __IOM uint32_t MSTR_IT_DELAY; /**< Master Inter-transfer Delay, Address offset: 0x38 */
649 __IOM uint32_t SPIEN; /**< SPI Enable, Address offset: 0x3C */
650 __IOM uint32_t SPI_GP_SET; /**< GPO Set / GPO State, Address offset: 0x40 */
651 __IOM uint32_t SPI_GP_CLEAR; /**< GPO Clear / GPI State, Address offset: 0x44 */
652 __IM uint32_t RX_DATA0_31; /**< 32-bit LSB word(0~31), Address offset: 0x48 */
653 __IM uint32_t RX_DATA32_63; /**< 32-bit LSB word(32~63), Address offset: 0x4C */
654 __IM uint32_t RX_DATA64_95; /**< 32-bit LSB word(64~95), Address offset: 0x50 */
655 __IM uint32_t RX_DATA96_127; /**< 32-bit MSB word(96~127), Address offset: 0x54 */
656 __OM uint32_t P_IV; /**< 32-BIT IV Key, Address offset: 0x58 */
657 __IOM uint32_t FLASH_WRITE; /**< use for flash write, Address offset: 0x5C */
658 __IOM uint32_t P_KEY_VALID_KPORT; /**< Status bit, Address offset: 0x60 */
659 __IOM uint32_t P_RD_KEY_EN_KPORT; /**< Enable read key on keyport, Address offset: 0x64 */
660 __IOM uint32_t P_KEY_ADDR; /**< Present key address, Address offset: 0x68 */
661 __IOM uint32_t P_KEYPORT_MASK; /**< Present key mask, Address offset: 0x6C */
662 __IOM uint32_t BYPASS; /**< Enable Bypass, Address offset: 0x70 */
663 } QSPI_REGS;
664
665 /* XQSPI/XIP Registers */
666 typedef struct {
667 __IOM uint32_t CTRL0; /**< XIP Control 0 Register, Address offset: 0x00 */
668 __IOM uint32_t CTRL1; /**< XIP Control 1 Register, Address offset: 0x04 */
669 __IOM uint32_t CTRL2; /**< XIP Control 2 Register, Address offset: 0x08 */
670 __IOM uint32_t CTRL3; /**< XIP Enable Request, Address offset: 0x0C */
671 __IOM uint32_t STAT; /**< XIP Enable Output (Stat0), Address offset: 0x10 */
672 __IM uint32_t INTEN; /**< Interrupt Enable (Intr0), Address offset: 0x14 */
673 __IM uint32_t INTSTAT; /**< Interrupt Status (Intr1), Address offset: 0x18 */
674 __IM uint32_t INTREQ; /**< Interrupt Status (Intr2), Address offset: 0x1C */
675 __OM uint32_t INTSET; /**< Interrupt Set (Intr3), Address offset: 0x20 */
676 __OM uint32_t INTCLR; /**< Interrupt Clear (Intr4), Address offset: 0x24 */
677 } XIP_REGS;
678
679 typedef struct _xqspi_regs {
680 CACHE_REGS CACHE; /**< CACHE Registers, Address offset: 0x000 */
681 __IM uint32_t RESERVED0[249];
682 QSPI_REGS QSPI; /**< QSPI Registers, Address offset: 0x400 */
683 __IM uint32_t RESERVED1[483];
684 XIP_REGS XIP; /**< XIP Registers, Address offset: 0xC00 */
685 } xqspi_regs_t;
686
687 /**
688 * @brief EFUSE
689 */
690 typedef struct _efuse_regs {
691 __IOM uint32_t TPGM; /**< EFUSE_TPGM, Address offset: 0x000 */
692 __IOM uint32_t PGENB; /**< EFUSE_PGENB, Address offset: 0x004 */
693 __IM uint32_t TEST_MODE; /**< EFUSE_TEST_MODE, Address offset: 0x008 */
694 __OM uint32_t OPERATION; /**< EFUSE_OPERATION, Address offset: 0x00C */
695 __IM uint32_t STAT; /**< EFUSE_STATUS, Address offset: 0x010 */
696 __IOM uint32_t KEY_MASK; /**< EFUSE_KEY_MASK, Address offset: 0x014 */
697 __IOM uint32_t CRC_ADDR; /**< EFUSE_CRC_START_ADDR, Address offset: 0x018 */
698 __IM uint32_t CRC_OUTPUT; /**< EFUSE_CRC_OUTPUT, Address offset: 0x01C */
699 __IOM uint32_t TRIM_ADDR; /**< EFUSE_TRIM_ADDR, Address offset: 0x020 */
700 __IOM uint32_t TRIM_LEN; /**< EFUSE_TRIM_LEN, Address offset: 0x024 */
701 __IM uint32_t TRIM[14]; /**< EFUSE_TRIM, Address offset: 0x028 */
702 } efuse_regs_t;
703
704 /**
705 * @brief RNG
706 */
707 typedef struct _rng_regs {
708 __IOM uint32_t CTRL; /**< RNG_CTRL, Address offset: 0x000 */
709 __IOM uint32_t STATUS; /**< RNG_STATUS, Address offset: 0x004 */
710 __IM uint32_t DATA; /**< RNG_DATA, Address offset: 0x008 */
711 __IOM uint32_t RESERVED; /**< RESERVED, Address offset: 0x00C */
712 __IM uint32_t LR_STATUS; /**< RNG_LR_STATUS, Address offset: 0x010 */
713 __IOM uint32_t CONFIG; /**< RNG_CONFIG, Address offset: 0x014 */
714 __IOM uint32_t TSCON; /**< RNG_TSCON, Address offset: 0x018 */
715 __IOM uint32_t FROCFG; /**< RNG_FROCFG, Address offset: 0x01C */
716 __OM uint32_t USER_SEED; /**< RNG_USER_SEED, Address offset: 0x020 */
717 __IOM uint32_t LRCON; /**< RNG_LRCON, Address offset: 0x024 */
718 } rng_regs_t;
719
720 /** @} */ /* End of group Peripheral_registers_structures */
721
722
723 /* ==================================== End of section using anonymous unions ==================================== */
724 #if defined (__CC_ARM)
725 #pragma pop
726 #elif defined (__ICCARM__)
727 /* leave anonymous unions enabled */
728 #elif (__ARMCC_VERSION >= 6010050)
729 #pragma clang diagnostic pop
730 #elif defined (__GNUC__)
731 /* anonymous unions are enabled by default */
732 #elif defined (__TMS470__)
733 /* anonymous unions are enabled by default */
734 #elif defined (__TASKING__)
735 #pragma warning restore
736 #elif defined (__CSMC__)
737 /* anonymous unions are enabled by default */
738 #else
739 #warning Not supported compiler type
740 #endif
741
742
743 /* ================================================================================================================= */
744 /* ================ Device Specific Peripheral Address Map ================ */
745 /* ================================================================================================================= */
746
747 /** @addtogroup Peripheral_memory_map
748 * @{
749 */
750
751 #define ROM_BASE ((uint32_t)0x00000000UL)
752 #define FLASH_BASE ((uint32_t)0x01000000UL)
753 #define SRAM_BASE ((uint32_t)0x30000000UL)
754 #define PERIPH_BASE ((uint32_t)0xA0000000UL)
755
756 #define TIMER0_BASE (PERIPH_BASE + 0x00000000UL)
757 #define TIMER1_BASE (PERIPH_BASE + 0x00001000UL)
758 #define DUAL_TIMER0_BASE (PERIPH_BASE + 0x00002000UL)
759 #define DUAL_TIMER1_BASE (PERIPH_BASE + 0x00002020UL)
760 #define WDT_BASE (PERIPH_BASE + 0x00008000UL)
761 #define SPIM_BASE (PERIPH_BASE + 0x0000C000UL)
762 #define SPIS_BASE (PERIPH_BASE + 0x0000C100UL)
763 #define QSPI0_BASE (PERIPH_BASE + 0x0000C200UL)
764 #define I2C0_BASE (PERIPH_BASE + 0x0000C300UL)
765 #define I2C1_BASE (PERIPH_BASE + 0x0000C400UL)
766 #define AON_BASE (PERIPH_BASE + 0x0000C500UL)
767 #define UART0_BASE (PERIPH_BASE + 0x0000C600UL)
768 #define UART1_BASE (PERIPH_BASE + 0x0000C700UL)
769 #define QSPI1_BASE (PERIPH_BASE + 0x0000C800UL)
770 #define PWM0_BASE (PERIPH_BASE + 0x0000C900UL)
771 #define I2S_M_BASE (PERIPH_BASE + 0x0000CA00UL)
772 #define PWM1_BASE (PERIPH_BASE + 0x0000CC00UL)
773 #define XQSPI_BASE (PERIPH_BASE + 0x0000D000UL)
774 #define MCU_SUB_BASE (PERIPH_BASE + 0x0000E000UL)
775 #define I2S_S_BASE (PERIPH_BASE + 0x0000F000UL)
776 #define ISO7816_BASE (PERIPH_BASE + 0x0000F200UL)
777 #define GPIO0_BASE (PERIPH_BASE + 0x00010000UL)
778 #define GPIO1_BASE (PERIPH_BASE + 0x00011000UL)
779 #define GPIO2_BASE (PERIPH_BASE + 0x00012000UL)
780 #define DMA_BASE (PERIPH_BASE + 0x00013000UL)
781 #define PKC_BASE (PERIPH_BASE + 0x00014000UL)
782 #define AES_BASE (PERIPH_BASE + 0x00015400UL)
783 #define HMAC_BASE (PERIPH_BASE + 0x00015800UL)
784 #define EFUSE_BASE (PERIPH_BASE + 0x00016400UL)
785 #define RNG_BASE (PERIPH_BASE + 0x00017800UL)
786
787 #define PKC_SPRAM_BASE (PKC_BASE + 0x00000800UL)
788 #define KRAM_BASE (PERIPH_BASE + 0x00017000UL)
789 #define EFUSE_STORAGE_BASE (PERIPH_BASE + 0x00016000UL)
790
791 /** @} */ /* End of group Peripheral_memory_map */
792
793
794 /* ================================================================================================================= */
795 /* ================ Peripheral declaration ================ */
796 /* ================================================================================================================= */
797
798 /** @addtogroup Peripheral_declaration
799 * @{
800 */
801
802 #define TIMER0 ((timer_regs_t *)TIMER0_BASE)
803 #define TIMER1 ((timer_regs_t *)TIMER1_BASE)
804 #define DUAL_TIMER0 ((dual_timer_regs_t *)DUAL_TIMER0_BASE)
805 #define DUAL_TIMER1 ((dual_timer_regs_t *)DUAL_TIMER1_BASE)
806 #define WDT ((wdt_regs_t *)WDT_BASE)
807 #define SPIM ((ssi_regs_t *)SPIM_BASE)
808 #define SPIS ((ssi_regs_t *)SPIS_BASE)
809 #define QSPI0 ((ssi_regs_t *)QSPI0_BASE)
810 #define QSPI1 ((ssi_regs_t *)QSPI1_BASE)
811 #define I2C0 ((i2c_regs_t *)I2C0_BASE)
812 #define I2C1 ((i2c_regs_t *)I2C1_BASE)
813 #define AON ((aon_regs_t *)AON_BASE)
814 #define UART0 ((uart_regs_t *)UART0_BASE)
815 #define UART1 ((uart_regs_t *)UART1_BASE)
816 #define PWM0 ((pwm_regs_t *)PWM0_BASE)
817 #define PWM1 ((pwm_regs_t *)PWM1_BASE)
818 #define I2S_M ((i2s_regs_t *)I2S_M_BASE)
819 #define I2S_S ((i2s_regs_t *)I2S_S_BASE)
820 #define ISO7816 ((iso7816_regs_t *)ISO7816_BASE)
821 #define XQSPI ((xqspi_regs_t *)XQSPI_BASE)
822 #define MCU_SUB ((mcu_sub_regs_t *)MCU_SUB_BASE)
823 #define GPIO0 ((gpio_regs_t *)GPIO0_BASE)
824 #define GPIO1 ((gpio_regs_t *)GPIO1_BASE)
825 #define GPIO2 ((gpio_regs_t *)GPIO2_BASE)
826 #define DMA ((dma_regs_t *)DMA_BASE)
827 #define PKC ((pkc_regs_t *)PKC_BASE)
828 #define AES ((aes_regs_t *)AES_BASE)
829 #define HMAC ((hmac_regs_t *)HMAC_BASE)
830 #define EFUSE ((efuse_regs_t *)EFUSE_BASE)
831 #define RNG ((rng_regs_t *)RNG_BASE)
832
833 /** @} */ /* End of group Peripheral_declaration */
834
835 /** @addtogroup Peripheral_Registers_Bits_Definition
836 * @{
837 */
838
839 /* ================================================================================================================= */
840 /* ================ AES ================ */
841 /* ================================================================================================================= */
842
843 /******************* Bit definition for AES_CTRL register *******************/
844 #define AES_CTRL_ENABLE_Pos (0U)
845 #define AES_CTRL_ENABLE_Len (1U)
846 #define AES_CTRL_ENABLE_Msk (1U << AES_CTRL_ENABLE_Pos)
847 #define AES_CTRL_ENABLE AES_CTRL_ENABLE_Msk
848
849 #define AES_CTRL_START_NORMAL_Pos (1U)
850 #define AES_CTRL_START_NORMAL_Len (1U)
851 #define AES_CTRL_START_NORMAL_Msk (1U << AES_CTRL_START_NORMAL_Pos)
852 #define AES_CTRL_START_NORMAL AES_CTRL_START_NORMAL_Msk
853
854 #define AES_CTRL_START_DMA_Pos (2U)
855 #define AES_CTRL_START_DMA_Len (1U)
856 #define AES_CTRL_START_DMA_Msk (1U << AES_CTRL_START_DMA_Pos)
857 #define AES_CTRL_START_DMA AES_CTRL_START_DMA_Msk
858
859 #define AES_CTRL_ENABLE_RKEY_Pos (3U)
860 #define AES_CTRL_ENABLE_RKEY_Len (1U)
861 #define AES_CTRL_ENABLE_RKEY_Msk (1U << AES_CTRL_ENABLE_RKEY_Pos)
862 #define AES_CTRL_ENABLE_RKEY AES_CTRL_ENABLE_RKEY_Msk
863
864 /******************* Bit definition for AES_CONFIG register *******************/
865 #define AES_CONFIG_KEYMODE_Pos (0U)
866 #define AES_CONFIG_KEYMODE_Len (2U)
867 #define AES_CONFIG_KEYMODE_Msk (3U << AES_CONFIG_KEYMODE_Pos)
868 #define AES_CONFIG_KEYMODE AES_CONFIG_KEYMODE_Msk
869
870 #define AES_CONFIG_ENABLE_FULLMASK_Pos (3U)
871 #define AES_CONFIG_ENABLE_FULLMASK_Len (1U)
872 #define AES_CONFIG_ENABLE_FULLMASK_Msk (1U << AES_CONFIG_ENABLE_FULLMASK_Pos)
873 #define AES_CONFIG_ENABLE_FULLMASK AES_CONFIG_ENABLE_FULLMASK_Msk
874
875 #define AES_CONFIG_ENABLE_ENCRYPTION_Pos (4U)
876 #define AES_CONFIG_ENABLE_ENCRYPTION_Len (1U)
877 #define AES_CONFIG_ENABLE_ENCRYPTION_Msk (1U << AES_CONFIG_ENABLE_ENCRYPTION_Pos)
878 #define AES_CONFIG_ENABLE_ENCRYPTION AES_CONFIG_ENABLE_ENCRYPTION_Msk
879
880 #define AES_CONFIG_LOADSEED_Pos (5U)
881 #define AES_CONFIG_LOADSEED_Len (1U)
882 #define AES_CONFIG_LOADSEED_Msk (1U << AES_CONFIG_LOADSEED_Pos)
883 #define AES_CONFIG_LOADSEED AES_CONFIG_LOADSEED_Msk
884
885 #define AES_CONFIG_FIRSTBLOCK_Pos (6U)
886 #define AES_CONFIG_FIRSTBLOCK_Len (1U)
887 #define AES_CONFIG_FIRSTBLOCK_Msk (1U << AES_CONFIG_FIRSTBLOCK_Pos)
888 #define AES_CONFIG_FIRSTBLOCK AES_CONFIG_FIRSTBLOCK_Msk
889
890 #define AES_CONFIG_ENDIAN_Pos (7U)
891 #define AES_CONFIG_ENDIAN_Len (1U)
892 #define AES_CONFIG_ENDIAN_Msk (1U << AES_CONFIG_ENDIAN_Pos)
893 #define AES_CONFIG_ENDIAN AES_CONFIG_ENDIAN_Msk
894
895 #define AES_CONFIG_OPMODE_Pos (8U)
896 #define AES_CONFIG_OPMODE_Len (3U)
897 #define AES_CONFIG_OPMODE_Msk (7U << AES_CONFIG_OPMODE_Pos)
898 #define AES_CONFIG_OPMODE AES_CONFIG_OPMODE_Msk
899
900 #define AES_CONFIG_KEYTYPE_Pos (11U)
901 #define AES_CONFIG_KEYTYPE_Len (2U)
902 #define AES_CONFIG_KEYTYPE_Msk (3U << AES_CONFIG_KEYTYPE_Pos)
903 #define AES_CONFIG_KEYTYPE AES_CONFIG_KEYTYPE_Msk
904
905 /******************* Bit definition for AES_STATUS register *******************/
906 #define AES_STATUS_READY_Pos (0U)
907 #define AES_STATUS_READY_Len (1U)
908 #define AES_STATUS_READY_Msk (1U << AES_STATUS_READY_Pos)
909 #define AES_STATUS_READY AES_STATUS_READY_Msk
910
911 #define AES_STATUS_TRANSDONE_Pos (1U)
912 #define AES_STATUS_TRANSDONE_Len (1U)
913 #define AES_STATUS_TRANSDONE_Msk (1U << AES_STATUS_TRANSDONE_Pos)
914 #define AES_STATUS_TRANSDONE AES_STATUS_TRANSDONE_Msk
915
916 #define AES_STATUS_TRANSERR_Pos (2U)
917 #define AES_STATUS_TRANSERR_Len (1U)
918 #define AES_STATUS_TRANSERR_Msk (1U << AES_STATUS_TRANSERR_Pos)
919 #define AES_STATUS_TRANSERR AES_STATUS_TRANSERR_Msk
920
921 #define AES_STATUS_KEYVALID_Pos (3U)
922 #define AES_STATUS_KEYVALID_Len (1U)
923 #define AES_STATUS_KEYVALID_Msk (1U << AES_STATUS_KEYVALID_Pos)
924 #define AES_STATUS_KEYVALID AES_STATUS_KEYVALID_Msk
925
926 /******************* Bit definition for AES_INTERRUPT register *******************/
927 #define AES_INTERRUPT_DONE_Pos (0U)
928 #define AES_INTERRUPT_DONE_Len (1U)
929 #define AES_INTERRUPT_DONE_Msk (1U << AES_INTERRUPT_DONE_Pos)
930 #define AES_INTERRUPT_DONE AES_INTERRUPT_DONE_Msk
931
932 #define AES_INTERRUPT_ENABLE_Pos (1U)
933 #define AES_INTERRUPT_ENABLE_Len (1U)
934 #define AES_INTERRUPT_ENABLE_Msk (1U << AES_INTERRUPT_ENABLE_Pos)
935 #define AES_INTERRUPT_ENABLE AES_INTERRUPT_ENABLE_Msk
936
937 /******************* Bit definition for AES_TRAN_SIZE register *******************/
938 #define AES_TRAN_SIZE_Pos (0U)
939 #define AES_TRAN_SIZE_Len (15U)
940 #define AES_TRAN_SIZE_Msk (0x00007FFFU)
941 #define AES_TRAN_SIZE AES_TRAN_SIZE_Msk
942
943 /******************* Bit definition for AES_RSTART_ADDR register *******************/
944 #define AES_RSTART_ADDR_Pos (0U)
945 #define AES_RSTART_ADDR_Len (32U)
946 #define AES_RSTART_ADDR_Msk (0xFFFFFFFFU)
947 #define AES_RSTART_ADDR AES_RSTART_ADDR_Msk
948
949 /******************* Bit definition for AES_WSTART_ADDR register *******************/
950 #define AES_WSTART_ADDR_Pos (0U)
951 #define AES_WSTART_ADDR_Len (32U)
952 #define AES_WSTART_ADDR_Msk (0xFFFFFFFFU)
953 #define AES_WSTART_ADDR AES_WSTART_ADDR_Msk
954
955 /******************* Bit definition for AES_KEY_ADDR register *******************/
956 #define AES_KEY_ADDR_Pos (0U)
957 #define AES_KEY_ADDR_Len (32U)
958 #define AES_KEY_ADDR_Msk (0xFFFFFFFFU)
959 #define AES_KEY_ADDR AES_KEY_ADDR_Msk
960
961 /******************* Bit definition for AES_DATA_OUT register *******************/
962 #define AES_DATA_OUT_Pos (0U)
963 #define AES_DATA_OUT_Len (32U)
964 #define AES_DATA_OUT_Msk (0xFFFFFFFFU)
965 #define AES_DATA_OUT AES_DATA_OUT_Msk
966
967 /******************* Bit definition for AES_KEY register *******************/
968 #define AES_KEY_Pos (0U)
969 #define AES_KEY_Len (32U)
970 #define AES_KEY_Msk (0xFFFFFFFFU)
971 #define AES_KEY AES_KEY_Msk
972
973 /******************* Bit definition for AES_SEED_IN register *******************/
974 #define AES_SEED_IN_Pos (0U)
975 #define AES_SEED_IN_Len (32U)
976 #define AES_SEED_IN_Msk (0xFFFFFFFFU)
977 #define AES_SEED_IN AES_SEED_IN_Msk
978
979 /******************* Bit definition for AES_SEED_OUT register *******************/
980 #define AES_SEED_OUT_Pos (0U)
981 #define AES_SEED_OUT_Len (32U)
982 #define AES_SEED_OUT_Msk (0xFFFFFFFFU)
983 #define AES_SEED_OUT AES_SEED_OUT_Msk
984
985 /******************* Bit definition for AES_SEED_IMASK register *******************/
986 #define AES_SEED_IMASK_Pos (0U)
987 #define AES_SEED_IMASK_Len (32U)
988 #define AES_SEED_IMASK_Msk (0xFFFFFFFFU)
989 #define AES_SEED_IMASK AES_SEED_IMASK_Msk
990
991 /******************* Bit definition for AES_SEED_OSBOX register *******************/
992 #define AES_SEED_OSBOX_Pos (0U)
993 #define AES_SEED_OSBOX_Len (32U)
994 #define AES_SEED_OSBOX_Msk (0xFFFFFFFFU)
995 #define AES_SEED_OSBOX AES_SEED_OSBOX_Msk
996
997 /******************* Bit definition for AES_VECTOR_INIT register *******************/
998 #define AES_VECTOR_INIT_Pos (0U)
999 #define AES_VECTOR_INIT_Len (32U)
1000 #define AES_VECTOR_INIT_Msk (0xFFFFFFFFU)
1001 #define AES_VECTOR_INIT AES_VECTOR_INIT_Msk
1002
1003 /******************* Bit definition for AES_DATA_IN register *******************/
1004 #define AES_DATA_IN_Pos (0U)
1005 #define AES_DATA_IN_Len (32U)
1006 #define AES_DATA_IN_Msk (0xFFFFFFFFU)
1007 #define AES_DATA_IN AES_DATA_IN_Msk
1008
1009
1010 /* ================================================================================================================= */
1011 /* ================ AON ================ */
1012 /* ================================================================================================================= */
1013 /******************* Bit definition for AON_REG_PWR_RET01 register **********/
1014 #define AON_PWR_REG01_WAKE_UP_SEL_Pos (24U)
1015 #define AON_PWR_REG01_WAKE_UP_SEL_Len (6U)
1016 #define AON_PWR_REG01_WAKE_UP_SEL_Msk (0x3FU << AON_PWR_REG01_WAKE_UP_SEL_Pos)
1017 #define AON_PWR_REG01_WAKE_UP_SEL AON_PWR_REG01_WAKE_UP_SEL_Msk
1018 #define AON_PWR_REG01_WAKE_UP_SEL_TIMER (0x1U << AON_PWR_REG01_WAKE_UP_SEL_Pos)
1019 #define AON_PWR_REG01_WAKE_UP_SEL_EXTWKUP (0x2U << AON_PWR_REG01_WAKE_UP_SEL_Pos)
1020 #define AON_PWR_REG01_WAKE_UP_SEL_BLE (0x4U << AON_PWR_REG01_WAKE_UP_SEL_Pos)
1021 #define AON_PWR_REG01_WAKE_UP_SEL_CALENDAR (0x8U << AON_PWR_REG01_WAKE_UP_SEL_Pos)
1022 #define AON_PWR_REG01_WAKE_UP_SEL_PMU_BOD_FEDGE (0x10U << AON_PWR_REG01_WAKE_UP_SEL_Pos)
1023 #define AON_PWR_REG01_WAKE_UP_SEL_MSIO_COMP (0x20U << AON_PWR_REG01_WAKE_UP_SEL_Pos)
1024
1025 #define AON_PWR_REG01_SMC_WAKEUP_REQ_Pos (22U)
1026 #define AON_PWR_REG01_SMC_WAKEUP_REQ_Len (1U)
1027 #define AON_PWR_REG01_SMC_WAKEUP_REQ_Msk (0x1U << AON_PWR_REG01_SMC_WAKEUP_REQ_Pos)
1028 #define AON_PWR_REG01_SMC_WAKEUP_REQ AON_PWR_REG01_SMC_WAKEUP_REQ_Msk
1029
1030 #define AON_PWR_REG01_XF_TAG_RET_Pos (21U)
1031 #define AON_PWR_REG01_XF_TAG_RET_Len (1U)
1032 #define AON_PWR_REG01_XF_TAG_RET_Msk (0x1U << AON_PWR_REG01_XF_TAG_RET_Pos)
1033 #define AON_PWR_REG01_XF_TAG_RET AON_PWR_REG01_XF_TAG_RET_Msk
1034
1035 #define AON_PWR_REG01_XF_SCK_CLK_SEL_Pos (18U)
1036 #define AON_PWR_REG01_XF_SCK_CLK_SEL_Len (3U)
1037 #define AON_PWR_REG01_XF_SCK_CLK_SEL_Msk (0x7U << AON_PWR_REG01_XF_SCK_CLK_SEL_Pos)
1038 #define AON_PWR_REG01_XF_SCK_CLK_SEL AON_PWR_REG01_XF_SCK_CLK_SEL_Msk
1039
1040 #define AON_PWR_REG01_SWD_ENABLE_Pos (17U)
1041 #define AON_PWR_REG01_SWD_ENABLE_Len (1U)
1042 #define AON_PWR_REG01_SWD_ENABLE_Msk (0x7U << AON_PWR_REG01_SWD_ENABLE_Pos)
1043 #define AON_PWR_REG01_SWD_ENABLE AON_PWR_REG01_SWD_ENABLE_Msk
1044
1045 #define AON_PWR_REG01_BM_REMAP_Pos (13U)
1046 #define AON_PWR_REG01_BM_REMAP_Len (4U)
1047 #define AON_PWR_REG01_BM_REMAP_Msk (0xFU << AON_PWR_REG01_BM_REMAP_Pos)
1048 #define AON_PWR_REG01_BM_REMAP AON_PWR_REG01_BM_REMAP_Msk
1049
1050 #define AON_PWR_REG01_COMM_CORE_RST_N_Pos (12U)
1051 #define AON_PWR_REG01_COMM_CORE_RST_N_Len (1U)
1052 #define AON_PWR_REG01_COMM_CORE_RST_N_Msk (0x1U << AON_PWR_REG01_COMM_CORE_RST_N_Pos)
1053 #define AON_PWR_REG01_COMM_CORE_RST_N AON_PWR_REG01_COMM_CORE_RST_N_Msk
1054
1055 #define AON_PWR_REG01_COMM_TIMER_RST_N_Pos (11U)
1056 #define AON_PWR_REG01_COMM_TIMER_RST_N_Len (1U)
1057 #define AON_PWR_REG01_COMM_TIMER_RST_N_Msk (0x1U << AON_PWR_REG01_COMM_TIMER_RST_N_Pos)
1058 #define AON_PWR_REG01_COMM_TIMER_RST_N AON_PWR_REG01_COMM_TIMER_RST_N_Msk
1059
1060 #define AON_PWR_REG01_ISO_EN_PD_COMM_TIMER_Pos (9U)
1061 #define AON_PWR_REG01_ISO_EN_PD_COMM_TIMER_Len (1U)
1062 #define AON_PWR_REG01_ISO_EN_PD_COMM_TIMER_Msk (0x1U << AON_PWR_REG01_ISO_EN_PD_COMM_TIMER_Pos)
1063 #define AON_PWR_REG01_ISO_EN_PD_COMM_TIMER AON_PWR_REG01_ISO_EN_PD_COMM_TIMER_Msk
1064
1065 #define AON_PWR_REG01_ISO_EN_PD_COMM_CORE_Pos (8U)
1066 #define AON_PWR_REG01_ISO_EN_PD_COMM_CORE_Len (1U)
1067 #define AON_PWR_REG01_ISO_EN_PD_COMM_CORE_Msk (0x1U << AON_PWR_REG01_ISO_EN_PD_COMM_CORE_Pos)
1068 #define AON_PWR_REG01_ISO_EN_PD_COMM_CORE AON_PWR_REG01_ISO_EN_PD_COMM_CORE_Msk
1069
1070 #define AON_PWR_REG01_PWR_EN_PD_COMM_TIMER_Pos (7U)
1071 #define AON_PWR_REG01_PWR_EN_PD_COMM_TIMER_Len (1U)
1072 #define AON_PWR_REG01_PWR_EN_PD_COMM_TIMER_Msk (0x1U << AON_PWR_REG01_PWR_EN_PD_COMM_TIMER_Pos)
1073 #define AON_PWR_REG01_PWR_EN_PD_COMM_TIMER AON_PWR_REG01_PWR_EN_PD_COMM_TIMER_Msk
1074
1075 #define AON_PWR_REG01_PWR_EN_PD_COMM_CORE_Pos (6U)
1076 #define AON_PWR_REG01_PWR_EN_PD_COMM_CORE_Len (1U)
1077 #define AON_PWR_REG01_PWR_EN_PD_COMM_CORE_Msk (0x1U << AON_PWR_REG01_PWR_EN_PD_COMM_CORE_Pos)
1078 #define AON_PWR_REG01_PWR_EN_PD_COMM_CORE AON_PWR_REG01_PWR_EN_PD_COMM_CORE_Msk
1079
1080 #define AON_PWR_REG01_EFLASH_PAD_EN_Pos (5U)
1081 #define AON_PWR_REG01_EFLASH_PAD_EN_Len (1U)
1082 #define AON_PWR_REG01_EFLASH_PAD_EN_Msk (0x1U << AON_PWR_REG01_EFLASH_PAD_EN_Pos)
1083 #define AON_PWR_REG01_EFLASH_PAD_EN AON_PWR_REG01_EFLASH_PAD_EN_Msk
1084
1085 #define AON_PWR_REG01_XO_2MHZ_ENA_Pos (4U)
1086 #define AON_PWR_REG01_XO_2MHZ_ENA_Len (1U)
1087 #define AON_PWR_REG01_XO_2MHZ_ENA_Msk (0x1U << AON_PWR_REG01_XO_2MHZ_ENA_Pos)
1088 #define AON_PWR_REG01_XO_2MHZ_ENA AON_PWR_REG01_XO_2MHZ_ENA_Msk
1089
1090 #define AON_PWR_REG01_XF_XO_DIV1_Pos (3U)
1091 #define AON_PWR_REG01_XF_XO_DIV1_Len (1U)
1092 #define AON_PWR_REG01_XF_XO_DIV1_Msk (0x1U << AON_PWR_REG01_XF_XO_DIV1_Pos)
1093 #define AON_PWR_REG01_XF_XO_DIV1 AON_PWR_REG01_XF_XO_DIV1_Msk
1094
1095 #define AON_PWR_REG01_SYS_CLK_SEL_Pos (0U)
1096 #define AON_PWR_REG01_SYS_CLK_SEL_Len (3U)
1097 #define AON_PWR_REG01_SYS_CLK_SEL_Msk (0x7U << AON_PWR_REG01_SYS_CLK_SEL_Pos)
1098 #define AON_PWR_REG01_SYS_CLK_SEL AON_PWR_REG01_SYS_CLK_SEL_Msk
1099
1100 /******************* Bit definition for AON_REG_SNSADC_CFG register **********/
1101 #define AON_SNSADC_CFG_SNSADC_REG4_Pos (24U)
1102 #define AON_SNSADC_CFG_SNSADC_REG4_Len (8U)
1103 #define AON_SNSADC_CFG_SNSADC_REG4_Msk (0xFFU << AON_SNSADC_CFG_SNSADC_REG4_Pos)
1104 #define AON_SNSADC_CFG_SNSADC_REG4 AON_SNSADC_CFG_SNSADC_REG4_Msk
1105 #define AON_SNSADC_CFG_MAS_RST_Pos (31U)
1106 #define AON_SNSADC_CFG_MAS_RST_Msk (0x1U << AON_SNSADC_CFG_MAS_RST_Pos)
1107 #define AON_SNSADC_CFG_EN_Pos (30U)
1108 #define AON_SNSADC_CFG_EN_Msk (0x1U << AON_SNSADC_CFG_EN_Pos)
1109 #define AON_SNSADC_CFG_REF_SEL_Pos (27U)
1110 #define AON_SNSADC_CFG_REF_SEL_Msk (0x7U << AON_SNSADC_CFG_REF_SEL_Pos)
1111 #define AON_SNSADC_CFG_REF_HP_Pos (24U)
1112 #define AON_SNSADC_CFG_REF_HP_Msk (0x7U << AON_SNSADC_CFG_REF_HP_Pos)
1113
1114 #define AON_SNSADC_CFG_SNSADC_REG3_Pos (16U)
1115 #define AON_SNSADC_CFG_SNSADC_REG3_Len (8U)
1116 #define AON_SNSADC_CFG_SNSADC_REG3_Msk (0xFFU << AON_SNSADC_CFG_SNSADC_REG3_Pos)
1117 #define AON_SNSADC_CFG_SNSADC_REG3 AON_SNSADC_CFG_SNSADC_REG3_Msk
1118 #define AON_SNSADC_CFG_CHN_P_Pos (19U)
1119 #define AON_SNSADC_CFG_CHN_P_Msk (0x7U << AON_SNSADC_CFG_CHN_P_Pos)
1120 #define AON_SNSADC_CFG_CHN_N_Pos (16U)
1121 #define AON_SNSADC_CFG_CHN_N_Msk (0x7U << AON_SNSADC_CFG_CHN_N_Pos)
1122
1123 #define AON_SNSADC_CFG_SNSADC_REG2_Pos (8U)
1124 #define AON_SNSADC_CFG_SNSADC_REG2_Len (8U)
1125 #define AON_SNSADC_CFG_SNSADC_REG2_Msk (0xFFU << AON_SNSADC_CFG_SNSADC_REG2_Pos)
1126 #define AON_SNSADC_CFG_SNSADC_REG2 AON_SNSADC_CFG_SNSADC_REG2_Msk
1127 #define AON_SNSADC_CFG_TEMP_EN_Pos (15U)
1128 #define AON_SNSADC_CFG_TEMP_EN_Msk (0x1U << AON_SNSADC_CFG_TEMP_EN_Pos)
1129 #define AON_SNSADC_CFG_VBAT_EN_Pos (14U)
1130 #define AON_SNSADC_CFG_VBAT_EN_Msk (0x1U << AON_SNSADC_CFG_VBAT_EN_Pos)
1131 #define AON_SNSADC_CFG_SINGLE_EN_Pos (13U)
1132 #define AON_SNSADC_CFG_SINGLE_EN_Msk (0x1U << AON_SNSADC_CFG_SINGLE_EN_Pos)
1133 #define AON_SNSADC_CFG_OFS_CAL_EN_Pos (12U)
1134 #define AON_SNSADC_CFG_OFS_CAL_EN_Msk (0x1U << AON_SNSADC_CFG_OFS_CAL_EN_Pos)
1135 #define AON_SNSADC_CFG_DYMAMIC_Pos (8U)
1136 #define AON_SNSADC_CFG_DYMAMIC_Msk (0x7U << AON_SNSADC_CFG_DYMAMIC_Pos)
1137
1138 #define AON_SNSADC_CFG_SNSADC_REG1_Pos (0U)
1139 #define AON_SNSADC_CFG_SNSADC_REG1_Len (8U)
1140 #define AON_SNSADC_CFG_SNSADC_REG1_Msk (0xFFU << AON_SNSADC_CFG_SNSADC_REG1_Pos)
1141 #define AON_SNSADC_CFG_SNSADC_REG1 AON_SNSADC_CFG_SNSADC_REG1_Msk
1142 #define AON_SNSADC_CFG_REF_VALUE_Pos (0U)
1143 #define AON_SNSADC_CFG_REF_VALUE_Msk (0xFU << AON_SNSADC_CFG_REF_VALUE_Pos)
1144
1145 /******************* Bit definition for AON_REG_RF_REG_0 register **********/
1146 #define AON_RF_REG_0_IO_LDO_REG1_Pos (24U)
1147 #define AON_RF_REG_0_IO_LDO_REG1_Len (8U)
1148 #define AON_RF_REG_0_IO_LDO_REG1_Msk (0xFFU << AON_RF_REG_0_IO_LDO_REG1_Pos)
1149 #define AON_RF_REG_0_IO_LDO_REG1 AON_RF_REG_0_IO_LDO_REG1_Msk
1150
1151 #define AON_RF_REG_0_LPD_REG2_Pos (16U)
1152 #define AON_RF_REG_0_LPD_REG2_Len (8U)
1153 #define AON_RF_REG_0_LPD_REG2_Msk (0xFFU << AON_RF_REG_0_LPD_REG2_Pos)
1154 #define AON_RF_REG_0_LPD_REG2 AON_RF_REG_0_LPD_REG2_Msk
1155
1156 #define AON_RF_REG_0_LPD_REG1_Pos (8U)
1157 #define AON_RF_REG_0_LPD_REG1_Len (8U)
1158 #define AON_RF_REG_0_LPD_REG1_Msk (0xFFU << AON_RF_REG_0_LPD_REG1_Pos)
1159 #define AON_RF_REG_0_LPD_REG1 AON_RF_REG_0_LPD_REG1_Msk
1160
1161 #define AON_RF_REG_0_RTC_REG1_Pos (0U)
1162 #define AON_RF_REG_0_RTC_REG1_Len (8U)
1163 #define AON_RF_REG_0_RTC_REG1_Msk (0xFFU << AON_RF_REG_0_RTC_REG1_Pos)
1164 #define AON_RF_REG_0_RTC_REG1 AON_RF_REG_0_RTC_REG1_Msk
1165
1166 #define AON_RF_REG_0_DYN_CLK_CTRL_Pos (16U)
1167 #define AON_RF_REG_0_DYN_CLK_CTRL_Len (3U)
1168 #define AON_RF_REG_0_DYN_CLK_CTRL_Msk (0x7U << AON_RF_REG_0_DYN_CLK_CTRL_Pos)
1169 #define AON_RF_REG_0_DYN_CLK_CTRL AON_RF_REG_0_DYN_CLK_CTRL_Msk
1170
1171 #define AON_RF_REG_0_BGAP_STATIC_EN_LV_Pos (19U)
1172 #define AON_RF_REG_0_BGAP_STATIC_EN_LV_Len (1U)
1173 #define AON_RF_REG_0_BGAP_STATIC_EN_LV_Msk (0x1U << AON_RF_REG_0_BGAP_STATIC_EN_LV_Pos)
1174 #define AON_RF_REG_0_BGAP_STATIC_EN_LV_EN (0x1U << AON_RF_REG_0_BGAP_STATIC_EN_LV_Pos)
1175 #define AON_RF_REG_0_BGAP_STATIC_EN_LV_DIS (0x0U << AON_RF_REG_0_BGAP_STATIC_EN_LV_Pos)
1176
1177 #define AON_RF_REG_0_RCOSC_BIAS_CNTRL_Pos (22)
1178 #define AON_RF_REG_0_RCOSC_BIAS_CNTRL_Len (2U)
1179 #define AON_RF_REG_0_RCOSC_BIAS_CNTRL_Msk (0x03 << AON_RF_REG_0_BGAP_STATIC_EN_LV_Pos)
1180
1181
1182 #define AON_RF_REG_0_CTRL_TEMPCO_Pos (13U)
1183 #define AON_RF_REG_0_CTRL_TEMPCO_Len (3U)
1184 #define AON_RF_REG_0_CTRL_TEMPCO_Msk (0x7U << AON_RF_REG_0_CTRL_TEMPCO_Pos)
1185 #define AON_RF_REG_0_CTRL_TEMPCO AON_RF_REG_0_CTRL_TEMPCO_Msk
1186
1187 #define AON_RF_REG_0_CTRL_RET_Pos (11U)
1188 #define AON_RF_REG_0_CTRL_RET_Len (2U)
1189 #define AON_RF_REG_0_CTRL_RET_Msk (0x3U << AON_RF_REG_0_CTRL_RET_Pos)
1190 #define AON_RF_REG_0_CTRL_RET AON_RF_REG_0_CTRL_RET_Msk
1191
1192 #define AON_RF_REG_0_CTRL_BGAP_Pos (9U)
1193 #define AON_RF_REG_0_CTRL_BGAP_Len (2U)
1194 #define AON_RF_REG_0_CTRL_BGAP_Msk (0x3U << AON_RF_REG_0_CTRL_BGAP_Pos)
1195 #define AON_RF_REG_0_CTRL_BGAP AON_RF_REG_0_CTRL_BGAP_Msk
1196
1197 #define AON_RF_REG_0_BGAP_VOLTAGE_EN_Pos (8U)
1198 #define AON_RF_REG_0_BGAP_VOLTAGE_EN_Len (1U)
1199 #define AON_RF_REG_0_BGAP_VOLTAGE_ON (0x1U << AON_RF_REG_0_BGAP_VOLTAGE_EN_Pos)
1200 #define AON_RF_REG_0_BGAP_VOLTAGE_OFF (0x0U << AON_RF_REG_0_BGAP_VOLTAGE_EN_Pos)
1201
1202 #define AON_RF_REG_0_LPD_REG1_Pos (8U)
1203 #define AON_RF_REG_0_LPD_REG1_Len (8U)
1204 #define AON_RF_REG_0_LPD_REG1_Msk (0xFFU << AON_RF_REG_0_LPD_REG1_Pos)
1205 #define AON_RF_REG_0_LPD_REG1 AON_RF_REG_0_LPD_REG1_Msk
1206
1207 #define AON_RF_REG_0_RTC_REG1_Pos (0U)
1208 #define AON_RF_REG_0_RTC_REG1_Len (8U)
1209 #define AON_RF_REG_0_RTC_REG1_Msk (0xFFU << AON_RF_REG_0_RTC_REG1_Pos)
1210 #define AON_RF_REG_0_RTC_REG1 AON_RF_REG_0_RTC_REG1_Msk
1211
1212 /******************* Bit definition for AON_REG_RF_REG_1 register **********/
1213 #define AON_RF_REG_1_DCDC_REG4_Pos (24U)
1214 #define AON_RF_REG_1_DCDC_REG4_Len (8U)
1215 #define AON_RF_REG_1_DCDC_REG4_Msk (0xFFU << AON_RF_REG_1_DCDC_REG4_Pos)
1216 #define AON_RF_REG_1_DCDC_REG4 AON_RF_REG_1_DCDC_REG4_Msk
1217
1218 #define AON_RF_REG_1_DCDC_REG3_Pos (16U)
1219 #define AON_RF_REG_1_DCDC_REG3_Len (8U)
1220 #define AON_RF_REG_1_DCDC_REG3_Msk (0xFFU << AON_RF_REG_1_DCDC_REG3_Pos)
1221 #define AON_RF_REG_1_DCDC_REG3 AON_RF_REG_1_DCDC_REG3_Msk
1222
1223 #define AON_RF_REG_1_EN_INJ_Pos (14U)
1224 #define AON_RF_REG_1_EN_INJ_Msk (0x1 << AON_RF_REG_1_EN_INJ_Pos)
1225 #define AON_RF_REG_1_EN_INJ_ON (0x1 << AON_RF_REG_1_EN_INJ_Pos)
1226 #define AON_RF_REG_1_EN_INJ_OFF (0x0 << AON_RF_REG_1_EN_INJ_Pos)
1227
1228 #define AON_RF_REG_1_TON_Pos (11U)
1229 #define AON_RF_REG_1_TON_Len (3U)
1230 #define AON_RF_REG_1_TON_Msk (0x7U << AON_RF_REG_1_TON_Pos)
1231 #define AON_RF_REG_1_TON AON_RF_REG_1_TON_Msk
1232
1233 #define AON_RF_REG_1_DCDC_REG2_Pos (8U)
1234 #define AON_RF_REG_1_DCDC_REG2_Len (8U)
1235 #define AON_RF_REG_1_DCDC_REG2_Msk (0xFFU << AON_RF_REG_1_DCDC_REG2_Pos)
1236 #define AON_RF_REG_1_DCDC_REG2 AON_RF_REG_1_DCDC_REG2_Msk
1237
1238 #define AON_RF_REG_1_DCDC_REG1_Pos (0U)
1239 #define AON_RF_REG_1_DCDC_REG1_Len (8U)
1240 #define AON_RF_REG_1_DCDC_REG1_Msk (0xFFU << AON_RF_REG_1_DCDC_REG1_Pos)
1241 #define AON_RF_REG_1_DCDC_REG1 AON_RF_REG_1_DCDC_REG1_Msk
1242
1243 /******************* Bit definition for AON_REG_RF_REG_2 register **********/
1244 #define AON_RF_REG_2_TON_EN_Pos (17U)
1245 #define AON_RF_REG_2_TON_EN_Msk (0x1U << AON_RF_REG_2_TON_EN_Pos)
1246 #define AON_RF_REG_2_TON_EN_ON (0x1 << AON_RF_REG_2_TON_EN_Pos)
1247 #define AON_RF_REG_2_TON_EN_OFF (0x0 << AON_RF_REG_2_TON_EN_Pos)
1248
1249 #define AON_RF_REG_2_GP_REG2_Pos (16U)
1250 #define AON_RF_REG_2_GP_REG2_Len (8U)
1251 #define AON_RF_REG_2_GP_REG2_Msk (0xFFU << AON_RF_REG_2_GP_REG2_Pos)
1252 #define AON_RF_REG_2_GP_REG2 AON_RF_REG_2_GP_REG2_Msk
1253
1254 #define AON_RF_REG_2_GP_REG1_Pos (8U)
1255 #define AON_RF_REG_2_GP_REG1_Len (8U)
1256 #define AON_RF_REG_2_GP_REG1_Msk (0xFFU << AON_RF_REG_2_GP_REG1_Pos)
1257 #define AON_RF_REG_2_GP_REG1 AON_RF_REG_2_GP_REG1_Msk
1258 #define AON_RF_REG_2_EFUSE_VDD_EN (0x4U << AON_RF_REG_2_GP_REG1_Pos)
1259
1260 #define AON_RF_REG_2_MUX1_REG1_Pos (0U)
1261 #define AON_RF_REG_2_MUX1_REG1_Len (8U)
1262 #define AON_RF_REG_2_MUX1_REG1_Msk (0xFFU << AON_RF_REG_2_MUX1_REG1_Pos)
1263 #define AON_RF_REG_2_MUX1_REG1 AON_RF_REG_2_MUX1_REG1_Msk
1264
1265 /******************* Bit definition for AON_REG_CALENDAR_TIMER_CTL register **********/
1266 #define AON_CALENDAR_TIMER_CTL_WRAP_INT_EN_Pos (13U)
1267 #define AON_CALENDAR_TIMER_CTL_WRAP_INT_EN_Len (1U)
1268 #define AON_CALENDAR_TIMER_CTL_WRAP_INT_EN_Msk (0x1U << AON_CALENDAR_TIMER_CTL_WRAP_INT_EN_Pos)
1269 #define AON_CALENDAR_TIMER_CTL_WRAP_INT_EN AON_CALENDAR_TIMER_CTL_WRAP_INT_EN_Msk
1270
1271 #define AON_CALENDAR_TIMER_CTL_ALARM_INT_EN_Pos (12U)
1272 #define AON_CALENDAR_TIMER_CTL_ALARM_INT_EN_Len (1U)
1273 #define AON_CALENDAR_TIMER_CTL_ALARM_INT_EN_Msk (0x1U << AON_CALENDAR_TIMER_CTL_ALARM_INT_EN_Pos)
1274 #define AON_CALENDAR_TIMER_CTL_ALARM_INT_EN AON_CALENDAR_TIMER_CTL_ALARM_INT_EN_Msk
1275
1276 #define AON_CALENDAR_TIMER_CTL_CLK_SEL_Pos (8U)
1277 #define AON_CALENDAR_TIMER_CTL_CLK_SEL_Len (3U)
1278 #define AON_CALENDAR_TIMER_CTL_CLK_SEL_Msk (0x7U << AON_CALENDAR_TIMER_CTL_CLK_SEL_Pos)
1279 #define AON_CALENDAR_TIMER_CTL_CLK_SEL AON_CALENDAR_TIMER_CTL_CLK_SEL_Msk
1280
1281 #define AON_CALENDAR_TIMER_CTL_WRAP_CNT_Pos (4U)
1282 #define AON_CALENDAR_TIMER_CTL_WRAP_CNT_Len (4U)
1283 #define AON_CALENDAR_TIMER_CTL_WRAP_CNT_Msk (0xFU << AON_CALENDAR_TIMER_CTL_WRAP_CNT_Pos)
1284 #define AON_CALENDAR_TIMER_CTL_WRAP_CNT AON_CALENDAR_TIMER_CTL_WRAP_CNT_Msk
1285
1286 #define AON_CALENDAR_TIMER_CTL_ALARM_VAL_LOAD_Pos (2U)
1287 #define AON_CALENDAR_TIMER_CTL_ALARM_VAL_LOAD_Len (1U)
1288 #define AON_CALENDAR_TIMER_CTL_ALARM_VAL_LOAD_Msk (0x1U << AON_CALENDAR_TIMER_CTL_ALARM_VAL_LOAD_Pos)
1289 #define AON_CALENDAR_TIMER_CTL_ALARM_VAL_LOAD AON_CALENDAR_TIMER_CTL_ALARM_VAL_LOAD_Msk
1290
1291 #define AON_CALENDAR_TIMER_CTL_VAL_LOAD_Pos (1U)
1292 #define AON_CALENDAR_TIMER_CTL_VAL_LOAD_Len (1U)
1293 #define AON_CALENDAR_TIMER_CTL_VAL_LOAD_Msk (0x1U << AON_CALENDAR_TIMER_CTL_VAL_LOAD_Pos)
1294 #define AON_CALENDAR_TIMER_CTL_VAL_LOAD AON_CALENDAR_TIMER_CTL_VAL_LOAD_Msk
1295
1296 #define AON_CALENDAR_TIMER_CTL_EN_Pos (0U)
1297 #define AON_CALENDAR_TIMER_CTL_EN_Len (1U)
1298 #define AON_CALENDAR_TIMER_CTL_EN_Msk (0x1U << AON_CALENDAR_TIMER_CTL_EN_Pos)
1299 #define AON_CALENDAR_TIMER_CTL_EN AON_CALENDAR_TIMER_CTL_EN_Msk
1300
1301 /******************* Bit definition for AON_REG_MEM_STD_OVR register **********/
1302 #define AON_MEM_STD_OVR_MCU_KEYRAM_STDBY_N_Pos (30U)
1303 #define AON_MEM_STD_OVR_MCU_KEYRAM_STDBY_N_Len (1U)
1304 #define AON_MEM_STD_OVR_MCU_KEYRAM_STDBY_N_Msk (0x1U << AON_MEM_STD_OVR_MCU_KEYRAM_STDBY_N_Pos)
1305 #define AON_MEM_STD_OVR_MCU_KEYRAM_STDBY_N AON_MEM_STD_OVR_MCU_KEYRAM_STDBY_N_Msk
1306
1307 #define AON_MEM_STD_OVR_PMEM_STDBY_N_Pos (29U)
1308 #define AON_MEM_STD_OVR_PMEM_STDBY_N_Len (1U)
1309 #define AON_MEM_STD_OVR_PMEM_STDBY_N_Msk (0x1U << AON_MEM_STD_OVR_PMEM_STDBY_N_Pos)
1310 #define AON_MEM_STD_OVR_PMEM_STDBY_N AON_MEM_STD_OVR_PMEM_STDBY_N_Msk
1311
1312 #define AON_MEM_STD_OVR_MCU_ICACHE_STDBY_N_Pos (28U)
1313 #define AON_MEM_STD_OVR_MCU_ICACHE_STDBY_N_Len (1U)
1314 #define AON_MEM_STD_OVR_MCU_ICACHE_STDBY_N_Msk (1U << AON_MEM_STD_OVR_MCU_ICACHE_STDBY_N_Pos)
1315 #define AON_MEM_STD_OVR_MCU_ICACHE_STDBY_N AON_MEM_STD_OVR_MCU_ICACHE_STDBY_N_Msk
1316
1317 #define AON_MEM_STD_OVR_MCU_HTM_STDBY_N_Pos (27U)
1318 #define AON_MEM_STD_OVR_MCU_HTM_STDBY_N_Len (1U)
1319 #define AON_MEM_STD_OVR_MCU_HTM_STDBY_N_Msk (1U << AON_MEM_STD_OVR_MCU_HTM_STDBY_N_Pos)
1320 #define AON_MEM_STD_OVR_MCU_HTM_STDBY_N AON_MEM_STD_OVR_MCU_HTM_STDBY_N_Msk
1321
1322 #define AON_MEM_STD_OVR_MCU_MEM_STDBY_N_Pos (16U)
1323 #define AON_MEM_STD_OVR_MCU_MEM_STDBY_N_Len (11U)
1324 #define AON_MEM_STD_OVR_MCU_MEM_STDBY_N_Msk (0x7FFU << AON_MEM_STD_OVR_MCU_MEM_STDBY_N_Pos)
1325 #define AON_MEM_STD_OVR_MCU_MEM_STDBY_N AON_MEM_STD_OVR_MCU_MEM_STDBY_N_Msk
1326
1327 #define AON_MEM_STD_OVR_KEYRAM_ISO_VDD_N_Pos (14U)
1328 #define AON_MEM_STD_OVR_KEYRAM_ISO_VDD_N_Len (1U)
1329 #define AON_MEM_STD_OVR_KEYRAM_ISO_VDD_N_Msk (0x1U << AON_MEM_STD_OVR_KEYRAM_ISO_VDD_N_Pos)
1330 #define AON_MEM_STD_OVR_KEYRAM_ISO_VDD_N AON_MEM_STD_OVR_KEYRAM_ISO_VDD_N_Msk
1331
1332 #define AON_MEM_STD_OVR_EF_CACHE_ISO_VDD_N_Pos (13U)
1333 #define AON_MEM_STD_OVR_EF_CACHE_ISO_VDD_N_Len (1U)
1334 #define AON_MEM_STD_OVR_EF_CACHE_ISO_VDD_N_Msk (0x1U << AON_MEM_STD_OVR_EF_CACHE_ISO_VDD_N_Pos)
1335 #define AON_MEM_STD_OVR_EF_CACHE_ISO_VDD_N AON_MEM_STD_OVR_EF_CACHE_ISO_VDD_N_Msk
1336
1337 #define AON_MEM_STD_OVR_HTABLE_ISO_VDD_N_Pos (12U)
1338 #define AON_MEM_STD_OVR_HTABLE_ISO_VDD_N_Len (1U)
1339 #define AON_MEM_STD_OVR_HTABLE_ISO_VDD_N_Msk (0x1U << AON_MEM_STD_OVR_HTABLE_ISO_VDD_N_Pos)
1340 #define AON_MEM_STD_OVR_HTABLE_ISO_VDD_N AON_MEM_STD_OVR_HTABLE_ISO_VDD_N_Msk
1341
1342 #define AON_MEM_STD_OVR_PMEM_ISO_VDD_N_Pos (11U)
1343 #define AON_MEM_STD_OVR_PMEM_ISO_VDD_N_Len (1U)
1344 #define AON_MEM_STD_OVR_PMEM_ISO_VDD_N_Msk (0x1U << AON_MEM_STD_OVR_PMEM_ISO_VDD_N_Pos)
1345 #define AON_MEM_STD_OVR_PMEM_ISO_VDD_N AON_MEM_STD_OVR_PMEM_ISO_VDD_N_Msk
1346
1347 #define AON_MEM_STD_OVR_MCU_MEM_ISO_VDD_N_Pos (0U)
1348 #define AON_MEM_STD_OVR_MCU_MEM_ISO_VDD_N_Len (11U)
1349 #define AON_MEM_STD_OVR_MCU_MEM_ISO_VDD_N_Msk (0x7FF << AON_MEM_STD_OVR_MCU_MEM_ISO_VDD_N_Pos)
1350 #define AON_MEM_STD_OVR_MCU_MEM_ISO_VDD_N AON_MEM_STD_OVR_MCU_MEM_ISO_VDD_N_Msk
1351
1352 /******************* Bit definition for AON_REG_RF_REG_3 register **********/
1353 #define AON_RF_REG_3_IO_LDO_REG2_Pos (24U)
1354 #define AON_RF_REG_3_IO_LDO_REG2_Len (8U)
1355 #define AON_RF_REG_3_IO_LDO_REG2_Msk (0xFFU << AON_RF_REG_3_IO_LDO_REG2_Pos)
1356 #define AON_RF_REG_3_IO_LDO_REG2 AON_RF_REG_3_IO_LDO_REG2_Msk
1357
1358 #define AON_RF_REG_3_LDO_5V_REG1_Pos (8U)
1359 #define AON_RF_REG_3_LDO_5V_REG1_Len (8U)
1360 #define AON_RF_REG_3_LDO_5V_REG1_Msk (0xFFU << AON_RF_REG_3_LDO_5V_REG1_Pos)
1361 #define AON_RF_REG_3_LDO_5V_REG1 AON_RF_REG_3_LDO_5V_REG1_Msk
1362
1363 #define AON_RF_REG_3_RTC_EN_Pos (7U)
1364 #define AON_RF_REG_3_RTC_EN_Len (1U)
1365 #define AON_RF_REG_3_RTC_EN_Msk (0x1U << AON_RF_REG_3_RTC_EN_Pos)
1366 #define AON_RF_REG_3_RTC_EN AON_RF_REG_3_RTC_EN_Msk
1367 #define AON_RF_REG_3_RTC_DIS (0x0U << AON_RF_REG_3_RTC_EN_Pos)
1368
1369 #define AON_RF_REG_3_BOD_STATIC_LV_Pos (5U)
1370 #define AON_RF_REG_3_BOD_STATIC_LV_Len (1U)
1371 #define AON_RF_REG_3_BOD_STATIC_LV_Msk (0x1U << AON_RF_REG_3_BOD_STATIC_LV_Pos)
1372 #define AON_RF_REG_3_BOD_STATIC_LV_EN (0x1U << AON_RF_REG_3_BOD_STATIC_LV_Pos)
1373 #define AON_RF_REG_3_BOD_STATIC_LV_DIS (0x0U << AON_RF_REG_3_BOD_STATIC_LV_Pos)
1374 #define AON_RF_REG_3_BOD_LVL_CTRL_LV_Pos (2U)
1375 #define AON_RF_REG_3_BOD_LVL_CTRL_LV_Len (3U)
1376 #define AON_RF_REG_3_BOD_LVL_CTRL_LV_Msk (0x7U << AON_RF_REG_3_BOD_LVL_CTRL_LV_Pos)
1377 #define AON_RF_REG_3_BOD_LVL_CTRL_LV AON_RF_REG_3_BOD_LVL_CTRL_LV_Msk
1378 #define AON_RF_REG_3_BOD2_EN_Pos (1U)
1379 #define AON_RF_REG_3_BOD2_EN_Len (1U)
1380 #define AON_RF_REG_3_BOD2_EN_Msk (0x1U << AON_RF_REG_3_BOD2_EN_Pos)
1381 #define AON_RF_REG_3_BOD2_EN (0x1U << AON_RF_REG_3_BOD2_EN_Pos)
1382 #define AON_RF_REG_3_BOD2_DIS (0x0U << AON_RF_REG_3_BOD2_EN_Pos)
1383
1384 #define AON_RF_REG_3_BOD_EN_Pos (0U)
1385 #define AON_RF_REG_3_BOD_EN_Len (1U)
1386 #define AON_RF_REG_3_BOD_EN_Msk (0x1U << AON_RF_REG_3_BOD_EN_Pos)
1387 #define AON_RF_REG_3_BOD_EN (0x1U << AON_RF_REG_3_BOD_EN_Pos)
1388 #define AON_RF_REG_3_BOD_DIS (0x0U << AON_RF_REG_3_BOD_EN_Pos)
1389
1390 #define AON_RF_REG_3_BOD_REG1_Pos (0U)
1391 #define AON_RF_REG_3_BOD_REG1_Len (8U)
1392 #define AON_RF_REG_3_BOD_REG1_Msk (0xFFU << AON_RF_REG_3_BOD_REG1_Pos)
1393 #define AON_RF_REG_3_BOD_REG1 AON_RF_REG_3_BOD_REG1_Msk
1394
1395 /******************* Bit definition for AON_REG_RF_REG_4 register **********/
1396 #define AON_RF_REG_4_DIG_LDO_REG1_Pos (16U)
1397 #define AON_RF_REG_4_DIG_LDO_REG1_Len (8U)
1398 #define AON_RF_REG_4_DIG_LDO_REG1_Msk (0xFFU << AON_RF_REG_4_DIG_LDO_REG1_Pos)
1399 #define AON_RF_REG_4_DIG_LDO_REG1 AON_RF_REG_4_DIG_LDO_REG1_Msk
1400
1401 #define AON_RF_REG_4_CLK_PERIOD_Pos (12U)
1402 #define AON_RF_REG_4_CLK_PERIOD_Len (4U)
1403 #define AON_RF_REG_4_CLK_PERIOD_Msk (0xF << AON_RF_REG_4_CLK_PERIOD_Pos)
1404 #define AON_RF_REG_4_CLK_PERIOD AON_RF_REG_4_CLK_PERIOD_Msk
1405
1406 #define AON_RF_REG_4_DCDC_REG6_Pos (8U)
1407 #define AON_RF_REG_4_DCDC_REG6_Len (8U)
1408 #define AON_RF_REG_4_DCDC_REG6_Msk (0xFFU << AON_RF_REG_4_DCDC_REG6_Pos)
1409 #define AON_RF_REG_4_DCDC_REG6 AON_RF_REG_4_DCDC_REG6_Msk
1410
1411 #define AON_RF_REG_4_DCDC_REG5_Pos (0U)
1412 #define AON_RF_REG_4_DCDC_REG5_Len (8U)
1413 #define AON_RF_REG_4_DCDC_REG5_Msk (0xFFU << AON_RF_REG_4_DCDC_REG5_Pos)
1414 #define AON_RF_REG_4_DCDC_REG5 AON_RF_REG_4_DCDC_REG5_Msk
1415
1416 /******************* Bit definition for AON_REG_RF_REG_5 register **********/
1417 #define AON_RF_REG_5_MUX_REG2_Pos (24U)
1418 #define AON_RF_REG_5_MUX_REG2_Len (8U)
1419 #define AON_RF_REG_5_MUX_REG2_Msk (0xFFU << AON_RF_REG_5_MUX_REG2_Pos)
1420 #define AON_RF_REG_5_MUX_REG2 AON_RF_REG_5_MUX_REG2_Msk
1421
1422 #define AON_RF_REG_5_MUX_REG1_Pos (16U)
1423 #define AON_RF_REG_5_MUX_REG1_Len (8U)
1424 #define AON_RF_REG_5_MUX_REG1_Msk (0xFFU << AON_RF_REG_5_MUX_REG1_Pos)
1425 #define AON_RF_REG_5_MUX_REG1 AON_RF_REG_5_MUX_REG1_Msk
1426
1427 #define AON_RF_REG_5_LPD_REG3_Pos (0U)
1428 #define AON_RF_REG_5_LPD_REG3_Len (8U)
1429 #define AON_RF_REG_5_LPD_REG3_Msk (0xFFU << AON_RF_REG_5_LPD_REG3_Pos)
1430 #define AON_RF_REG_5_LPD_REG3 AON_RF_REG_5_LPD_REG3_Msk
1431
1432 #define AON_RF_REG_5_RCOSC_EN_Pos (7)
1433 #define AON_RF_REG_5_RCOSC_EN_Len (1U)
1434 #define AON_RF_REG_5_RCOSC_EN_Msk (0x01 << AON_RF_REG_5_RCOSC_EN_Pos)
1435 #define AON_RF_REG_5_RCOSC_EN (AON_RF_REG_5_RCOSC_EN_Msk)
1436
1437 #define AON_RF_REG_5_RCOSC_DELAY_EN_Pos (6)
1438 #define AON_RF_REG_5_RCOSC_DELAY_EN_Len (1U)
1439 #define AON_RF_REG_5_RCOSC_DELAY_EN_Msk (0x01 << AON_RF_REG_5_RCOSC_DELAY_EN_Pos)
1440 #define AON_RF_REG_5_RCOSC_DELAY_EN (0x01 << AON_RF_REG_5_RCOSC_DELAY_EN_Pos)
1441
1442 #define AON_RF_REG_5_RCOSC_RDIV_DELAY_Pos (3)
1443 #define AON_RF_REG_5_RCOSC_RDIV_DELAY_Len (3U)
1444 #define AON_RF_REG_5_RCOSC_RDIV_DELAY_Msk (0x07 << AON_RF_REG_5_RCOSC_RDIV_DELAY_Pos)
1445 #define AON_RF_REG_5_RCOSC_RDIV_DELAY (AON_RF_REG_5_RCOSC_RDIV_DELAY_Msk)
1446
1447 #define AON_RF_REG_5_RCOSC_RESN_CNTRL_Pos (0)
1448 #define AON_RF_REG_5_RCOSC_RESN_CNTRL_Len (3U)
1449 #define AON_RF_REG_5_RCOSC_RESN_CNTRL_Msk (0x07 << AON_RF_REG_5_RCOSC_RESN_CNTRL_Pos)
1450 #define AON_RF_REG_5_RCOSC_RESN_CNTRL (AON_RF_REG_5_RCOSC_RESN_CNTRL_Msk)
1451
1452 /******************* Bit definition for AON_REG_RF_REG_6 register **********/
1453 #define AON_RF_REG_6_CPLL_REG1_Pos (0U)
1454 #define AON_RF_REG_6_CPLL_REG1_Len (32U)
1455 #define AON_RF_REG_6_CPLL_REG1_Msk (0xFFFFFFFFU)
1456 #define AON_RF_REG_6_CPLL_REG1 AON_RF_REG_6_CPLL_REG1_Msk
1457
1458 /******************* Bit definition for AON_REG_RF_REG_7 register **********/
1459 #define AON_RF_REG_7_CPLL_REG2_Pos (0U)
1460 #define AON_RF_REG_7_CPLL_REG2_Len (32U)
1461 #define AON_RF_REG_7_CPLL_REG2_Msk (0xFFFFFFFFU)
1462 #define AON_RF_REG_7_CPLL_REG2 AON_RF_REG_7_CPLL_REG2_Msk
1463
1464 /******************* Bit definition for AON_REG_RF_REG_8 register **********/
1465 #define AON_RF_REG_8_XO_REG1_Pos (0U)
1466 #define AON_RF_REG_8_XO_REG1_Len (32U)
1467 #define AON_RF_REG_8_XO_REG1_Msk (0xFFFFFFFFU)
1468 #define AON_RF_REG_8_XO_REG1 AON_RF_REG_8_XO_REG1_Msk
1469
1470 /******************* Bit definition for AON_REG_RF_REG_9 register **********/
1471 #define AON_RF_REG_9_XO_REG2_Pos (0U)
1472 #define AON_RF_REG_9_XO_REG2_Len (32U)
1473 #define AON_RF_REG_9_XO_REG2_Msk (0xFFFFFFFFU)
1474 #define AON_RF_REG_9_XO_REG2 AON_RF_REG_9_XO_REG2_Msk
1475
1476 /******************* Bit definition for AON_REG_MSIO_PAD_CFG_0 register **********/
1477 #define AON_MSIO_PAD_CFG_0_OE_N_Pos (24U)
1478 #define AON_MSIO_PAD_CFG_0_OE_N_Len (5U)
1479 #define AON_MSIO_PAD_CFG_0_OE_N_Msk (0x1FU << AON_MSIO_PAD_CFG_0_OE_N_Pos)
1480 #define AON_MSIO_PAD_CFG_0_OE_N AON_MSIO_PAD_CFG_0_OE_N_Msk
1481
1482 #define AON_MSIO_PAD_CFG_0_IE_N_Pos (16U)
1483 #define AON_MSIO_PAD_CFG_0_IE_N_Len (5U)
1484 #define AON_MSIO_PAD_CFG_0_IE_N_Msk (0x1FU << AON_MSIO_PAD_CFG_0_IE_N_Pos)
1485 #define AON_MSIO_PAD_CFG_0_IE_N AON_MSIO_PAD_CFG_0_IE_N_Msk
1486
1487 #define AON_MSIO_PAD_CFG_0_IN_Pos (8U)
1488 #define AON_MSIO_PAD_CFG_0_IN_Len (5U)
1489 #define AON_MSIO_PAD_CFG_0_IN_Msk (0x1FU << AON_MSIO_PAD_CFG_0_IN_Pos)
1490 #define AON_MSIO_PAD_CFG_0_IN AON_MSIO_PAD_CFG_0_IN_Msk
1491
1492 #define AON_MSIO_PAD_CFG_0_RE_N_Pos (0U)
1493 #define AON_MSIO_PAD_CFG_0_RE_N_Len (5U)
1494 #define AON_MSIO_PAD_CFG_0_RE_N_Msk (0x1FU << AON_MSIO_PAD_CFG_0_RE_N_Pos)
1495 #define AON_MSIO_PAD_CFG_0_RE_N AON_MSIO_PAD_CFG_0_RE_N_Msk
1496
1497 /******************* Bit definition for AON_REG_MSIO_PAD_CFG_1 register **********/
1498 #define AON_MSIO_PAD_CFG_1_ADC_CLK_EN_Pos (31U)
1499 #define AON_MSIO_PAD_CFG_1_ADC_CLK_EN_Len (1U)
1500 #define AON_MSIO_PAD_CFG_1_ADC_CLK_EN_Msk (0x1U << AON_MSIO_PAD_CFG_1_ADC_CLK_EN_Pos)
1501 #define AON_MSIO_PAD_CFG_1_ADC_CLK_EN AON_MSIO_PAD_CFG_1_ADC_CLK_EN_Msk
1502
1503 #define AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos (28U)
1504 #define AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Len (3U)
1505 #define AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Msk (0x7U << AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Pos)
1506 #define AON_MSIO_PAD_CFG_1_ADC_CLK_SEL AON_MSIO_PAD_CFG_1_ADC_CLK_SEL_Msk
1507
1508 #define AON_MSIO_PAD_CFG_1_MCU_OVR_Pos (22U)
1509 #define AON_MSIO_PAD_CFG_1_MCU_OVR_Len (5U)
1510 #define AON_MSIO_PAD_CFG_1_MCU_OVR_Msk (0x1FU << AON_MSIO_PAD_CFG_1_MCU_OVR_Pos)
1511 #define AON_MSIO_PAD_CFG_1_MCU_OVR AON_MSIO_PAD_CFG_1_MCU_OVR_Msk
1512
1513 #define AON_COMM_DEEPSLCNTL_EXTWKUPDSB_Pos (21U)
1514 #define AON_COMM_DEEPSLCNTL_EXTWKUPDSB_Len (1U)
1515 #define AON_COMM_DEEPSLCNTL_EXTWKUPDSB_Msk (0x1U << AON_COMM_DEEPSLCNTL_EXTWKUPDSB_Pos)
1516 #define AON_COMM_DEEPSLCNTL_EXTWKUPDSB AON_COMM_DEEPSLCNTL_EXTWKUPDSB_Msk
1517
1518 #define AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ_Pos (20U)
1519 #define AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ_Len (1U)
1520 #define AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ_Msk (0x1U << AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ_Pos)
1521 #define AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ AON_COMM_DEEPSLCNTL_SOFT_WAKEUP_REQ_Msk
1522
1523 #define AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON_Pos (18U)
1524 #define AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON_Len (1U)
1525 #define AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON_Msk (0x1U << AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON_Pos)
1526 #define AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON AON_COMM_DEEPSLCNTL_DEEP_SLEEP_ON_Msk
1527
1528 #define AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN_Pos (17U)
1529 #define AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN_Len (1U)
1530 #define AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN_Msk (0x1U << AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN_Pos)
1531 #define AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN AON_COMM_DEEPSLCNTL_RADIO_SLEEP_EN_Msk
1532
1533 #define AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN_Pos (16U)
1534 #define AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN_Len (1U)
1535 #define AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN_Msk (0x1U << AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN_Pos)
1536 #define AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN AON_COMM_DEEPSLCNTL_OSC_SLEEP_EN_Msk
1537
1538 #define AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT_Pos (15U)
1539 #define AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT_Len (1U)
1540 #define AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT_Msk (0x1U << AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT_Pos)
1541 #define AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT AON_COMM_DEEPSLCNTL_DEEP_SLEEP_STAT_Msk
1542
1543 #define AON_MSIO_PAD_CFG_1_RTYPE_Pos (8U)
1544 #define AON_MSIO_PAD_CFG_1_RTYPE_Len (5U)
1545 #define AON_MSIO_PAD_CFG_1_RTYPE_Msk (0x1FU << AON_MSIO_PAD_CFG_1_RTYPE_Pos)
1546 #define AON_MSIO_PAD_CFG_1_RTYPE AON_MSIO_PAD_CFG_1_RTYPE_Msk
1547
1548 #define AON_MSIO_PAD_CFG_1_AE_N_Pos (0U)
1549 #define AON_MSIO_PAD_CFG_1_AE_N_Len (5U)
1550 #define AON_MSIO_PAD_CFG_1_AE_N_Msk (0x1FU << AON_MSIO_PAD_CFG_1_AE_N_Pos)
1551 #define AON_MSIO_PAD_CFG_1_AE_N AON_MSIO_PAD_CFG_1_AE_N_Msk
1552
1553 /******************* Bit definition for AON_REG_SLP_EVENT register **********/
1554 #define AON_SLP_EVENT_SLP_TIMER_MODE_Pos (30U)
1555 #define AON_SLP_EVENT_SLP_TIMER_MODE_Len (2U)
1556 #define AON_SLP_EVENT_SLP_TIMER_MODE_Msk (0x3U << AON_SLP_EVENT_SLP_TIMER_MODE_Pos)
1557 #define AON_SLP_EVENT_SLP_TIMER_MODE AON_SLP_EVENT_SLP_TIMER_MODE_Msk
1558 #define AON_SLP_EVENT_SLP_TIMER_MODE_NORMAL (0x0U << AON_SLP_EVENT_SLP_TIMER_MODE_Pos)
1559 #define AON_SLP_EVENT_SLP_TIMER_MODE_SINGLE (0x1U << AON_SLP_EVENT_SLP_TIMER_MODE_Pos)
1560 #define AON_SLP_EVENT_SLP_TIMER_MODE_RELOAD (0x2U << AON_SLP_EVENT_SLP_TIMER_MODE_Pos)
1561 #define AON_SLP_EVENT_SLP_TIMER_MODE_DISABLE (0x3U << AON_SLP_EVENT_SLP_TIMER_MODE_Pos)
1562
1563 #define AON_SLP_EVENT_EXT_WKUP_STATUS_Pos (16U)
1564 #define AON_SLP_EVENT_EXT_WKUP_STATUS_Len (8U)
1565 #define AON_SLP_EVENT_EXT_WKUP_STATUS_Msk (0xFFU << AON_SLP_EVENT_EXT_WKUP_STATUS_Pos)
1566 #define AON_SLP_EVENT_EXT_WKUP_STATUS AON_SLP_EVENT_EXT_WKUP_STATUS_Msk
1567
1568 #define AON_SLP_EVENT_CALENDAR_TIMER_WRAP_Pos (9U)
1569 #define AON_SLP_EVENT_CALENDAR_TIMER_WRAP_Len (1U)
1570 #define AON_SLP_EVENT_CALENDAR_TIMER_WRAP_Msk (0x1U << AON_SLP_EVENT_CALENDAR_TIMER_WRAP_Pos)
1571 #define AON_SLP_EVENT_CALENDAR_TIMER_WRAP AON_SLP_EVENT_CALENDAR_TIMER_WRAP_Msk
1572
1573 #define AON_SLP_EVENT_CALENDAR_TIMER_ALARM_Pos (8U)
1574 #define AON_SLP_EVENT_CALENDAR_TIMER_ALARM_Len (1U)
1575 #define AON_SLP_EVENT_CALENDAR_TIMER_ALARM_Msk (0x1U << AON_SLP_EVENT_CALENDAR_TIMER_ALARM_Pos)
1576 #define AON_SLP_EVENT_CALENDAR_TIMER_ALARM AON_SLP_EVENT_CALENDAR_TIMER_ALARM_Msk
1577
1578 #define AON_SLP_EVENT_WDT_REBOOT_Pos (6U)
1579 #define AON_SLP_EVENT_WDT_REBOOT_Len (1U)
1580 #define AON_SLP_EVENT_WDT_REBOOT_Msk (0x1U << AON_SLP_EVENT_WDT_REBOOT_Pos)
1581 #define AON_SLP_EVENT_WDT_REBOOT AON_SLP_EVENT_WDT_REBOOT_Msk
1582
1583 #define AON_SLP_EVENT_PMU_MSIO_COMP_Pos (4U)
1584 #define AON_SLP_EVENT_PMU_MSIO_COMP_Len (1U)
1585 #define AON_SLP_EVENT_PMU_MSIO_COMP_Msk (0x1U << AON_SLP_EVENT_PMU_MSIO_COMP_Pos)
1586 #define AON_SLP_EVENT_PMU_MSIO_COMP AON_SLP_EVENT_PMU_MSIO_COMP_Msk
1587
1588 #define AON_SLP_EVENT_PMU_BOD_FEDGE_Pos (3U)
1589 #define AON_SLP_EVENT_PMU_BOD_FEDGE_Len (1U)
1590 #define AON_SLP_EVENT_PMU_BOD_FEDGE_Msk (0x1U << AON_SLP_EVENT_PMU_BOD_FEDGE_Pos)
1591 #define AON_SLP_EVENT_PMU_BOD_FEDGE AON_SLP_EVENT_PMU_BOD_FEDGE_Msk
1592
1593 #define AON_SLP_EVENT_EXTWKUP_Pos (2U)
1594 #define AON_SLP_EVENT_EXTWKUP_Len (1U)
1595 #define AON_SLP_EVENT_EXTWKUP_Msk (0x1U << AON_SLP_EVENT_EXTWKUP_Pos)
1596 #define AON_SLP_EVENT_EXTWKUP AON_SLP_EVENT_EXTWKUP_Msk
1597
1598 #define AON_SLP_EVENT_TIMER_Pos (1U)
1599 #define AON_SLP_EVENT_TIMER_Len (1U)
1600 #define AON_SLP_EVENT_TIMER_Msk (0x1U << AON_SLP_EVENT_TIMER_Pos)
1601 #define AON_SLP_EVENT_TIMER AON_SLP_EVENT_TIMER_Msk
1602
1603 #define AON_SLP_EVENT_SMCOSCEN_Pos (0U)
1604 #define AON_SLP_EVENT_SMCOSCEN_Len (1U)
1605 #define AON_SLP_EVENT_SMCOSCEN_Msk (0x1U << AON_SLP_EVENT_SMCOSCEN_Pos)
1606 #define AON_SLP_EVENT_SMCOSCEN AON_SLP_EVENT_SMCOSCEN_Msk
1607
1608 /******************* Bit definition for AON_REG_WARM_BOOT_TIME register **********/
1609 #define AON_WARM_BOOT_TIME_TUNE_C_Pos (24U)
1610 #define AON_WARM_BOOT_TIME_TUNE_C_Len (7U)
1611 #define AON_WARM_BOOT_TIME_TUNE_C_Msk (0x7FU << AON_WARM_BOOT_TIME_TUNE_C_Pos)
1612 #define AON_WARM_BOOT_TIME_TUNE_C AON_WARM_BOOT_TIME_TUNE_C_Msk
1613
1614 #define AON_WARM_BOOT_TIME_DIG_LDO_D_Pos (16U)
1615 #define AON_WARM_BOOT_TIME_DIG_LDO_D_Len (7U)
1616 #define AON_WARM_BOOT_TIME_DIG_LDO_D_Msk (0x7FU << AON_WARM_BOOT_TIME_DIG_LDO_D_Pos)
1617 #define AON_WARM_BOOT_TIME_DIG_LDO_D AON_WARM_BOOT_TIME_DIG_LDO_D_Msk
1618
1619 #define AON_WARM_BOOT_TIME_COUNTER_B_Pos (8U)
1620 #define AON_WARM_BOOT_TIME_COUNTER_B_Len (7U)
1621 #define AON_WARM_BOOT_TIME_COUNTER_B_Msk (0x7FU << AON_WARM_BOOT_TIME_COUNTER_B_Pos)
1622 #define AON_WARM_BOOT_TIME_COUNTER_B AON_WARM_BOOT_TIME_COUNTER_B_Msk
1623
1624 #define AON_WARM_BOOT_TIME_COUNTER_A_Pos (0U)
1625 #define AON_WARM_BOOT_TIME_COUNTER_A_Len (7U)
1626 #define AON_WARM_BOOT_TIME_COUNTER_A_Msk (0x7FU << AON_WARM_BOOT_TIME_COUNTER_A_Pos)
1627 #define AON_WARM_BOOT_TIME_COUNTER_A AON_WARM_BOOT_TIME_COUNTER_A_Msk
1628
1629 /******************* Bit definition for AON_REG_RF_REG_10 register **********/
1630 #define AON_RF_REG_10_MSIO_0 (0U)
1631 #define AON_RF_REG_10_MSIO_1 (1U)
1632 #define AON_RF_REG_10_MSIO_2 (2U)
1633 #define AON_RF_REG_10_MSIO_3 (3U)
1634 #define AON_RF_REG_10_MSIO_4 (4U)
1635 #define AON_RF_REG_10_VTEMP (5U)
1636 #define AON_RF_REG_10_VBATT (6U)
1637 #define AON_RF_REG_10_VREF (7U)
1638
1639 #define AON_RF_REG_10_XO_BYP_Pos (24U)
1640 #define AON_RF_REG_10_XO_BYP_Len (1U)
1641 #define AON_RF_REG_10_XO_BYP_Msk (0x1U << AON_RF_REG_10_XO_BYP_Pos)
1642 #define AON_RF_REG_10_XO_BYP AON_RF_REG_10_XO_BYP_Msk
1643
1644 #define AON_RF_REG_10_COMP_REF_CTRL_LV_Pos (16U)
1645 #define AON_RF_REG_10_COMP_REF_CTRL_LV_Len (6U)
1646 #define AON_RF_REG_10_COMP_REF_CTRL_LV_Msk (0x3FU << AON_RF_REG_10_COMP_REF_CTRL_LV_Pos)
1647 #define AON_RF_REG_10_COMP_REF_CTRL_LV AON_RF_REG_10_COMP_REF_CTRL_LV_Msk
1648
1649 #define AON_RF_REG_10_LPD_REG6_Pos (16U)
1650 #define AON_RF_REG_10_LPD_REG6_Len (8U)
1651 #define AON_RF_REG_10_LPD_REG6_Msk (0xFFU << AON_RF_REG_10_LPD_REG6_Pos)
1652 #define AON_RF_REG_10_LPD_REG6 AON_RF_REG_10_LPD_REG6_Msk
1653
1654 #define AON_RF_REG_10_COMP_BATT_LVL_CTRL_LV_Pos (12U)
1655 #define AON_RF_REG_10_COMP_BATT_LVL_CTRL_LV_Len (3U)
1656 #define AON_RF_REG_10_COMP_BATT_LVL_CTRL_LV_Msk (0x7U << AON_RF_REG_10_COMP_BATT_LVL_CTRL_LV_Pos)
1657 #define AON_RF_REG_10_COMP_BATT_LVL_CTRL_LV AON_RF_REG_10_COMP_BATT_LVL_CTRL_LV_Msk
1658
1659 #define AON_RF_REG_10_ICOMP_CTRL_LV_Pos (8U)
1660 #define AON_RF_REG_10_ICOMP_CTRL_LV_Len (4U)
1661 #define AON_RF_REG_10_ICOMP_CTRL_LV_Msk (0xFU << AON_RF_REG_10_ICOMP_CTRL_LV_Pos)
1662 #define AON_RF_REG_10_ICOMP_CTRL_LV AON_RF_REG_10_ICOMP_CTRL_LV_Msk
1663
1664 #define AON_RF_REG_10_LPD_REG5_Pos (8U)
1665 #define AON_RF_REG_10_LPD_REG5_Len (8U)
1666 #define AON_RF_REG_10_LPD_REG5_Msk (0xFFU << AON_RF_REG_10_LPD_REG5_Pos)
1667 #define AON_RF_REG_10_LPD_REG5 AON_RF_REG_10_LPD_REG5_Msk
1668
1669 #define AON_RF_REG_10_WAKE_COMP_EN_Pos (6U)
1670 #define AON_RF_REG_10_WAKE_COMP_EN_Len (1U)
1671 #define AON_RF_REG_10_WAKE_COMP_EN_Msk (0x1U << AON_RF_REG_10_WAKE_COMP_EN_Pos)
1672 #define AON_RF_REG_10_WAKE_COMP_EN AON_RF_REG_10_WAKE_COMP_EN_Msk
1673
1674 #define AON_RF_REG_10_CHANNEL_SEL_N_Pos (3U)
1675 #define AON_RF_REG_10_CHANNEL_SEL_N_Len (3U)
1676 #define AON_RF_REG_10_CHANNEL_SEL_N_Msk (0x7U << AON_RF_REG_10_CHANNEL_SEL_N_Pos)
1677 #define AON_RF_REG_10_CHANNEL_SEL_N AON_RF_REG_10_CHANNEL_SEL_N_Msk
1678
1679 #define AON_RF_REG_10_CHANNEL_SEL_P_Pos (0U)
1680 #define AON_RF_REG_10_CHANNEL_SEL_P_Len (3U)
1681 #define AON_RF_REG_10_CHANNEL_SEL_P_Msk (0x7U << AON_RF_REG_10_CHANNEL_SEL_P_Pos)
1682 #define AON_RF_REG_10_CHANNEL_SEL_P AON_RF_REG_10_CHANNEL_SEL_P_Msk
1683
1684 #define AON_RF_REG_10_LPD_REG4_Pos (0U)
1685 #define AON_RF_REG_10_LPD_REG4_Len (8U)
1686 #define AON_RF_REG_10_LPD_REG4_Msk (0xFFU << AON_RF_REG_10_LPD_REG4_Pos)
1687 #define AON_RF_REG_10_LPD_REG4 AON_RF_REG_10_LPD_REG4_Msk
1688
1689 /******************* Bit definition for AON_REG_AON_PAD_CTL0 register **************/
1690 #define AON_PAD_CTL0_COMM_TIMER_CLK_SEL_Pos (28U)
1691 #define AON_PAD_CTL0_COMM_TIMER_CLK_SEL_Len (2U)
1692 #define AON_PAD_CTL0_COMM_TIMER_CLK_SEL_Msk (0x3U << AON_PAD_CTL0_COMM_TIMER_CLK_SEL_Pos)
1693 #define AON_PAD_CTL0_COMM_TIMER_CLK_SEL AON_PAD_CTL0_COMM_TIMER_CLK_SEL_Msk
1694 #define AON_PAD_CTL0_COMM_TIMER_CLK_SEL_RNG (0x00 << AON_PAD_CTL0_COMM_TIMER_CLK_SEL_Pos)
1695 #define AON_PAD_CTL0_COMM_TIMER_CLK_SEL_RTC (0x01 << AON_PAD_CTL0_COMM_TIMER_CLK_SEL_Pos)
1696 #define AON_PAD_CTL0_COMM_TIMER_CLK_SEL_RNG2 (0x03 << AON_PAD_CTL0_COMM_TIMER_CLK_SEL_Pos)
1697
1698 #define AON_PAD_CTL0_MCU_OVR_Pos (16U)
1699 #define AON_PAD_CTL0_MCU_OVR_Len (8U)
1700 #define AON_PAD_CTL0_MCU_OVR_Msk (0xFFU << AON_PAD_CTL0_MCU_OVR_Pos)
1701 #define AON_PAD_CTL0_MCU_OVR AON_PAD_CTL0_MCU_OVR_Msk
1702
1703 #define AON_PAD_CTL0_GPO_RTYPE_Pos (8U)
1704 #define AON_PAD_CTL0_GPO_RTYPE_Len (8U)
1705 #define AON_PAD_CTL0_GPO_RTYPE_Msk (0xFFU << AON_PAD_CTL0_GPO_RTYPE_Pos)
1706 #define AON_PAD_CTL0_GPO_RTYPE AON_PAD_CTL0_GPO_RTYPE_Msk
1707
1708 #define AON_PAD_CTL0_GPO_RE_N_Pos (0U)
1709 #define AON_PAD_CTL0_GPO_RE_N_Len (8U)
1710 #define AON_PAD_CTL0_GPO_RE_N_Msk (0xFFU << AON_PAD_CTL0_GPO_RE_N_Pos)
1711 #define AON_PAD_CTL0_GPO_RE_N AON_PAD_CTL0_GPO_RE_N_Msk
1712
1713 /******************* Bit definition for AON_REG_MEM_N_SLP_CTL register ****************/
1714 #define AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos (25U)
1715 #define AON_MEM_CTL_DPAD_LE_WKUP_VAL_Len (1U)
1716 #define AON_MEM_CTL_DPAD_LE_WKUP_VAL_Msk (0x1U << AON_MEM_CTL_DPAD_LE_WKUP_VAL_Pos)
1717 #define AON_MEM_CTL_DPAD_LE_WKUP_VAL AON_MEM_CTL_DPAD_LE_WKUP_VAL_Msk
1718
1719 #define AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos (24U)
1720 #define AON_MEM_CTL_DPAD_LE_SLP_VAL_Len (1U)
1721 #define AON_MEM_CTL_DPAD_LE_SLP_VAL_Msk (0x1U << AON_MEM_CTL_DPAD_LE_SLP_VAL_Pos)
1722 #define AON_MEM_CTL_DPAD_LE_SLP_VAL AON_MEM_CTL_DPAD_LE_SLP_VAL_Msk
1723
1724 #define AON_MEM_CTL_SLP_Pos (16U)
1725 #define AON_MEM_CTL_SLP_Len (7U)
1726 #define AON_MEM_CTL_SLP_Msk (0x7FU << AON_MEM_CTL_SLP_Pos)
1727 #define AON_MEM_CTL_SLP_EN AON_MEM_CTL_SLP_Msk
1728 #define AON_MEM_CTL_SLP_ALL (AON_MEM_CTL_SLP_TRN_OFF_DCDC | \
1729 AON_MEM_CTL_SLP_TRN_OFF_XO | \
1730 AON_MEM_CTL_SLP_TRN_OFF_PLL_EN | \
1731 AON_MEM_CTL_SLP_TRN_OFF_PLL_TUNE | \
1732 AON_MEM_CTL_SLP_TRN_OFF_LDO_EN | \
1733 AON_MEM_CTL_SLP_TRN_OFF_PLL_RST | \
1734 AON_MEM_CTL_SLP_TRN_OFF_IO_LDO_EN)
1735
1736 #define AON_MEM_CTL_SLP_TRN_OFF_IO_LDO_EN_Pos (22U)
1737 #define AON_MEM_CTL_SLP_TRN_OFF_IO_LDO_EN_Len (1U)
1738 #define AON_MEM_CTL_SLP_TRN_OFF_IO_LDO_EN_Msk (0x1U << AON_MEM_CTL_SLP_TRN_OFF_IO_LDO_EN_Pos)
1739 #define AON_MEM_CTL_SLP_TRN_OFF_IO_LDO_EN AON_MEM_CTL_SLP_TRN_OFF_IO_LDO_EN_Msk
1740
1741 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_RST_Pos (21U)
1742 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_RST_Len (1U)
1743 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_RST_Msk (0x1U << AON_MEM_CTL_SLP_TRN_OFF_PLL_RST_Pos)
1744 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_RST AON_MEM_CTL_SLP_TRN_OFF_PLL_RST_Msk
1745
1746 #define AON_MEM_CTL_SLP_TRN_OFF_LDO_EN_Pos (20U)
1747 #define AON_MEM_CTL_SLP_TRN_OFF_LDO_EN_Len (1U)
1748 #define AON_MEM_CTL_SLP_TRN_OFF_LDO_EN_Msk (0x1U << AON_MEM_CTL_SLP_TRN_OFF_LDO_EN_Pos)
1749 #define AON_MEM_CTL_SLP_TRN_OFF_LDO_EN AON_MEM_CTL_SLP_TRN_OFF_LDO_EN_Msk
1750
1751 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_TUNE_Pos (19U)
1752 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_TUNE_Len (1U)
1753 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_TUNE_Msk (0x1U << AON_MEM_CTL_SLP_TRN_OFF_PLL_TUNE_Pos)
1754 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_TUNE AON_MEM_CTL_SLP_TRN_OFF_PLL_TUNE_Msk
1755
1756 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_EN_Pos (18U)
1757 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_EN_Len (1U)
1758 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_EN_Msk (0x1U << AON_MEM_CTL_SLP_TRN_OFF_PLL_EN_Pos)
1759 #define AON_MEM_CTL_SLP_TRN_OFF_PLL_EN AON_MEM_CTL_SLP_TRN_OFF_PLL_EN_Msk
1760
1761 #define AON_MEM_CTL_SLP_TRN_OFF_XO_Pos (17U)
1762 #define AON_MEM_CTL_SLP_TRN_OFF_XO_Len (1U)
1763 #define AON_MEM_CTL_SLP_TRN_OFF_XO_Msk (0x1U << AON_MEM_CTL_SLP_TRN_OFF_XO_Pos)
1764 #define AON_MEM_CTL_SLP_TRN_OFF_XO AON_MEM_CTL_SLP_TRN_OFF_XO_Msk
1765
1766 #define AON_MEM_CTL_SLP_TRN_OFF_DCDC_Pos (16U)
1767 #define AON_MEM_CTL_SLP_TRN_OFF_DCDC_Len (1U)
1768 #define AON_MEM_CTL_SLP_TRN_OFF_DCDC_Msk (0x1U << AON_MEM_CTL_SLP_TRN_OFF_DCDC_Pos)
1769 #define AON_MEM_CTL_SLP_TRN_OFF_DCDC AON_MEM_CTL_SLP_TRN_OFF_DCDC_Msk
1770
1771 #define AON_MEM_CTL_MEM_BTRM_Pos (8U)
1772 #define AON_MEM_CTL_MEM_BTRM_Len (4U)
1773 #define AON_MEM_CTL_MEM_BTRM_Msk (0xFU << AON_MEM_CTL_MEM_BTRM_Pos)
1774 #define AON_MEM_CTL_MEM_BTRM AON_MEM_CTL_MEM_BTRM_Msk
1775
1776 #define AON_MEM_CTL_NON_CRITICAL_MEM_RWM_Pos (6U)
1777 #define AON_MEM_CTL_NON_CRITICAL_MEM_RWM_Len (2U)
1778 #define AON_MEM_CTL_NON_CRITICAL_MEM_RWM_Msk (0x3U << AON_MEM_CTL_NON_CRITICAL_MEM_RWM_Pos)
1779 #define AON_MEM_CTL_NON_CRITICAL_MEM_RWM AON_MEM_CTL_NON_CRITICAL_MEM_RWM_Msk
1780
1781 #define AON_MEM_CTL_NON_CRITICAL_MEM_WM_Pos (5U)
1782 #define AON_MEM_CTL_NON_CRITICAL_MEM_WM_Len (1U)
1783 #define AON_MEM_CTL_NON_CRITICAL_MEM_WM_Msk (0x1U << AON_MEM_CTL_NON_CRITICAL_MEM_WM_Pos)
1784 #define AON_MEM_CTL_NON_CRITICAL_MEM_WM AON_MEM_CTL_NON_CRITICAL_MEM_WM_Msk
1785
1786 #define AON_MEM_CTL_NON_CRITICAL_MEM_RM_Pos (4U)
1787 #define AON_MEM_CTL_NON_CRITICAL_MEM_RM_Len (1U)
1788 #define AON_MEM_CTL_NON_CRITICAL_MEM_RM_Msk (0x1U << AON_MEM_CTL_NON_CRITICAL_MEM_RM_Pos)
1789 #define AON_MEM_CTL_NON_CRITICAL_MEM_RM AON_MEM_CTL_NON_CRITICAL_MEM_RM_Msk
1790
1791 #define AON_MEM_CTL_CRITICAL_MEM_RWM_Pos (2U)
1792 #define AON_MEM_CTL_CRITICAL_MEM_RWM_Len (2U)
1793 #define AON_MEM_CTL_CRITICAL_MEM_RWM_Msk (0x3U << AON_MEM_CTL_CRITICAL_MEM_RWM_Pos)
1794 #define AON_MEM_CTL_CRITICAL_MEM_RWM AON_MEM_CTL_CRITICAL_MEM_RWM_Msk
1795
1796 #define AON_MEM_CTL_CRITICAL_MEM_WM_Pos (1U)
1797 #define AON_MEM_CTL_CRITICAL_MEM_WM_Len (1U)
1798 #define AON_MEM_CTL_CRITICAL_MEM_WM_Msk (0x1U << AON_MEM_CTL_CRITICAL_MEM_WM_Pos)
1799 #define AON_MEM_CTL_CRITICAL_MEM_WM AON_MEM_CTL_CRITICAL_MEM_WM_Msk
1800
1801 #define AON_MEM_CTL_CRITICAL_MEM_RM_Pos (0U)
1802 #define AON_MEM_CTL_CRITICAL_MEM_RM_Len (1U)
1803 #define AON_MEM_CTL_CRITICAL_MEM_RM_Msk (0x1U << AON_MEM_CTL_CRITICAL_MEM_RM_Pos)
1804 #define AON_MEM_CTL_CRITICAL_MEM_RM AON_MEM_CTL_CRITICAL_MEM_RM_Msk
1805
1806 /********************* Bit definition for AON_REG_EXT_WKUP_CTL register ************************************/
1807 #define AON_EXT_WKUP_CTL_WDT_ALARM_Pos (27U)
1808 #define AON_EXT_WKUP_CTL_WDT_ALARM_Len (5U)
1809 #define AON_EXT_WKUP_CTL_WDT_ALARM_Msk (0x1FU << AON_EXT_WKUP_CTL_WDT_ALARM_Pos)
1810 #define AON_EXT_WKUP_CTL_WDT_ALARM AON_EXT_WKUP_CTL_WDT_ALARM_Msk
1811
1812 #define AON_EXT_WKUP_CTL_WDT_RUNNING_Pos (26U)
1813 #define AON_EXT_WKUP_CTL_WDT_RUNNING_Len (1U)
1814 #define AON_EXT_WKUP_CTL_WDT_RUNNING_Msk (0x1U << AON_EXT_WKUP_CTL_WDT_RUNNING_Pos)
1815 #define AON_EXT_WKUP_CTL_WDT_RUNNING AON_EXT_WKUP_CTL_WDT_RUNNING_Msk
1816
1817 #define AON_EXT_WKUP_CTL_WDT_RELOAD_Pos (25U)
1818 #define AON_EXT_WKUP_CTL_WDT_RELOAD_Len (1U)
1819 #define AON_EXT_WKUP_CTL_WDT_RELOAD_Msk (0x1U << AON_EXT_WKUP_CTL_WDT_RELOAD_Pos)
1820 #define AON_EXT_WKUP_CTL_WDT_RELOAD AON_EXT_WKUP_CTL_WDT_RELOAD_Msk
1821
1822 #define AON_EXT_WKUP_CTL_WDT_EN_Pos (24U)
1823 #define AON_EXT_WKUP_CTL_WDT_EN_Len (1U)
1824 #define AON_EXT_WKUP_CTL_WDT_EN_Msk (0x1U << AON_EXT_WKUP_CTL_WDT_EN_Pos)
1825 #define AON_EXT_WKUP_CTL_WDT_EN AON_EXT_WKUP_CTL_WDT_EN_Msk
1826
1827 #define AON_EXT_WKUP_CTL_TYPE_Pos (16U)
1828 #define AON_EXT_WKUP_CTL_TYPE_Len (8U)
1829 #define AON_EXT_WKUP_CTL_TYPE_Msk (0xFFU << AON_EXT_WKUP_CTL_TYPE_Pos)
1830 #define AON_EXT_WKUP_CTL_TYPE AON_EXT_WKUP_CTL_TYPE_Msk
1831
1832 #define AON_EXT_WKUP_CTL_INVERT_Pos (8U)
1833 #define AON_EXT_WKUP_CTL_INVERT_Len (8U)
1834 #define AON_EXT_WKUP_CTL_INVERT_Msk (0xFFU << AON_EXT_WKUP_CTL_INVERT_Pos)
1835 #define AON_EXT_WKUP_CTL_INVERT AON_EXT_WKUP_CTL_INVERT_Msk
1836
1837 #define AON_EXT_WKUP_CTL_SRC_EN_Pos (0U)
1838 #define AON_EXT_WKUP_CTL_SRC_EN_Len (8U)
1839 #define AON_EXT_WKUP_CTL_SRC_EN_Msk (0xFFU << AON_EXT_WKUP_CTL_SRC_EN_Pos)
1840 #define AON_EXT_WKUP_CTL_SRC_EN AON_EXT_WKUP_CTL_SRC_EN_Msk
1841
1842 /********************* Bit definition for AON_REG_AON_PAD_CTL1 register ***************************************/
1843 #define AON_PAD_CTL1_TIMER_READ_SEL_Pos (30U)
1844 #define AON_PAD_CTL1_TIMER_READ_SEL_Len (2U)
1845 #define AON_PAD_CTL1_TIMER_READ_SEL_Msk (0x3U << AON_PAD_CTL1_TIMER_READ_SEL_Pos)
1846 #define AON_PAD_CTL1_TIMER_READ_SEL AON_PAD_CTL1_TIMER_READ_SEL_Msk
1847 #define AON_PAD_CTL1_TIMER_READ_SEL_CAL_TIMER (0x0U << AON_PAD_CTL1_TIMER_READ_SEL_Pos)
1848 #define AON_PAD_CTL1_TIMER_READ_SEL_AON_WDT (0x1U << AON_PAD_CTL1_TIMER_READ_SEL_Pos)
1849 #define AON_PAD_CTL1_TIMER_READ_SEL_SLP_TIMER (0x2U << AON_PAD_CTL1_TIMER_READ_SEL_Pos)
1850 #define AON_PAD_CTL1_TIMER_READ_SEL_CAL_ALARM (0x3U << AON_PAD_CTL1_TIMER_READ_SEL_Pos)
1851
1852 #define AON_PAD_CTL1_MEM_STDBY_VDDISO_OVR_EN_Pos (25U)
1853 #define AON_PAD_CTL1_MEM_STDBY_VDDISO_OVR_EN_Len (1U)
1854 #define AON_PAD_CTL1_MEM_STDBY_VDDISO_OVR_EN_Msk (0x1U << AON_PAD_CTL1_MEM_STDBY_VDDISO_OVR_EN_Pos)
1855 #define AON_PAD_CTL1_MEM_STDBY_VDDISO_OVR_EN AON_PAD_CTL1_MEM_STDBY_VDDISO_OVR_EN_Msk
1856
1857 #define AON_PAD_CTL1_O_AON_GPI_Pos (16U)
1858 #define AON_PAD_CTL1_O_AON_GPI_Len (6U)
1859 #define AON_PAD_CTL1_O_AON_GPI_Msk (0x3FU << AON_PAD_CTL1_O_AON_GPI_Pos)
1860 #define AON_PAD_CTL1_O_AON_GPI AON_PAD_CTL1_O_AON_GPI_Msk
1861
1862 #define AON_PAD_CTL1_AON_GPO_Pos (8U)
1863 #define AON_PAD_CTL1_AON_GPO_Len (8U)
1864 #define AON_PAD_CTL1_AON_GPO_Msk (0xFFU << AON_PAD_CTL1_AON_GPO_Pos)
1865 #define AON_PAD_CTL1_AON_GPO AON_PAD_CTL1_AON_GPO_Msk
1866
1867 #define AON_PAD_CTL1_AON_GPO_OE_N_Pos (0U)
1868 #define AON_PAD_CTL1_AON_GPO_OE_N_Len (8U)
1869 #define AON_PAD_CTL1_AON_GPO_OE_N_Msk (0xFFU << AON_PAD_CTL1_AON_GPO_OE_N_Pos)
1870 #define AON_PAD_CTL1_AON_GPO_OE_N AON_PAD_CTL1_AON_GPO_OE_N_Msk
1871
1872 /********************* Bit definition for AON_REG_MEM_PWR_SLP register **************************************/
1873 #define AON_MEM_PWR_SLP_PD_MCU_KEYRAM_Pos (28U)
1874 #define AON_MEM_PWR_SLP_PD_MCU_KEYRAM_Len (2U)
1875 #define AON_MEM_PWR_SLP_PD_MCU_KEYRAM_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_KEYRAM_Pos)
1876 #define AON_MEM_PWR_SLP_PD_MCU_KEYRAM AON_MEM_PWR_SLP_PD_MCU_KEYRAM_Msk
1877
1878 #define AON_MEM_PWR_SLP_PD_PACKET_MEM_Pos (26U)
1879 #define AON_MEM_PWR_SLP_PD_PACKET_MEM_Len (2U)
1880 #define AON_MEM_PWR_SLP_PD_PACKET_MEM_Msk (0x3U << AON_MEM_PWR_SLP_PD_PACKET_MEM_Pos)
1881 #define AON_MEM_PWR_SLP_PD_PACKET_MEM AON_MEM_PWR_SLP_PD_PACKET_MEM_Msk
1882
1883 #define AON_MEM_PWR_SLP_PD_MCU_ICACHE_Pos (24U)
1884 #define AON_MEM_PWR_SLP_PD_MCU_ICACHE_Len (2U)
1885 #define AON_MEM_PWR_SLP_PD_MCU_ICACHE_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_ICACHE_Pos)
1886 #define AON_MEM_PWR_SLP_PD_MCU_ICACHE AON_MEM_PWR_SLP_PD_MCU_ICACHE_Msk
1887
1888 #define AON_MEM_PWR_SLP_PD_MCU_HTM_Pos (22U)
1889 #define AON_MEM_PWR_SLP_PD_MCU_HTM_Len (2U)
1890 #define AON_MEM_PWR_SLP_PD_MCU_HTM_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_HTM_Pos)
1891 #define AON_MEM_PWR_SLP_PD_MCU_HTM AON_MEM_PWR_SLP_PD_MCU_HTM_Msk
1892
1893 #define AON_MEM_PWR_SLP_PD_MCU_10_Pos (20U)
1894 #define AON_MEM_PWR_SLP_PD_MCU_10_Len (2U)
1895 #define AON_MEM_PWR_SLP_PD_MCU_10_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_10_Pos)
1896 #define AON_MEM_PWR_SLP_PD_MCU_10 AON_MEM_PWR_SLP_PD_MCU_10_Msk
1897
1898 #define AON_MEM_PWR_SLP_PD_MCU_09_Pos (18U)
1899 #define AON_MEM_PWR_SLP_PD_MCU_09_Len (2U)
1900 #define AON_MEM_PWR_SLP_PD_MCU_09_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_09_Pos)
1901 #define AON_MEM_PWR_SLP_PD_MCU_09 AON_MEM_PWR_SLP_PD_MCU_09_Msk
1902
1903 #define AON_MEM_PWR_SLP_PD_MCU_08_Pos (16U)
1904 #define AON_MEM_PWR_SLP_PD_MCU_08_Len (2U)
1905 #define AON_MEM_PWR_SLP_PD_MCU_08_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_08_Pos)
1906 #define AON_MEM_PWR_SLP_PD_MCU_08 AON_MEM_PWR_SLP_PD_MCU_08_Msk
1907
1908 #define AON_MEM_PWR_SLP_PD_MCU_07_Pos (14U)
1909 #define AON_MEM_PWR_SLP_PD_MCU_07_Len (2U)
1910 #define AON_MEM_PWR_SLP_PD_MCU_07_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_07_Pos)
1911 #define AON_MEM_PWR_SLP_PD_MCU_07 AON_MEM_PWR_SLP_PD_MCU_07_Msk
1912
1913 #define AON_MEM_PWR_SLP_PD_MCU_06_Pos (12U)
1914 #define AON_MEM_PWR_SLP_PD_MCU_06_Len (2U)
1915 #define AON_MEM_PWR_SLP_PD_MCU_06_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_06_Pos)
1916 #define AON_MEM_PWR_SLP_PD_MCU_06 AON_MEM_PWR_SLP_PD_MCU_06_Msk
1917
1918 #define AON_MEM_PWR_SLP_PD_MCU_05_Pos (10U)
1919 #define AON_MEM_PWR_SLP_PD_MCU_05_Len (2U)
1920 #define AON_MEM_PWR_SLP_PD_MCU_05_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_05_Pos)
1921 #define AON_MEM_PWR_SLP_PD_MCU_05 AON_MEM_PWR_SLP_PD_MCU_05_Msk
1922
1923 #define AON_MEM_PWR_SLP_PD_MCU_04_Pos (8U)
1924 #define AON_MEM_PWR_SLP_PD_MCU_04_Len (2U)
1925 #define AON_MEM_PWR_SLP_PD_MCU_04_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_04_Pos)
1926 #define AON_MEM_PWR_SLP_PD_MCU_04 AON_MEM_PWR_SLP_PD_MCU_04_Msk
1927
1928 #define AON_MEM_PWR_SLP_PD_MCU_03_Pos (6U)
1929 #define AON_MEM_PWR_SLP_PD_MCU_03_Len (2U)
1930 #define AON_MEM_PWR_SLP_PD_MCU_03_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_03_Pos)
1931 #define AON_MEM_PWR_SLP_PD_MCU_03 AON_MEM_PWR_SLP_PD_MCU_03_Msk
1932
1933 #define AON_MEM_PWR_SLP_PD_MCU_02_Pos (4U)
1934 #define AON_MEM_PWR_SLP_PD_MCU_02_Len (2U)
1935 #define AON_MEM_PWR_SLP_PD_MCU_02_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_02_Pos)
1936 #define AON_MEM_PWR_SLP_PD_MCU_02 AON_MEM_PWR_SLP_PD_MCU_02_Msk
1937
1938 #define AON_MEM_PWR_SLP_PD_MCU_01_Pos (2U)
1939 #define AON_MEM_PWR_SLP_PD_MCU_01_Len (2U)
1940 #define AON_MEM_PWR_SLP_PD_MCU_01_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_01_Pos)
1941 #define AON_MEM_PWR_SLP_PD_MCU_01 AON_MEM_PWR_SLP_PD_MCU_01_Msk
1942
1943 #define AON_MEM_PWR_SLP_PD_MCU_00_Pos (0U)
1944 #define AON_MEM_PWR_SLP_PD_MCU_00_Len (2U)
1945 #define AON_MEM_PWR_SLP_PD_MCU_00_Msk (0x3U << AON_MEM_PWR_SLP_PD_MCU_00_Pos)
1946 #define AON_MEM_PWR_SLP_PD_MCU_00 AON_MEM_PWR_SLP_PD_MCU_00_Msk
1947
1948 /**************************** Bit definition for AON_REG_MEM_PWR_WKUP register *****************************/
1949 #define AON_MEM_PWR_WKUP_PD_MCU_KEYRAM_Pos (28U)
1950 #define AON_MEM_PWR_WKUP_PD_MCU_KEYRAM_Len (2U)
1951 #define AON_MEM_PWR_WKUP_PD_MCU_KEYRAM_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_KEYRAM_Pos)
1952 #define AON_MEM_PWR_WKUP_PD_MCU_KEYRAM AON_MEM_PWR_WKUP_PD_MCU_KEYRAM_Msk
1953
1954 #define AON_MEM_PWR_WKUP_PD_PACKET_MEM_Pos (26U)
1955 #define AON_MEM_PWR_WKUP_PD_PACKET_MEM_Len (2U)
1956 #define AON_MEM_PWR_WKUP_PD_PACKET_MEM_Msk (0x3U << AON_MEM_PWR_WKUP_PD_PACKET_MEM_Pos)
1957 #define AON_MEM_PWR_WKUP_PD_PACKET_MEM AON_MEM_PWR_WKUP_PD_PACKET_MEM_Msk
1958
1959 #define AON_MEM_PWR_WKUP_PD_MCU_ICACHE_Pos (24U)
1960 #define AON_MEM_PWR_WKUP_PD_MCU_ICACHE_Len (2U)
1961 #define AON_MEM_PWR_WKUP_PD_MCU_ICACHE_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_ICACHE_Pos)
1962 #define AON_MEM_PWR_WKUP_PD_MCU_ICACHE AON_MEM_PWR_WKUP_PD_MCU_ICACHE_Msk
1963
1964 #define AON_MEM_PWR_WKUP_PD_MCU_HTM_Pos (22U)
1965 #define AON_MEM_PWR_WKUP_PD_MCU_HTM_Len (2U)
1966 #define AON_MEM_PWR_WKUP_PD_MCU_HTM_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_HTM_Pos)
1967 #define AON_MEM_PWR_WKUP_PD_MCU_HTM AON_MEM_PWR_WKUP_PD_MCU_HTM_Msk
1968
1969 #define AON_MEM_PWR_WKUP_PD_MCU_10_Pos (20U)
1970 #define AON_MEM_PWR_WKUP_PD_MCU_10_Len (2U)
1971 #define AON_MEM_PWR_WKUP_PD_MCU_10_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_10_Pos)
1972 #define AON_MEM_PWR_WKUP_PD_MCU_10 AON_MEM_PWR_WKUP_PD_MCU_10_Msk
1973
1974 #define AON_MEM_PWR_WKUP_PD_MCU_09_Pos (18U)
1975 #define AON_MEM_PWR_WKUP_PD_MCU_09_Len (2U)
1976 #define AON_MEM_PWR_WKUP_PD_MCU_09_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_09_Pos)
1977 #define AON_MEM_PWR_WKUP_PD_MCU_09 AON_MEM_PWR_WKUP_PD_MCU_09_Msk
1978
1979 #define AON_MEM_PWR_WKUP_PD_MCU_08_Pos (16U)
1980 #define AON_MEM_PWR_WKUP_PD_MCU_08_Len (2U)
1981 #define AON_MEM_PWR_WKUP_PD_MCU_08_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_08_Pos)
1982 #define AON_MEM_PWR_WKUP_PD_MCU_08 AON_MEM_PWR_WKUP_PD_MCU_08_Msk
1983
1984 #define AON_MEM_PWR_WKUP_PD_MCU_07_Pos (14U)
1985 #define AON_MEM_PWR_WKUP_PD_MCU_07_Len (2U)
1986 #define AON_MEM_PWR_WKUP_PD_MCU_07_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_07_Pos)
1987 #define AON_MEM_PWR_WKUP_PD_MCU_07 AON_MEM_PWR_WKUP_PD_MCU_07_Msk
1988
1989 #define AON_MEM_PWR_WKUP_PD_MCU_06_Pos (12U)
1990 #define AON_MEM_PWR_WKUP_PD_MCU_06_Len (2U)
1991 #define AON_MEM_PWR_WKUP_PD_MCU_06_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_06_Pos)
1992 #define AON_MEM_PWR_WKUP_PD_MCU_06 AON_MEM_PWR_WKUP_PD_MCU_06_Msk
1993
1994 #define AON_MEM_PWR_WKUP_PD_MCU_05_Pos (10U)
1995 #define AON_MEM_PWR_WKUP_PD_MCU_05_Len (2U)
1996 #define AON_MEM_PWR_WKUP_PD_MCU_05_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_05_Pos)
1997 #define AON_MEM_PWR_WKUP_PD_MCU_05 AON_MEM_PWR_WKUP_PD_MCU_05_Msk
1998
1999 #define AON_MEM_PWR_WKUP_PD_MCU_04_Pos (8U)
2000 #define AON_MEM_PWR_WKUP_PD_MCU_04_Len (2U)
2001 #define AON_MEM_PWR_WKUP_PD_MCU_04_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_04_Pos)
2002 #define AON_MEM_PWR_WKUP_PD_MCU_04 AON_MEM_PWR_WKUP_PD_MCU_04_Msk
2003
2004 #define AON_MEM_PWR_WKUP_PD_MCU_03_Pos (6U)
2005 #define AON_MEM_PWR_WKUP_PD_MCU_03_Len (2U)
2006 #define AON_MEM_PWR_WKUP_PD_MCU_03_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_03_Pos)
2007 #define AON_MEM_PWR_WKUP_PD_MCU_03 AON_MEM_PWR_WKUP_PD_MCU_03_Msk
2008
2009 #define AON_MEM_PWR_WKUP_PD_MCU_02_Pos (4U)
2010 #define AON_MEM_PWR_WKUP_PD_MCU_02_Len (2U)
2011 #define AON_MEM_PWR_WKUP_PD_MCU_02_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_02_Pos)
2012 #define AON_MEM_PWR_WKUP_PD_MCU_02 AON_MEM_PWR_WKUP_PD_MCU_02_Msk
2013
2014 #define AON_MEM_PWR_WKUP_PD_MCU_01_Pos (2U)
2015 #define AON_MEM_PWR_WKUP_PD_MCU_01_Len (2U)
2016 #define AON_MEM_PWR_WKUP_PD_MCU_01_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_01_Pos)
2017 #define AON_MEM_PWR_WKUP_PD_MCU_01 AON_MEM_PWR_WKUP_PD_MCU_01_Msk
2018
2019 #define AON_MEM_PWR_WKUP_PD_MCU_00_Pos (0U)
2020 #define AON_MEM_PWR_WKUP_PD_MCU_00_Len (2U)
2021 #define AON_MEM_PWR_WKUP_PD_MCU_00_Msk (0x3U << AON_MEM_PWR_WKUP_PD_MCU_00_Pos)
2022 #define AON_MEM_PWR_WKUP_PD_MCU_00 AON_MEM_PWR_WKUP_PD_MCU_00_Msk
2023
2024 /*********************** Bit definition for AON_REG_PWR_RET28 register ***************************/
2025 #define AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME_Pos (0U)
2026 #define AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME_Len (32U)
2027 #define AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME_Msk (0xFFFFFFFFU)
2028 #define AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME AON_COMM_TMR_DEEPSLWKUP_DEEPSLTIME_Msk
2029
2030 /*********************** Bit definition for AON_REG_PWR_RET29 register ************************/
2031 #define AON_COMM_TMR_ENBPRESET_TWEXT_Pos (21U)
2032 #define AON_COMM_TMR_ENBPRESET_TWEXT_Len (11U)
2033 #define AON_COMM_TMR_ENBPRESET_TWEXT_Msk (0x07FFU << AON_COMM_TMR_ENBPRESET_TWEXT_Pos)
2034 #define AON_COMM_TMR_ENBPRESET_TWEXT AON_COMM_TMR_ENBPRESET_TWEXT_Msk
2035
2036 #define AON_COMM_TMR_ENBPRESET_TWOSC_Pos (10U)
2037 #define AON_COMM_TMR_ENBPRESET_TWOSC_Len (11U)
2038 #define AON_COMM_TMR_ENBPRESET_TWOSC_Msk (0x07FFU << AON_COMM_TMR_ENBPRESET_TWOSC_Pos)
2039 #define AON_COMM_TMR_ENBPRESET_TWOSC AON_COMM_TMR_ENBPRESET_TWOSC_Msk
2040
2041 #define AON_COMM_TMR_ENBPRESET_TWRM_Pos (0U)
2042 #define AON_COMM_TMR_ENBPRESET_TWRM_Len (10U)
2043 #define AON_COMM_TMR_ENBPRESET_TWRM_Msk (0x03FFU << AON_COMM_TMR_ENBPRESET_TWRM_Pos)
2044 #define AON_COMM_TMR_ENBPRESET_TWRM AON_COMM_TMR_ENBPRESET_TWRM_Msk
2045
2046 /*********************** Bit definition for AON_REG_PWR_RET31 register *********************************/
2047 #define AON_PWR_REG31_FPGA_DBG_MUX_SEL_Pos (0U)
2048 #define AON_PWR_REG31_FPGA_DBG_MUX_SEL_Len (2U)
2049 #define AON_PWR_REG31_FPGA_DBG_MUX_SEL_Msk (0x3U << AON_PWR_REG31_FPGA_DBG_MUX_SEL_Pos)
2050 #define AON_PWR_REG31_FPGA_DBG_MUX_SEL AON_PWR_REG31_FPGA_DBG_MUX_SEL_Msk
2051
2052 /*********************** Bit definition for AON_REG_PSC_CMD register ***************************************/
2053 #define AON_PSC_CMD_MCU_PWR_BUSY_Pos (1U)
2054 #define AON_PSC_CMD_MCU_PWR_BUSY_Len (1U)
2055 #define AON_PSC_CMD_MCU_PWR_BUSY_Msk (0x1U << AON_PSC_CMD_MCU_PWR_BUSY_Pos)
2056 #define AON_PSC_CMD_MCU_PWR_BUSY AON_PSC_CMD_MCU_PWR_BUSY_Msk
2057
2058 #define AON_PSC_CMD_MCU_PWR_REQ_Pos (0U)
2059 #define AON_PSC_CMD_MCU_PWR_REQ_Len (1U)
2060 #define AON_PSC_CMD_MCU_PWR_REQ_Msk (0x1U << AON_PSC_CMD_MCU_PWR_REQ_Pos)
2061 #define AON_PSC_CMD_MCU_PWR_REQ AON_PSC_CMD_MCU_PWR_REQ_Msk
2062
2063 /********************** Bit definition for AON_REG_PSC_CMD_OPC register ************************************/
2064 #define AON_PSC_CMD_OPC_OPCODE_Pos (0U)
2065 #define AON_PSC_CMD_OPC_OPCODE_Len (8U)
2066 #define AON_PSC_CMD_OPC_OPCODE_Msk (0xFFU << AON_PSC_CMD_OPC_OPCODE_Pos)
2067 #define AON_PSC_CMD_OPC_OPCODE AON_PSC_CMD_OPC_OPCODE_Msk
2068 #define AON_PSC_CMD_OPC_OPCODE_LOOPBACK (0x0U << AON_PSC_CMD_OPC_OPCODE_Pos)
2069 #define AON_PSC_CMD_OPC_OPCODE_EF_DIR_ON (0x1U << AON_PSC_CMD_OPC_OPCODE_Pos)
2070 #define AON_PSC_CMD_OPC_OPCODE_32_TIMER_LD (0x2U << AON_PSC_CMD_OPC_OPCODE_Pos)
2071 #define AON_PSC_CMD_OPC_OPCODE_DEEP_SLEEP (0x3U << AON_PSC_CMD_OPC_OPCODE_Pos)
2072 #define AON_PSC_CMD_OPC_OPCODE_EF_DIR_OFF (0x4U << AON_PSC_CMD_OPC_OPCODE_Pos)
2073 #define AON_PSC_CMD_OPC_OPCODE_EXT_CLK (0x5U << AON_PSC_CMD_OPC_OPCODE_Pos)
2074 #define AON_PSC_CMD_OPC_OPCODE_RNG_CLK (0x6U << AON_PSC_CMD_OPC_OPCODE_Pos)
2075 #define AON_PSC_CMD_OPC_OPCODE_RTC_CLK (0x7U << AON_PSC_CMD_OPC_OPCODE_Pos)
2076 #define AON_PSC_CMD_OPC_OPCODE_RNG2_CLK (0x8U << AON_PSC_CMD_OPC_OPCODE_Pos)
2077 #define AON_PSC_CMD_OPC_OPCODE_LD_MEM_SLP_CFG (0x9U << AON_PSC_CMD_OPC_OPCODE_Pos)
2078 #define AON_PSC_CMD_OPC_OPCODE_LD_MEM_WKUP_CFG (0xAU << AON_PSC_CMD_OPC_OPCODE_Pos)
2079 #define AON_PSC_CMD_OPC_OPCODE_DPAD_LE_HI (0xBU << AON_PSC_CMD_OPC_OPCODE_Pos)
2080 #define AON_PSC_CMD_OPC_OPCODE_DPAD_LE_LO (0xCU << AON_PSC_CMD_OPC_OPCODE_Pos)
2081 #define AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_0 (0x10U << AON_PSC_CMD_OPC_OPCODE_Pos)
2082 #define AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_1 (0x11U << AON_PSC_CMD_OPC_OPCODE_Pos)
2083 #define AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_2 (0x12U << AON_PSC_CMD_OPC_OPCODE_Pos)
2084 #define AON_PSC_CMD_OPC_OPCODE_SLP_TIMER_MODE_3 (0x13U << AON_PSC_CMD_OPC_OPCODE_Pos)
2085
2086 /******************* Bit definition for AON_REG_TIMER_VALUE register **********/
2087 #define AON_TIMER_VALUE_PWR_CTL_TIMER_32B_Pos (0U)
2088 #define AON_TIMER_VALUE_PWR_CTL_TIMER_32B_Len (32U)
2089 #define AON_TIMER_VALUE_PWR_CTL_TIMER_32B_Msk (0xFFFFFFFFU)
2090 #define AON_TIMER_VALUE_PWR_CTL_TIMER_32B AON_TIMER_VALUE_PWR_CTL_TIMER_32B_Msk
2091
2092 /********************* Bit definition for AON_REG_TIMER_VAL register **************************************/
2093 #define AON_TIMER_VAL_READ_Pos (0U)
2094 #define AON_TIMER_VAL_READ_Len (32U)
2095 #define AON_TIMER_VAL_READ_Msk (0xFFFFFFFFU)
2096 #define AON_TIMER_VAL_READ AON_TIMER_VAL_READ_Msk
2097
2098 /*********************** Bit definition for AON_REG_FPGA_CTRL register *********************************/
2099 #define AON_REG_FPGA_CTRL_MUX_SEL_Pos (0U)
2100 #define AON_REG_FPGA_CTRL_MUX_SEL_Len (2U)
2101 #define AON_REG_FPGA_CTRL_MUX_SEL_Msk (0x3U << AON_REG_FPGA_CTRL_MUX_SEL_Pos)
2102 #define AON_REG_FPGA_CTRL_MUX_SEL AON_REG_FPGA_CTRL_MUX_SEL_Msk
2103
2104 #define AON_REG_FPGA_CTRL_EXIST_Pos (4U)
2105 #define AON_REG_FPGA_CTRL_EXIST_Len (1U)
2106 #define AON_REG_FPGA_CTRL_EXIST_Msk (0x1U << AON_REG_FPGA_CTRL_EXIST_Pos)
2107 #define AON_REG_FPGA_CTRL_EXIST AON_REG_FPGA_CTRL_EXIST_Msk
2108
2109 /********************** Bit definition for AON_REG_ST_CALIB_REG register ***********************************/
2110 #define AON_ST_CALIB_REG_STCALIB_Pos (0U)
2111 #define AON_ST_CALIB_REG_STCALIB_Len (27U)
2112 #define AON_ST_CALIB_REG_STCALIB_Msk (0x7FFFFFFU << AON_ST_CALIB_REG_STCALIB_Pos)
2113 #define AON_ST_CALIB_REG_STCALIB AON_ST_CALIB_REG_STCALIB_Msk
2114
2115
2116 /* ================================================================================================================= */
2117 /* ================ DMA ================ */
2118 /* ================================================================================================================= */
2119
2120 /******************* Bit definition for DMA_SAR register ********************/
2121 #define DMA_SAR_CSA_Pos (0U)
2122 #define DMA_SAR_CSA_Len (32U)
2123 #define DMA_SAR_CSA_Msk (0xFFFFFFFFU)
2124 #define DMA_SAR_CSA DMA_SAR_CSA_Msk
2125
2126 /******************* Bit definition for DMA_DAR register ********************/
2127 #define DMA_DAR_CDA_Pos (0U)
2128 #define DMA_DAR_CDA_Len (32U)
2129 #define DMA_DAR_CDA_Msk (0xFFFFFFFFU)
2130 #define DMA_DAR_CDA DMA_DAR_CDA_Msk
2131
2132 /******************* Bit definition for DMA_CTLL register *******************/
2133 #define DMA_CTLL_TT_FC_Pos (20U)
2134 #define DMA_CTLL_TT_FC_Len (2U)
2135 #define DMA_CTLL_TT_FC_Msk (0x3U << DMA_CTLL_TT_FC_Pos)
2136 #define DMA_CTLL_TT_FC DMA_CTLL_TT_FC_Msk
2137 #define DMA_CTLL_TT_FC_M2M (0x0U << DMA_CTLL_TT_FC_Pos)
2138 #define DMA_CTLL_TT_FC_M2P (0x1U << DMA_CTLL_TT_FC_Pos)
2139 #define DMA_CTLL_TT_FC_P2M (0x2U << DMA_CTLL_TT_FC_Pos)
2140 #define DMA_CTLL_TT_FC_P2P (0x3U << DMA_CTLL_TT_FC_Pos)
2141
2142 #define DMA_CTLL_SRC_MSIZE_Pos (14U)
2143 #define DMA_CTLL_SRC_MSIZE_Len (3U)
2144 #define DMA_CTLL_SRC_MSIZE_Msk (0x7U << DMA_CTLL_SRC_MSIZE_Pos)
2145 #define DMA_CTLL_SRC_MSIZE DMA_CTLL_SRC_MSIZE_Msk
2146 #define DMA_CTLL_SRC_MSIZE_1 (0x0U << DMA_CTLL_SRC_MSIZE_Pos)
2147 #define DMA_CTLL_SRC_MSIZE_4 (0x1U << DMA_CTLL_SRC_MSIZE_Pos)
2148 #define DMA_CTLL_SRC_MSIZE_8 (0x2U << DMA_CTLL_SRC_MSIZE_Pos)
2149 #define DMA_CTLL_SRC_MSIZE_16 (0x3U << DMA_CTLL_SRC_MSIZE_Pos)
2150 #define DMA_CTLL_SRC_MSIZE_32 (0x4U << DMA_CTLL_SRC_MSIZE_Pos)
2151 #define DMA_CTLL_SRC_MSIZE_64 (0x5U << DMA_CTLL_SRC_MSIZE_Pos)
2152 #define DMA_CTLL_SRC_MSIZE_128 (0x6U << DMA_CTLL_SRC_MSIZE_Pos)
2153 #define DMA_CTLL_SRC_MSIZE_256 (0x7U << DMA_CTLL_SRC_MSIZE_Pos)
2154
2155 #define DMA_CTLL_DST_MSIZE_Pos (11U)
2156 #define DMA_CTLL_DST_MSIZE_Len (3U)
2157 #define DMA_CTLL_DST_MSIZE_Msk (0x7U << DMA_CTLL_DST_MSIZE_Pos)
2158 #define DMA_CTLL_DST_MSIZE DMA_CTLL_DST_MSIZE_Msk
2159 #define DMA_CTLL_DST_MSIZE_1 (0x0U << DMA_CTLL_DST_MSIZE_Pos)
2160 #define DMA_CTLL_DST_MSIZE_4 (0x1U << DMA_CTLL_DST_MSIZE_Pos)
2161 #define DMA_CTLL_DST_MSIZE_8 (0x2U << DMA_CTLL_DST_MSIZE_Pos)
2162 #define DMA_CTLL_DST_MSIZE_16 (0x3U << DMA_CTLL_DST_MSIZE_Pos)
2163 #define DMA_CTLL_DST_MSIZE_32 (0x4U << DMA_CTLL_DST_MSIZE_Pos)
2164 #define DMA_CTLL_DST_MSIZE_64 (0x5U << DMA_CTLL_DST_MSIZE_Pos)
2165 #define DMA_CTLL_DST_MSIZE_128 (0x6U << DMA_CTLL_DST_MSIZE_Pos)
2166 #define DMA_CTLL_DST_MSIZE_256 (0x7U << DMA_CTLL_DST_MSIZE_Pos)
2167
2168 #define DMA_CTLL_SINC_Pos (9U)
2169 #define DMA_CTLL_SINC_Len (2U)
2170 #define DMA_CTLL_SINC_Msk (0x3U << DMA_CTLL_SINC_Pos)
2171 #define DMA_CTLL_SINC DMA_CTLL_SINC_Msk
2172 #define DMA_CTLL_SINC_INC (0x0U << DMA_CTLL_SINC_Pos)
2173 #define DMA_CTLL_SINC_DEC (0x1U << DMA_CTLL_SINC_Pos)
2174 #define DMA_CTLL_SINC_NO (0x2U << DMA_CTLL_SINC_Pos)
2175
2176 #define DMA_CTLL_DINC_Pos (7U)
2177 #define DMA_CTLL_DINC_Len (2U)
2178 #define DMA_CTLL_DINC_Msk (0x3U << DMA_CTLL_DINC_Pos)
2179 #define DMA_CTLL_DINC DMA_CTLL_DINC_Msk
2180 #define DMA_CTLL_DINC_INC (0x0U << DMA_CTLL_DINC_Pos)
2181 #define DMA_CTLL_DINC_DEC (0x1U << DMA_CTLL_DINC_Pos)
2182 #define DMA_CTLL_DINC_NO (0x2U << DMA_CTLL_DINC_Pos)
2183
2184 #define DMA_CTLL_SRC_TR_WIDTH_Pos (4U)
2185 #define DMA_CTLL_SRC_TR_WIDTH_Len (2U)
2186 #define DMA_CTLL_SRC_TR_WIDTH_Msk (0x3U << DMA_CTLL_SRC_TR_WIDTH_Pos)
2187 #define DMA_CTLL_SRC_TR_WIDTH DMA_CTLL_SRC_TR_WIDTH_Msk
2188 #define DMA_CTLL_SRC_TR_WIDTH_8 (0x0U << DMA_CTLL_SRC_TR_WIDTH_Pos)
2189 #define DMA_CTLL_SRC_TR_WIDTH_16 (0x1U << DMA_CTLL_SRC_TR_WIDTH_Pos)
2190 #define DMA_CTLL_SRC_TR_WIDTH_32 (0x2U << DMA_CTLL_SRC_TR_WIDTH_Pos)
2191
2192 #define DMA_CTLL_DST_TR_WIDTH_Pos (1U)
2193 #define DMA_CTLL_DST_TR_WIDTH_Len (2U)
2194 #define DMA_CTLL_DST_TR_WIDTH_Msk (0x3U << DMA_CTLL_DST_TR_WIDTH_Pos)
2195 #define DMA_CTLL_DST_TR_WIDTH DMA_CTLL_DST_TR_WIDTH_Msk
2196 #define DMA_CTLL_DST_TR_WIDTH_8 (0x0U << DMA_CTLL_DST_TR_WIDTH_Pos)
2197 #define DMA_CTLL_DST_TR_WIDTH_16 (0x1U << DMA_CTLL_DST_TR_WIDTH_Pos)
2198 #define DMA_CTLL_DST_TR_WIDTH_32 (0x2U << DMA_CTLL_DST_TR_WIDTH_Pos)
2199
2200 #define DMA_CTLL_INT_EN_Pos (0U)
2201 #define DMA_CTLL_INT_EN_Len (1U)
2202 #define DMA_CTLL_INT_EN_Msk (0x1U << DMA_CTLL_INT_EN_Pos)
2203 #define DMA_CTLL_INI_EN DMA_CTLL_INT_EN_Msk
2204
2205 /******************* Bit definition for DMA_CTLH register *******************/
2206 #define DMA_CTLH_BLOCK_TS_Pos (0U)
2207 #define DMA_CTLH_BLOCK_TS_Len (12U)
2208 #define DMA_CTLH_BLOCK_TS_Msk (0xFFFU << DMA_CTLH_BLOCK_TS_Pos)
2209 #define DMA_CTLH_BLOCK_TS DMA_CTLH_BLOCK_TS_Msk
2210
2211 /******************* Bit definition for DMA_CFGL register *******************/
2212 #define DMA_CFGL_RELOAD_DST_Pos (31U)
2213 #define DMA_CFGL_RELOAD_DST_Len (1U)
2214 #define DMA_CFGL_RELOAD_DST_Msk (0x1U << DMA_CFGL_RELOAD_DST_Pos)
2215 #define DMA_CFGL_RELOAD_DST DMA_CFGL_RELOAD_DST_Msk
2216
2217 #define DMA_CFGL_RELOAD_SRC_Pos (30U)
2218 #define DMA_CFGL_RELOAD_SRC_Len (1U)
2219 #define DMA_CFGL_RELOAD_SRC_Msk (0x1U << DMA_CFGL_RELOAD_SRC_Pos)
2220 #define DMA_CFGL_RELOAD_SRC DMA_CFGL_RELOAD_SRC_Msk
2221
2222 #define DMA_CFGL_HS_SEL_SRC_Pos (11U)
2223 #define DMA_CFGL_HS_SEL_SRC_Len (1U)
2224 #define DMA_CFGL_HS_SEL_SRC_Msk (0x1U << DMA_CFGL_HS_SEL_SRC_Pos)
2225 #define DMA_CFGL_HS_SEL_SRC DMA_CFGL_HS_SEL_SRC_Msk
2226
2227 #define DMA_CFGL_HS_SEL_DST_Pos (10U)
2228 #define DMA_CFGL_HS_SEL_DST_Len (1U)
2229 #define DMA_CFGL_HS_SEL_DST_Msk (0x1U << DMA_CFGL_HS_SEL_DST_Pos)
2230 #define DMA_CFGL_HS_SEL_DST DMA_CFGL_HS_SEL_DST_Msk
2231
2232 #define DMA_CFGL_FIFO_EMPTY_Pos (9U)
2233 #define DMA_CFGL_FIFO_EMPTY_Len (1U)
2234 #define DMA_CFGL_FIFO_EMPTY_Msk (0x1U << DMA_CFGL_FIFO_EMPTY_Pos)
2235 #define DMA_CFGL_FIFO_EMPTY DMA_CFGL_FIFO_EMPTY_Msk
2236
2237 #define DMA_CFGL_CH_SUSP_Pos (8U)
2238 #define DMA_CFGL_CH_SUSP_Len (1U)
2239 #define DMA_CFGL_CH_SUSP_Msk (0x1U << DMA_CFGL_CH_SUSP_Pos)
2240 #define DMA_CFGL_CH_SUSP DMA_CFGL_CH_SUSP_Msk
2241
2242 #define DMA_CFGL_CH_PRIOR_Pos (5U)
2243 #define DMA_CFGL_CH_PRIOR_Len (3U)
2244 #define DMA_CFGL_CH_PRIOR_Msk (0x7U << DMA_CFGL_CH_PRIOR_Pos)
2245 #define DMA_CFGL_CH_PRIOR DMA_CFGL_CH_PRIOR_Msk
2246 #define DMA_CFGL_CH_PRIOR_0 (0x0U << DMA_CFGL_CH_PRIOR_Pos)
2247 #define DMA_CFGL_CH_PRIOR_1 (0x1U << DMA_CFGL_CH_PRIOR_Pos)
2248 #define DMA_CFGL_CH_PRIOR_2 (0x2U << DMA_CFGL_CH_PRIOR_Pos)
2249 #define DMA_CFGL_CH_PRIOR_3 (0x3U << DMA_CFGL_CH_PRIOR_Pos)
2250 #define DMA_CFGL_CH_PRIOR_4 (0x4U << DMA_CFGL_CH_PRIOR_Pos)
2251 #define DMA_CFGL_CH_PRIOR_5 (0x5U << DMA_CFGL_CH_PRIOR_Pos)
2252 #define DMA_CFGL_CH_PRIOR_6 (0x6U << DMA_CFGL_CH_PRIOR_Pos)
2253 #define DMA_CFGL_CH_PRIOR_7 (0x7U << DMA_CFGL_CH_PRIOR_Pos)
2254
2255 /******************* Bit definition for DMA_CFGH register ********************/
2256 #define DMA_CFGH_DST_PER_Pos (11U)
2257 #define DMA_CFGH_DST_PER_Len (4U)
2258 #define DMA_CFGH_DST_PER_Msk (0xFU << DMA_CFGH_DST_PER_Pos)
2259 #define DMA_CFGH_DST_PER DMA_CFGH_DST_PER_Msk
2260
2261 #define DMA_CFGH_SRC_PER_Pos (7U)
2262 #define DMA_CFGH_SRC_PER_Len (4U)
2263 #define DMA_CFGH_SRC_PER_Msk (0xFU << DMA_CFGH_SRC_PER_Pos)
2264 #define DMA_CFGH_SRC_PER DMA_CFGH_SRC_PER_Msk
2265
2266 #define DMA_CFGH_PROTCTL_Pos (2U)
2267 #define DMA_CFGH_PROTCTL_Len (3U)
2268 #define DMA_CFGH_PROTCTL_Msk (0x7U << DMA_CFGH_PROTCTL_Pos)
2269 #define DMA_CFGH_PROTCTL DMA_CFGH_PROTCTL_Msk
2270
2271 #define DMA_CFGH_FIFO_MODE_Pos (2U)
2272 #define DMA_CFGH_FIFO_MODE_Len (1U)
2273 #define DMA_CFGH_FIFO_MODE_Msk (0x1U << DMA_CFGH_FIFO_MODE_Pos)
2274 #define DMA_CFGH_FIFO_MODE DMA_CFGH_FIFO_MODE_Msk
2275
2276 /******************* Bit definition for DMA_RAW_TFR register *****************/
2277 #define DMA_RAW_TFR_Pos (0U)
2278 #define DMA_RAW_TFR_Len (8U)
2279 #define DMA_RAW_TFR_Msk (0xFFU << DMA_RAW_TFR_Pos)
2280 #define DMA_RAW_TFR DMA_RAW_TFR_Msk
2281
2282 /******************* Bit definition for DMA_RAW_BLK register *****************/
2283 #define DMA_RAW_BLK_Pos (0U)
2284 #define DMA_RAW_BLK_Len (8U)
2285 #define DMA_RAW_BLK_Msk (0xFFU << DMA_RAW_BLK_Pos)
2286 #define DMA_RAW_BLK DMA_RAW_BLK_Msk
2287
2288 /******************* Bit definition for DMA_RAW_SRC_TRN register *************/
2289 #define DMA_RAW_SRC_TRN_Pos (0U)
2290 #define DMA_RAW_SRC_TRN_Len (8U)
2291 #define DMA_RAW_SRC_TRN_Msk (0xFFU << DMA_RAW_SRC_TRN_Pos)
2292 #define DMA_RAW_SRC_TRN DMA_RAW_SRC_TRN_Msk
2293
2294 /******************* Bit definition for DMA_RAW_DST_TRN register *************/
2295 #define DMA_RAW_DST_TRN_Pos (0U)
2296 #define DMA_RAW_DST_TRN_Len (8U)
2297 #define DMA_RAW_DST_TRN_Msk (0xFFU << DMA_RAW_DST_TRN_Pos)
2298 #define DMA_RAW_DST_TRN DMA_RAW_DST_TRN_Msk
2299
2300 /******************* Bit definition for DMA_RAW_ERR register *****************/
2301 #define DMA_RAW_ERR_Pos (0U)
2302 #define DMA_RAW_ERR_Len (8U)
2303 #define DMA_RAW_ERR_Msk (0xFFU << DMA_RAW_ERR_Pos)
2304 #define DMA_RAW_ERR DMA_RAW_ERR_Msk
2305
2306 /******************* Bit definition for DMA_STAT_TFR register ****************/
2307 #define DMA_STAT_TFR_Pos (0U)
2308 #define DMA_STAT_TFR_Len (8U)
2309 #define DMA_STAT_TFR_Msk (0xFFUL << DMA_STAT_TFR_Pos)
2310 #define DMA_STAT_TFR DMA_STAT_TFR_Msk
2311
2312 /******************* Bit definition for DMA_STAT_BLK register ****************/
2313 #define DMA_STAT_BLK_Pos (0U)
2314 #define DMA_STAT_BLK_Len (8U)
2315 #define DMA_STAT_BLK_Msk (0xFFU << DMA_STAT_BLK_Pos)
2316 #define DMA_STAT_BLK DMA_STAT_BLK_Msk
2317
2318 /******************* Bit definition for DMA_STAT_SRC_TRN register ************/
2319 #define DMA_STAT_SRC_TRN_Pos (0U)
2320 #define DMA_STAT_SRC_TRN_Len (8U)
2321 #define DMA_STAT_SRC_TRN_Msk (0xFFU << DMA_STAT_SRC_TRN_Pos)
2322 #define DMA_STAT_SRC_TRN DMA_STAT_SRC_TRN_Msk
2323
2324 /******************* Bit definition for DMA_STAT_DST_TRN register ************/
2325 #define DMA_STAT_DST_TRN_Pos (0U)
2326 #define DMA_STAT_DST_TRN_Len (8U)
2327 #define DMA_STAT_DST_TRN_Msk (0xFFU << DMA_STAT_DST_TRN_Pos)
2328 #define DMA_STAT_DST_TRN DMA_STAT_DST_TRN_Msk
2329
2330 /******************* Bit definition for DMA_STAT_ERR register ****************/
2331 #define DMA_STAT_ERR_Pos (0U)
2332 #define DMA_STAT_ERR_Len (8U)
2333 #define DMA_STAT_ERR_Msk (0xFFU << DMA_STAT_ERR_Pos)
2334 #define DMA_STAT_ERR DMA_STAT_ERR_Msk
2335
2336 /******************* Bit definition for DMA_MASK_TFR register ****************/
2337 #define DMA_MASK_TFR_WE_Pos (8U)
2338 #define DMA_MASK_TFR_WE_Len (8U)
2339 #define DMA_MASK_TFR_WE_Msk (0xFFU << DMA_MASK_TFR_WE_Pos)
2340 #define DMA_MASK_TFR_WE DMA_MASK_TFR_WE_Msk
2341
2342 #define DMA_MASK_TFR_Pos (0U)
2343 #define DMA_MASK_TFR_Len (8U)
2344 #define DMA_MASK_TFR_Msk (0xFFU << DMA_MASK_TFR_Pos)
2345 #define DMA_MASK_TFR DMA_MASK_TFR_Msk
2346
2347 /******************* Bit definition for DMA_MASK_BLK register ****************/
2348 #define DMA_MASK_BLK_WE_Pos (8U)
2349 #define DMA_MASK_BLK_WE_Len (8U)
2350 #define DMA_MASK_BLK_WE_Msk (0xFFU << DMA_MASK_BLK_WE_Pos)
2351 #define DMA_MASK_BLK_WE DMA_MASK_BLK_WE_Msk
2352
2353 #define DMA_MASK_BLK_Pos (0U)
2354 #define DMA_MASK_BLK_Len (8U)
2355 #define DMA_MASK_BLK_Msk (0xFFU << DMA_MASK_BLK_Pos)
2356 #define DMA_MASK_BLK DMA_MASK_BLK_Msk
2357
2358 /******************* Bit definition for DMA_MASK_SRC_TRN register ************/
2359 #define DMA_MASK_SRC_TRN_WE_Pos (8U)
2360 #define DMA_MASK_SRC_TRN_WE_Len (8U)
2361 #define DMA_MASK_SRC_TRN_WE_Msk (0x1U << DMA_MASK_SRC_TRN_WE_Pos)
2362 #define DMA_MASK_SRC_TRN_WE DMA_MASK_SRC_TRN_WE_Msk
2363
2364 #define DMA_MASK_SRC_TRN_Pos (0U)
2365 #define DMA_MASK_SRC_TRN_Len (8U)
2366 #define DMA_MASK_SRC_TRN_Msk (0xFFU << DMA_MASK_SRC_TRN_Pos)
2367 #define DMA_MASK_SRC_TRN DMA_MASK_SRC_TRN_Msk
2368
2369 /******************* Bit definition for DMA_MASK_DST_TRN register ************/
2370 #define DMA_MASK_DST_TRN_WE_Pos (8U)
2371 #define DMA_MASK_DST_TRN_WE_Len (8U)
2372 #define DMA_MASK_DST_TRN_WE_Msk (0xFFU << DMA_MASK_DST_TRN_WE_Pos)
2373 #define DMA_MASK_DST_TRN_WE DMA_MASK_DST_TRN_WE_Msk
2374
2375 #define DMA_MASK_DST_TRN_Pos (0U)
2376 #define DMA_MASK_DST_TRN_Len (8U)
2377 #define DMA_MASK_DST_TRN_Msk (0xFFU << DMA_MASK_DST_TRN_Pos)
2378 #define DMA_MASK_DST_TRN DMA_MASK_DST_TRN_Msk
2379
2380 /******************* Bit definition for DMA_MASK_ERR register ****************/
2381 #define DMA_MASK_ERR_WE_Pos (8U)
2382 #define DMA_MASK_ERR_WE_Len (8U)
2383 #define DMA_MASK_ERR_WE_Msk (0xFFU << DMA_MASK_ERR_WE_Pos)
2384 #define DMA_MASK_ERR_WE DMA_MASK_ERR_WE_Msk
2385
2386 #define DMA_MASK_ERR_Pos (0U)
2387 #define DMA_MASK_ERR_Len (8U)
2388 #define DMA_MASK_ERR_Msk (0xFFU << DMA_MASK_ERR_Pos)
2389 #define DMA_MASK_ERR DMA_MASK_ERR_Msk
2390
2391 /******************* Bit definition for DMA_CLR_TFR register *****************/
2392 #define DMA_CLR_TFR_Pos (0U)
2393 #define DMA_CLR_TFR_Len (8U)
2394 #define DMA_CLR_TFR_Msk (0xFFU << DMA_CLR_TFR_Pos)
2395 #define DMA_CLR_TFR DMA_CLR_TFR_Msk
2396
2397 /******************* Bit definition for DMA_CLR_BLK register *****************/
2398 #define DMA_CLR_BLK_Pos (0U)
2399 #define DMA_CLR_BLK_Len (8U)
2400 #define DMA_CLR_BLK_Msk (0xFFU << DMA_CLR_BLK_Pos)
2401 #define DMA_CLR_BLK DMA_CLR_BLK_Msk
2402
2403 /******************* Bit definition for DMA_CLR_SRC_TRN register *************/
2404 #define DMA_CLR_SRC_TRN_Pos (0U)
2405 #define DMA_CLR_SRC_TRN_Len (8U)
2406 #define DMA_CLR_SRC_TRN_Msk (0xFFU << DMA_CLR_SRC_TRN_Pos)
2407 #define DMA_CLR_SRC_TRN DMA_CLR_SRC_TRN_Msk
2408
2409 /******************* Bit definition for DMA_CLR_DST_TRN register *************/
2410 #define DMA_CLR_DST_TRN_Pos (0U)
2411 #define DMA_CLR_DST_TRN_Len (8U)
2412 #define DMA_CLR_DST_TRN_Msk (0xFFU << DMA_CLR_DST_TRN_Pos)
2413 #define DMA_CLR_DST_TRN DMA_CLR_DST_TRN_Msk
2414
2415 /******************* Bit definition for DMA_CLR_ERR register *****************/
2416 #define DMA_CLR_ERR_Pos (0U)
2417 #define DMA_CLR_ERR_Len (8U)
2418 #define DMA_CLR_ERR_Msk (0xFFU << DMA_CLR_ERR_Pos)
2419 #define DMA_CLR_ERR DMA_CLR_ERR_Msk
2420
2421 /******************* Bit definition for DMA_STATUS_INT register **************/
2422 #define DMA_STAT_INT_ERR_Pos (4U)
2423 #define DMA_STAT_INT_ERR_Len (1U)
2424 #define DMA_STAT_INT_ERR_Msk (0x1U << DMA_STAT_INT_ERR_Pos)
2425 #define DMA_STAT_INT_ERR DMA_STAT_INT_ERR_Msk
2426
2427 #define DMA_STAT_INT_DST_Pos (3U)
2428 #define DMA_STAT_INT_DST_Len (1U)
2429 #define DMA_STAT_INT_DST_Msk (0x1U << DMA_STAT_INT_DST_Pos)
2430 #define DMA_STAT_INT_DST DMA_STAT_INT_DST_Msk
2431
2432 #define DMA_STAT_INT_SRC_Pos (2U)
2433 #define DMA_STAT_INT_SRC_Len (1U)
2434 #define DMA_STAT_INT_SRC_Msk (0x1U << DMA_STAT_INT_SRC_Pos)
2435 #define DMA_STAT_INT_SRC DMA_STAT_INT_SRC_Msk
2436
2437 #define DMA_STAT_INT_BLK_Pos (1U)
2438 #define DMA_STAT_INT_BLK_Len (1U)
2439 #define DMA_STAT_INT_BLK_Msk (0x1U << DMA_STAT_INT_BLK_Pos)
2440 #define DMA_STAT_INT_BLK DMA_STAT_INT_BLK_Msk
2441
2442 #define DMA_STAT_INT_TFR_Pos (0U)
2443 #define DMA_STAT_INT_TFR_Len (1U)
2444 #define DMA_STAT_INT_TFR_Msk (0x1U << DMA_STAT_INT_TFR_Pos)
2445 #define DMA_STAT_INT_TFR DMA_STAT_INT_TFR_Msk
2446
2447 /******************* Bit definition for DMA_REQ_SRC_REG register *************/
2448 #define DMA_REQ_SRC_WE_Pos (8U)
2449 #define DMA_REQ_SRC_WE_Len (8U)
2450 #define DMA_REQ_SRC_WE_Msk (0xFFU << DMA_REQ_SRC_WE_Pos)
2451 #define DMA_REQ_SRC_WE DMA_REQ_SRC_WE_Msk
2452
2453 #define DMA_REQ_SRC_Pos (0U)
2454 #define DMA_REQ_SRC_Len (8U)
2455 #define DMA_REQ_SRC_Msk (0xFFU << DMA_REQ_SRC_Pos)
2456 #define DMA_REQ_SRC DMA_REQ_SRC_Msk
2457
2458 /******************* Bit definition for DMA_REQ_DST_REG register *************/
2459 #define DMA_REQ_DST_WE_Pos (8U)
2460 #define DMA_REQ_DST_WE_Len (8U)
2461 #define DMA_REQ_DST_WE_Msk (0xFFU << DMA_REQ_DST_WE_Pos)
2462 #define DMA_REQ_DST_WE DMA_REQ_DST_WE_Msk
2463
2464 #define DMA_REQ_DST_Pos (0U)
2465 #define DMA_REQ_DST_Len (8U)
2466 #define DMA_REQ_DST_Msk (0xFFU << DMA_REQ_DST_Pos)
2467 #define DMA_REQ_DST DMA_REQ_DST_Msk
2468
2469 /******************* Bit definition for DMA_SGL_REQ_SRC_REG register *********/
2470 #define DMA_SGL_REQ_SRC_WE_Pos (8U)
2471 #define DMA_SGL_REQ_SRC_WE_Len (8U)
2472 #define DMA_SGL_REQ_SRC_WE_Msk (0xFFU << DMA_SGL_REQ_SRC_WE_Pos)
2473 #define DMA_SGL_REQ_SRC_WE DMA_SGL_REQ_SRC_WE_Msk
2474
2475 #define DMA_SGL_REQ_SRC_Pos (0U)
2476 #define DMA_SGL_REQ_SRC_Len (8U)
2477 #define DMA_SGL_REQ_SRC_Msk (0xFFU << DMA_SGL_REQ_SRC_Pos)
2478 #define DMA_SGL_REQ_SRC DMA_SGL_REQ_SRC_Msk
2479
2480 /******************* Bit definition for DMA_SGL_REQ_DST_REG register *********/
2481 #define DMA_SGL_REQ_DST_WE_Pos (8U)
2482 #define DMA_SGL_REQ_DST_WE_Len (8U)
2483 #define DMA_SGL_REQ_DST_WE_Msk (0xFFU << DMA_SGL_REQ_DST_WE_Pos)
2484 #define DMA_SGL_REQ_DST_WE DMA_SGL_REQ_DST_WE_Msk
2485
2486 #define DMA_SGL_REQ_DST_Pos (0U)
2487 #define DMA_SGL_REQ_DST_Len (8U)
2488 #define DMA_SGL_REQ_DST_Msk (0xFFU << DMA_SGL_REQ_DST_Pos)
2489 #define DMA_SGL_REQ_DST DMA_SGL_REQ_DST_Msk
2490
2491 /******************* Bit definition for DMA_LST_SRC_REG register *********/
2492 #define DMA_LST_SRC_WE_Pos (8U)
2493 #define DMA_LST_SRC_WE_Len (8U)
2494 #define DMA_LST_SRC_WE_Msk (0xFFU << DMA_LST_SRC_WE_Pos)
2495 #define DMA_LST_SRC_WE DMA_LST_SRC_WE_Msk
2496
2497 #define DMA_LST_SRC_Pos (0U)
2498 #define DMA_LST_SRC_Len (8U)
2499 #define DMA_LST_SRC_Msk (0xFFU << DMA_LST_SRC_Pos)
2500 #define DMA_LST_SRC DMA_LST_SRC_Msk
2501
2502 /******************* Bit definition for DMA_LST_DST_REG register *********/
2503 #define DMA_LST_DST_WE_Pos (8U)
2504 #define DMA_LST_DST_WE_Len (8U)
2505 #define DMA_LST_DST_WE_Msk (0xFFU << DMA_LST_DST_WE_Pos)
2506 #define DMA_LST_DST_WE DMA_LST_DST_WE_Msk
2507
2508 #define DMA_LST_DST_Pos (0U)
2509 #define DMA_LST_DST_Len (8U)
2510 #define DMA_LST_DST_Msk (0xFFU << DMA_LST_DST_Pos)
2511 #define DMA_LST_DST DMA_LST_DST_Msk
2512
2513 /******************* Bit definition for DMA_CFG_REG register ****************/
2514 #define DMA_MODULE_CFG_EN_Pos (0U)
2515 #define DMA_MODULE_CFG_EN_Len (1U)
2516 #define DMA_MODULE_CFG_EN_Msk (0x1U << DMA_MODULE_CFG_EN_Pos)
2517 #define DMA_MODULE_CFG_EN DMA_MODULE_CFG_EN_Msk
2518
2519 /******************* Bit definition for DMA_CH_EN_REG register **************/
2520 #define DMA_CH_WE_EN_Pos (8U)
2521 #define DMA_CH_WE_EN_Len (8U)
2522 #define DMA_CH_WE_EN_Msk (0xFFU << DMA_CH_WE_EN_Pos)
2523 #define DMA_CH_WE_EN DMA_CH_WE_EN_Msk
2524
2525 #define DMA_CH_EN_Pos (0U)
2526 #define DMA_CH_EN_Len (8U)
2527 #define DMA_CH_EN_Msk (0xFFU << DMA_CH_EN_Pos)
2528 #define DMA_CH_EN DMA_CH_EN_Msk
2529
2530
2531 /* ================================================================================================================= */
2532 /* ================ DUAL_TIMER ================ */
2533 /* ================================================================================================================= */
2534
2535 /******************* Bit definition for DUAL_TIMER_RELOAD register ************/
2536 #define DUAL_TIMER_RELOAD_RELOAD_Pos (0U)
2537 #define DUAL_TIMER_RELOAD_RELOAD_Len (32U)
2538 #define DUAL_TIMER_RELOAD_RELOAD_Msk (0xFFFFFFFFU)
2539 #define DUAL_TIMER_RELOAD_RELOAD DUAL_TIMER_RELOAD_RELOAD_Msk
2540
2541 /******************* Bit definition for DUAL_TIMER_VALUE register *************/
2542 #define DUAL_TIMER_VALUE_VALUE_Pos (0U)
2543 #define DUAL_TIMER_VALUE_VALUE_Len (32U)
2544 #define DUAL_TIMER_VALUE_VALUE_Msk (0xFFFFFFFFU)
2545 #define DUAL_TIMER_VALUE_VALUE DUAL_TIMER_VALUE_VALUE_Msk
2546
2547 /******************* Bit definition for DUAL_TIMER_CTRL register **************/
2548 #define DUAL_TIMER_CTRL_EN_Pos (7U)
2549 #define DUAL_TIMER_CTRL_EN_Len (1U)
2550 #define DUAL_TIMER_CTRL_EN_Msk (0x1U << DUAL_TIMER_CTRL_EN_Pos)
2551 #define DUAL_TIMER_CTRL_EN DUAL_TIMER_CTRL_EN_Msk
2552
2553 #define DUAL_TIMER_CTRL_MODE_Pos (6U)
2554 #define DUAL_TIMER_CTRL_MODE_Len (1U)
2555 #define DUAL_TIMER_CTRL_MODE_Msk (0x1U << DUAL_TIMER_CTRL_MODE_Pos)
2556 #define DUAL_TIMER_CTRL_MODE DUAL_TIMER_CTRL_MODE_Msk
2557
2558 #define DUAL_TIMER_CTRL_INTEN_Pos (5U)
2559 #define DUAL_TIMER_CTRL_INTEN_Len (1U)
2560 #define DUAL_TIMER_CTRL_INTEN_Msk (0x1U << DUAL_TIMER_CTRL_INTEN_Pos)
2561 #define DUAL_TIMER_CTRL_INTEN DUAL_TIMER_CTRL_INTEN_Msk
2562
2563 #define DUAL_TIMER_CTRL_PRE_Pos (2U)
2564 #define DUAL_TIMER_CTRL_PRE_Len (2U)
2565 #define DUAL_TIMER_CTRL_PRE_Msk (0x3U << DUAL_TIMER_CTRL_PRE_Pos)
2566 #define DUAL_TIMER_CTRL_PRE DUAL_TIMER_CTRL_PRE_Msk
2567
2568 #define DUAL_TIMER_CTRL_SIZE_Pos (1U)
2569 #define DUAL_TIMER_CTRL_SIZE_Len (1U)
2570 #define DUAL_TIMER_CTRL_SIZE_Msk (0x1U << DUAL_TIMER_CTRL_SIZE_Pos)
2571 #define DUAL_TIMER_CTRL_SIZE DUAL_TIMER_CTRL_SIZE_Msk
2572
2573 #define DUAL_TIMER_CTRL_ONESHOT_Pos (0U)
2574 #define DUAL_TIMER_CTRL_ONESHOT_Len (1U)
2575 #define DUAL_TIMER_CTRL_ONESHOT_Msk (0x1U << DUAL_TIMER_CTRL_ONESHOT_Pos)
2576 #define DUAL_TIMER_CTRL_ONESHOT DUAL_TIMER_CTRL_ONESHOT_Msk
2577
2578 /******************* Bit definition for DUAL_TIMER_INT_CLR register ***********/
2579 #define DUAL_TIMER_INT_CLR_Pos (0U)
2580 #define DUAL_TIMER_INT_CLR_Len (32U)
2581 #define DUAL_TIMER_INT_CLR_Msk (0xFFFFFFFFU)
2582 #define DUAL_TIMER_INT_CLR DUAL_TIMER_INT_CLR_Msk
2583
2584 /******************* Bit definition for DUAL_TIMER_RAW_INT_STAT register ******/
2585 #define DUAL_TIMER_RIS_RTI_Pos (0U)
2586 #define DUAL_TIMER_RIS_RTI_Len (1U)
2587 #define DUAL_TIMER_RIS_RTI_Msk (0x1U << DUAL_TIMER_RIS_RTI_Pos)
2588 #define DUAL_TIMER_RIS_RTI DUAL_TIMER_RIS_RTI_Msk
2589
2590 /******************* Bit definition for DUAL_TIMER_INT_STAT register **********/
2591 #define DUAL_TIMER_ISR_TI_Pos (0U)
2592 #define DUAL_TIMER_ISR_TI_Len (1U)
2593 #define DUAL_TIMER_ISR_TI_Msk (0x1U << DUAL_TIMER_ISR_TI_Pos)
2594 #define DUAL_TIMER_ISR_TI DUAL_TIMER_ISR_TI_Msk
2595
2596 /******************* Bit definition for DUAL_TIMER_BGLOAD register ************/
2597 #define DUAL_TIMER_BLR_BL_Pos (0U)
2598 #define DUAL_TIMER_BLR_BL_Len (32U)
2599 #define DUAL_TIMER_BLR_BL_Msk (0xFFFFFFFFU)
2600 #define DUAL_TIMER_BLR_BL DUAL_TIMER_BLR_BL_Msk
2601
2602
2603 /* ================================================================================================================= */
2604 /* ================ GPIO ================ */
2605 /* ================================================================================================================= */
2606
2607 /******************* Bit definition for GPIO_DATA register ******************/
2608 #define GPIO_DATA_Pos (0U)
2609 #define GPIO_DATA_Len (16U)
2610 #define GPIO_DATA_Msk (0xFFFFU << GPIO_DATA_Pos)
2611 #define GPIO_DATA GPIO_DATA_Msk /**< Data */
2612
2613 /******************* Bit definition for GPIO_DATAOUT register ***************/
2614 #define GPIO_DATAOUT_Pos (0U)
2615 #define GPIO_DATAOUT_Len (16U)
2616 #define GPIO_DATAOUT_Msk (0xFFFFU << GPIO_DATAOUT_Pos)
2617 #define GPIO_DATAOUT GPIO_DATAOUT_Msk /**< Data Output */
2618
2619 /******************* Bit definition for GPIO_OUTENSET register ***************/
2620 #define GPIO_OUTENSET_Pos (0U)
2621 #define GPIO_OUTENSET_Len (16U)
2622 #define GPIO_OUTENSET_Msk (0xFFFFU << GPIO_OUTENSET_Pos)
2623 #define GPIO_OUTENSET GPIO_OUTENSET_Msk /**< Data Output Enable Set*/
2624
2625 /******************* Bit definition for GPIO_OUTENCLR register ***************/
2626 #define GPIO_OUTENCLR_Pos (0U)
2627 #define GPIO_OUTENCLR_Len (16U)
2628 #define GPIO_OUTENCLR_Msk (0xFFFFU << GPIO_OUTENCLR_Pos)
2629 #define GPIO_OUTENCLR GPIO_OUTENCLR_Msk /**< Data Output Enable Clear */
2630
2631 /******************* Bit definition for GPIO_INTENSET register ***************/
2632 #define GPIO_INTENSET_Pos (0U)
2633 #define GPIO_INTENSET_Len (16U)
2634 #define GPIO_INTENSET_Msk (0xFFFFU << GPIO_INTENSET_Pos)
2635 #define GPIO_INTENSET GPIO_INTENSET_Msk /**< Interrupt Enable Set */
2636
2637 /******************* Bit definition for GPIO_INTENCLR register ***************/
2638 #define GPIO_INTENCLR_Pos (0U)
2639 #define GPIO_INTENCLR_Len (16U)
2640 #define GPIO_INTENCLR_Msk (0xFFFFU << GPIO_INTENCLR_Pos)
2641 #define GPIO_INTENCLR GPIO_INTENCLR_Msk /**< Interrupt Enable clear */
2642
2643 /******************* Bit definition for GPIO_INTTYPESET register ***************/
2644 #define GPIO_INTTYPESET_Pos (0U)
2645 #define GPIO_INTTYPESET_Len (16U)
2646 #define GPIO_INTTYPESET_Msk (0xFFFFU << GPIO_INTTYPESET_Pos)
2647 #define GPIO_INTTYPESET GPIO_INTTYPESET_Msk /**< Interrupt Type Set */
2648
2649 /******************* Bit definition for GPIO_INTTYPECLR register ***************/
2650 #define GPIO_INTTYPECLR_Pos (0U)
2651 #define GPIO_INTTYPECLR_Len (16U)
2652 #define GPIO_INTTYPECLR_Msk (0xFFFFU << GPIO_INTTYPECLR_Pos)
2653 #define GPIO_INTTYPECLR GPIO_INTTYPECLR_Msk /**< Interrupt Type Clear */
2654
2655 /******************* Bit definition for GPIO_INTPOLSET register ***************/
2656 #define GPIO_INTPOLSET_Pos (0U)
2657 #define GPIO_INTPOLSET_Len (16U)
2658 #define GPIO_INTPOLSET_Msk (0xFFFFU << GPIO_INTPOLSET_Pos)
2659 #define GPIO_INTPOLSET GPIO_INTPOLSET_Msk /**< Interrupt Polarity-level Set */
2660
2661 /******************* Bit definition for GPIO_INTPOLCLR register ***************/
2662 #define GPIO_INTPOLCLR_Pos (0U)
2663 #define GPIO_INTPOLCLR_Len (16U)
2664 #define GPIO_INTPOLCLR_Msk (0xFFFFU << GPIO_INTPOLCLR_Pos)
2665 #define GPIO_INTPOLCLR GPIO_INTPOLCLR_Msk /**< Interrupt Polarity-level Clear */
2666
2667 /******************* Bit definition for GPIO_INTSTAT register ***************/
2668 #define GPIO_INTSTAT_Pos (0U)
2669 #define GPIO_INTSTAT_Len (16U)
2670 #define GPIO_INTSTAT_Msk (0xFFFFU << GPIO_INTSTAT_Pos)
2671 #define GPIO_INTSTAT GPIO_INTSTAT_Msk /**< Interrupt Status */
2672
2673 /******************* Bit definition for GPIO_MASKLOWBYTE register ***********/
2674 #define GPIO_MASKLOWBYTE_DATA_Pos (0U)
2675 #define GPIO_MASKLOWBYTE_DATA_Len (8U)
2676 #define GPIO_MASKLOWBYTE_DATA_Msk (0xFFU << GPIO_MASKLOWBYTE_DATA_Pos)
2677 #define GPIO_MASKLOWBYTE_DATA GPIO_MASKLOWBYTE_DATA_Msk /**< Lower 8 bits masked access */
2678
2679 /******************* Bit definition for GPIO_MASKLOWBYTE register ***********/
2680 #define GPIO_MASKHIGHBYTE_DATA_Pos (8U)
2681 #define GPIO_MASKHIGHBYTE_DATA_Len (8U)
2682 #define GPIO_MASKHIGHBYTE_DATA_Msk (0xFFU << GPIO_MASKHIGHBYTE_DATA_Pos)
2683 #define GPIO_MASKHIGHBYTE_DATA GPIO_MASKHIGHBYTE_DATA /**< Higher 8 bits masked access */
2684
2685
2686 /* ================================================================================================================= */
2687 /* ================ HMAC ================ */
2688 /* ================================================================================================================= */
2689
2690 /******************* Bit definition for HMAC_CTRL register ******************/
2691 #define HMAC_CTRL_ENABLE_Pos (0U)
2692 #define HMAC_CTRL_ENABLE_Len (1U)
2693 #define HMAC_CTRL_ENABLE_Msk (1U << HMAC_CTRL_ENABLE_Pos)
2694 #define HMAC_CTRL_ENABLE HMAC_CTRL_ENABLE_Msk
2695
2696 #define HMAC_CTRL_START_DMA_Pos (1U)
2697 #define HMAC_CTRL_START_DMA_Len (1U)
2698 #define HMAC_CTRL_START_DMA_Msk (1U << HMAC_CTRL_START_DMA_Pos)
2699 #define HMAC_CTRL_START_DMA HMAC_CTRL_START_DMA_Msk
2700
2701 #define HMAC_CTRL_ENABLE_RKEY_Pos (2U)
2702 #define HMAC_CTRL_ENABLE_RKEY_Len (1U)
2703 #define HMAC_CTRL_ENABLE_RKEY_Msk (1U << HMAC_CTRL_ENABLE_RKEY_Pos)
2704 #define HMAC_CTRL_ENABLE_RKEY HMAC_CTRL_ENABLE_RKEY_Msk
2705
2706 #define HMAC_CTRL_LASTTRANSFER_Pos (3U)
2707 #define HMAC_CTRL_LASTTRANSFER_Len (1U)
2708 #define HMAC_CTRL_LASTTRANSFER_Msk (1U << HMAC_CTRL_LASTTRANSFER_Pos)
2709 #define HMAC_CTRL_LASTTRANSFER HMAC_CTRL_LASTTRANSFER_Msk
2710
2711 /******************* Bit definition for HMAC_CONFIG register ****************/
2712 #define HMAC_CONFIG_ENABLE_USERHASH_Pos (0U)
2713 #define HMAC_CONFIG_ENABLE_USERHASH_Len (1U)
2714 #define HMAC_CONFIG_ENABLE_USERHASH_Msk (1U << HMAC_CONFIG_ENABLE_USERHASH_Pos)
2715 #define HMAC_CONFIG_ENABLE_USERHASH HMAC_CONFIG_ENABLE_USERHASH_Msk
2716
2717 #define HMAC_CONFIG_ENDIAN_Pos (1U)
2718 #define HMAC_CONFIG_ENDIAN_Len (1U)
2719 #define HMAC_CONFIG_ENDIAN_Msk (1U << HMAC_CONFIG_ENDIAN_Pos)
2720 #define HMAC_CONFIG_ENDIAN HMAC_CONFIG_ENDIAN_Msk
2721
2722 #define HMAC_CONFIG_KEYTYPE_Pos (2U)
2723 #define HMAC_CONFIG_KEYTYPE_Len (2U)
2724 #define HMAC_CONFIG_KEYTYPE_Msk (3U << HMAC_CONFIG_KEYTYPE_Pos)
2725 #define HMAC_CONFIG_KEYTYPE HMAC_CONFIG_KEYTYPE_Msk
2726
2727 #define HMAC_CONFIG_CALCTYPE_Pos (4U)
2728 #define HMAC_CONFIG_CALCTYPE_Len (1U)
2729 #define HMAC_CONFIG_CALCTYPE_Msk (1U << HMAC_CONFIG_CALCTYPE_Pos)
2730 #define HMAC_CONFIG_CALCTYPE HMAC_CONFIG_CALCTYPE_Msk
2731
2732 #define HMAC_CONFIG_PRIVATE_Pos (5U)
2733 #define HMAC_CONFIG_PRIVATE_Len (1U)
2734 #define HMAC_CONFIG_PRIVATE_Msk (1U << HMAC_CONFIG_PRIVATE_Pos)
2735 #define HMAC_CONFIG_PRIVATE HMAC_CONFIG_PRIVATE_Msk
2736
2737 /******************* Bit definition for HMAC_STATUS register ****************/
2738 #define HMAC_STATUS_DATAREADY_SHA_Pos (0U)
2739 #define HMAC_STATUS_DATAREADY_SHA_Len (1U)
2740 #define HMAC_STATUS_DATAREADY_SHA_Msk (1U << HMAC_STATUS_DATAREADY_SHA_Pos)
2741 #define HMAC_STATUS_DATAREADY_SHA HMAC_STATUS_DATAREADY_SHA_Msk
2742
2743 #define HMAC_STATUS_MESSAGEDONE_DMA_Pos (1U)
2744 #define HMAC_STATUS_MESSAGEDONE_DMA_Len (1U)
2745 #define HMAC_STATUS_MESSAGEDONE_DMA_Msk (1U << HMAC_STATUS_MESSAGEDONE_DMA_Pos)
2746 #define HMAC_STATUS_MESSAGEDONE_DMA HMAC_STATUS_MESSAGEDONE_DMA_Msk
2747
2748 #define HMAC_STATUS_TRANSERR_DMA_Pos (2U)
2749 #define HMAC_STATUS_TRANSERR_DMA_Len (1U)
2750 #define HMAC_STATUS_TRANSERR_DMA_Msk (1U << HMAC_STATUS_TRANSERR_DMA_Pos)
2751 #define HMAC_STATUS_TRANSERR_DMA HMAC_STATUS_TRANSERR_DMA_Msk
2752
2753 #define HMAC_STATUS_KEYVALID_Pos (3U)
2754 #define HMAC_STATUS_KEYVALID_Len (1U)
2755 #define HMAC_STATUS_KEYVALID_Msk (1U << HMAC_STATUS_KEYVALID_Pos)
2756 #define HMAC_STATUS_KEYVALID HMAC_STATUS_KEYVALID_Msk
2757
2758 #define HMAC_STATUS_DATAREADY_HMAC_Pos (4U)
2759 #define HMAC_STATUS_DATAREADY_HMAC_Len (1U)
2760 #define HMAC_STATUS_DATAREADY_HMAC_Msk (1U << HMAC_STATUS_DATAREADY_HMAC_Pos)
2761 #define HMAC_STATUS_DATAREADY_HMAC HMAC_STATUS_DATAREADY_HMAC_Msk
2762
2763 #define HMAC_STATUS_TRANSDONE_DMA_Pos (5U)
2764 #define HMAC_STATUS_TRANSDONE_DMA_Len (1U)
2765 #define HMAC_STATUS_TRANSDONE_DMA_Msk (1U << HMAC_STATUS_TRANSDONE_DMA_Pos)
2766 #define HMAC_STATUS_TRANSDONE_DMA HMAC_STATUS_TRANSDONE_DMA_Msk
2767
2768 /******************* Bit definition for HMAC_TRAN_SIZE register *************/
2769 #define HMAC_TRANSIZE_Pos (0U)
2770 #define HMAC_TRANSIZE_Len (15U)
2771 #define HMAC_TRANSIZE_Msk (0x7FFFU << HMAC_TRANSIZE_Pos)
2772 #define HMAC_TRANSIZE HMAC_TRANSIZE_Msk
2773
2774 /******************* Bit definition for HMAC_INTERRUPT register *************/
2775 #define HMAC_INTERRUPT_DONE_Pos (0U)
2776 #define HMAC_INTERRUPT_DONE_Len (1U)
2777 #define HMAC_INTERRUPT_DONE_Msk (1U << HMAC_INTERRUPT_DONE_Pos)
2778 #define HMAC_INTERRUPT_DONE HMAC_INTERRUPT_DONE_Msk
2779
2780 #define HMAC_INTERRUPT_ENABLE_Pos (1U)
2781 #define HMAC_INTERRUPT_ENABLE_Len (1U)
2782 #define HMAC_INTERRUPT_ENABLE_Msk (1U << HMAC_INTERRUPT_ENABLE_Pos)
2783 #define HMAC_INTERRUPT_ENABLE HMAC_INTERRUPT_ENABLE_Msk
2784
2785 /******************* Bit definition for HMAC_RSTART_ADDR register ***********/
2786 #define HMAC_RSTART_ADDR_Pos (0U)
2787 #define HMAC_RSTART_ADDR_Len (32U)
2788 #define HMAC_RSTART_ADDR_Msk (0xFFFFFFFFU << HMAC_RSTART_ADDR_Pos)
2789 #define HMAC_RSTART_ADDR HMAC_RSTART_ADDR_Msk
2790
2791 /******************* Bit definition for HMAC_WSTART_ADDR register ***********/
2792 #define HMAC_WSTART_ADDR_Pos (0U)
2793 #define HMAC_WSTART_ADDR_Len (32U)
2794 #define HMAC_WSTART_ADDR_Msk (0xFFFFFFFFU << HMAC_WSTART_ADDR_Pos)
2795 #define HMAC_WSTART_ADDR HMAC_WSTART_ADDR_Msk
2796
2797 /******************* Bit definition for HMAC_USER_HASH register *************/
2798 #define HMAC_USERHASH_Pos (0U)
2799 #define HMAC_USERHASH_Len (32U)
2800 #define HMAC_USERHASH_Msk (0xFFFFFFFFU << HMAC_USERHASH_Pos)
2801 #define HMAC_USERHASH HMAC_USERHASH_Msk
2802
2803 /******************* Bit definition for HMAC_FIFO_OUT register **************/
2804 #define HMAC_FIFO_OUT_Pos (0U)
2805 #define HMAC_FIFO_OUT_Len (32U)
2806 #define HMAC_FIFO_OUT_Msk (0xFFFFFFFFU << HMAC_FIFO_OUT_Pos)
2807 #define HMAC_FIFO_OUT HMAC_FIFO_OUT_Msk
2808
2809 /******************* Bit definition for HMAC_MESSAGE_FIFO register **********/
2810 #define HMAC_FIFO_MESSAGE_Pos (0U)
2811 #define HMAC_FIFO_MESSAGE_Len (32U)
2812 #define HMAC_FIFO_MESSAGE_Msk (0xFFFFFFFFU << HMAC_FIFO_MESSAGE_Pos)
2813 #define HMAC_FIFO_MESSAGE HMAC_FIFO_MESSAGE_Msk
2814
2815 /******************* Bit definition for HMAC_KEY register *******************/
2816 #define HMAC_KEY_Pos (0U)
2817 #define HMAC_KEY_Len (32U)
2818 #define HMAC_KEY_Msk (0xFFFFFFFFU << HMAC_KEY_Pos)
2819 #define HMAC_KEY HMAC_KEY_Msk
2820
2821 /******************* Bit definition for HMAC_KEY_ADDR register **************/
2822 #define HMAC_KEY_ADDR_Pos (0U)
2823 #define HMAC_KEY_ADDR_Len (32U)
2824 #define HMAC_KEY_ADDR_Msk (0xFFFFFFFFU << HMAC_KEY_ADDR_Pos)
2825 #define HMAC_KEY_ADDR HMAC_KEY_ADDR_Msk
2826
2827 /******************* Bit definition for HMAC_KPORT_MASK register ************/
2828 #define HMAC_KPORT_MASK_Pos (0U)
2829 #define HMAC_KPORT_MASK_Len (32U)
2830 #define HMAC_KPORT_MASK_Msk (0xFFFFFFFFU << HMAC_KPORT_MASK_Pos)
2831 #define HMAC_KPORT_MASK HMAC_KPORT_MASK_Msk
2832
2833
2834 /* ================================================================================================================= */
2835 /* ================ I2C ================ */
2836 /* ================================================================================================================= */
2837 #define I2C_TXFIFO_SIZE (8U)
2838 #define I2C_RXFIFO_SIZE (8U)
2839
2840 /******************* Bit definition for IC_CON register *********************/
2841 #define I2C_CON_BUS_CLR_FEATURE_CTRL_Pos (11U)
2842 #define I2C_CON_BUS_CLR_FEATURE_CTRL_Len (1U)
2843 #define I2C_CON_BUS_CLR_FEATURE_CTRL_Msk (0x1U << I2C_CON_BUS_CLR_FEATURE_CTRL_Pos)
2844 #define I2C_CON_BUS_CLR_FEATURE_CTRL I2C_CON_BUS_CLR_FEATURE_CTRL_Msk
2845
2846 #define I2C_CON_STOP_DET_IF_MASTER_ACTIVE_Pos (10U)
2847 #define I2C_CON_STOP_DET_IF_MASTER_ACTIVE_Len (1U)
2848 #define I2C_CON_STOP_DET_IF_MASTER_ACTIVE_Msk (0x1U << I2C_CON_STOP_DET_IF_MASTER_ACTIVE_Pos)
2849 #define I2C_CON_STOP_DET_IF_MASTER_ACTIVE I2C_CON_STOP_DET_IF_MASTER_ACTIVE_Msk
2850
2851 #define I2C_CON_RX_FIFO_FULL_HLD_CTRL_Pos (9U)
2852 #define I2C_CON_RX_FIFO_FULL_HLD_CTRL_Len (1U)
2853 #define I2C_CON_RX_FIFO_FULL_HLD_CTRL_Msk (0x1U << I2C_CON_RX_FIFO_FULL_HLD_CTRL_Pos)
2854 #define I2C_CON_RX_FIFO_FULL_HLD_CTRL I2C_CON_RX_FIFO_FULL_HLD_CTRL_Msk
2855
2856 #define I2C_CON_TX_EMPTY_CTRL_Pos (8U)
2857 #define I2C_CON_TX_EMPTY_CTRL_Len (1U)
2858 #define I2C_CON_TX_EMPTY_CTRL_Msk (0x1U << I2C_CON_TX_EMPTY_CTRL_Pos)
2859 #define I2C_CON_TX_EMPTY_CTRL I2C_CON_TX_EMPTY_CTRL_Msk
2860
2861 #define I2C_CON_STOP_DET_IF_ADDRESSED_Pos (7U)
2862 #define I2C_CON_STOP_DET_IF_ADDRESSED_Len (1U)
2863 #define I2C_CON_STOP_DET_IF_ADDRESSED_Msk (0x1U << I2C_CON_STOP_DET_IF_ADDRESSED_Pos)
2864 #define I2C_CON_STOP_DET_IF_ADDRESSED I2C_CON_STOP_DET_IF_ADDRESSED_Msk
2865
2866 #define I2C_CON_SLV_DIS_Pos (6U)
2867 #define I2C_CON_SLV_DIS_Len (1U)
2868 #define I2C_CON_SLV_DIS_Msk (0x1U << I2C_CON_SLV_DIS_Pos)
2869 #define I2C_CON_SLV_DIS I2C_CON_SLV_DIS_Msk
2870
2871 #define I2C_CON_RESTART_EN_Pos (5U)
2872 #define I2C_CON_RESTART_EN_Len (1U)
2873 #define I2C_CON_RESTART_EN_Msk (0x1U << I2C_CON_RESTART_EN_Pos)
2874 #define I2C_CON_RESTART_EN I2C_CON_RESTART_EN_Msk
2875
2876 #define I2C_CON_10BITADDR_MST_Pos (4U)
2877 #define I2C_CON_10BITADDR_MST_Len (1U)
2878 #define I2C_CON_10BITADDR_MST_Msk (0x1U << I2C_CON_10BITADDR_MST_Pos)
2879 #define I2C_CON_10BITADDR_MST I2C_CON_10BITADDR_MST_Msk
2880
2881 #define I2C_CON_10BITADDR_SLV_Pos (3U)
2882 #define I2C_CON_10BITADDR_SLV_Len (1U)
2883 #define I2C_CON_10BITADDR_SLV_Msk (0x1U << I2C_CON_10BITADDR_SLV_Pos)
2884 #define I2C_CON_10BITADDR_SLV I2C_CON_10BITADDR_SLV_Msk
2885
2886 #define I2C_CON_SPEED_Pos (1U)
2887 #define I2C_CON_SPEED_Len (2U)
2888 #define I2C_CON_SPEED_Msk (0x3U << I2C_CON_SPEED_Pos)
2889 #define I2C_CON_SPEED I2C_CON_SPEED_Msk
2890 #define I2C_CON_SPEED_STANDARD (0x1U << I2C_CON_SPEED_Pos)
2891 #define I2C_CON_SPEED_FAST (0x2U << I2C_CON_SPEED_Pos)
2892 #define I2C_CON_SPEED_HIGH (0x3U << I2C_CON_SPEED_Pos)
2893
2894 #define I2C_CON_MST_MODE_Pos (0U)
2895 #define I2C_CON_MST_MODE_Len (1U)
2896 #define I2C_CON_MST_MODE_Msk (0x1U << I2C_CON_MST_MODE_Pos)
2897 #define I2C_CON_MST_MODE I2C_CON_MST_MODE_Msk
2898
2899 /******************* Bit definition for IC_TAR register *********************/
2900 #define I2C_TAR_SPECIAL_Pos (11U)
2901 #define I2C_TAR_SPECIAL_Len (1U)
2902 #define I2C_TAR_SPECIAL_Msk (0x1U << I2C_TAR_SPECIAL_Pos)
2903 #define I2C_TAR_SPECIAL I2C_TAR_SPECIAL_Msk
2904
2905 #define I2C_TAR_GC_OR_START_Pos (10U)
2906 #define I2C_TAR_GC_OR_START_Len (1U)
2907 #define I2C_TAR_GC_OR_START_Msk (0x0U << I2C_TAR_GC_OR_START_Pos)
2908 #define I2C_TAR_GC_OR_START I2C_TAR_GC_OR_START_Msk
2909
2910 #define I2C_TAR_ADDR_Pos (0U)
2911 #define I2C_TAR_ADDR_Len (10U)
2912 #define I2C_TAR_ADDR_Msk (0x3FFU << I2C_TAR_ADDR_Pos)
2913 #define I2C_TAR_ADDR I2C_TAR_ADDR_Msk
2914 #define I2C_TAR_ADDR_7BIT (0x07FU << I2C_TAR_ADDR_Pos)
2915 #define I2C_TAR_ADDR_10BIT (0x3FFU << I2C_TAR_ADDR_Pos)
2916
2917 /******************* Bit definition for IC_SAR register *********************/
2918 #define I2C_SAR_ADDR_Pos (0U)
2919 #define I2C_SAR_ADDR_Len (10U)
2920 #define I2C_SAR_ADDR_Msk (0x3FFU << I2C_SAR_ADDR_Pos)
2921 #define I2C_SAR_ADDR_7BIT (0x07FU << I2C_SAR_ADDR_Pos)
2922 #define I2C_SAR_ADDR_10BIT (0x3FFU << I2C_SAR_ADDR_Pos)
2923
2924 /******************* Bit definition for IC_HS_MADDR register ****************/
2925 #define I2C_HS_MADDR_HS_MAR_Pos (0U)
2926 #define I2C_HS_MADDR_HS_MAR_Len (3U)
2927 #define I2C_HS_MADDR_HS_MAR_Msk (0x7U << I2C_HS_MADDR_HS_MAR_Pos)
2928 #define I2C_HS_MADDR_HS_MAR I2C_HS_MADDR_HS_MAR_Msk
2929
2930 /******************* Bit definition for IC_DATA_CMD register ****************/
2931 #define I2C_DATA_CMD_RESTART_Pos (10U)
2932 #define I2C_DATA_CMD_RESTART_Len (1U)
2933 #define I2C_DATA_CMD_RESTART_Msk (0x1U << I2C_DATA_CMD_RESTART_Pos)
2934 #define I2C_DATA_CMD_RESTART I2C_DATA_CMD_RESTART_Msk
2935
2936 #define I2C_DATA_CMD_STOP_Pos (9U)
2937 #define I2C_DATA_CMD_STOP_Len (1U)
2938 #define I2C_DATA_CMD_STOP_Msk (0x1U << I2C_DATA_CMD_STOP_Pos)
2939 #define I2C_DATA_CMD_STOP I2C_DATA_CMD_STOP_Msk
2940
2941 #define I2C_DATA_CMD_CMD_Pos (8U)
2942 #define I2C_DATA_CMD_CMD_Len (1U)
2943 #define I2C_DATA_CMD_CMD_Msk (0x1U << I2C_DATA_CMD_CMD_Pos)
2944 #define I2C_DATA_CMD_CMD I2C_DATA_CMD_CMD_Msk
2945
2946 #define I2C_DATA_CMD_DAT_Pos (0U)
2947 #define I2C_DATA_CMD_DAT_Len (8U)
2948 #define I2C_DATA_CMD_DAT_Msk (0xFFU << I2C_DATA_CMD_DAT_Pos)
2949 #define I2C_DATA_CMD_DAT I2C_DATA_CMD_DAT_Msk
2950
2951 /******************* Bit definition for IC_SS_SCL_HCNT register *************/
2952 #define I2C_SS_SCL_HCNT_Pos (0U)
2953 #define I2C_SS_SCL_HCNT_Len (16U)
2954 #define I2C_SS_SCL_HCNT_Msk (0xFFFFU << I2C_SS_SCL_HCNT_Pos)
2955 #define I2C_SS_SCL_HCNT I2C_SS_SCL_HCNT_Msk
2956
2957 /******************* Bit definition for IC_SS_SCL_LCNT register *************/
2958 #define I2C_SS_SCL_LCNT_Pos (0U)
2959 #define I2C_SS_SCL_LCNT_Len (16U)
2960 #define I2C_SS_SCL_LCNT_Msk (0xFFFFU << I2C_SS_SCL_LCNT_Pos)
2961 #define I2C_SS_SCL_LCNT I2C_SS_SCL_LCNT_Msk
2962
2963 /******************* Bit definition for IC_FS_SCL_HCNT register *************/
2964 #define I2C_FS_SCL_HCNT_Pos (0U)
2965 #define I2C_FS_SCL_HCNT_Len (16U)
2966 #define I2C_FS_SCL_HCNT_Msk (0xFFFFU << I2C_FS_SCL_HCNT_Pos)
2967 #define I2C_FS_SCL_HCNT I2C_FS_SCL_HCNT_Msk
2968
2969 /******************* Bit definition for IC_FS_SCL_LCNT register *************/
2970 #define I2C_FS_SCL_LCNT_Pos (0U)
2971 #define I2C_FS_SCL_LCNT_Len (16U)
2972 #define I2C_FS_SCL_LCNT_Msk (0xFFFFU << I2C_FS_SCL_LCNT_Pos)
2973 #define I2C_FS_SCL_LCNT I2C_FS_SCL_LCNT_Msk
2974
2975 /******************* Bit definition for IC_HS_SCL_HCNT register *************/
2976 #define I2C_HS_SCL_HCNT_Pos (0U)
2977 #define I2C_HS_SCL_HCNT_Len (16U)
2978 #define I2C_HS_SCL_HCNT_Msk (0xFFFFU << I2C_HS_SCL_HCNT_Pos)
2979 #define I2C_HS_SCL_HCNT I2C_HS_SCL_HCNT_Msk
2980
2981 /******************* Bit definition for IC_HS_SCL_LCNT register *************/
2982 #define I2C_HS_SCL_LCNT_Pos (0U)
2983 #define I2C_HS_SCL_LCNT_Len (16U)
2984 #define I2C_HS_SCL_LCNT_Msk (0xFFFFU << I2C_HS_SCL_LCNT_Pos)
2985 #define I2C_HS_SCL_LCNT I2C_HS_SCL_LCNT_Msk
2986
2987 /** Bit definition for IC_INTR_STAT/IC_INTR_MASK/IC_RAW_INTR_STAT register **/
2988 #define I2C_INTR_ALL (0x3FFFU)
2989
2990 #define I2C_INTR_MST_ON_HOLD_Pos (13U)
2991 #define I2C_INTR_MST_ON_HOLD_Len (1U)
2992 #define I2C_INTR_MST_ON_HOLD_Msk (0x1U << I2C_INTR_MST_ON_HOLD_Pos)
2993 #define I2C_INTR_MST_ON_HOLD I2C_INTR_MST_ON_HOLD_Msk
2994
2995 #define I2C_INTR_RESTART_DET_Pos (12U)
2996 #define I2C_INTR_RESTART_DET_Len (1U)
2997 #define I2C_INTR_RESTART_DET_Msk (0x1U << I2C_INTR_RESTART_DET_Pos)
2998 #define I2C_INTR_RESTART_DET I2C_INTR_RESTART_DET_Msk
2999
3000 #define I2C_INTR_GEN_CALL_Pos (11U)
3001 #define I2C_INTR_GEN_CALL_Len (1U)
3002 #define I2C_INTR_GEN_CALL_Msk (0x1U << I2C_INTR_GEN_CALL_Pos)
3003 #define I2C_INTR_GEN_CALL I2C_INTR_GEN_CALL_Msk
3004
3005 #define I2C_INTR_START_DET_Pos (10U)
3006 #define I2C_INTR_START_DET_Len (1U)
3007 #define I2C_INTR_START_DET_Msk (0x1U << I2C_INTR_START_DET_Pos)
3008 #define I2C_INTR_START_DET I2C_INTR_START_DET_Msk
3009
3010 #define I2C_INTR_STOP_DET_Pos (9U)
3011 #define I2C_INTR_STOP_DET_Len (1U)
3012 #define I2C_INTR_STOP_DET_Msk (0x1U << I2C_INTR_STOP_DET_Pos)
3013 #define I2C_INTR_STOP_DET I2C_INTR_STOP_DET_Msk
3014
3015 #define I2C_INTR_ACTIVITY_Pos (8U)
3016 #define I2C_INTR_ACTIVITY_Len (1U)
3017 #define I2C_INTR_ACTIVITY_Msk (0x1U << I2C_INTR_ACTIVITY_Pos)
3018 #define I2C_INTR_ACTIVITY I2C_INTR_ACTIVITY_Msk
3019
3020 #define I2C_INTR_RX_DONE_Pos (7U)
3021 #define I2C_INTR_RX_DONE_Len (1U)
3022 #define I2C_INTR_RX_DONE_Msk (0x1U << I2C_INTR_RX_DONE_Pos)
3023 #define I2C_INTR_RX_DONE I2C_INTR_RX_DONE_Msk
3024
3025 #define I2C_INTR_TX_ABRT_Pos (6U)
3026 #define I2C_INTR_TX_ABRT_Len (1U)
3027 #define I2C_INTR_TX_ABRT_Msk (0x1U << I2C_INTR_TX_ABRT_Pos)
3028 #define I2C_INTR_TX_ABRT I2C_INTR_TX_ABRT_Msk
3029
3030 #define I2C_INTR_RD_REQ_Pos (5U)
3031 #define I2C_INTR_RD_REQ_Len (1U)
3032 #define I2C_INTR_RD_REQ_Msk (0x1U << I2C_INTR_RD_REQ_Pos)
3033 #define I2C_INTR_RD_REQ I2C_INTR_RD_REQ_Msk
3034
3035 #define I2C_INTR_TX_EMPTY_Pos (4U)
3036 #define I2C_INTR_TX_EMPTY_Len (1U)
3037 #define I2C_INTR_TX_EMPTY_Msk (0x1U << I2C_INTR_TX_EMPTY_Pos)
3038 #define I2C_INTR_TX_EMPTY I2C_INTR_TX_EMPTY_Msk
3039
3040 #define I2C_INTR_TX_OVER_Pos (3U)
3041 #define I2C_INTR_TX_OVER_Len (1U)
3042 #define I2C_INTR_TX_OVER_Msk (0x1U << I2C_INTR_TX_OVER_Pos)
3043 #define I2C_INTR_TX_OVER I2C_INTR_TX_OVER_Msk
3044
3045 #define I2C_INTR_RX_FULL_Pos (2U)
3046 #define I2C_INTR_RX_FULL_Len (1U)
3047 #define I2C_INTR_RX_FULL_Msk (0x1U << I2C_INTR_RX_FULL_Pos)
3048 #define I2C_INTR_RX_FULL I2C_INTR_RX_FULL_Msk
3049
3050 #define I2C_INTR_RX_OVER_Pos (1U)
3051 #define I2C_INTR_RX_OVER_Len (1U)
3052 #define I2C_INTR_RX_OVER_Msk (0x1U << I2C_INTR_RX_OVER_Pos)
3053 #define I2C_INTR_RX_OVER I2C_INTR_RX_OVER_Msk
3054
3055 #define I2C_INTR_RX_UNDER_Pos (0U)
3056 #define I2C_INTR_RX_UNDER_Len (1U)
3057 #define I2C_INTR_RX_UNDER_Msk (0x1U << I2C_INTR_RX_UNDER_Pos)
3058 #define I2C_INTR_RX_UNDER I2C_INTR_RX_UNDER_Msk
3059
3060 /******************* Bit definition for IC_RX_TL register *******************/
3061 #define I2C_RX_TL_RXTL_Pos (0U)
3062 #define I2C_RX_TL_RXTL_Len (8U)
3063 #define I2C_RX_TL_RXTL_Msk (0xFFU << I2C_RX_TL_RXTL_Pos)
3064 #define I2C_RX_TL_RXTL I2C_RX_TL_RXTL_Msk
3065
3066 /******************* Bit definition for IC_TX_TL register *******************/
3067 #define I2C_TX_TL_TXTL_Pos (0U)
3068 #define I2C_TX_TL_TXTL_Len (8U)
3069 #define I2C_TX_TL_TXTL_Msk (0xFFU << I2C_TX_TL_TXTL_Pos)
3070 #define I2C_TX_TL_TXTL I2C_TX_TL_TXTL_Msk
3071
3072 /******************* Bit definition for IC_ENABLE register ******************/
3073 #define I2C_ENABLE_ABORT_Pos (1U)
3074 #define I2C_ENABLE_ABORT_Len (1U)
3075 #define I2C_ENABLE_ABORT_Msk (0x1U << I2C_ENABLE_ABORT_Pos)
3076 #define I2C_ENABLE_ABORT I2C_ENABLE_ABORT_Msk
3077
3078 #define I2C_ENABLE_ENABLE_Pos (0U)
3079 #define I2C_ENABLE_ENABLE_Len (1U)
3080 #define I2C_ENABLE_ENABLE_Msk (0x1U << I2C_ENABLE_ENABLE_Pos)
3081 #define I2C_ENABLE_ENABLE I2C_ENABLE_ENABLE_Msk
3082
3083 /******************* Bit definition for IC_STATUS register ******************/
3084 #define I2C_STATUS_SLV_ACTIVITY_Pos (6U)
3085 #define I2C_STATUS_SLV_ACTIVITY_Len (1U)
3086 #define I2C_STATUS_SLV_ACTIVITY_Msk (0x1U << I2C_STATUS_SLV_ACTIVITY_Pos)
3087 #define I2C_STATUS_SLV_ACTIVITY I2C_STATUS_SLV_ACTIVITY_Msk
3088
3089 #define I2C_STATUS_MST_ACTIVITY_Pos (5U)
3090 #define I2C_STATUS_MST_ACTIVITY_Len (1U)
3091 #define I2C_STATUS_MST_ACTIVITY_Msk (0x1U << I2C_STATUS_MST_ACTIVITY_Pos)
3092 #define I2C_STATUS_MST_ACTIVITY I2C_STATUS_MST_ACTIVITY_Msk
3093
3094 #define I2C_STATUS_RFF_Pos (4U)
3095 #define I2C_STATUS_RFF_Len (1U)
3096 #define I2C_STATUS_RFF_Msk (0x1U << I2C_STATUS_RFF_Pos)
3097 #define I2C_STATUS_RFF I2C_STATUS_RFF_Msk
3098
3099 #define I2C_STATUS_RFNE_Pos (3U)
3100 #define I2C_STATUS_RFNE_Len (1U)
3101 #define I2C_STATUS_RFNE_Msk (0x1U << I2C_STATUS_RFNE_Pos)
3102 #define I2C_STATUS_RFNE I2C_STATUS_RFNE_Msk
3103
3104 #define I2C_STATUS_TFE_Pos (2U)
3105 #define I2C_STATUS_TFE_Len (1U)
3106 #define I2C_STATUS_TFE_Msk (0x1U << I2C_STATUS_TFE_Pos)
3107 #define I2C_STATUS_TFE I2C_STATUS_TFE_Msk
3108
3109 #define I2C_STATUS_TFNF_Pos (1U)
3110 #define I2C_STATUS_TFNF_Len (1U)
3111 #define I2C_STATUS_TFNF_Msk (0x1U << I2C_STATUS_TFNF_Pos)
3112 #define I2C_STATUS_TFNF I2C_STATUS_TFNF_Msk
3113
3114 #define I2C_STATUS_ACTIVITY_Pos (0U)
3115 #define I2C_STATUS_ACTIVITY_Len (1U)
3116 #define I2C_STATUS_ACTIVITY_Msk (0x1U << I2C_STATUS_ACTIVITY_Pos)
3117 #define I2C_STATUS_ACTIVITY I2C_STATUS_ACTIVITY_Msk
3118
3119 /******************* Bit definition for IC_RXFLR register *******************/
3120 #define I2C_RXFLR_RXFLR_Pos (0U)
3121 #define I2C_RXFLR_RXFLR_Len (8U)
3122 #define I2C_RXFLR_RXFLR_Msk (0xFFU << I2C_RXFLR_RXFLR_Pos)
3123 #define I2C_RXFLR_RXFLR I2C_RXFLR_RXFLR_Msk
3124
3125 /******************* Bit definition for IC_TXFLR register *******************/
3126 #define I2C_TXFLR_TXFLR_Pos (0U)
3127 #define I2C_TXFLR_TXFLR_Len (8U)
3128 #define I2C_TXFLR_TXFLR_Msk (0xFFU << I2C_TXFLR_TXFLR_Pos)
3129 #define I2C_TXFLR_TXFLR I2C_TXFLR_TXFLR_Msk
3130
3131 /******************* Bit definition for IC_SDA_HOLD register *******************/
3132 #define I2C_SDA_HOLD_RX_HOLD_Pos (16U)
3133 #define I2C_SDA_HOLD_RX_HOLD_Len (16U)
3134 #define I2C_SDA_HOLD_RX_HOLD_Msk (0xFFFFU << I2C_SDA_HOLD_RX_HOLD_Pos)
3135 #define I2C_SDA_HOLD_RX_HOLD I2C_SDA_HOLD_RX_HOLD_Msk
3136
3137 #define I2C_SDA_HOLD_TX_HOLD_Pos (0U)
3138 #define I2C_SDA_HOLD_TX_HOLD_Len (16U)
3139 #define I2C_SDA_HOLD_TX_HOLD_Msk (0xFFFFU << I2C_SDA_HOLD_TX_HOLD_Pos)
3140 #define I2C_SDA_HOLD_TX_HOLD I2C_SDA_HOLD_TX_HOLD_Msk
3141
3142 /******************* Bit definition for IC_TX_ABRT_SOURCE register **********/
3143 #define I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Pos (23U)
3144 #define I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Len (9U)
3145 #define I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Msk (0x1FFU << I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Pos)
3146 #define I2C_TX_ABRT_SRC_TX_FLUSH_CNT I2C_TX_ABRT_SRC_TX_FLUSH_CNT_Msk
3147
3148 #define I2C_TX_ABRT_SRC_USER_ABRT_Pos (16U)
3149 #define I2C_TX_ABRT_SRC_USER_ABRT_Len (1U)
3150 #define I2C_TX_ABRT_SRC_USER_ABRT_Msk (0x1U << I2C_TX_ABRT_SRC_USER_ABRT_Pos)
3151 #define I2C_TX_ABRT_SRC_USER_ABRT I2C_TX_ABRT_SRC_USER_ABRT_Msk
3152
3153 #define I2C_TX_ABRT_SRC_SLVRD_INTX_Pos (15U)
3154 #define I2C_TX_ABRT_SRC_SLVRD_INTX_Len (1U)
3155 #define I2C_TX_ABRT_SRC_SLVRD_INTX_Msk (0x1U << I2C_TX_ABRT_SRC_SLVRD_INTX_Pos)
3156 #define I2C_TX_ABRT_SRC_SLVRD_INTX I2C_TX_ABRT_SRC_SLVRD_INTX_Msk
3157
3158 #define I2C_TX_ABRT_SRC_SLV_ARBLOST_Pos (14U)
3159 #define I2C_TX_ABRT_SRC_SLV_ARBLOST_Len (1U)
3160 #define I2C_TX_ABRT_SRC_SLV_ARBLOST_Msk (0x1U << I2C_TX_ABRT_SRC_SLV_ARBLOST_Pos)
3161 #define I2C_TX_ABRT_SRC_SLV_ARBLOST I2C_TX_ABRT_SRC_SLV_ARBLOST_Msk
3162
3163 #define I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO_Pos (13U)
3164 #define I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO_Len (1U)
3165 #define I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO_Msk (0x1U << I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO_Pos)
3166 #define I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO I2C_TX_ABRT_SRC_SLVFLUSH_TXFIFO_Msk
3167
3168 #define I2C_TX_ABRT_SRC_ARB_LOST_Pos (12U)
3169 #define I2C_TX_ABRT_SRC_ARB_LOST_Len (1U)
3170 #define I2C_TX_ABRT_SRC_ARB_LOST_Msk (0x1U << I2C_TX_ABRT_SRC_ARB_LOST_Pos)
3171 #define I2C_TX_ABRT_SRC_ARB_LOST I2C_TX_ABRT_SRC_ARB_LOST_Msk
3172
3173 #define I2C_TX_ABRT_SRC_MST_DIS_Pos (11U)
3174 #define I2C_TX_ABRT_SRC_MST_DIS_Len (1U)
3175 #define I2C_TX_ABRT_SRC_MST_DIS_Msk (0x1U << I2C_TX_ABRT_SRC_MST_DIS_Pos)
3176 #define I2C_TX_ABRT_SRC_MST_DIS I2C_TX_ABRT_SRC_MST_DIS_Msk
3177
3178 #define I2C_TX_ABRT_SRC_10B_RD_NORSTRT_Pos (10U)
3179 #define I2C_TX_ABRT_SRC_10B_RD_NORSTRT_Len (1U)
3180 #define I2C_TX_ABRT_SRC_10B_RD_NORSTRT_Msk (0x1U << I2C_TX_ABRT_SRC_10B_RD_NORSTRT_Pos)
3181 #define I2C_TX_ABRT_SRC_10B_RD_NORSTRT I2C_TX_ABRT_SRC_10B_RD_NORSTRT_Msk
3182
3183 #define I2C_TX_ABRT_SRC_SBYTE_NORSTRT_Pos (9U)
3184 #define I2C_TX_ABRT_SRC_SBYTE_NORSTRT_Len (1U)
3185 #define I2C_TX_ABRT_SRC_SBYTE_NORSTRT_Msk (0x1U << I2C_TX_ABRT_SRC_SBYTE_NORSTRT_Pos)
3186 #define I2C_TX_ABRT_SRC_SBYTE_NORSTRT I2C_TX_ABRT_SRC_SBYTE_NORSTRT_Msk
3187
3188 #define I2C_TX_ABRT_SRC_HS_NORSTRT_Pos (8U)
3189 #define I2C_TX_ABRT_SRC_HS_NORSTRT_Len (1U)
3190 #define I2C_TX_ABRT_SRC_HS_NORSTRT_Msk (0x1U << I2C_TX_ABRT_SRC_HS_NORSTRT_Pos)
3191 #define I2C_TX_ABRT_SRC_HS_NORSTRT I2C_TX_ABRT_SRC_HS_NORSTRT_Msk
3192
3193 #define I2C_TX_ABRT_SRC_SBYTE_ACKDET_Pos (7U)
3194 #define I2C_TX_ABRT_SRC_SBYTE_ACKDET_Len (1U)
3195 #define I2C_TX_ABRT_SRC_SBYTE_ACKDET_Msk (0x1U << I2C_TX_ABRT_SRC_SBYTE_ACKDET_Pos)
3196 #define I2C_TX_ABRT_SRC_SBYTE_ACKDET I2C_TX_ABRT_SRC_SBYTE_ACKDET_Msk
3197
3198 #define I2C_TX_ABRT_SRC_HS_ACKDET_Pos (6U)
3199 #define I2C_TX_ABRT_SRC_HS_ACKDET_Len (1U)
3200 #define I2C_TX_ABRT_SRC_HS_ACKDET_Msk (0x1U << I2C_TX_ABRT_SRC_HS_ACKDET_Pos)
3201 #define I2C_TX_ABRT_SRC_HS_ACKDET I2C_TX_ABRT_SRC_HS_ACKDET_Msk
3202
3203 #define I2C_TX_ABRT_SRC_GCALL_READ_Pos (5U)
3204 #define I2C_TX_ABRT_SRC_GCALL_READ_Len (1U)
3205 #define I2C_TX_ABRT_SRC_GCALL_READ_Msk (0x1U << I2C_TX_ABRT_SRC_GCALL_READ_Pos)
3206 #define I2C_TX_ABRT_SRC_GCALL_READ I2C_TX_ABRT_SRC_GCALL_READ_Msk
3207
3208 #define I2C_TX_ABRT_SRC_GCALL_NOACK_Pos (4U)
3209 #define I2C_TX_ABRT_SRC_GCALL_NOACK_Len (1U)
3210 #define I2C_TX_ABRT_SRC_GCALL_NOACK_Msk (0x1U << I2C_TX_ABRT_SRC_GCALL_NOACK_Pos)
3211 #define I2C_TX_ABRT_SRC_GCALL_NOACK I2C_TX_ABRT_SRC_GCALL_NOACK_Msk
3212
3213 #define I2C_TX_ABRT_SRC_TXDATA_NOACK_Pos (3U)
3214 #define I2C_TX_ABRT_SRC_TXDATA_NOACK_Len (1U)
3215 #define I2C_TX_ABRT_SRC_TXDATA_NOACK_Msk (0x1U << I2C_TX_ABRT_SRC_TXDATA_NOACK_Pos)
3216 #define I2C_TX_ABRT_SRC_TXDATA_NOACK I2C_TX_ABRT_SRC_TXDATA_NOACK_Msk
3217
3218 #define I2C_TX_ABRT_SRC_10ADDR2_NOACK_Pos (2U)
3219 #define I2C_TX_ABRT_SRC_10ADDR2_NOACK_Len (1U)
3220 #define I2C_TX_ABRT_SRC_10ADDR2_NOACK_Msk (0x1U << I2C_TX_ABRT_SRC_10ADDR2_NOACK_Pos)
3221 #define I2C_TX_ABRT_SRC_10ADDR2_NOACK I2C_TX_ABRT_SRC_10ADDR2_NOACK_Msk
3222
3223 #define I2C_TX_ABRT_SRC_10ADDR1_NOACK_Pos (1U)
3224 #define I2C_TX_ABRT_SRC_10ADDR1_NOACK_Len (1U)
3225 #define I2C_TX_ABRT_SRC_10ADDR1_NOACK_Msk (0x1U << I2C_TX_ABRT_SRC_10ADDR1_NOACK_Pos)
3226 #define I2C_TX_ABRT_SRC_10ADDR1_NOACK I2C_TX_ABRT_SRC_10ADDR1_NOACK_Msk
3227
3228 #define I2C_TX_ABRT_SRC_7B_ADDR_NOACK_Pos (0U)
3229 #define I2C_TX_ABRT_SRC_7B_ADDR_NOACK_Len (1U)
3230 #define I2C_TX_ABRT_SRC_7B_ADDR_NOACK_Msk (0x1U << I2C_TX_ABRT_SRC_7B_ADDR_NOACK_Pos)
3231 #define I2C_TX_ABRT_SRC_7B_ADDR_NOACK I2C_TX_ABRT_SRC_7B_ADDR_NOACK_Msk
3232
3233 /******************* Bit definition for IC_DMA_CR register *******************/
3234 #define I2C_DMA_CR_TDMAE_Pos (1U)
3235 #define I2C_DMA_CR_TDMAE_Len (1U)
3236 #define I2C_DMA_CR_TDMAE_Msk (0x1U << I2C_DMA_CR_TDMAE_Pos)
3237 #define I2C_DMA_CR_TDMAE I2C_DMA_CR_TDMAE_Msk
3238
3239 #define I2C_DMA_CR_RDMAE_Pos (0U)
3240 #define I2C_DMA_CR_RDMAE_Len (1U)
3241 #define I2C_DMA_CR_RDMAE_Msk (0x1U << I2C_DMA_CR_RDMAE_Pos)
3242 #define I2C_DMA_CR_RDMAE I2C_DMA_CR_RDMAE_Msk
3243
3244 /******************* Bit definition for IC_DMA_TDLR register ****************/
3245 #define I2C_DMA_TDLR_DMATDL_Pos (0U)
3246 #define I2C_DMA_TDLR_DMATDL_Len (8U)
3247 #define I2C_DMA_TDLR_DMATDL_Msk (0xFFU << I2C_DMA_TDLR_DMATDL_Pos)
3248 #define I2C_DMA_TDLR_DMATDL I2C_DMA_TDLR_DMATDL_Msk
3249
3250 /******************* Bit definition for IC_DMA_RDLR register ****************/
3251 #define I2C_DMA_RDLR_DMARDL_Pos (0U)
3252 #define I2C_DMA_RDLR_DMARDL_Len (8U)
3253 #define I2C_DMA_RDLR_DMARDL_Msk (0xFFU << I2C_DMA_RDLR_DMARDL_Pos)
3254 #define I2C_DMA_RDLR_DMARDL I2C_DMA_RDLR_DMARDL_Msk
3255
3256 /******************* Bit definition for IC_SDA_SETUP register ***************/
3257 #define I2C_SDA_SETUP_SDA_SETUP_Pos (0U)
3258 #define I2C_SDA_SETUP_SDA_SETUP_Len (8U)
3259 #define I2C_SDA_SETUP_SDA_SETUP_Msk (0xFFU << I2C_SDA_SETUP_SDA_SETUP_Pos)
3260 #define I2C_SDA_SETUP_SDA_SETUP I2C_SDA_SETUP_SDA_SETUP_Msk
3261
3262 /******************* Bit definition for IC_ACK_GENERAL_CALL register ********/
3263 #define I2C_ACK_GENERAL_CALL_ACK_GC_Pos (0U)
3264 #define I2C_ACK_GENERAL_CALL_ACK_GC_Len (1U)
3265 #define I2C_ACK_GENERAL_CALL_ACK_GC_Msk (0x1U << I2C_ACK_GENERAL_CALL_ACK_GC_Pos)
3266 #define I2C_ACK_GENERAL_CALL_ACK_GC I2C_ACK_GENERAL_CALL_ACK_GC_Msk
3267
3268 /******************* Bit definition for IC_ENABLE_STATUS register ***********/
3269 #define I2C_ENABLE_STATUS_SLV_RX_LOST_Pos (2U)
3270 #define I2C_ENABLE_STATUS_SLV_RX_LOST_Len (1U)
3271 #define I2C_ENABLE_STATUS_SLV_RX_LOST_Msk (0x1U << I2C_ENABLE_STATUS_SLV_RX_LOST_Pos)
3272 #define I2C_ENABLE_STATUS_SLV_RX_LOST I2C_ENABLE_STATUS_SLV_RX_LOST_Msk
3273
3274 #define I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY_Pos (1U)
3275 #define I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY_Len (1U)
3276 #define I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY_Msk (0x1U << I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY_Pos)
3277 #define I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY I2C_ENABLE_STATUS_SLV_DIS_WHL_BUSY_Msk
3278
3279 #define I2C_ENABLE_STATUS_IC_EN_Pos (0U)
3280 #define I2C_ENABLE_STATUS_IC_EN_Len (1U)
3281 #define I2C_ENABLE_STATUS_IC_EN_Msk (0x1U << I2C_ENABLE_STATUS_IC_EN_Pos)
3282 #define I2C_ENABLE_STATUS_IC_EN I2C_ENABLE_STATUS_IC_EN_Msk
3283
3284 /******************* Bit definition for IC_FS_SPKLEN register ***************/
3285 #define I2C_FS_SPKLEN_FS_SPKLEN_Pos (0U)
3286 #define I2C_FS_SPKLEN_FS_SPKLEN_Len (8U)
3287 #define I2C_FS_SPKLEN_FS_SPKLEN_Msk (0xFFU << I2C_FS_SPKLEN_FS_SPKLEN_Pos)
3288 #define I2C_FS_SPKLEN_FS_SPKLEN I2C_FS_SPKLEN_FS_SPKLEN_Msk
3289
3290 /******************* Bit definition for IC_HS_SPKLEN register ***************/
3291 #define I2C_HS_SPKLEN_HS_SPKLEN_Pos (0U)
3292 #define I2C_HS_SPKLEN_HS_SPKLEN_Len (8U)
3293 #define I2C_HS_SPKLEN_HS_SPKLEN_Msk (0xFFU << I2C_HS_SPKLEN_HS_SPKLEN_Pos)
3294 #define I2C_HS_SPKLEN_HS_SPKLEN I2C_HS_SPKLEN_HS_SPKLEN_Msk
3295
3296
3297 /* ================================================================================================================= */
3298 /* ================ I2S ================ */
3299 /* ================================================================================================================= */
3300 #define I2S_TXFIFO_SIZE (16U)
3301 #define I2S_RXFIFO_SIZE (16U)
3302
3303 /******************* Bit definition for ENABLE register *********************/
3304 #define I2S_ENABLE_EN_Pos (0U)
3305 #define I2S_ENABLE_EN_Len (1U)
3306 #define I2S_ENABLE_EN_Msk (0x1U << I2S_ENABLE_EN_Pos)
3307 #define I2S_ENABLE_EN I2S_ENABLE_EN_Msk
3308
3309 /******************* Bit definition for RBEN register ***********************/
3310 #define I2S_RBEN_EN_Pos (0U)
3311 #define I2S_RBEN_EN_Len (1U)
3312 #define I2S_RBEN_EN_Msk (0x1U << I2S_RBEN_EN_Pos)
3313 #define I2S_RBEN_EN I2S_RBEN_EN_Msk
3314
3315 /******************* Bit definition for TBEN register ***********************/
3316 #define I2S_TBEN_EN_Pos (0U)
3317 #define I2S_TBEN_EN_Len (1U)
3318 #define I2S_TBEN_EN_Msk (0x1U << I2S_TBEN_EN_Pos)
3319 #define I2S_TBEN_EN I2S_TBEN_EN_Msk
3320
3321 /******************* Bit definition for CLKEN register **********************/
3322 #define I2S_CLKEN_EN_Pos (0U)
3323 #define I2S_CLKEN_EN_Len (1U)
3324 #define I2S_CLKEN_EN_Msk (0x1U << I2S_CLKEN_EN_Pos)
3325 #define I2S_CLKEN_EN I2S_CLKEN_EN_Msk
3326
3327 /***************** Bit definition for CLKCONFIG register ********************/
3328 #define I2S_CLKCONFIG_WSS_Pos (3U)
3329 #define I2S_CLKCONFIG_WSS_Len (2U)
3330 #define I2S_CLKCONFIG_WSS_Msk (0x3U << I2S_CLKCONFIG_WSS_Pos)
3331 #define I2S_CLKCONFIG_WSS I2S_CLKCONFIG_WSS_Msk
3332
3333 #define I2S_CLKCONFIG_SCLKG_Pos (0U)
3334 #define I2S_CLKCONFIG_SCLKG_Len (3U)
3335 #define I2S_CLKCONFIG_SCLKG_Msk (0x7U << I2S_CLKCONFIG_SCLKG_Pos)
3336 #define I2S_CLKCONFIG_SCLKG I2S_CLKCONFIG_SCLKG_Msk
3337
3338 /***************** Bit definition for RXFIFO_RST register *******************/
3339 #define I2S_RXFIFO_RST_Pos (0U)
3340 #define I2S_RXFIFO_RST_Len (1U)
3341 #define I2S_RXFIFO_RST_Msk (0x1U << I2S_RXFIFO_RST_Pos)
3342 #define I2S_RXFIFO_RST I2S_RXFIFO_RST_Msk
3343
3344 /***************** Bit definition for TXFIFO_RST register *******************/
3345 #define I2S_TXFIFO_RST_Pos (0U)
3346 #define I2S_TXFIFO_RST_Len (1U)
3347 #define I2S_TXFIFO_RST_Msk (0x1U << I2S_TXFIFO_RST_Pos)
3348 #define I2S_TXFIFO_RST I2S_TXFIFO_RST_Msk
3349
3350 /******************* Bit definition for DATA_L register *********************/
3351 #define I2S_DATA_L_Pos (0U)
3352 #define I2S_DATA_L_Len (32U)
3353 #define I2S_DATA_L_Msk (0xFFFFFFFFU)
3354 #define I2S_DATA_L I2S_DATA_L_Msk
3355
3356 /******************* Bit definition for DATA_R register *********************/
3357 #define I2S_DATA_R_Pos (0U)
3358 #define I2S_DATA_R_Len (32U)
3359 #define I2S_DATA_R_Msk (0xFFFFFFFFU)
3360 #define I2S_DATA_R I2S_DATA_R_Msk
3361
3362 /******************** Bit definition for RXEN register **********************/
3363 #define I2S_RXEN_EN_Pos (0U)
3364 #define I2S_RXEN_EN_Len (1U)
3365 #define I2S_RXEN_EN_Msk (0x1U << I2S_RXEN_EN_Pos)
3366 #define I2S_RXEN_EN I2S_RXEN_EN_Msk
3367
3368 /******************** Bit definition for TXEN register **********************/
3369 #define I2S_TXEN_EN_Pos (0U)
3370 #define I2S_TXEN_EN_Len (1U)
3371 #define I2S_TXEN_EN_Msk (0x1U << I2S_TXEN_EN_Pos)
3372 #define I2S_TXEN_EN I2S_TXEN_EN_Msk
3373
3374 /******************* Bit definition for RXSIZE register *********************/
3375 #define I2S_RXSIZE_WLEN_Pos (0U)
3376 #define I2S_RXSIZE_WLEN_Len (3U)
3377 #define I2S_RXSIZE_WLEN_Msk (0x7U << I2S_RXSIZE_WLEN_Pos)
3378 #define I2S_RXSIZE_WLEN I2S_RXSIZE_WLEN_Msk
3379
3380 /******************* Bit definition for TXSIZE register *********************/
3381 #define I2S_TXSIZE_WLEN_Pos (0U)
3382 #define I2S_TXSIZE_WLEN_Len (3U)
3383 #define I2S_TXSIZE_WLEN_Msk (0x7U << I2S_TXSIZE_WLEN_Pos)
3384 #define I2S_TXSIZE_WLEN I2S_TXSIZE_WLEN_Msk
3385
3386 /******************* Bit definition for INTSTAT register ********************/
3387 #define I2S_INTSTAT_TXFO_Pos (5U)
3388 #define I2S_INTSTAT_TXFO_Len (1U)
3389 #define I2S_INTSTAT_TXFO_Msk (0x1U << I2S_INTSTAT_TXFO_Pos)
3390 #define I2S_INTSTAT_TXFO I2S_INTSTAT_TXFO_Msk
3391
3392 #define I2S_INTSTAT_TXFE_Pos (4U)
3393 #define I2S_INTSTAT_TXFE_Len (1U)
3394 #define I2S_INTSTAT_TXFE_Msk (0x1U << I2S_INTSTAT_TXFE_Pos)
3395 #define I2S_INTSTAT_TXFE I2S_INTSTAT_TXFE_Msk
3396
3397 #define I2S_INTSTAT_RXFO_Pos (1U)
3398 #define I2S_INTSTAT_RXFO_Len (1U)
3399 #define I2S_INTSTAT_RXFO_Msk (0x1U << I2S_INTSTAT_RXFO_Pos)
3400 #define I2S_INTSTAT_RXFO I2S_INTSTAT_RXFO_Msk
3401
3402 #define I2S_INTSTAT_RXDA_Pos (0U)
3403 #define I2S_INTSTAT_RXDA_Len (1U)
3404 #define I2S_INTSTAT_RXDA_Msk (0x1U << I2S_INTSTAT_RXDA_Pos)
3405 #define I2S_INTSTAT_RXDA I2S_INTSTAT_RXDA_Msk
3406
3407 /******************* Bit definition for INTMASK register ********************/
3408 #define I2S_INTMASK_TXFO_Pos (5U)
3409 #define I2S_INTMASK_TXFO_Len (1U)
3410 #define I2S_INTMASK_TXFO_Msk (0x1U << I2S_INTSTAT_TXFO_Pos)
3411 #define I2S_INTMASK_TXFO I2S_INTSTAT_TXFO_Msk
3412
3413 #define I2S_INTMASK_TXFE_Pos (4U)
3414 #define I2S_INTMASK_TXFE_Len (1U)
3415 #define I2S_INTMASK_TXFE_Msk (0x1U << I2S_INTSTAT_TXFE_Pos)
3416 #define I2S_INTMASK_TXFE I2S_INTSTAT_TXFE_Msk
3417
3418 #define I2S_INTMASK_RXFO_Pos (1U)
3419 #define I2S_INTMASK_RXFO_Len (1U)
3420 #define I2S_INTMASK_RXFO_Msk (0x1U << I2S_INTSTAT_RXFO_Pos)
3421 #define I2S_INTMASK_RXFO I2S_INTSTAT_RXFO_Msk
3422
3423 #define I2S_INTMASK_RXDA_Pos (0U)
3424 #define I2S_INTMASK_RXDA_Len (1U)
3425 #define I2S_INTMASK_RXDA_Msk (0x1U << I2S_INTSTAT_RXDA_Pos)
3426 #define I2S_INTMASK_RXDA I2S_INTSTAT_RXDA_Msk
3427
3428 /******************** Bit definition for RXOVR register *********************/
3429 #define I2S_RXOVR_RXCHO_Pos (0U)
3430 #define I2S_RXOVR_RXCHO_Len (1U)
3431 #define I2S_RXOVR_RXCHO_Msk (0x1U << I2S_RXOVR_RXCHO_Pos)
3432 #define I2S_RXOVR_RXCHO I2S_RXOVR_RXCHO_Msk
3433
3434 /******************** Bit definition for TXOVR register *********************/
3435 #define I2S_TXOVR_TXCHO_Pos (0U)
3436 #define I2S_TXOVR_TXCHO_Len (1U)
3437 #define I2S_TXOVR_TXCHO_Msk (0x1U << I2S_TXOVR_TXCHO_Pos)
3438 #define I2S_TXOVR_TXCHO I2S_TXOVR_TXCHO_Msk
3439
3440 /****************** Bit definition for RXFIFO_TL register *******************/
3441 #define I2S_RXFIFO_TL_Pos (0U)
3442 #define I2S_RXFIFO_TL_Len (4U)
3443 #define I2S_RXFIFO_TL_Msk (0xFU << I2S_RXFIFO_TL_Pos)
3444 #define I2S_RXFIFO_TL I2S_RXFIFO_TL_Msk
3445
3446 /****************** Bit definition for TXFIFO_TL register *******************/
3447 #define I2S_TXFIFO_TL_Pos (0U)
3448 #define I2S_TXFIFO_TL_Len (4U)
3449 #define I2S_TXFIFO_TL_Msk (0xFU << I2S_TXFIFO_TL_Pos)
3450 #define I2S_TXFIFO_TL I2S_TXFIFO_TL_Msk
3451
3452 /**************** Bit definition for RXFIFO_FLUSH register ******************/
3453 #define I2S_RXFIFO_FLUSH_Pos (0U)
3454 #define I2S_RXFIFO_FLUSH_Len (1U)
3455 #define I2S_RXFIFO_FLUSH_Msk (0x1U << I2S_RXFIFO_FLUSH_Pos)
3456 #define I2S_RXFIFO_FLUSH I2S_RXFIFO_FLUSH_Msk
3457
3458 /**************** Bit definition for TXFIFO_FLUSH register ******************/
3459 #define I2S_TXFIFO_FLUSH_Pos (0U)
3460 #define I2S_TXFIFO_FLUSH_Len (1U)
3461 #define I2S_TXFIFO_FLUSH_Msk (0x1U << I2S_TXFIFO_FLUSH_Pos)
3462 #define I2S_TXFIFO_FLUSH I2S_TXFIFO_FLUSH_Msk
3463
3464 /******************** Bit definition for RXDMA register *********************/
3465 #define I2S_RXDMA_Pos (0U)
3466 #define I2S_RXDMA_Len (32U)
3467 #define I2S_RXDMA_Msk (0xFFFFFFFFU)
3468 #define I2S_RXDMA I2S_RXDMA_Msk
3469
3470 /****************** Bit definition for RXDMA_RST register *******************/
3471 #define I2S_RXDMA_RST_Pos (0U)
3472 #define I2S_RXDMA_RST_Len (1U)
3473 #define I2S_RXDMA_RST_Msk (0x1U << I2S_RXDMA_RST_Pos)
3474 #define I2S_RXDMA_RST I2S_RXDMA_RST_Msk
3475
3476 /******************** Bit definition for TXDMA register *********************/
3477 #define I2S_TXDMA_Pos (0U)
3478 #define I2S_TXDMA_Len (32U)
3479 #define I2S_TXDMA_Msk (0xFFFFFFFFU)
3480 #define I2S_TXDMA I2S_TXDMA_Msk
3481
3482 /****************** Bit definition for TXDMA_RST register *******************/
3483 #define I2S_TXDMA_RST_Pos (0U)
3484 #define I2S_TXDMA_RST_Len (1U)
3485 #define I2S_TXDMA_RST_Msk (0x1U << I2S_TXDMA_RST_Pos)
3486 #define I2S_TXDMA_RST I2S_TXDMA_RST_Msk
3487
3488 /****************** Bit definition for I2S_PARAM2 register ******************/
3489 #define I2S_PARAM2_RXSIZE_3_Pos (10U)
3490 #define I2S_PARAM2_RXSIZE_3_Len (3U)
3491 #define I2S_PARAM2_RXSIZE_3_Msk (0x7U << I2S_PARAM2_RXSIZE_3_Pos)
3492 #define I2S_PARAM2_RXSIZE_3 I2S_PARAM2_RXSIZE_3_Msk
3493
3494 #define I2S_PARAM2_RXSIZE_2_Pos (7U)
3495 #define I2S_PARAM2_RXSIZE_2_Len (3U)
3496 #define I2S_PARAM2_RXSIZE_2_Msk (0x7U << I2S_PARAM2_RXSIZE_2_Pos)
3497 #define I2S_PARAM2_RXSIZE_2 I2S_PARAM2_RXSIZE_2_Msk
3498
3499 #define I2S_PARAM2_RXSIZE_1_Pos (3U)
3500 #define I2S_PARAM2_RXSIZE_1_Len (3U)
3501 #define I2S_PARAM2_RXSIZE_1_Msk (0x7U << I2S_PARAM2_RXSIZE_1_Pos)
3502 #define I2S_PARAM2_RXSIZE_1 I2S_PARAM2_RXSIZE_1_Msk
3503
3504 #define I2S_PARAM2_RXSIZE_0_Pos (0U)
3505 #define I2S_PARAM2_RXSIZE_0_Len (3U)
3506 #define I2S_PARAM2_RXSIZE_0_Msk (0x7U << I2S_PARAM2_RXSIZE_0_Pos)
3507 #define I2S_PARAM2_RXSIZE_0 I2S_PARAM2_RXSIZE_0_Msk
3508
3509 /****************** Bit definition for I2S_PARAM1 register ******************/
3510 #define I2S_PARAM1_TXSIZE_3_Pos (25U)
3511 #define I2S_PARAM1_TXSIZE_3_Len (3U)
3512 #define I2S_PARAM1_TXSIZE_3_Msk (0x7U << I2S_PARAM1_TXSIZE_3_Pos)
3513 #define I2S_PARAM1_TXSIZE_3 I2S_PARAM1_TXSIZE_3_Msk
3514
3515 #define I2S_PARAM1_TXSIZE_2_Pos (22U)
3516 #define I2S_PARAM1_TXSIZE_2_Len (3U)
3517 #define I2S_PARAM1_TXSIZE_2_Msk (0x7U << I2S_PARAM1_TXSIZE_2_Pos)
3518 #define I2S_PARAM1_TXSIZE_2 I2S_PARAM1_TXSIZE_2_Msk
3519
3520 #define I2S_PARAM1_TXSIZE_1_Pos (19U)
3521 #define I2S_PARAM1_TXSIZE_1_Len (3U)
3522 #define I2S_PARAM1_TXSIZE_1_Msk (0x7U << I2S_PARAM1_TXSIZE_1_Pos)
3523 #define I2S_PARAM1_TXSIZE_1 I2S_PARAM1_TXSIZE_1_Msk
3524
3525 #define I2S_PARAM1_TXSIZE_0_Pos (16U)
3526 #define I2S_PARAM1_TXSIZE_0_Len (3U)
3527 #define I2S_PARAM1_TXSIZE_0_Msk (0x7U << I2S_PARAM1_TXSIZE_0_Pos)
3528 #define I2S_PARAM1_TXSIZE_0 I2S_PARAM1_TXSIZE_0_Msk
3529
3530 #define I2S_PARAM1_TXCHN_Pos (9U)
3531 #define I2S_PARAM1_TXCHN_Len (2U)
3532 #define I2S_PARAM1_TXCHN_Msk (0x3U << I2S_PARAM1_TXCHN_Pos)
3533 #define I2S_PARAM1_TXCHN I2S_PARAM1_TXCHN_Msk
3534
3535 #define I2S_PARAM1_RXCHN_Pos (7U)
3536 #define I2S_PARAM1_RXCHN_Len (2U)
3537 #define I2S_PARAM1_RXCHN_Msk (0x3U << I2S_PARAM1_RXCHN_Pos)
3538 #define I2S_PARAM1_RXCHN I2S_PARAM1_RXCHN_Msk
3539
3540 #define I2S_PARAM1_RXBLOCK_Pos (6U)
3541 #define I2S_PARAM1_RXBLOCK_Len (1U)
3542 #define I2S_PARAM1_RXBLOCK_Msk (0x1U << I2S_PARAM1_RXBLOCK_Pos)
3543 #define I2S_PARAM1_RXBLOCK I2S_PARAM1_RXBLOCK_Msk
3544
3545 #define I2S_PARAM1_TXBLOCK_Pos (5U)
3546 #define I2S_PARAM1_TXBLOCK_Len (1U)
3547 #define I2S_PARAM1_TXBLOCK_Msk (0x1U << I2S_PARAM1_TXBLOCK_Pos)
3548 #define I2S_PARAM1_TXBLOCK I2S_PARAM1_TXBLOCK_Msk
3549
3550 #define I2S_PARAM1_MODE_Pos (4U)
3551 #define I2S_PARAM1_MODE_Len (1U)
3552 #define I2S_PARAM1_MODE_Msk (0x1U << I2S_PARAM1_MODE_Pos)
3553 #define I2S_PARAM1_MODE I2S_PARAM1_MODE_Msk
3554
3555 #define I2S_PARAM1_FIFO_DEPTH_Pos (2U)
3556 #define I2S_PARAM1_FIFO_DEPTH_Len (2U)
3557 #define I2S_PARAM1_FIFO_DEPTH_Msk (0x3U << I2S_PARAM1_FIFO_DEPTH_Pos)
3558 #define I2S_PARAM1_FIFO_DEPTH I2S_PARAM1_FIFO_DEPTH_Msk
3559
3560 #define I2S_PARAM1_APB_DATA_WIDTH_Pos (0U)
3561 #define I2S_PARAM1_APB_DATA_WIDTH_Len (2U)
3562 #define I2S_PARAM1_APB_DATA_WIDTH_Msk (0x3U << I2S_PARAM1_APB_DATA_WIDTH_Pos)
3563 #define I2S_PARAM1_APB_DATA_WIDTH I2S_PARAM1_APB_DATA_WIDTH_Msk
3564
3565 /****************** Bit definition for I2S_VERSION register *****************/
3566 #define I2S_COMP_VERSION_Pos (0U)
3567 #define I2S_COMP_VERSION_Len (32U)
3568 #define I2S_COMP_VERSION_Msk (0xFFFFFFFFU)
3569 #define I2S_COMP_VERSION I2S_COMP_VERSION_Msk
3570
3571 /******************* Bit definition for I2S_TYPE register *******************/
3572 #define I2S_COMP_TYPE_Pos (0U)
3573 #define I2S_COMP_TYPE_Len (32U)
3574 #define I2S_COMP_TYPE_Msk (0xFFFFFFFFU)
3575 #define I2S_COMP_TYPE I2S_COMP_TYPE_Msk
3576
3577
3578 /* ================================================================================================================= */
3579 /* ================ ISO7816 ================ */
3580 /* ================================================================================================================= */
3581 /******************* Bit definition for ISO7816_CTRL register *******************/
3582 #define ISO7816_CTRL_ACTION_POS (0U)
3583 #define ISO7816_CTRL_ACTION_Len (3U)
3584 #define ISO7816_CTRL_ACTION_Msk (0x7UL << ISO7816_CTRL_ACTION_POS)
3585 #define ISO7816_CTRL_ACTION ISO7816_CTRL_ACTION_Msk
3586
3587 #define ISO7816_CTRL_RX_RETYR_MC_POS (8U)
3588 #define ISO7816_CTRL_RX_RETYR_MC_Len (1U)
3589 #define ISO7816_CTRL_RX_RETYR_MC_Msk (0x1UL << ISO7816_CTRL_RX_RETYR_MC_POS)
3590 #define ISO7816_CTRL_RX_RETYR_MC ISO7816_CTRL_RX_RETYR_MC_Msk
3591
3592 #define ISO7816_CTRL_TX_RETYR_MC_POS (12U)
3593 #define ISO7816_CTRL_TX_RETYR_MC_Len (1U)
3594 #define ISO7816_CTRL_TX_RETYR_MC_Msk (0x1UL << ISO7816_CTRL_TX_RETYR_MC_POS)
3595 #define ISO7816_CTRL_TX_RETYR_MC ISO7816_CTRL_TX_RETYR_MC_Msk
3596
3597 #define ISO7816_CTRL_IRQ_DONE_CLR_POS (20U)
3598 #define ISO7816_CTRL_IRQ_DONE_CLR_Len (1U)
3599 #define ISO7816_CTRL_IRQ_DONE_CLR_Msk (0x1UL << ISO7816_CTRL_IRQ_DONE_CLR_POS)
3600 #define ISO7816_CTRL_IRQ_DONE_CLR ISO7816_CTRL_IRQ_DONE_CLR_Msk
3601
3602 #define ISO7816_CTRL_IRQ_RX_EC_POS (21U)
3603 #define ISO7816_CTRL_IRQ_RX_EC_Len (1U)
3604 #define ISO7816_CTRL_IRQ_RX_EC_Msk (0x1UL << ISO7816_CTRL_IRQ_RX_EC_POS)
3605 #define ISO7816_CTRL_IRQ_RX_EC ISO7816_CTRL_IRQ_RX_EC_Msk
3606
3607 #define ISO7816_CTRL_IRQ_RETYR_EC_POS (22U)
3608 #define ISO7816_CTRL_IRQ_RETYR_EC_Len (1U)
3609 #define ISO7816_CTRL_IRQ_RETYR_EC_Msk (0x1UL << ISO7816_CTRL_IRQ_RETYR_EC_POS)
3610 #define ISO7816_CTRL_IRQ_RETYR_EC ISO7816_CTRL_IRQ_RETYR_EC_Msk
3611
3612 #define ISO7816_CTRL_IRQ_DMA_EC_POS (23U)
3613 #define ISO7816_CTRL_IRQ_DMA_EC_Len (1U)
3614 #define ISO7816_CTRL_IRQ_DMA_EC_Msk (0x1UL << ISO7816_CTRL_IRQ_DMA_EC_POS)
3615 #define ISO7816_CTRL_IRQ_DMA_EC ISO7816_CTRL_IRQ_DMA_EC_Msk
3616
3617 #define ISO7816_CTRL_IRQ_STAT_EC_POS (24U)
3618 #define ISO7816_CTRL_IRQ_STAT_EC_Len (1U)
3619 #define ISO7816_CTRL_IRQ_STAT_EC_Msk (0x1UL << ISO7816_CTRL_IRQ_STAT_EC_POS)
3620 #define ISO7816_CTRL_IRQ_STAT_EC ISO7816_CTRL_IRQ_STAT_EC_Msk
3621
3622 #define ISO7816_CTRL_IRQ_PRESENCE_CLR_POS (25U)
3623 #define ISO7816_CTRL_IRQ_PRESENCE_CLR_Len (1U)
3624 #define ISO7816_CTRL_IRQ_PRESENCE_CLR_Msk (0x1UL << ISO7816_CTRL_IRQ_PRESENCE_CLR_POS)
3625 #define ISO7816_CTRL_IRQ_PRESENCE_CLR ISO7816_CTRL_IRQ_PRESENCE_CLR_Msk
3626
3627 #define ISO7816_CTRL_IRQ_TEST_CLR_POS (30U)
3628 #define ISO7816_CTRL_IRQ_TEST_CLR_Len (1U)
3629 #define ISO7816_CTRL_IRQ_TEST_CLR_Msk (0x1UL << ISO7816_CTRL_IRQ_TEST_CLR_POS)
3630 #define ISO7816_CTRL_IRQ_TEST_CLR ISO7816_CTRL_IRQ_TEST_CLR_Msk
3631
3632 #define ISO7816_CTRL_IRQ_TEST_SET_POS (31U)
3633 #define ISO7816_CTRL_IRQ_TEST_SET_Len (1U)
3634 #define ISO7816_CTRL_IRQ_TEST_SET_Msk (0x1UL << ISO7816_CTRL_IRQ_TEST_SET_POS)
3635 #define ISO7816_CTRL_IRQ_TEST_SET ISO7816_CTRL_IRQ_TEST_SET_Msk
3636
3637 /******************* Bit definition for ISO7816_STAT register *******************/
3638 #define ISO7816_INTR_ALL (0x43F00000)
3639
3640 #define ISO7816_STAT_PWR_STAT_POS (0U)
3641 #define ISO7816_STAT_PWR_STAT_Len (4U)
3642 #define ISO7816_STAT_PWR_STAT_Msk (0xFUL << ISO7816_STAT_PWR_STAT_POS)
3643 #define ISO7816_STAT_PWR_STAT ISO7816_STAT_PWR_STAT_Msk
3644
3645 #define ISO7816_STAT_IO_STAT_POS (4U)
3646 #define ISO7816_STAT_IO_STAT_Len (3U)
3647 #define ISO7816_STAT_IO_STAT_Msk (0x7UL << ISO7816_STAT_IO_STAT_POS)
3648 #define ISO7816_STAT_IO_STAT ISO7816_STAT_IO_STAT_Msk
3649
3650 #define ISO7816_STAT_RX_RETRY_MAX_POS (8U)
3651 #define ISO7816_STAT_RX_RETRY_MAX_Len (3U)
3652 #define ISO7816_STAT_RX_RETRY_MAX_Msk (0x7UL << ISO7816_STAT_RX_RETRY_MAX_POS)
3653 #define ISO7816_STAT_RX_RETRY_MAX ISO7816_STAT_RX_RETRY_MAX_Msk
3654
3655 #define ISO7816_STAT_TX_RETRY_MAX_POS (12U)
3656 #define ISO7816_STAT_TX_RETRY_MAX_Len (3U)
3657 #define ISO7816_STAT_TX_RETRY_MAX_Msk (0x7UL << ISO7816_STAT_TX_RETRY_MAX_POS)
3658 #define ISO7816_STAT_TX_RETRY_MAX ISO7816_STAT_TX_RETRY_MAX_Msk
3659
3660 #define ISO7816_STAT_BUSY_POS (16U)
3661 #define ISO7816_STAT_BUSY_Len (1U)
3662 #define ISO7816_STAT_BUSY_Msk (0x1UL << ISO7816_STAT_BUSY_POS)
3663 #define ISO7816_STAT_BUSY ISO7816_STAT_BUSY_Msk
3664
3665 #define ISO7816_STAT_PRESENCE_STAT_POS (17U)
3666 #define ISO7816_STAT_PRESENCE_STAT_Len (1U)
3667 #define ISO7816_STAT_PRESENCE_STAT_Msk (0x1UL << ISO7816_STAT_PRESENCE_STAT_POS)
3668 #define ISO7816_STAT_PRESENCE_STAT ISO7816_STAT_PRESENCE_STAT_Msk
3669
3670 #define ISO7816_STAT_IRQ_DONE_POS (20U)
3671 #define ISO7816_STAT_IRQ_DONE_Len (1U)
3672 #define ISO7816_STAT_IRQ_DONE_Msk (0x1UL << ISO7816_STAT_IRQ_DONE_POS)
3673 #define ISO7816_STAT_IRQ_DONE ISO7816_STAT_IRQ_DONE_Msk
3674
3675 #define ISO7816_STAT_IRQ_RX_ERR_POS (21U)
3676 #define ISO7816_STAT_IRQ_RX_ERR_Len (1U)
3677 #define ISO7816_STAT_IRQ_RX_ERR_Msk (0x1UL << ISO7816_STAT_IRQ_RX_ERR_POS)
3678 #define ISO7816_STAT_IRQ_RX_ERR ISO7816_STAT_IRQ_RX_ERR_Msk
3679
3680 #define ISO7816_STAT_IRQ_RETRY_ERR_POS (22U)
3681 #define ISO7816_STAT_IRQ_RETRY_ERR_Len (1U)
3682 #define ISO7816_STAT_IRQ_RETRY_ERR_Msk (0x1UL << ISO7816_STAT_IRQ_RETRY_ERR_POS)
3683 #define ISO7816_STAT_IRQ_RETRY_ERR ISO7816_STAT_IRQ_RETRY_ERR_Msk
3684
3685 #define ISO7816_STAT_IRQ_DMA_ERR_POS (23U)
3686 #define ISO7816_STAT_IRQ_DMA_ERR_Len (1U)
3687 #define ISO7816_STAT_IRQ_DMA_ERR_Msk (0x1UL << ISO7816_STAT_IRQ_DMA_ERR_POS)
3688 #define ISO7816_STAT_IRQ_DMA_ERR ISO7816_STAT_IRQ_DMA_ERR_Msk
3689
3690 #define ISO7816_STAT_IRQ_STAT_ERR_POS (24U)
3691 #define ISO7816_STAT_IRQ_STAT_ERR_Len (1U)
3692 #define ISO7816_STAT_IRQ_STAT_ERR_Msk (0x1UL << ISO7816_STAT_IRQ_STAT_ERR_POS)
3693 #define ISO7816_STAT_IRQ_STAT_ERR ISO7816_STAT_IRQ_STAT_ERR_Msk
3694
3695 #define ISO7816_STAT_IRQ_PRESENCE_POS (25U)
3696 #define ISO7816_STAT_IRQ_PRESENCE_Len (1U)
3697 #define ISO7816_STAT_IRQ_PRESENCE_Msk (0x1UL << ISO7816_STAT_IRQ_PRESENCE_POS)
3698 #define ISO7816_STAT_IRQ_PRESENCE ISO7816_STAT_IRQ_PRESENCE_Msk
3699
3700 #define ISO7816_STAT_IRQ_TEST_POS (30U)
3701 #define ISO7816_STAT_IRQ_TEST_Len (1U)
3702 #define ISO7816_STAT_IRQ_TEST_Msk (0x1UL << ISO7816_STAT_IRQ_TEST_POS)
3703 #define ISO7816_STAT_IRQ_TEST ISO7816_STAT_IRQ_TEST_Msk
3704
3705 /******************* Bit definition for ISO7816_CLK_CFG register *******************/
3706 #define ISO7816_CLK_CFG_ETU_DIV_POS (0U)
3707 #define ISO7816_CLK_CFG_ETU_DIV_Len (10U)
3708 #define ISO7816_CLK_CFG_ETU_DIV_Msk (0x3FFUL << ISO7816_CLK_CFG_ETU_DIV_POS)
3709 #define ISO7816_CLK_CFG_ETU_DIV ISO7816_CLK_CFG_ETU_DIV_Msk
3710
3711 #define ISO7816_CLK_CFG_CLK_DIV_POS (16U)
3712 #define ISO7816_CLK_CFG_CLK_DIV_Len (8U)
3713 #define ISO7816_CLK_CFG_CLK_DIV_Msk (0xFFUL << ISO7816_CLK_CFG_CLK_DIV_POS)
3714 #define ISO7816_CLK_CFG_CLK_DIV ISO7816_CLK_CFG_CLK_DIV_Msk
3715
3716 #define ISO7816_CLK_CFG_CLK_STOP_SEL_POS (31U)
3717 #define ISO7816_CLK_CFG_CLK_STOP_SEL_Len (1U)
3718 #define ISO7816_CLK_CFG_CLK_STOP_SEL_Msk (0x1UL << ISO7816_CLK_CFG_CLK_STOP_SEL_POS)
3719 #define ISO7816_CLK_CFG_CLK_STOP_SEL ISO7816_CLK_CFG_CLK_STOP_SEL_Msk
3720
3721 /******************* Bit definition for ISO7816_TIMES_CFG register *******************/
3722 #define ISO7816_TIMES_CFG_GUARD_TIME_POS (0U)
3723 #define ISO7816_TIMES_CFG_GUARD_TIME_Len (10U)
3724 #define ISO7816_TIMES_CFG_GUARD_TIME_Msk (0x3FFUL << ISO7816_TIMES_CFG_GUARD_TIME_POS)
3725 #define ISO7816_TIMES_CFG_GUARD_TIME ISO7816_TIMES_CFG_GUARD_TIME_Msk
3726
3727 #define ISO7816_TIMES_CFG_WAIT_TIME_POS (12U)
3728 #define ISO7816_TIMES_CFG_WAIT_TIME_Len (18U)
3729 #define ISO7816_TIMES_CFG_WAIT_TIME_Msk (0x3FFFFUL << ISO7816_TIMES_CFG_WAIT_TIME_POS)
3730 #define ISO7816_TIMES_CFG_WAIT_TIME ISO7816_TIMES_CFG_WAIT_TIME_Msk
3731
3732 /******************* Bit definition for ISO7816_DATA_CFG register *******************/
3733 #define ISO7816_DATA_CFG_CODING_POS (0U)
3734 #define ISO7816_DATA_CFG_CODING_Len (1U)
3735 #define ISO7816_DATA_CFG_CODING_Msk (0x1UL << ISO7816_DATA_CFG_CODING_POS)
3736 #define ISO7816_DATA_CFG_CODING ISO7816_DATA_CFG_CODING_Msk
3737
3738 #define ISO7816_DATA_CFG_DETECT_CODING_POS (1U)
3739 #define ISO7816_DATA_CFG_DETECT_CODING_Len (1U)
3740 #define ISO7816_DATA_CFG_DETECT_CODING_Msk (0x1UL << ISO7816_DATA_CFG_DETECT_CODING_POS)
3741 #define ISO7816_DATA_CFG_DETECT_CODING ISO7816_DATA_CFG_DETECT_CODING_Msk
3742
3743 #define ISO7816_DATA_CFG_RETRY_LIMIT_POS (4U)
3744 #define ISO7816_DATA_CFG_RETRY_LIMIT_Len (3U)
3745 #define ISO7816_DATA_CFG_RETRY_LIMIT_Msk (0x7UL << ISO7816_DATA_CFG_RETRY_LIMIT_POS)
3746 #define ISO7816_DATA_CFG_RETRY_LIMIT ISO7816_DATA_CFG_RETRY_LIMIT_Msk
3747
3748 /******************* Bit definition for ISO7816_ADDR register *******************/
3749 #define ISO7816_ADDR_ADDR_FRAC_POS (0U)
3750 #define ISO7816_ADDR_ADDR_FRAC_Len (2U)
3751 #define ISO7816_ADDR_ADDR_FRAC_Msk (0x3UL << ISO7816_ADDR_ADDR_FRAC_POS)
3752 #define ISO7816_ADDR_ADDR_FRAC ISO7816_ADDR_ADDR_FRAC_Msk
3753
3754 #define ISO7816_ADDR_ADDR_POS (2U)
3755 #define ISO7816_ADDR_ADDR_Len (18U)
3756 #define ISO7816_ADDR_ADDR_Msk (0x3FFFFUL << ISO7816_ADDR_ADDR_POS)
3757 #define ISO7816_ADDR_ADDR ISO7816_ADDR_ADDR_Msk
3758
3759 /******************* Bit definition for ISO7816_START_ADDR register *******************/
3760 #define ISO7816_START_ADDR_START_ADDR_POS (2U)
3761 #define ISO7816_START_ADDR_START_ADDR_Len (18U)
3762 #define ISO7816_START_ADDR_START_ADDR_Msk (0x3FFFFUL << ISO7816_START_ADDR_START_ADDR_POS)
3763 #define ISO7816_START_ADDR_START_ADDR ISO7816_START_ADDR_START_ADDR_Msk
3764
3765 #define ISO7816_START_ADDR_BASE_ADDR_POS (20U)
3766 #define ISO7816_START_ADDR_BASE_ADDR_Len (12U)
3767 #define ISO7816_START_ADDR_BASE_ADDR_Msk (0xFFFUL << ISO7816_START_ADDR_BASE_ADDR_POS)
3768 #define ISO7816_START_ADDR_BASE_ADDR ISO7816_START_ADDR_BASE_ADDR_Msk
3769
3770 /******************* Bit definition for ISO7816_RX_END_ADDR register *******************/
3771 #define ISO7816_RX_END_ADDR_RX_END_AF_POS (0U)
3772 #define ISO7816_RX_END_ADDR_RX_END_AF_Len (2U)
3773 #define ISO7816_RX_END_ADDR_RX_END_AF_Msk (0x3UL << ISO7816_RX_END_ADDR_RX_END_AF_POS)
3774 #define ISO7816_RX_END_ADDR_RX_END_AF ISO7816_RX_END_ADDR_RX_END_AF_Msk
3775
3776 #define ISO7816_RX_END_ADDR_RX_END_ADDR_POS (2U)
3777 #define ISO7816_RX_END_ADDR_RX_END_ADDR_Len (18U)
3778 #define ISO7816_RX_END_ADDR_RX_END_ADDR_Msk (0x3FFFFUL << ISO7816_RX_END_ADDR_RX_END_ADDR_POS)
3779 #define ISO7816_RX_END_ADDR_RX_END_ADDR ISO7816_RX_END_ADDR_RX_END_ADDR_Msk
3780
3781 /******************* Bit definition for ISO7816_TX_END_ADDR register *******************/
3782 #define ISO7816_TX_END_ADDR_TX_END_AF_POS (0U)
3783 #define ISO7816_TX_END_ADDR_TX_END_AF_Len (2U)
3784 #define ISO7816_TX_END_ADDR_TX_END_AF_Msk (0x3UL << ISO7816_TX_END_ADDR_TX_END_AF_POS)
3785 #define ISO7816_TX_END_ADDR_TX_END_AF ISO7816_TX_END_ADDR_TX_END_AF_Msk
3786
3787 #define ISO7816_TX_END_ADDR_TX_END_ADDR_POS (2U)
3788 #define ISO7816_TX_END_ADDR_TX_END_ADDR_Len (18U)
3789 #define ISO7816_TX_END_ADDR_TX_END_ADDR_Msk (0x3FFFFUL << ISO7816_TX_END_ADDR_TX_END_ADDR_POS)
3790 #define ISO7816_TX_END_ADDR_TX_END_ADDR ISO7816_TX_END_ADDR_TX_END_ADDR_Msk
3791
3792 /* ================================================================================================================= */
3793 /* ================ MCU_SUB ================ */
3794 /* ================================================================================================================= */
3795 /******************* Bit definition for MCU_SUB_REG_SENSE_ADC_FIFO register ****************/
3796 #define MCU_SUB_SNSADC_FF_DATA_Pos (0U)
3797 #define MCU_SUB_SNSADC_FF_DATA_Len (32U)
3798 #define MCU_SUB_SNSADC_FF_DATA_Msk (0xFFFFFFFFU)
3799 #define MCU_SUB_SNSADC_FF_DATA MCU_SUB_SNSADC_FF_DATA_Msk
3800
3801 /******************* Bit definition for MCU_SUB_REG_SENSE_FF_THRESH register ****/
3802 #define MCU_SUB_SNSADC_FF_THRESH_Pos (0U)
3803 #define MCU_SUB_SNSADC_FF_THRESH_Len (6U)
3804 #define MCU_SUB_SNSADC_FF_THRESH_Msk (0x3FU << MCU_SUB_SNSADC_FF_THRESH_Pos)
3805 #define MCU_SUB_SNSADC_FF_THRESH MCU_SUB_SNSADC_FF_THRESH_Msk
3806
3807 /******************* Bit definition for MCU_SUB_REG_SENSE_ADC_STAT register *****/
3808 #define MCU_SUB_SNSADC_STAT_VAL_Pos (8U)
3809 #define MCU_SUB_SNSADC_STAT_VAL_Len (1U)
3810 #define MCU_SUB_SNSADC_STAT_VAL_Msk (0x1U << MCU_SUB_SNSADC_STAT_VAL_Pos)
3811 #define MCU_SUB_SNSADC_STAT_VAL MCU_SUB_SNSADC_STAT_VAL_Msk
3812
3813 #define MCU_SUB_SNSADC_STAT_FF_COUNT_Pos (0U)
3814 #define MCU_SUB_SNSADC_STAT_FF_COUNT_Len (7U)
3815 #define MCU_SUB_SNSADC_STAT_FF_COUNT_Msk (0x7FU << MCU_SUB_SNSADC_STAT_FF_COUNT_Pos)
3816 #define MCU_SUB_SNSADC_STAT_FF_COUNT MCU_SUB_SNSADC_STAT_FF_COUNT_Msk
3817
3818
3819 /******************* Bit definition for MCU_SUB_REG_COMM_TMR_DEEPSLPSTAT register ***********/
3820 #define MCU_SUB_COMM_TMR_DEEPSLPSTAT_DEEPSLDUR_Pos (0U)
3821 #define MCU_SUB_COMM_TMR_DEEPSLPSTAT_DEEPSLDUR_Len (32U)
3822 #define MCU_SUB_COMM_TMR_DEEPSLPSTAT_DEEPSLDUR_Msk (0xFFFFFFFFU)
3823 #define MCU_SUB_COMM_TMR_DEEPSLPSTAT_DEEPSLDUR MCU_SUB_COMM_TMR_DEEPSLPSTAT_DEEPSLDUR_Msk
3824
3825 /*************** Bit definition for MCU_SUB_REG_DPAD_RE_N_BUS register ********/
3826 #define MCU_SUB_DPAD_RE_N_BUS_Pos (0U)
3827 #define MCU_SUB_DPAD_RE_N_BUS_Len (32U)
3828 #define MCU_SUB_DPAD_RE_N_BUS_Msk (0xFFFFFFFFU)
3829 #define MCU_SUB_DPAD_RE_N_BUS MCU_SUB_DPAD_RE_N_BUS_Msk
3830
3831 /************* Bit definition for MCU_SUB_REG_DPAD_RTYP_BUS register **********/
3832 #define MCU_SUB_DPAD_RTYP_BUS_Pos (0U)
3833 #define MCU_SUB_DPAD_RTYP_BUS_Len (32U)
3834 #define MCU_SUB_DPAD_RTYP_BUS_Msk (0xFFFFFFFFU)
3835 #define MCU_SUB_DPAD_RTYP_BUS MCU_SUB_DPAD_RTYP_BUS_Msk
3836
3837 /********** Bit definition for MCU_SUB_REG_DPAD_IE_N_BUS register *************/
3838 #define MCU_SUB_DPAD_IE_N_BUS_Pos (0U)
3839 #define MCU_SUB_DPAD_IE_N_BUS_Len (32U)
3840 #define MCU_SUB_DPAD_IE_N_BUS_Msk (0xFFFFFFFFU)
3841 #define MCU_SUB_DPAD_IE_N_BUS MCU_SUB_DPAD_IE_N_BUS_Msk
3842
3843 /********** Bit definition for MCU_SUB_REG_MSIO_REG register ******************/
3844 #define MCU_SUB_MSIO_REG0_PFAST_CS_CTRL_Pos (8U)
3845 #define MCU_SUB_MSIO_REG0_PFAST_CS_CTRL_Len (4U)
3846 #define MCU_SUB_MSIO_REG0_PFAST_CS_CTRL_Msk (0xFU << MCU_SUB_MSIO_REG0_PFAST_CS_CTRL_Pos)
3847 #define MCU_SUB_MSIO_REG0_PFAST_CS_CTRL MCU_SUB_MSIO_REG0_PFAST_CS_CTRL_Msk
3848
3849 #define MCU_SUB_MSIO_REG0_MSIO_C_Pos (0U)
3850 #define MCU_SUB_MSIO_REG0_MSIO_C_Len (5U)
3851 #define MCU_SUB_MSIO_REG0_MSIO_C_Msk (0x1FU << MCU_SUB_MSIO_REG0_MSIO_C_Pos)
3852 #define MCU_SUB_MSIO_REG0_MSIO_C MCU_SUB_MSIO_REG0_MSIO_C_Msk
3853
3854 /********** Bit definition for MCU_SUB_REG_BLE_FERP_CTL register ****************/
3855 #define MUC_SUB_BLE_FERP_CTL_TESTBUS_SEL_Pos (4U)
3856 #define MUC_SUB_BLE_FERP_CTL_TESTBUS_SEL_Len (3U)
3857 #define MUC_SUB_BLE_FERP_CTL_TESTBUS_SEL_Msk (0x7U << MUC_SUB_BLE_FERP_CTL_TESTBUS_SEL_Pos)
3858 #define MUC_SUB_BLE_FERP_CTL_TESTBUS_SEL MUC_SUB_BLE_FERP_CTL_TESTBUS_SEL_Msk
3859
3860 #define MCU_SUB_BLE_FERP_CTL_FERP_EN_Pos (0U)
3861 #define MCU_SUB_BLE_FERP_CTL_FERP_EN_Len (1U)
3862 #define MCU_SUB_BLE_FERP_CTL_FERP_EN_Msk (0x1U << MCU_SUB_BLE_FERP_CTL_FERP_EN_Pos)
3863 #define MCU_SUB_BLE_FERP_CTL_FERP_EN MCU_SUB_BLE_FERP_CTL_FERP_EN_Msk
3864
3865 /********** Bit definition for MCU_SUB_REG_DMA_ACC_SEL register ****************/
3866 #define MCU_SUB_DMA_ACC_SEL_I2C1_I2SS_Pos (1U)
3867 #define MCU_SUB_DMA_ACC_SEL_I2C1_I2SS_Len (1U)
3868 #define MCU_SUB_DMA_ACC_SEL_I2C1_I2SS_Msk (0x1U << MCU_SUB_DMA_ACC_SEL_I2C1_I2SS_Pos)
3869 #define MCU_SUB_DMA_ACC_SEL_I2C1_I2SS MCU_SUB_DMA_ACC_SEL_I2C1_I2SS_Msk
3870
3871 #define MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM_Pos (0U)
3872 #define MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM_Len (1U)
3873 #define MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM_Msk (0x1U << MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM_Pos)
3874 #define MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM_Msk
3875
3876 /********** Bit definition for MCU_SUB_REG_SECURITY_RESET register ****************/
3877 #define MCU_SUB_SECURITY_RESET_PRESENT_Pos (6U)
3878 #define MCU_SUB_SECURITY_RESET_PRESENT_Len (1U)
3879 #define MCU_SUB_SECURITY_RESET_PRESENT_Msk (0x1U << MCU_SUB_SECURITY_RESET_PRESENT_Pos)
3880 #define MCU_SUB_SECURITY_RESET_PRESENT MCU_SUB_SECURITY_RESET_PRESENT_Msk
3881
3882 #define MCU_SUB_SECURITY_RESET_TRNG_Pos (5U)
3883 #define MCU_SUB_SECURITY_RESET_TRNG_Len (1U)
3884 #define MCU_SUB_SECURITY_RESET_TRNG_Msk (0x1U << MCU_SUB_SECURITY_RESET_TRNG_Pos)
3885 #define MCU_SUB_SECURITY_RESET_TRNG MCU_SUB_SECURITY_RESET_TRNG_Msk
3886
3887 #define MCU_SUB_SECURITY_RESET_RAMKEY_Pos (4U)
3888 #define MCU_SUB_SECURITY_RESET_RAMKEY_Len (1U)
3889 #define MCU_SUB_SECURITY_RESET_RAMKEY_Msk (0x1U << MCU_SUB_SECURITY_RESET_RAMKEY_Pos)
3890 #define MCU_SUB_SECURITY_RESET_RAMKEY MCU_SUB_SECURITY_RESET_RAMKEY_Msk
3891
3892 #define MCU_SUB_SECURITY_RESET_EFUSE_Pos (3U)
3893 #define MCU_SUB_SECURITY_RESET_EFUSE_Len (1U)
3894 #define MCU_SUB_SECURITY_RESET_EFUSE_Msk (0x1U << MCU_SUB_SECURITY_RESET_EFUSE_Pos)
3895 #define MCU_SUB_SECURITY_RESET_EFUSE MCU_SUB_SECURITY_RESET_EFUSE_Msk
3896
3897 #define MCU_SUB_SECURITY_RESET_PKC_Pos (2U)
3898 #define MCU_SUB_SECURITY_RESET_PKC_Len (1U)
3899 #define MCU_SUB_SECURITY_RESET_PKC_Msk (0x1U << MCU_SUB_SECURITY_RESET_PKC_Pos)
3900 #define MCU_SUB_SECURITY_RESET_PKC MCU_SUB_SECURITY_RESET_PKC_Msk
3901
3902 #define MCU_SUB_SECURITY_RESET_HMAC_Pos (1U)
3903 #define MCU_SUB_SECURITY_RESET_HMAC_Len (1U)
3904 #define MCU_SUB_SECURITY_RESET_HMAC_Msk (0x1U << MCU_SUB_SECURITY_RESET_HMAC_Pos)
3905 #define MCU_SUB_SECURITY_RESET_HMAC MCU_SUB_SECURITY_RESET_HMAC_Msk
3906
3907 #define MCU_SUB_SECURITY_RESET_AES_Pos (0U)
3908 #define MCU_SUB_SECURITY_RESET_AES_Len (1U)
3909 #define MCU_SUB_SECURITY_RESET_AES_Msk (0x1U << MCU_SUB_SECURITY_RESET_AES_Pos)
3910 #define MCU_SUB_SECURITY_RESET_AES MCU_SUB_SECURITY_RESET_AES_Msk
3911
3912 /********** Bit definition for MCU_SUB_REG_PMU_ID_REG register *****************/
3913 #define MCU_SUB_PMU_ID_Pos (0U)
3914 #define MCU_SUB_PMU_ID_Len (8U)
3915 #define MCU_SUB_PMU_ID_Msk (0xFFU << MCU_SUB_PMU_ID_Pos)
3916 #define MCU_SUB_PMU_ID MCU_SUB_PMU_ID_Msk
3917
3918 /********** Bit definition for MCU_SUB_REG_PWR_AVG_CTL_REG register ************/
3919 #define MCU_SUB_PWR_AVG_CTL0_TPA_ADC_OUT_Pos (24U)
3920 #define MCU_SUB_PWR_AVG_CTL0_TPA_ADC_OUT_Len (8U)
3921 #define MCU_SUB_PWR_AVG_CTL0_TPA_ADC_OUT_Msk (0xFFU << MCU_SUB_PWR_AVG_CTL0_TPA_ADC_OUT_Pos)
3922 #define MCU_SUB_PWR_AVG_CTL0_TPA_ADC_OUT MCU_SUB_PWR_AVG_CTL0_TPA_ADC_OUT_Msk
3923
3924 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_ERR_Pos (18U)
3925 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_ERR_Len (1U)
3926 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_ERR_Msk (0x1U << MCU_SUB_PWR_AVG_CTL0_AVG_PWR_ERR_Pos)
3927 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_ERR MCU_SUB_PWR_AVG_CTL0_AVG_PWR_ERR_Msk
3928
3929 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_RDY_Pos (16U)
3930 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_RDY_Len (1U)
3931 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_RDY_Msk (0x1U << MCU_SUB_PWR_AVG_CTL0_AVG_PWR_RDY_Pos)
3932 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_RDY MCU_SUB_PWR_AVG_CTL0_AVG_PWR_RDY_Msk
3933
3934 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_Pos (8U)
3935 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_Len (8U)
3936 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR_Msk (0xFFU << MCU_SUB_PWR_AVG_CTL0_AVG_PWR_Pos)
3937 #define MCU_SUB_PWR_AVG_CTL0_AVG_PWR MCU_SUB_PWR_AVG_CTL0_AVG_PWR_Msk
3938
3939 #define MCU_SUB_PWR_AVG_CTL0_SAMPL_PWR_Pos (4U)
3940 #define MCU_SUB_PWR_AVG_CTL0_SAMPL_PWR_Len (4U)
3941 #define MCU_SUB_PWR_AVG_CTL0_SAMPL_PWR_Msk (0xFU << MCU_SUB_PWR_AVG_CTL0_SAMPL_PWR_Pos)
3942 #define MCU_SUB_PWR_AVG_CTL0_SAMPL_PWR MCU_SUB_PWR_AVG_CTL0_SAMPL_PWR_Msk
3943
3944 #define MCU_SUB_PWR_AVG_CTL0_BLE_F_TX_EN_Pos (3U)
3945 #define MCU_SUB_PWR_AVG_CTL0_BLE_F_TX_EN_Len (1U)
3946 #define MCU_SUB_PWR_AVG_CTL0_BLE_F_TX_EN_Msk (0x1 << MCU_SUB_PWR_AVG_CTL0_BLE_F_TX_EN_Pos)
3947 #define MCU_SUB_PWR_AVG_CTL0_BLE_F_TX_EN MCU_SUB_PWR_AVG_CTL0_BLE_F_TX_EN_Msk
3948
3949 #define MCU_SUB_PWR_AVG_CTL0_ONESHOT_EN_Pos (2U)
3950 #define MCU_SUB_PWR_AVG_CTL0_ONESHOT_EN_Len (1U)
3951 #define MCU_SUB_PWR_AVG_CTL0_ONESHOT_EN_Msk (0x1 << MCU_SUB_PWR_AVG_CTL0_ONESHOT_EN_Pos)
3952 #define MCU_SUB_PWR_AVG_CTL0_ONESHOT_EN MCU_SUB_PWR_AVG_CTL0_ONESHOT_EN_Msk
3953
3954 #define MCU_SUB_PWR_AVG_CTL0_PWR_AVG_EN_Pos (0U)
3955 #define MCU_SUB_PWR_AVG_CTL0_PWR_AVG_EN_Len (1U)
3956 #define MCU_SUB_PWR_AVG_CTL0_PWR_AVG_EN_Msk (0x1 << MCU_SUB_PWR_AVG_CTL0_PWR_AVG_EN_Pos)
3957 #define MCU_SUB_PWR_AVG_CTL0_PWR_AVG_EN MCU_SUB_PWR_AVG_CTL0_PWR_AVG_EN_Msk
3958
3959 /********** Bit definition for MCU_SUB_REG_CLK_CAL_CTL_REG0 register ************/
3960 #define MCU_SUB_CLK_CAL_CTL0_EN_Pos (0U)
3961 #define MCU_SUB_CLK_CAL_CTL0_EN_Len (1U)
3962 #define MCU_SUB_CLK_CAL_CTL0_EN_Msk (0x1U << MCU_SUB_CLK_CAL_CTL0_EN_Pos)
3963 #define MCU_SUB_CLK_CAL_CTL0_EN MCU_SUB_CLK_CAL_CTL0_EN_Msk
3964
3965 #define MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_EN_Pos (1U)
3966 #define MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_EN_Len (1U)
3967 #define MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_EN_Msk (0x1U << MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_EN_Pos)
3968 #define MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_EN MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_EN_Msk
3969
3970 #define MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_VAL_Pos (4U)
3971 #define MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_VAL_Len (12U)
3972 #define MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_VAL_Msk (0xFFFU << MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_VAL_Pos)
3973 #define MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_VAL MCU_SUB_CLK_CAL_CTL0_CNT_LOAD_VAL_Msk
3974
3975 #define MCU_SUB_CLK_CAL_CTL0_STS_CNT_RDY_Pos (16U)
3976 #define MCU_SUB_CLK_CAL_CTL0_STS_CNT_RDY_Len (1U)
3977 #define MCU_SUB_CLK_CAL_CTL0_STS_CNT_RDY_Msk (0x1U << MCU_SUB_CLK_CAL_CTL0_STS_CNT_RDY_Pos)
3978 #define MCU_SUB_CLK_CAL_CTL0_STS_CNT_RDY MCU_SUB_CLK_CAL_CTL0_STS_CNT_RDY_Msk
3979
3980 /********** Bit definition for MCU_SUB_REG_CLK_CAL_CTL_REG1 register ************/
3981 #define MCU_SUB_CLK_CAL_CTL1_STS_CNT_VAL_Pos (0U)
3982 #define MCU_SUB_CLK_CAL_CTL1_STS_CNT_VAL_Len (24U)
3983 #define MCU_SUB_CLK_CAL_CTL1_STS_CNT_VAL_Msk (0xFFFFFFU << MCU_SUB_CLK_CAL_CTL1_STS_CNT_VAL_Pos)
3984 #define MCU_SUB_CLK_CAL_CTL1_STS_CNT_VAL MCU_SUB_CLK_CAL_CTL1_STS_CNT_VAL_Msk
3985
3986 /********** Bit definition for MCU_SUB_REG_DPAD_MUX_CTL_00_07 register **********/
3987 #define MCU_SUB_DPAD_MUX_CTL_00_07_Pos (0U)
3988 #define MCU_SUB_DPAD_MUX_CTL_00_07_Len (32U)
3989 #define MCU_SUB_DPAD_MUX_CTL_00_07_Msk (0xFFFFFFFFU)
3990 #define MCU_SUB_DPAD_MUX_CTL_00_07 MCU_SUB_DPAD_MUX_CTL_00_07_Msk
3991
3992 #define MCU_SUB_DPAD_MUX_CTL_SEL_Msk (0xFU)
3993 #define MCU_SUB_DPAD_MUX_CTL_SEL_00 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 0)
3994 #define MCU_SUB_DPAD_MUX_CTL_SEL_01 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 4)
3995 #define MCU_SUB_DPAD_MUX_CTL_SEL_02 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 8)
3996 #define MCU_SUB_DPAD_MUX_CTL_SEL_03 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 12)
3997 #define MCU_SUB_DPAD_MUX_CTL_SEL_04 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 16)
3998 #define MCU_SUB_DPAD_MUX_CTL_SEL_05 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 20)
3999 #define MCU_SUB_DPAD_MUX_CTL_SEL_06 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 24)
4000 #define MCU_SUB_DPAD_MUX_CTL_SEL_07 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 28)
4001
4002 /********** Bit definition for MCU_SUB_REG_DPAD_MUX_CTL_08_15 register **********/
4003 #define MCU_SUB_DPAD_MUX_CTL_08_15_Pos (0U)
4004 #define MCU_SUB_DPAD_MUX_CTL_08_15_Len (32U)
4005 #define MCU_SUB_DPAD_MUX_CTL_08_15_Msk (0xFFFFFFFFU)
4006 #define MCU_SUB_DPAD_MUX_CTL_08_15 MCU_SUB_DPAD_MUX_CTL_08_15_Msk
4007
4008 #define MCU_SUB_DPAD_MUX_CTL_SEL_08 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 0)
4009 #define MCU_SUB_DPAD_MUX_CTL_SEL_09 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 4)
4010 #define MCU_SUB_DPAD_MUX_CTL_SEL_10 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 8)
4011 #define MCU_SUB_DPAD_MUX_CTL_SEL_11 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 12)
4012 #define MCU_SUB_DPAD_MUX_CTL_SEL_12 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 16)
4013 #define MCU_SUB_DPAD_MUX_CTL_SEL_13 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 20)
4014 #define MCU_SUB_DPAD_MUX_CTL_SEL_14 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 24)
4015 #define MCU_SUB_DPAD_MUX_CTL_SEL_15 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 28)
4016
4017 /********** Bit definition for MCU_SUB_REG_DPAD_MUX_CTL_16_23 register **********/
4018 #define MCU_SUB_DPAD_MUX_CTL_16_23_Pos (0U)
4019 #define MCU_SUB_DPAD_MUX_CTL_16_23_Len (32U)
4020 #define MCU_SUB_DPAD_MUX_CTL_16_23_Msk (0xFFFFFFFFU)
4021 #define MCU_SUB_DPAD_MUX_CTL_16_23 MCU_SUB_DPAD_MUX_CTL_16_23_Msk
4022
4023 #define MCU_SUB_DPAD_MUX_CTL_SEL_16 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 0)
4024 #define MCU_SUB_DPAD_MUX_CTL_SEL_17 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 4)
4025 #define MCU_SUB_DPAD_MUX_CTL_SEL_18 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 8)
4026 #define MCU_SUB_DPAD_MUX_CTL_SEL_19 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 12)
4027 #define MCU_SUB_DPAD_MUX_CTL_SEL_20 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 16)
4028 #define MCU_SUB_DPAD_MUX_CTL_SEL_21 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 20)
4029 #define MCU_SUB_DPAD_MUX_CTL_SEL_22 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 24)
4030 #define MCU_SUB_DPAD_MUX_CTL_SEL_23 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 28)
4031
4032 /********** Bit definition for MCU_SUB_REG_DPAD_MUX_CTL_24_31 register ***********/
4033 #define MCU_SUB_DPAD_MUX_CTL_24_31_Pos (0U)
4034 #define MCU_SUB_DPAD_MUX_CTL_24_31_Len (32U)
4035 #define MCU_SUB_DPAD_MUX_CTL_24_31_Msk (0xFFFFFFFFU)
4036 #define MCU_SUB_DPAD_MUX_CTL_24_31 MCU_SUB_DPAD_MUX_CTL_24_31_Msk
4037
4038 #define MCU_SUB_DPAD_MUX_CTL_SEL_24 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 0)
4039 #define MCU_SUB_DPAD_MUX_CTL_SEL_25 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 4)
4040 #define MCU_SUB_DPAD_MUX_CTL_SEL_26 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 8)
4041 #define MCU_SUB_DPAD_MUX_CTL_SEL_27 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 12)
4042 #define MCU_SUB_DPAD_MUX_CTL_SEL_28 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 16)
4043 #define MCU_SUB_DPAD_MUX_CTL_SEL_29 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 20)
4044 #define MCU_SUB_DPAD_MUX_CTL_SEL_30 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 24)
4045 #define MCU_SUB_DPAD_MUX_CTL_SEL_31 (MCU_SUB_DPAD_MUX_CTL_SEL_Msk << 28)
4046
4047 /********** Bit definition for MCU_SUB_REG_EFUSE_PWR_DELTA0 register ***********/
4048 #define MCU_SUB_EFUSE_PWR_DELTA0_Pos (0U)
4049 #define MCU_SUB_EFUSE_PWR_DELTA0_Len (16U)
4050 #define MCU_SUB_EFUSE_PWR_DELTA0_Msk (0xFFFFU << MCU_SUB_EFUSE_PWR_DELTA0_Pos)
4051 #define MCU_SUB_EFUSE_PWR_DELTA0 MCU_SUB_EFUSE_PWR_DELTA0_Msk
4052
4053 #define MCU_SUB_EFUSE_PWR_DELTA1_Pos (16U)
4054 #define MCU_SUB_EFUSE_PWR_DELTA1_Len (16U)
4055 #define MCU_SUB_EFUSE_PWR_DELTA1_Msk (0xFFFFU << MCU_SUB_EFUSE_PWR_DELTA1_Pos)
4056 #define MCU_SUB_EFUSE_PWR_DELTA1 MCU_SUB_EFUSE_PWR_DELTA1_Msk
4057
4058 /********** Bit definition for MCU_SUB_REG_EFUSE_PWR_DELTA0 register ***********/
4059 #define MCU_SUB_EFUSE_PWR_DELTA2_Pos (0U)
4060 #define MCU_SUB_EFUSE_PWR_DELTA2_Len (16U)
4061 #define MCU_SUB_EFUSE_PWR_DELTA2_Msk (0xFFFFU << MCU_SUB_EFUSE_PWR_DELTA2_Pos)
4062 #define MCU_SUB_EFUSE_PWR_DELTA2 MCU_SUB_EFUSE_PWR_DELTA2_Msk
4063
4064 /********** Bit definition for MCU_SUB_REG_EFUSE_PWR_CTRL0 register ***********/
4065 #define MCU_SUB_EFUSE_PWR_CTL0_EN_Pos (0U)
4066 #define MCU_SUB_EFUSE_PWR_CTL0_EN_Len (1U)
4067 #define MCU_SUB_EFUSE_PWR_CTL0_EN_Msk (0x1U << MCU_SUB_EFUSE_PWR_CTL0_EN_Pos)
4068 #define MCU_SUB_EFUSE_PWR_CTL0_EN MCU_SUB_EFUSE_PWR_CTL0_EN_Msk
4069
4070 #define MCU_SUB_EFUSE_PWR_CTL0_BGN_Pos (2U)
4071 #define MCU_SUB_EFUSE_PWR_CTL0_BGN_Len (1U)
4072 #define MCU_SUB_EFUSE_PWR_CTL0_BGN_Msk (0x1U << MCU_SUB_EFUSE_PWR_CTL0_BGN_Pos)
4073 #define MCU_SUB_EFUSE_PWR_CTL0_BGN MCU_SUB_EFUSE_PWR_CTL0_BGN_Msk
4074
4075 #define MCU_SUB_EFUSE_PWR_CTL0_STP_Pos (4U)
4076 #define MCU_SUB_EFUSE_PWR_CTL0_STP_Len (1U)
4077 #define MCU_SUB_EFUSE_PWR_CTL0_STP_Msk (0x1U << MCU_SUB_EFUSE_PWR_CTL0_STP_Pos)
4078 #define MCU_SUB_EFUSE_PWR_CTL0_STP MCU_SUB_EFUSE_PWR_CTL0_STP_Msk
4079
4080 /********** Bit definition for MCU_SUB_REG_EFUSE_PWR_CTRL1 register ***********/
4081 #define MCU_SUB_EFUSE_PWR_CTL0_EN_DONE_Pos (0U)
4082 #define MCU_SUB_EFUSE_PWR_CTL0_EN_DONE_Len (1U)
4083 #define MCU_SUB_EFUSE_PWR_CTL0_EN_DONE_Msk (0x1U << MCU_SUB_EFUSE_PWR_CTL0_EN_DONE_Pos)
4084 #define MCU_SUB_EFUSE_PWR_CTL0_EN_DONE MCU_SUB_EFUSE_PWR_CTL0_EN_DONE_Msk
4085
4086 #define MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE_Pos (4U)
4087 #define MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE_Len (1U)
4088 #define MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE_Msk (0x1U << MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE_Pos)
4089 #define MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE MCU_SUB_EFUSE_PWR_CTL0_DIS_DONE_Msk
4090
4091 /********** Bit definition for MCU_SUB_REG_I2S_CLK_CFG register ***********/
4092 #define MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL_Pos (18U)
4093 #define MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL_Len (1U)
4094 #define MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL_Msk (0x1U << MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL_Pos)
4095 #define MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL_Msk
4096
4097 #define MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN_Pos (16U)
4098 #define MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN_Len (1U)
4099 #define MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN_Msk (0x1U << MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN_Pos)
4100 #define MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN_Msk
4101
4102 #define MCU_SUB_I2S_CLK_CFG_DIV_CNT_Pos (0U)
4103 #define MCU_SUB_I2S_CLK_CFG_DIV_CNT_Len (12U)
4104 #define MCU_SUB_I2S_CLK_CFG_DIV_CNT_Msk (0xFFFU << MCU_SUB_I2S_CLK_CFG_DIV_CNT_Pos)
4105 #define MCU_SUB_I2S_CLK_CFG_DIV_CNT MCU_SUB_I2S_CLK_CFG_DIV_CNT_Msk
4106
4107 /********** Bit definition for MCU_SUB_REG_AON_PAD_MUX_CTL register ***********/
4108 #define MCU_SUB_AON_MUX_CTL_00_07_Pos (0U)
4109 #define MCU_SUB_AON_MUX_CTL_00_07_Len (32U)
4110 #define MCU_SUB_AON_MUX_CTL_00_07_Msk (0x00777770U)
4111 #define MCU_SUB_AON_MUX_CTL_00_07 MCU_SUB_AON_MUX_CTL_00_07_Msk
4112
4113 #define MCU_SUB_AON_MUX_CTL_SEL_Msk (0x7U)
4114 #define MCU_SUB_AON_MUX_CTL_SEL_01 (MCU_SUB_AON_MUX_CTL_SEL_Msk << 4)
4115 #define MCU_SUB_AON_MUX_CTL_SEL_02 (MCU_SUB_AON_MUX_CTL_SEL_Msk << 8)
4116 #define MCU_SUB_AON_MUX_CTL_SEL_03 (MCU_SUB_AON_MUX_CTL_SEL_Msk << 12)
4117 #define MCU_SUB_AON_MUX_CTL_SEL_04 (MCU_SUB_AON_MUX_CTL_SEL_Msk << 16)
4118 #define MCU_SUB_AON_MUX_CTL_SEL_05 (MCU_SUB_AON_MUX_CTL_SEL_Msk << 20)
4119
4120 /********** Bit definition for MCU_SUB_REG_MSIO_PAD_MUX_CTL register ***********/
4121 #define MCU_SUB_MSIO_MUX_CTL_00_04_Pos (0U)
4122 #define MCU_SUB_MSIO_MUX_CTL_00_04_Len (32U)
4123 #define MCU_SUB_MSIO_MUX_CTL_00_04_Msk (0x77777U)
4124 #define MCU_SUB_MSIO_MUX_CTL_00_04 MCU_SUB_MSIO_MUX_CTL_00_04_Msk
4125
4126 #define MCU_SUB_MSIO_MUX_CTL_SEL_Msk (0x7U)
4127 #define MCU_SUB_MSIO_MUX_CTL_SEL_00 (MCU_SUB_MSIO_MUX_CTL_SEL_Msk << 0)
4128 #define MCU_SUB_MSIO_MUX_CTL_SEL_01 (MCU_SUB_MSIO_MUX_CTL_SEL_Msk << 4)
4129 #define MCU_SUB_MSIO_MUX_CTL_SEL_02 (MCU_SUB_MSIO_MUX_CTL_SEL_Msk << 8)
4130 #define MCU_SUB_MSIO_MUX_CTL_SEL_03 (MCU_SUB_MSIO_MUX_CTL_SEL_Msk << 12)
4131 #define MCU_SUB_MSIO_MUX_CTL_SEL_04 (MCU_SUB_MSIO_MUX_CTL_SEL_Msk << 16)
4132
4133 /********** Bit definition for MCU_SUB_REG_MCU_SUBSYS_CG_CTRL_0 register ***********/
4134 #define MCU_SUB_WFI_MSK_HCLK_0 (0xFFFU)
4135
4136 #define MCU_SUB_WFI_I2S_S_HCLK_Pos (11U)
4137 #define MCU_SUB_WFI_I2S_S_HCLK_Len (1U)
4138 #define MCU_SUB_WFI_I2S_S_HCLK_Msk (0x01 << MCU_SUB_WFI_I2S_S_HCLK_Pos)
4139 #define MCU_SUB_WFI_I2S_S_HCLK MCU_SUB_WFI_I2S_S_HCLK_Msk
4140
4141 #define MCU_SUB_WFI_SERIAL_HCLK_Pos (10U)
4142 #define MCU_SUB_WFI_SERIAL_HCLK_Len (1U)
4143 #define MCU_SUB_WFI_SERIAL_HCLK_Msk (0x01 << MCU_SUB_WFI_SERIAL_HCLK_Pos)
4144 #define MCU_SUB_WFI_SERIAL_HCLK MCU_SUB_WFI_SERIAL_HCLK_Msk
4145
4146 #define MCU_SUB_WFI_APB_SUB_HCLK_Pos (9U)
4147 #define MCU_SUB_WFI_APB_SUB_HCLK_Len (1U)
4148 #define MCU_SUB_WFI_APB_SUB_HCLK_Msk (0x01 << MCU_SUB_WFI_APB_SUB_HCLK_Pos)
4149 #define MCU_SUB_WFI_APB_SUB_HCLK MCU_SUB_WFI_APB_SUB_HCLK_Msk
4150
4151 #define MCU_SUB_WFI_BLE_BRG_HCLK_Pos (8U)
4152 #define MCU_SUB_WFI_BLE_BRG_HCLK_Len (1U)
4153 #define MCU_SUB_WFI_BLE_BRG_HCLK_Msk (0x01 << MCU_SUB_WFI_BLE_BRG_HCLK_Pos)
4154 #define MCU_SUB_WFI_BLE_BRG_HCLK MCU_SUB_WFI_BLE_BRG_HCLK_Msk
4155
4156 #define MCU_SUB_WFI_DMA_HCLK_Pos (7U)
4157 #define MCU_SUB_WFI_DMA_HCLK_Len (1U)
4158 #define MCU_SUB_WFI_DMA_HCLK_Msk (0x01 << MCU_SUB_WFI_DMA_HCLK_Pos)
4159 #define MCU_SUB_WFI_DMA_HCLK MCU_SUB_WFI_DMA_HCLK_Msk
4160
4161 #define MCU_SUB_WFI_GPIO_HCLK_Pos (6U)
4162 #define MCU_SUB_WFI_GPIO_HCLK_Len (1U)
4163 #define MCU_SUB_WFI_GPIO_HCLK_Msk (0x01 << MCU_SUB_WFI_GPIO_HCLK_Pos)
4164 #define MCU_SUB_WFI_GPIO_HCLK MCU_SUB_WFI_GPIO_HCLK_Msk
4165
4166 #define MCU_SUB_WFI_SNSADC_HCLK_Pos (5U)
4167 #define MCU_SUB_WFI_SNSADC_HCLK_Len (1U)
4168 #define MCU_SUB_WFI_SNSADC_HCLK_Msk (0x01 << MCU_SUB_WFI_SNSADC_HCLK_Pos)
4169 #define MCU_SUB_WFI_SNSADC_HCLK MCU_SUB_WFI_SNSADC_HCLK_Msk
4170
4171 #define MCU_SUB_WFI_ROM_HCLK_Pos (4U)
4172 #define MCU_SUB_WFI_ROM_HCLK_Len (1U)
4173 #define MCU_SUB_WFI_ROM_HCLK_Msk (0x01 << MCU_SUB_WFI_ROM_HCLK_Pos)
4174 #define MCU_SUB_WFI_ROM_HCLK MCU_SUB_WFI_ROM_HCLK_Msk
4175
4176 #define MCU_SUB_WFI_PWM_HCLK_Pos (3U)
4177 #define MCU_SUB_WFI_PWM_HCLK_Len (1U)
4178 #define MCU_SUB_WFI_PWM_HCLK_Msk (0x01 << MCU_SUB_WFI_PWM_HCLK_Pos)
4179 #define MCU_SUB_WFI_PWM_HCLK MCU_SUB_WFI_PWM_HCLK_Msk
4180
4181 #define MCU_SUB_WFI_HTB_HCLK_Pos (2U)
4182 #define MCU_SUB_WFI_HTB_HCLK_Len (1U)
4183 #define MCU_SUB_WFI_HTB_HCLK_Msk (0x01 << MCU_SUB_WFI_HTB_HCLK_Pos)
4184 #define MCU_SUB_WFI_HTB_HCLK MCU_SUB_WFI_HTB_HCLK_Msk
4185
4186 #define MCU_SUB_WFI_SIM_HCLK_Pos (1U)
4187 #define MCU_SUB_WFI_SIM_HCLK_Len (1U)
4188 #define MCU_SUB_WFI_SIM_HCLK_Msk (0x01 << MCU_SUB_WFI_SIM_HCLK_Pos)
4189 #define MCU_SUB_WFI_SIM_HCLK MCU_SUB_WFI_SIM_HCLK_Msk
4190
4191 #define MCU_SUB_WFI_SECU_HCLK_Pos (0U)
4192 #define MCU_SUB_WFI_SECU_HCLK_Len (1U)
4193 #define MCU_SUB_WFI_SECU_HCLK_Msk (0x01 << MCU_SUB_WFI_SECU_HCLK_Pos)
4194 #define MCU_SUB_WFI_SECU_HCLK MCU_SUB_WFI_SECU_HCLK_Msk
4195
4196 /********** Bit definition for MCU_SUB_REG_MCU_SUBSYS_CG_CTRL_1 register ***********/
4197 #define MCU_SUB_FORCE_MSK_HCLK_0 (0xFFFU)
4198
4199 #define MCU_SUB_FORCE_I2S_S_HCLK_Pos (11U)
4200 #define MCU_SUB_FORCE_I2S_S_HCLK_Len (1U)
4201 #define MCU_SUB_FORCE_I2S_S_HCLK_Msk (0x01 << MCU_SUB_FORCE_I2S_S_HCLK_Pos)
4202 #define MCU_SUB_FORCE_I2S_S_HCLK MCU_SUB_FORCE_I2S_S_HCLK_Msk
4203
4204 #define MCU_SUB_FORCE_SERIAL_HCLK_Pos (10U)
4205 #define MCU_SUB_FORCE_SERIAL_HCLK_Len (1U)
4206 #define MCU_SUB_FORCE_SERIAL_HCLK_Msk (0x01 << MCU_SUB_FORCE_SERIAL_HCLK_Pos)
4207 #define MCU_SUB_FORCE_SERIAL_HCLK MCU_SUB_FORCE_SERIAL_HCLK_Msk
4208
4209 #define MCU_SUB_FORCE_APB_SUB_HCLK_Pos (9U)
4210 #define MCU_SUB_FORCE_APB_SUB_HCLK_Len (1U)
4211 #define MCU_SUB_FORCE_APB_SUB_HCLK_Msk (0x01 << MCU_SUB_FORCE_APB_SUB_HCLK_Pos)
4212 #define MCU_SUB_FORCE_APB_SUB_HCLK MCU_SUB_FORCE_APB_SUB_HCLK_Msk
4213
4214 #define MCU_SUB_FORCE_BLE_BRG_HCLK_Pos (8U)
4215 #define MCU_SUB_FORCE_BLE_BRG_HCLK_Len (1U)
4216 #define MCU_SUB_FORCE_BLE_BRG_HCLK_Msk (0x01 << MCU_SUB_FORCE_BLE_BRG_HCLK_Pos)
4217 #define MCU_SUB_FORCE_BLE_BRG_HCLK MCU_SUB_FORCE_BLE_BRG_HCLK_Msk
4218
4219 #define MCU_SUB_FORCE_DMA_HCLK_Pos (7U)
4220 #define MCU_SUB_FORCE_DMA_HCLK_Len (1U)
4221 #define MCU_SUB_FORCE_DMA_HCLK_Msk (0x01 << MCU_SUB_FORCE_DMA_HCLK_Pos)
4222 #define MCU_SUB_FORCE_DMA_HCLK MCU_SUB_FORCE_DMA_HCLK_Msk
4223
4224 #define MCU_SUB_FORCE_GPIO_HCLK_Pos (6U)
4225 #define MCU_SUB_FORCE_GPIO_HCLK_Len (1U)
4226 #define MCU_SUB_FORCE_GPIO_HCLK_Msk (0x01 << MCU_SUB_FORCE_GPIO_HCLK_Pos)
4227 #define MCU_SUB_FORCE_GPIO_HCLK MCU_SUB_FORCE_GPIO_HCLK_Msk
4228
4229 #define MCU_SUB_FORCE_SNSADC_HCLK_Pos (5U)
4230 #define MCU_SUB_FORCE_SNSADC_HCLK_Len (1U)
4231 #define MCU_SUB_FORCE_SNSADC_HCLK_Msk (0x01 << MCU_SUB_FORCE_SNSADC_HCLK_Pos)
4232 #define MCU_SUB_FORCE_SNSADC_HCLK MCU_SUB_FORCE_SNSADC_HCLK_Msk
4233
4234 #define MCU_SUB_FORCE_ROM_HCLK_Pos (4U)
4235 #define MCU_SUB_FORCE_ROM_HCLK_Len (1U)
4236 #define MCU_SUB_FORCE_ROM_HCLK_Msk (0x01 << MCU_SUB_FORCE_ROM_HCLK_Pos)
4237 #define MCU_SUB_FORCE_ROM_HCLK MCU_SUB_FORCE_ROM_HCLK_Msk
4238
4239 #define MCU_SUB_FORCE_PWM_HCLK_Pos (3U)
4240 #define MCU_SUB_FORCE_PWM_HCLK_Len (1U)
4241 #define MCU_SUB_FORCE_PWM_HCLK_Msk (0x01 << MCU_SUB_FORCE_PWM_HCLK_Pos)
4242 #define MCU_SUB_FORCE_PWM_HCLK MCU_SUB_FORCE_PWM_HCLK_Msk
4243
4244 #define MCU_SUB_FORCE_HTB_HCLK_Pos (2U)
4245 #define MCU_SUB_FORCE_HTB_HCLK_Len (1U)
4246 #define MCU_SUB_FORCE_HTB_HCLK_Msk (0x01 << MCU_SUB_FORCE_HTB_HCLK_Pos)
4247 #define MCU_SUB_FORCE_HTB_HCLK MCU_SUB_FORCE_HTB_HCLK_Msk
4248
4249 #define MCU_SUB_FORCE_SIM_HCLK_Pos (1U)
4250 #define MCU_SUB_FORCE_SIM_HCLK_Len (1U)
4251 #define MCU_SUB_FORCE_SIM_HCLK_Msk (0x01 << MCU_SUB_FORCE_SIM_HCLK_Pos)
4252 #define MCU_SUB_FORCE_SIM_HCLK MCU_SUB_FORCE_SIM_HCLK_Msk
4253
4254 #define MCU_SUB_FORCE_SECU_HCLK_Pos (0U)
4255 #define MCU_SUB_FORCE_SECU_HCLK_Len (1U)
4256 #define MCU_SUB_FORCE_SECU_HCLK_Msk (0x01 << MCU_SUB_FORCE_SECU_HCLK_Pos)
4257 #define MCU_SUB_FORCE_SECU_HCLK MCU_SUB_FORCE_SECU_HCLK_Msk
4258
4259 /********** Bit definition for MCU_SUB_REG_MCU_SUBSYS_CG_CTRL_2 register ***********/
4260 #define MCU_SUB_FORCE_MSK_HCLK_1 (0x00070000U)
4261
4262 #define MCU_SUB_FORCE_SRAM_HCLK_Pos (18U)
4263 #define MCU_SUB_FORCE_SRAM_HCLK_Len (1U)
4264 #define MCU_SUB_FORCE_SRAM_HCLK_Msk (0x1UL << MCU_SUB_FORCE_SRAM_HCLK_Pos)
4265 #define MCU_SUB_FORCE_SRAM_HCLK MCU_SUB_FORCE_SRAM_HCLK_Msk
4266
4267 #define MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos (17U)
4268 #define MCU_SUB_FORCE_XF_XQSPI_HCLK_Len (1U)
4269 #define MCU_SUB_FORCE_XF_XQSPI_HCLK_Msk (0x1UL << MCU_SUB_FORCE_XF_XQSPI_HCLK_Pos)
4270 #define MCU_SUB_FORCE_XF_XQSPI_HCLK MCU_SUB_FORCE_XF_XQSPI_HCLK_Msk
4271
4272 #define MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos (16U)
4273 #define MCU_SUB_FORCE_AON_MCUSUB_HCLK_Len (1U)
4274 #define MCU_SUB_FORCE_AON_MCUSUB_HCLK_Msk (0x1UL << MCU_SUB_FORCE_AON_MCUSUB_HCLK_Pos)
4275 #define MCU_SUB_FORCE_AON_MCUSUB_HCLK MCU_SUB_FORCE_AON_MCUSUB_HCLK_Msk
4276
4277 #define MCU_SUB_WFI_MSK_HCLK_1 (0x00000007U)
4278
4279 #define MCU_SUB_WFI_SRAM_HCLK_Pos (2U)
4280 #define MCU_SUB_WFI_SRAM_HCLK_Len (1U)
4281 #define MCU_SUB_WFI_SRAM_HCLK_Msk (0x1UL << MCU_SUB_WFI_SRAM_HCLK_Pos)
4282 #define MCU_SUB_WFI_SRAM_HCLK MCU_SUB_WFI_SRAM_HCLK_Msk
4283
4284 #define MCU_SUB_WFI_XF_XQSPI_HCLK_Pos (1U)
4285 #define MCU_SUB_WFI_XF_XQSPI_HCLK_Len (1U)
4286 #define MCU_SUB_WFI_XF_XQSPI_HCLK_Msk (0x1UL << MCU_SUB_WFI_XF_XQSPI_HCLK_Pos)
4287 #define MCU_SUB_WFI_XF_XQSPI_HCLK MCU_SUB_WFI_XF_XQSPI_HCLK_Msk
4288
4289 #define MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos (0U)
4290 #define MCU_SUB_WFI_AON_MCUSUB_HCLK_Len (1U)
4291 #define MCU_SUB_WFI_AON_MCUSUB_HCLK_Msk (0x1UL << MCU_SUB_WFI_AON_MCUSUB_HCLK_Pos)
4292 #define MCU_SUB_WFI_AON_MCUSUB_HCLK MCU_SUB_WFI_AON_MCUSUB_HCLK_Msk
4293
4294 /********** Bit definition for MCU_SUB_REG_MCU_PERIPH_GC register ***********/
4295 #define MCU_SUB_FORCE_MSK_HCLK_2 (0x0A01FF00U)
4296 #define MCU_SUB_WFI_MSK_HCLK_2 (0x05000000U)
4297 #define MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos (27U)
4298 #define MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Len (1U)
4299 #define MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Msk (0x1UL << MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Pos)
4300 #define MCU_SUB_FORCE_XQSPI_DIV4_PCLK MCU_SUB_FORCE_XQSPI_DIV4_PCLK_Msk
4301
4302 #define MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos (26U)
4303 #define MCU_SUB_WFI_XQSPI_DIV4_PCLK_Len (1U)
4304 #define MCU_SUB_WFI_XQSPI_DIV4_PCLK_Msk (0x1UL << MCU_SUB_WFI_XQSPI_DIV4_PCLK_Pos)
4305 #define MCU_SUB_WFI_XQSPI_DIV4_PCLK MCU_SUB_WFI_XQSPI_DIV4_PCLK_Msk
4306
4307 #define MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos (25U)
4308 #define MCU_SUB_FORCE_SECU_DIV4_PCLK_Len (1U)
4309 #define MCU_SUB_FORCE_SECU_DIV4_PCLK_Msk (0x1UL << MCU_SUB_FORCE_SECU_DIV4_PCLK_Pos)
4310 #define MCU_SUB_FORCE_SECU_DIV4_PCLK MCU_SUB_FORCE_SECU_DIV4_PCLK_Msk
4311
4312 #define MCU_SUB_WFI_SECU_DIV4_PCLK_Pos (24U)
4313 #define MCU_SUB_WFI_SECU_DIV4_PCLK_Len (1U)
4314 #define MCU_SUB_WFI_SECU_DIV4_PCLK_Msk (0x1UL << MCU_SUB_WFI_SECU_DIV4_PCLK_Pos)
4315 #define MCU_SUB_WFI_SECU_DIV4_PCLK MCU_SUB_WFI_SECU_DIV4_PCLK_Msk
4316
4317 #define MCU_SUB_FORCE_I2S_HCLK_Pos (16U)
4318 #define MCU_SUB_FORCE_I2S_HCLK_Len (1U)
4319 #define MCU_SUB_FORCE_I2S_HCLK_Msk (0x1UL << MCU_SUB_FORCE_I2S_HCLK_Pos)
4320 #define MCU_SUB_FORCE_I2S_HCLK MCU_SUB_FORCE_I2S_HCLK_Msk
4321
4322 #define MCU_SUB_FORCE_QSPI1_HCLK_Pos (15U)
4323 #define MCU_SUB_FORCE_QSPI1_HCLK_Len (1U)
4324 #define MCU_SUB_FORCE_QSPI1_HCLK_Msk (0x1UL << MCU_SUB_FORCE_QSPI1_HCLK_Pos)
4325 #define MCU_SUB_FORCE_QSPI1_HCLK MCU_SUB_FORCE_QSPI1_HCLK_Msk
4326
4327 #define MCU_SUB_FORCE_QSPI0_HCLK_Pos (14U)
4328 #define MCU_SUB_FORCE_QSPI0_HCLK_Len (1U)
4329 #define MCU_SUB_FORCE_QSPI0_HCLK_Msk (0x1UL << MCU_SUB_FORCE_QSPI0_HCLK_Pos)
4330 #define MCU_SUB_FORCE_QSPI0_HCLK MCU_SUB_FORCE_QSPI0_HCLK_Msk
4331
4332 #define MCU_SUB_FORCE_SPIS_HCLK_Pos (13U)
4333 #define MCU_SUB_FORCE_SPIS_HCLK_Len (1U)
4334 #define MCU_SUB_FORCE_SPIS_HCLK_Msk (0x1UL << MCU_SUB_FORCE_SPIS_HCLK_Pos)
4335 #define MCU_SUB_FORCE_SPIS_HCLK MCU_SUB_FORCE_SPIS_HCLK_Msk
4336
4337 #define MCU_SUB_FORCE_SPIM_HCLK_Pos (12U)
4338 #define MCU_SUB_FORCE_SPIM_HCLK_Len (1U)
4339 #define MCU_SUB_FORCE_SPIM_HCLK_Msk (0x1UL << MCU_SUB_FORCE_SPIM_HCLK_Pos)
4340 #define MCU_SUB_FORCE_SPIM_HCLK MCU_SUB_FORCE_SPIM_HCLK_Msk
4341
4342 #define MCU_SUB_FORCE_I2C1_HCLK_Pos (11U)
4343 #define MCU_SUB_FORCE_I2C1_HCLK_Len (1U)
4344 #define MCU_SUB_FORCE_I2C1_HCLK_Msk (0x1UL << MCU_SUB_FORCE_I2C1_HCLK_Pos)
4345 #define MCU_SUB_FORCE_I2C1_HCLK MCU_SUB_FORCE_I2C1_HCLK_Msk
4346
4347 #define MCU_SUB_FORCE_I2C0_HCLK_Pos (10U)
4348 #define MCU_SUB_FORCE_I2C0_HCLK_Len (1U)
4349 #define MCU_SUB_FORCE_I2C0_HCLK_Msk (0x1UL << MCU_SUB_FORCE_I2C0_HCLK_Pos)
4350 #define MCU_SUB_FORCE_I2C0_HCLK MCU_SUB_FORCE_I2C0_HCLK_Msk
4351
4352 #define MCU_SUB_FORCE_UART1_HCLK_Pos (9U)
4353 #define MCU_SUB_FORCE_UART1_HCLK_Len (1U)
4354 #define MCU_SUB_FORCE_UART1_HCLK_Msk (0x1UL << MCU_SUB_FORCE_UART1_HCLK_Pos)
4355 #define MCU_SUB_FORCE_UART1_HCLK MCU_SUB_FORCE_UART1_HCLK_Msk
4356
4357 #define MCU_SUB_FORCE_UART0_HCLK_Pos (8U)
4358 #define MCU_SUB_FORCE_UART0_HCLK_Len (1U)
4359 #define MCU_SUB_FORCE_UART0_HCLK_Msk (0x1UL << MCU_SUB_FORCE_UART0_HCLK_Pos)
4360 #define MCU_SUB_FORCE_UART0_HCLK MCU_SUB_FORCE_UART0_HCLK_Msk
4361
4362 #define MCU_SUB_I2S_LP_EN_Pos (2U)
4363 #define MCU_SUB_I2S_LP_EN_Len (1U)
4364 #define MCU_SUB_I2S_LP_EN_Msk (0x1UL << MCU_SUB_I2S_LP_EN_Pos)
4365 #define MCU_SUB_I2S_LP_EN MCU_SUB_I2S_LP_EN_Msk
4366
4367 #define MCU_SUB_UART_LP_PCLK_EN_Pos (1U)
4368 #define MCU_SUB_UART_LP_PCLK_EN_Len (1U)
4369 #define MCU_SUB_UART_LP_PCLK_EN_Msk (0x1UL << MCU_SUB_UART_LP_PCLK_EN_Pos)
4370 #define MCU_SUB_UART_LP_PCLK_EN MCU_SUB_UART_LP_PCLK_EN_Msk
4371
4372 #define MCU_SUB_UART_LP_SCLK_EN_Pos (0U)
4373 #define MCU_SUB_UART_LP_SCLK_EN_Len (1U)
4374 #define MCU_SUB_UART_LP_SCLK_EN_Msk (0x1UL << MCU_SUB_UART_LP_SCLK_EN_Pos)
4375 #define MCU_SUB_UART_LP_SCLK_EN MCU_SUB_UART_LP_SCLK_EN_Msk
4376
4377 /********** Bit definition for MCU_SUB_REG_BLE_DSLEEP_CORR_EN register ***********/
4378 #define MCU_SUB_BLE_DSLEEP_CORR_EN_Pos (0U)
4379 #define MCU_SUB_BLE_DSLEEP_CORR_EN_Len (2U)
4380 #define MCU_SUB_BLE_DSLEEP_CORR_EN_Msk (0x3U << MCU_SUB_BLE_DSLEEP_CORR_EN_Pos)
4381 #define MCU_SUB_BLE_DSLEEP_CORR_HW_EN (0x02 << MCU_SUB_BLE_DSLEEP_CORR_EN_Pos)
4382 #define MCU_SUB_BLE_DSLEEP_CORR_SW_EN (0x01 << MCU_SUB_BLE_DSLEEP_CORR_EN_Pos)
4383
4384 /********** Bit definition for MCU_SUB_REG_BLE_DSLEEP_HW_TIM_CORR register ***********/
4385 #define MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_CLK_PERIOD_Pos (12U)
4386 #define MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_CLK_PERIOD_Len (18U)
4387 #define MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_CLK_PERIOD_Msk (0x3FFFFU << MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_CLK_PERIOD_Pos)
4388 #define MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_CLK_PERIOD MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_CLK_PERIOD_Msk
4389
4390 #define MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_DELAY_Pos (0U)
4391 #define MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_DELAY_Len (9U)
4392 #define MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_DELAY_Msk (0x1FFU << MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_DELAY_Pos)
4393 #define MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_DELAY MCU_SUB_BLE_DSLEEP_HW_TIM_CORR_DELAY_Msk
4394
4395 /* ================================================================================================================= */
4396 /* ================ PKC ================ */
4397 /* ================================================================================================================= */
4398
4399 /******************* Bit definition for PKC_CTRL register *******************/
4400 #define PKC_CTRL_EN_Pos (0U)
4401 #define PKC_CTRL_EN_Len (1U)
4402 #define PKC_CTRL_EN_Msk (0x1U << PKC_CTRL_EN_Pos)
4403 #define PKC_CTRL_EN PKC_CTRL_EN_Msk
4404
4405 #define PKC_CTRL_START_Pos (1U)
4406 #define PKC_CTRL_START_Len (1U)
4407 #define PKC_CTRL_START_Msk (0x1U << PKC_CTRL_START_Pos)
4408 #define PKC_CTRL_START PKC_CTRL_START_Msk
4409
4410 #define PKC_CTRL_SWCTRL_Pos (4U)
4411 #define PKC_CTRL_SWCTRL_Len (1U)
4412 #define PKC_CTRL_SWCTRL_Msk (0x1U << PKC_CTRL_SWCTRL_Pos)
4413 #define PKC_CTRL_SWCTRL PKC_CTRL_SWCTRL_Msk
4414
4415 #define PKC_CTRL_SWRST_Pos (8U)
4416 #define PKC_CTRL_SWRST_Len (1U)
4417 #define PKC_CTRL_SWRST_Msk (0x1U << PKC_CTRL_SWRST_Pos)
4418 #define PKC_CTRL_SWRST PKC_CTRL_SWRST_Msk
4419
4420 /******************* Bit definition for PKC_CONFIG0 register ****************/
4421 #define PKC_CONFIG0_KPTR_Pos (0U)
4422 #define PKC_CONFIG0_KPTR_Len (9U)
4423 #define PKC_CONFIG0_KPTR_Msk (0x000001FFU)
4424 #define PKC_CONFIG0_KPTR PKC_CONFIG0_KPTR_Msk
4425
4426 #define PKC_CONFIG0_RPTR_Pos (16U)
4427 #define PKC_CONFIG0_RPTR_Len (9U)
4428 #define PKC_CONFIG0_RPTR_Msk (0x01FF0000U)
4429 #define PKC_CONFIG0_RPTR PKC_CONFIG0_RPTR_Msk
4430
4431 /******************* Bit definition for PKC_CONFIG1 register ****************/
4432 #define PKC_CONFIG1_PPTR_Pos (0U)
4433 #define PKC_CONFIG1_PPTR_Len (9U)
4434 #define PKC_CONFIG1_PPTR_Msk (0x000001FFU)
4435 #define PKC_CONFIG1_PPTR PKC_CONFIG1_PPTR_Msk
4436
4437 #define PKC_CONFIG1_RSQPTR_Pos (16U)
4438 #define PKC_CONFIG1_RSQPTR_Len (9U)
4439 #define PKC_CONFIG1_RSQPTR_Msk (0x01FF0000U)
4440 #define PKC_CONFIG1_RSQPTR PKC_CONFIG1_RSQPTR_Msk
4441
4442 /******************* Bit definition for PKC_CONFIG2 register ****************/
4443 #define PKC_CONFIG2_GXPTR_Pos (0U)
4444 #define PKC_CONFIG2_GXPTR_Len (9U)
4445 #define PKC_CONFIG2_GXPTR_Msk (0x000001FFU)
4446 #define PKC_CONFIG2_GXPTR PKC_CONFIG2_GXPTR_Msk
4447
4448 #define PKC_CONFIG2_GYPTR_Pos (16U)
4449 #define PKC_CONFIG2_GYPTR_Len (9U)
4450 #define PKC_CONFIG2_GYPTR_Msk (0x01FF0000U)
4451 #define PKC_CONFIG2_GYPTR PKC_CONFIG2_GYPTR_Msk
4452
4453 /******************* Bit definition for PKC_CONFIG3 register ****************/
4454 #define PKC_CONFIG3_GZPTR_Pos (0U)
4455 #define PKC_CONFIG3_GZPTR_Len (9U)
4456 #define PKC_CONFIG3_GZPTR_Msk (0x000001FFU)
4457 #define PKC_CONFIG3_GZPTR PKC_CONFIG3_GZPTR_Msk
4458
4459 #define PKC_CONFIG3_R0XPTR_Pos (16U)
4460 #define PKC_CONFIG3_R0XPTR_Len (9U)
4461 #define PKC_CONFIG3_R0XPTR_Msk (0x01FF0000U)
4462 #define PKC_CONFIG3_R0XPTR PKC_CONFIG3_R0XPTR_Msk
4463
4464 /******************* Bit definition for PKC_CONFIG4 register ****************/
4465 #define PKC_CONFIG4_R0YPTR_Pos (0U)
4466 #define PKC_CONFIG4_R0YPTR_Len (9U)
4467 #define PKC_CONFIG4_R0YPTR_Msk (0x000001FFU)
4468 #define PKC_CONFIG4_R0YPTR PKC_CONFIG4_R0YPTR_Msk
4469
4470 #define PKC_CONFIG4_R0ZPTR_Pos (16U)
4471 #define PKC_CONFIG4_R0ZPTR_Len (9U)
4472 #define PKC_CONFIG4_R0ZPTR_Msk (0x01FF0000U)
4473 #define PKC_CONFIG4_R0ZPTR PKC_CONFIG4_R0ZPTR_Msk
4474
4475 /******************* Bit definition for PKC_CONFIG5 register ****************/
4476 #define PKC_CONFIG5_R1XPTR_Pos (0U)
4477 #define PKC_CONFIG5_R1XPTR_Len (9U)
4478 #define PKC_CONFIG5_R1XPTR_Msk (0x000001FFU)
4479 #define PKC_CONFIG5_R1XPTR PKC_CONFIG5_R1XPTR_Msk
4480
4481 #define PKC_CONFIG5_R1YPTR_Pos (16U)
4482 #define PKC_CONFIG5_R1YPTR_Len (9U)
4483 #define PKC_CONFIG5_R1YPTR_Msk (0x01FF0000U)
4484 #define PKC_CONFIG5_R1YPTR PKC_CONFIG5_R1YPTR_Msk
4485
4486 /******************* Bit definition for PKC_CONFIG6 register ****************/
4487 #define PKC_CONFIG6_R1ZPTR_Pos (0U)
4488 #define PKC_CONFIG6_R1ZPTR_Len (9U)
4489 #define PKC_CONFIG6_R1ZPTR_Msk (0x000001FFU)
4490 #define PKC_CONFIG6_R1ZPTR PKC_CONFIG6_R1ZPTR_Msk
4491
4492 #define PKC_CONFIG6_TMP1PTR_Pos (16U)
4493 #define PKC_CONFIG6_TMP1PTR_Len (9U)
4494 #define PKC_CONFIG6_TMP1PTR_Msk (0x01FF0000U)
4495 #define PKC_CONFIG6_TMP1PTR PKC_CONFIG6_TMP1PTR_Msk
4496
4497 /******************* Bit definition for PKC_CONFIG7 register ****************/
4498 #define PKC_CONFIG7_TMP2PTR_Pos (0U)
4499 #define PKC_CONFIG7_TMP2PTR_Len (9U)
4500 #define PKC_CONFIG7_TMP2PTR_Msk (0x000001FFU)
4501 #define PKC_CONFIG7_TMP2PTR PKC_CONFIG7_TMP2PTR_Msk
4502
4503 #define PKC_CONFIG7_TMP3PTR_Pos (16U)
4504 #define PKC_CONFIG7_TMP3PTR_Len (9U)
4505 #define PKC_CONFIG7_TMP3PTR_Msk (0x01FF0000U)
4506 #define PKC_CONFIG7_TMP3PTR PKC_CONFIG7_TMP3PTR_Msk
4507
4508 /******************* Bit definition for PKC_CONFIG8 register ****************/
4509 #define PKC_CONFIG8_TMP4PTR_Pos (0U)
4510 #define PKC_CONFIG8_TMP4PTR_Len (9U)
4511 #define PKC_CONFIG8_TMP4PTR_Msk (0x000001FFU)
4512 #define PKC_CONFIG8_TMP4PTR PKC_CONFIG8_TMP4PTR_Msk
4513
4514 #define PKC_CONFIG8_TMP5PTR_Pos (16U)
4515 #define PKC_CONFIG8_TMP5PTR_Len (9U)
4516 #define PKC_CONFIG8_TMP5PTR_Msk (0x01FF0000U)
4517 #define PKC_CONFIG8_TMP5PTR PKC_CONFIG8_TMP5PTR_Msk
4518
4519 /******************* Bit definition for PKC_CONFIG9 register ****************/
4520 #define PKC_CONFIG9_TMP6PTR_Pos (0U)
4521 #define PKC_CONFIG9_TMP6PTR_Len (9U)
4522 #define PKC_CONFIG9_TMP6PTR_Msk (0x000001FFU)
4523 #define PKC_CONFIG9_TMP6PTR PKC_CONFIG9_TMP6PTR_Msk
4524
4525 #define PKC_CONFIG9_CONST1PTR_Pos (16U)
4526 #define PKC_CONFIG9_CONST1PTR_Len (9U)
4527 #define PKC_CONFIG9_CONST1PTR_Msk (0x01FF0000U)
4528 #define PKC_CONFIG9_CONST1PTR PKC_CONFIG9_CONST1PTR_Msk
4529
4530 /******************* Bit definition for PKC_CONFIG10 register ****************/
4531 #define PKC_CONFIG10_X1PTR_Pos (0U)
4532 #define PKC_CONFIG10_X1PTR_Len (9U)
4533 #define PKC_CONFIG10_X1PTR_Msk (0x000001FFU)
4534 #define PKC_CONFIG10_X1PTR PKC_CONFIG10_X1PTR_Msk
4535
4536 #define PKC_CONFIG10_X2PTR_Pos (16U)
4537 #define PKC_CONFIG10_X2PTR_Len (9U)
4538 #define PKC_CONFIG10_X2PTR_Msk (0x01FF0000U)
4539 #define PKC_CONFIG10_X2PTR PKC_CONFIG10_X2PTR_Msk
4540
4541 /******************* Bit definition for PKC_CONFIG11 register ****************/
4542 #define PKC_CONFIG11_MITMPPTR_Pos (0U)
4543 #define PKC_CONFIG11_MITMPPTR_Len (9U)
4544 #define PKC_CONFIG11_MITMPPTR_Msk (0x000001FFU)
4545 #define PKC_CONFIG11_MITMPPTR PKC_CONFIG11_MITMPPTR_Msk
4546
4547 #define PKC_CONFIG11_TMPKPTR_Pos (16U)
4548 #define PKC_CONFIG11_TMPKPTR_Len (9U)
4549 #define PKC_CONFIG11_TMPKPTR_Msk (0x01FF0000U)
4550 #define PKC_CONFIG11_TMPKPTR PKC_CONFIG11_TMPKPTR_Msk
4551
4552 /******************* Bit definition for PKC_CONFIG12 register ****************/
4553 #define PKC_CONFIG12_APTR_Pos (0U)
4554 #define PKC_CONFIG12_APTR_Len (9U)
4555 #define PKC_CONFIG12_APTR_Msk (0x000001FFU)
4556 #define PKC_CONFIG12_APTR PKC_CONFIG12_APTR_Msk
4557
4558 #define PKC_CONFIG12_BPTR_Pos (16U)
4559 #define PKC_CONFIG12_BPTR_Len (9U)
4560 #define PKC_CONFIG12_BPTR_Msk (0x01FF0000U)
4561 #define PKC_CONFIG12_BPTR PKC_CONFIG12_BPTR_Msk
4562
4563 /******************* Bit definition for PKC_CONFIG13 register ****************/
4564 #define PKC_CONFIG13_CONSTQ_Pos (0U)
4565 #define PKC_CONFIG13_CONSTQ_Len (32U)
4566 #define PKC_CONFIG13_CONSTQ_Msk (0xFFFFFFFFU)
4567 #define PKC_CONFIG13_CONSTQ PKC_CONFIG13_CONSTQ_Msk
4568
4569 /******************* Bit definition for PKC_SW_CTRL register *****************/
4570 #define PKC_SW_CTRL_OPSTART_Pos (0U)
4571 #define PKC_SW_CTRL_OPSTART_Len (1U)
4572 #define PKC_SW_CTRL_OPSTART_Msk (0x1U << PKC_SW_CTRL_OPSTART_Pos)
4573 #define PKC_SW_CTRL_OPSTART PKC_SW_CTRL_OPSTART_Msk
4574
4575 #define PKC_SW_CTRL_OPMODE_Pos (4U)
4576 #define PKC_SW_CTRL_OPMODE_Len (3U)
4577 #define PKC_SW_CTRL_OPMODE_Msk (0x7U << PKC_SW_CTRL_OPMODE_Pos)
4578 #define PKC_SW_CTRL_OPMODE PKC_SW_CTRL_OPMODE_Msk
4579
4580 #define PKC_SW_CTRL_STARTDM_Pos (8U)
4581 #define PKC_SW_CTRL_STARTDM_Len (1U)
4582 #define PKC_SW_CTRL_STARTDM_Msk (0x1U << PKC_SW_CTRL_STARTDM_Pos)
4583 #define PKC_SW_CTRL_STARTDM PKC_SW_CTRL_STARTDM_Msk
4584
4585 #define PKC_SW_CTRL_RANDEN_Pos (9U)
4586 #define PKC_SW_CTRL_RANDEN_Len (1U)
4587 #define PKC_SW_CTRL_RANDEN_Msk (0x1U << PKC_SW_CTRL_RANDEN_Pos)
4588 #define PKC_SW_CTRL_RANDEN PKC_SW_CTRL_RANDEN_Msk
4589
4590 /******************* Bit definition for PKC_SW_CONFIG0 register ************/
4591 #define PKC_SW_CONFIG0_MMAPTR_Pos (0U)
4592 #define PKC_SW_CONFIG0_MMAPTR_Len (9U)
4593 #define PKC_SW_CONFIG0_MMAPTR_Msk (0x000001FFU)
4594 #define PKC_SW_CONFIG0_MMAPTR PKC_SW_CONFIG0_MMAPTR_Msk
4595
4596 #define PKC_SW_CONFIG0_MMBPTR_Pos (16U)
4597 #define PKC_SW_CONFIG0_MMBPTR_Len (9U)
4598 #define PKC_SW_CONFIG0_MMBPTR_Msk (0x01FF0000U)
4599 #define PKC_SW_CONFIG0_MMBPTR PKC_SW_CONFIG0_MMBPTR_Msk
4600
4601 /******************* Bit definition for PKC_SW_CONFIG1 register ************/
4602 #define PKC_SW_CONFIG1_MMPPTR_Pos (0U)
4603 #define PKC_SW_CONFIG1_MMPPTR_Len (9U)
4604 #define PKC_SW_CONFIG1_MMPPTR_Msk (0x000001FFU)
4605 #define PKC_SW_CONFIG1_MMPPTR PKC_SW_CONFIG1_MMPPTR_Msk
4606
4607 #define PKC_SW_CONFIG1_MMCPTR_Pos (16U)
4608 #define PKC_SW_CONFIG1_MMCPTR_Len (9U)
4609 #define PKC_SW_CONFIG1_MMCPTR_Msk (0x01FF0000U)
4610 #define PKC_SW_CONFIG1_MMCPTR PKC_SW_CONFIG1_MMCPTR_Msk
4611
4612 /******************* Bit definition for PKC_SW_CONFIG2 register ************/
4613 #define PKC_SW_CONFIG2_MASAPTR_Pos (0U)
4614 #define PKC_SW_CONFIG2_MASAPTR_Len (9U)
4615 #define PKC_SW_CONFIG2_MASAPTR_Msk (0x000001FFU)
4616 #define PKC_SW_CONFIG2_MASAPTR PKC_SW_CONFIG2_MASAPTR_Msk
4617
4618 #define PKC_SW_CONFIG2_MASBPTR_Pos (16U)
4619 #define PKC_SW_CONFIG2_MASBPTR_Len (9U)
4620 #define PKC_SW_CONFIG2_MASBPTR_Msk (0x01FF0000U)
4621 #define PKC_SW_CONFIG2_MASBPTR PKC_SW_CONFIG2_MASBPTR_Msk
4622
4623 /******************* Bit definition for PKC_SW_CONFIG3 register ************/
4624 #define PKC_SW_CONFIG3_MASPPTR_Pos (0U)
4625 #define PKC_SW_CONFIG3_MASPPTR_Len (9U)
4626 #define PKC_SW_CONFIG3_MASPPTR_Msk (0x000001FFU)
4627 #define PKC_SW_CONFIG3_MASPPTR PKC_SW_CONFIG3_MASPPTR_Msk
4628
4629 #define PKC_SW_CONFIG3_MASCPTR_Pos (16U)
4630 #define PKC_SW_CONFIG3_MASCPTR_Len (9U)
4631 #define PKC_SW_CONFIG3_MASCPTR_Msk (0x01FF0000U)
4632 #define PKC_SW_CONFIG3_MASCPTR PKC_SW_CONFIG3_MASCPTR_Msk
4633
4634 /******************* Bit definition for PKC_SW_CONFIG4 register ************/
4635 #define PKC_SW_CONFIG4_MIUPTR_Pos (0U)
4636 #define PKC_SW_CONFIG4_MIUPTR_Len (9U)
4637 #define PKC_SW_CONFIG4_MIUPTR_Msk (0x000001FFU)
4638 #define PKC_SW_CONFIG4_MIUPTR PKC_SW_CONFIG4_MIUPTR_Msk
4639
4640 #define PKC_SW_CONFIG4_MIVPTR_Pos (16U)
4641 #define PKC_SW_CONFIG4_MIVPTR_Len (9U)
4642 #define PKC_SW_CONFIG4_MIVPTR_Msk (0x01FF0000U)
4643 #define PKC_SW_CONFIG4_MIVPTR PKC_SW_CONFIG4_MIVPTR_Msk
4644
4645 /******************* Bit definition for PKC_SW_CONFIG5 register ************/
4646 #define PKC_SW_CONFIG5_MIX1PTR_Pos (0U)
4647 #define PKC_SW_CONFIG5_MIX1PTR_Len (9U)
4648 #define PKC_SW_CONFIG5_MIX1PTR_Msk (0x000001FFU)
4649 #define PKC_SW_CONFIG5_MIX1PTR PKC_SW_CONFIG5_MIX1PTR_Msk
4650
4651 #define PKC_SW_CONFIG5_MIX2PTR_Pos (16U)
4652 #define PKC_SW_CONFIG5_MIX2PTR_Len (9U)
4653 #define PKC_SW_CONFIG5_MIX2PTR_Msk (0x01FF0000U)
4654 #define PKC_SW_CONFIG5_MIX2PTR PKC_SW_CONFIG5_MIX2PTR_Msk
4655
4656 /******************* Bit definition for PKC_SW_CONFIG6 register ************/
4657 #define PKC_SW_CONFIG6_MITMPPTR_Pos (0U)
4658 #define PKC_SW_CONFIG6_MITMPPTR_Len (9U)
4659 #define PKC_SW_CONFIG6_MITMPPTR_Msk (0x000001FFU)
4660 #define PKC_SW_CONFIG6_MITMPPTR PKC_SW_CONFIG6_MITMPPTR_Msk
4661
4662 /******************* Bit definition for PKC_SW_CONFIG7 register ************/
4663 #define PKC_SW_CONFIG7_WORDLEN_Pos (0U)
4664 #define PKC_SW_CONFIG7_WORDLEN_Len (6U)
4665 #define PKC_SW_CONFIG7_WORDLEN_Msk (0x0000003FU)
4666 #define PKC_SW_CONFIG7_WORDLEN PKC_SW_CONFIG7_WORDLEN_Msk
4667
4668 /******************* Bit definition for PKC_SW_CONFIG8 register ************/
4669 #define PKC_SW_CONFIG8_MIKOUT_Pos (0U)
4670 #define PKC_SW_CONFIG8_MIKOUT_Len (13U)
4671 #define PKC_SW_CONFIG8_MIKOUT_Msk (0x00001FFFU)
4672 #define PKC_SW_CONFIG8_MIKOUT PKC_SW_CONFIG8_MIKOUT_Msk
4673
4674 /******************* Bit definition for PKC_SW_CONFIG9 register ************/
4675 #define PKC_SW_CONFIG9_DMRNGSEED_Pos (0U)
4676 #define PKC_SW_CONFIG9_DMRNGSEED_Len (32U)
4677 #define PKC_SW_CONFIG9_DMRNGSEED_Msk (0xFFFFFFFFU)
4678 #define PKC_SW_CONFIG9_DMRNGSEED PKC_SW_CONFIG9_DMRNGSEED_Msk
4679
4680 /******************* Bit definition for PKC_SW_CONFIG10 register ************/
4681 #define PKC_SW_CONFIG10_BMAPTR_Pos (0U)
4682 #define PKC_SW_CONFIG10_BMAPTR_Len (9U)
4683 #define PKC_SW_CONFIG10_BMAPTR_Msk (0x000001FFU)
4684 #define PKC_SW_CONFIG10_BMAPTR PKC_SW_CONFIG10_BMAPTR_Msk
4685
4686 #define PKC_SW_CONFIG10_BMBPTR_Pos (16U)
4687 #define PKC_SW_CONFIG10_BMBPTR_Len (9U)
4688 #define PKC_SW_CONFIG10_BMBPTR_Msk (0x01FF0000U)
4689 #define PKC_SW_CONFIG10_BMBPTR PKC_SW_CONFIG10_BMBPTR_Msk
4690
4691 /******************* Bit definition for PKC_SW_CONFIG11 register ************/
4692 #define PKC_SW_CONFIG11_BMCPTR_Pos (0U)
4693 #define PKC_SW_CONFIG11_BMCPTR_Len (9U)
4694 #define PKC_SW_CONFIG11_BMCPTR_Msk (0x000001FFU)
4695 #define PKC_SW_CONFIG11_BMCPTR PKC_SW_CONFIG11_BMCPTR_Msk
4696
4697 #define PKC_SW_CONFIG11_BAAPTR_Pos (16U)
4698 #define PKC_SW_CONFIG11_BAAPTR_Len (9U)
4699 #define PKC_SW_CONFIG11_BAAPTR_Msk (0x01FF0000U)
4700 #define PKC_SW_CONFIG11_BAAPTR PKC_SW_CONFIG11_BAAPTR_Msk
4701
4702 /******************* Bit definition for PKC_SW_CONFIG12 register ************/
4703 #define PKC_SW_CONFIG12_BABPTR_Pos (0U)
4704 #define PKC_SW_CONFIG12_BABPTR_Len (9U)
4705 #define PKC_SW_CONFIG12_BABPTR_Msk (0x000001FFU)
4706 #define PKC_SW_CONFIG12_BABPTR PKC_SW_CONFIG12_BABPTR_Msk
4707
4708 #define PKC_SW_CONFIG12_BACPTR_Pos (16U)
4709 #define PKC_SW_CONFIG12_BACPTR_Len (9U)
4710 #define PKC_SW_CONFIG12_BACPTR_Msk (0x01FF0000U)
4711 #define PKC_SW_CONFIG12_BACPTR PKC_SW_CONFIG12_BACPTR_Msk
4712
4713 /******************* Bit definition for PKC_SW_CONFIG13 register ************/
4714 #define PKC_SW_CONFIG13_RANDSEED_Pos (0U)
4715 #define PKC_SW_CONFIG13_RANDSEED_Len (32U)
4716 #define PKC_SW_CONFIG13_RANDSEED_Msk (0xFFFFFFFFU)
4717 #define PKC_SW_CONFIG13_RANDSEED PKC_SW_CONFIG13_RANDSEED_Msk
4718
4719 /******************* Bit definition for PKC_INT_STATUS register ************/
4720 #define PKC_INTSTAT_DONE_Pos (0U)
4721 #define PKC_INTSTAT_DONE_Len (1U)
4722 #define PKC_INTSTAT_DONE_Msk (0x1U << PKC_INTSTAT_DONE_Pos)
4723 #define PKC_INTSTAT_DONE PKC_INTSTAT_DONE_Msk
4724
4725 #define PKC_INTSTAT_ERR_Pos (1U)
4726 #define PKC_INTSTAT_ERR_Len (1U)
4727 #define PKC_INTSTAT_ERR_Msk (0x1U << PKC_INTSTAT_ERR_Pos)
4728 #define PKC_INTSTAT_ERR PKC_INTSTAT_ERR_Msk
4729
4730 #define PKC_INTSTAT_BAOVF_Pos (2U)
4731 #define PKC_INTSTAT_BAOVF_Len (1U)
4732 #define PKC_INTSTAT_BAOVF_Msk (0x1U << PKC_INTSTAT_BAOVF_Pos)
4733 #define PKC_INTSTAT_BAOVF PKC_INTSTAT_BAOVF_Msk
4734
4735 /******************* Bit definition for PKC_INT_ENABLE register ************/
4736 #define PKC_INTEN_DONE_Pos (0U)
4737 #define PKC_INTEN_DONE_Len (1U)
4738 #define PKC_INTEN_DONE_Msk (0x1U << PKC_INTEN_DONE_Pos)
4739 #define PKC_INTEN_DONE PKC_INTEN_DONE_Msk
4740
4741 #define PKC_INTEN_ERR_Pos (1U)
4742 #define PKC_INTEN_ERR_Len (1U)
4743 #define PKC_INTEN_ERR_Msk (0x1U << PKC_INTEN_ERR_Pos)
4744 #define PKC_INTEN_ERR PKC_INTEN_ERR_Msk
4745
4746 #define PKC_INTEN_BAOVF_Pos (2U)
4747 #define PKC_INTEN_BAOVF_Len (1U)
4748 #define PKC_INTEN_BAOVF_Msk (0x1U << PKC_INTEN_BAOVF_Pos)
4749 #define PKC_INTEN_BAOVF PKC_INTEN_BAOVF_Msk
4750
4751 /******************* Bit definition for PKC_WORK_STATUS register ***********/
4752 #define PKC_WORKSTAT_BUSY_Pos (0U)
4753 #define PKC_WORKSTAT_BUSY_Len (1U)
4754 #define PKC_WORKSTAT_BUSY_Msk (0x1U << PKC_WORKSTAT_BUSY_Pos)
4755 #define PKC_WORKSTAT_BUSY PKC_WORKSTAT_BUSY_Msk
4756
4757 /******************* Bit definition for PKC_DUMMY0 register ****************/
4758 #define PKC_DUMMY0_DUMMY0_Pos (0U)
4759 #define PKC_DUMMY0_DUMMY0_Len (32U)
4760 #define PKC_DUMMY0_DUMMY0_Msk (0xFFFFFFFFU)
4761 #define PKC_DUMMY0_DUMMY0 PKC_DUMMY0_DUMMY0_Msk
4762
4763 /******************* Bit definition for PKC_DUMMY1 register ****************/
4764 #define PKC_DUMMY1_DUMMY1_Pos (0U)
4765 #define PKC_DUMMY1_DUMMY1_Len (32U)
4766 #define PKC_DUMMY1_DUMMY1_Msk (0xFFFFFFFFU)
4767 #define PKC_DUMMY1_DUMMY1 PKC_DUMMY1_DUMMY1_Msk
4768
4769 /******************* Bit definition for PKC_DUMMY2 register ****************/
4770 #define PKC_DUMMY2_DUMMY2_Pos (0U)
4771 #define PKC_DUMMY2_DUMMY2_Len (32U)
4772 #define PKC_DUMMY2_DUMMY2_Msk (0xFFFFFFFFU)
4773 #define PKC_DUMMY2_DUMMY2 PKC_DUMMY2_DUMMY2_Msk
4774
4775
4776 /* ================================================================================================================= */
4777 /* ================ PWM ================ */
4778 /* ================================================================================================================= */
4779
4780 /******************* Bit definition for PWM_MODE register *******************/
4781 #define PWM_MODE_EN_Pos (0U)
4782 #define PWM_MODE_EN_Len (1U)
4783 #define PWM_MODE_EN_Msk (0x1U << PWM_MODE_EN_Pos)
4784 #define PWM_MODE_EN PWM_MODE_EN_Msk
4785
4786 #define PWM_MODE_PAUSE_Pos (1U)
4787 #define PWM_MODE_PAUSE_Len (1U)
4788 #define PWM_MODE_PAUSE_Msk (0x1U << PWM_MODE_PAUSE_Pos)
4789 #define PWM_MODE_PAUSE PWM_MODE_PAUSE_Msk
4790
4791 #define PWM_MODE_BREATHEN_Pos (2U)
4792 #define PWM_MODE_BREATHEN_Len (1U)
4793 #define PWM_MODE_BREATHEN_Msk (0x1U << PWM_MODE_BREATHEN_Pos)
4794 #define PWM_MODE_BREATHEN PWM_MODE_BREATHEN_Msk
4795
4796 #define PWM_MODE_DPENA_Pos (3U)
4797 #define PWM_MODE_DPENA_Len (1U)
4798 #define PWM_MODE_DPENA_Msk (0x1U << PWM_MODE_DPENA_Pos)
4799 #define PWM_MODE_DPENA PWM_MODE_DPENA_Msk
4800
4801 #define PWM_MODE_DPENB_Pos (4U)
4802 #define PWM_MODE_DPENB_Len (1U)
4803 #define PWM_MODE_DPENB_Msk (0x1U << PWM_MODE_DPENB_Pos)
4804 #define PWM_MODE_DPENB PWM_MODE_DPENB_Msk
4805
4806 #define PWM_MODE_DPENC_Pos (5U)
4807 #define PWM_MODE_DPENC_Len (1U)
4808 #define PWM_MODE_DPENC_Msk (0x1U << PWM_MODE_DPENC_Pos)
4809 #define PWM_MODE_DPENC PWM_MODE_DPENC_Msk
4810
4811 /******************* Bit definition for PWM_UPDATE register *****************/
4812 #define PWM_UPDATE_SAG_Pos (0U)
4813 #define PWM_UPDATE_SAG_Len (1U)
4814 #define PWM_UPDATE_SAG_Msk (0x1U << PWM_UPDATE_SAG_Pos)
4815 #define PWM_UPDATE_SAG PWM_UPDATE_SAG_Msk
4816
4817 #define PWM_UPDATE_SA_Pos (1U)
4818 #define PWM_UPDATE_SA_Len (1U)
4819 #define PWM_UPDATE_SA_Msk (0x1U << PWM_UPDATE_SA_Pos)
4820 #define PWM_UPDATE_SA PWM_UPDATE_SA_Msk
4821
4822 #define PWM_UPDATE_SSPRD_Pos (8U)
4823 #define PWM_UPDATE_SSPRD_Len (1U)
4824 #define PWM_UPDATE_SSPRD_Msk (0x1U << PWM_UPDATE_SSPRD_Pos)
4825 #define PWM_UPDATE_SSPRD PWM_UPDATE_SSPRD_Msk
4826
4827 #define PWM_UPDATE_SSCMPA0_Pos (9U)
4828 #define PWM_UPDATE_SSCMPA0_Len (1U)
4829 #define PWM_UPDATE_SSCMPA0_Msk (0x1U << PWM_UPDATE_SSCMPA0_Pos)
4830 #define PWM_UPDATE_SSCMPA0 PWM_UPDATE_SSCMPA0_Msk
4831
4832 #define PWM_UPDATE_SSCMPA1_Pos (10U)
4833 #define PWM_UPDATE_SSCMPA1_Len (1U)
4834 #define PWM_UPDATE_SSCMPA1_Msk (0x1U << PWM_UPDATE_SSCMPA1_Pos)
4835 #define PWM_UPDATE_SSCMPA1 PWM_UPDATE_SSCMPA1_Msk
4836
4837 #define PWM_UPDATE_SSCMPB0_Pos (11U)
4838 #define PWM_UPDATE_SSCMPB0_Len (1U)
4839 #define PWM_UPDATE_SSCMPB0_Msk (0x1U << PWM_UPDATE_SSCMPB0_Pos)
4840 #define PWM_UPDATE_SSCMPB0 PWM_UPDATE_SSCMPB0_Msk
4841
4842 #define PWM_UPDATE_SSCMPB1_Pos (12U)
4843 #define PWM_UPDATE_SSCMPB1_Len (1U)
4844 #define PWM_UPDATE_SSCMPB1_Msk (0x1U << PWM_UPDATE_SSCMPB1_Pos)
4845 #define PWM_UPDATE_SSCMPB1 PWM_UPDATE_SSCMPB1_Msk
4846
4847 #define PWM_UPDATE_SSCMPC0_Pos (13U)
4848 #define PWM_UPDATE_SSCMPC0_Len (1U)
4849 #define PWM_UPDATE_SSCMPC0_Msk (0x1U << PWM_UPDATE_SSCMPC0_Pos)
4850 #define PWM_UPDATE_SSCMPC0 PWM_UPDATE_SSCMPC0_Msk
4851
4852 #define PWM_UPDATE_SSCMPC1_Pos (14U)
4853 #define PWM_UPDATE_SSCMPC1_Len (1U)
4854 #define PWM_UPDATE_SSCMPC1_Msk (0x1U << PWM_UPDATE_SSCMPC1_Pos)
4855 #define PWM_UPDATE_SSCMPC1 PWM_UPDATE_SSCMPC1_Msk
4856
4857 #define PWM_UPDATE_SSPAUSE_Pos (15U)
4858 #define PWM_UPDATE_SSPAUSE_Len (1U)
4859 #define PWM_UPDATE_SSPAUSE_Msk (0x1U << PWM_UPDATE_SSPAUSE_Pos)
4860 #define PWM_UPDATE_SSPAUSE PWM_UPDATE_SSPAUSE_Msk
4861
4862 #define PWM_UPDATE_SSBRPRD_Pos (16U)
4863 #define PWM_UPDATE_SSBRPRD_Len (1U)
4864 #define PWM_UPDATE_SSBRPRD_Msk (0x1U << PWM_UPDATE_SSBRPRD_Pos)
4865 #define PWM_UPDATE_SSBRPRD PWM_UPDATE_SSBRPRD_Msk
4866
4867 #define PWM_UPDATE_SSHOLD_Pos (17U)
4868 #define PWM_UPDATE_SSHOLD_Len (1U)
4869 #define PWM_UPDATE_SSHOLD_Msk (0x1U << PWM_UPDATE_SSHOLD_Pos)
4870 #define PWM_UPDATE_SSHOLD PWM_UPDATE_SSHOLD_Msk
4871
4872 #define PWM_UPDATE_SSAQCTRL_Pos (18U)
4873 #define PWM_UPDATE_SSAQCTRL_Len (1U)
4874 #define PWM_UPDATE_SSAQCTRL_Msk (0x1U << PWM_UPDATE_SSAQCTRL_Pos)
4875 #define PWM_UPDATE_SSAQCTRL PWM_UPDATE_SSAQCTRL_Msk
4876
4877 /******************* Bit definition for PWM_PRD register ********************/
4878 #define PWM_PRD_PRD_Pos (0U)
4879 #define PWM_PRD_PRD_Len (32U)
4880 #define PWM_PRD_PRD_Msk (0xFFFFFFFFU)
4881 #define PWM_PRD_PRD PWM_PRD_PRD_Msk
4882
4883 /******************* Bit definition for PWM_CMPA0 register ******************/
4884 #define PWM_CMPA0_CMPA0_Pos (0U)
4885 #define PWM_CMPA0_CMPA0_Len (32U)
4886 #define PWM_CMPA0_CMPA0_Msk (0xFFFFFFFFU)
4887 #define PWM_CMPA0_CMPA0 PWM_CMPA0_CMPA0_Msk
4888
4889 /******************* Bit definition for PWM_CMPA1 register ******************/
4890 #define PWM_CMPA1_CMPA1_Pos (0U)
4891 #define PWM_CMPA1_CMPA1_Len (32U)
4892 #define PWM_CMPA1_CMPA1_Msk (0xFFFFFFFFU)
4893 #define PWM_CMPA1_CMPA1 PWM_CMPA1_CMPA1_Msk
4894
4895 /******************* Bit definition for PWM_CMPB0 register ******************/
4896 #define PWM_CMPB0_CMPB0_Pos (0U)
4897 #define PWM_CMPB0_CMPB0_Len (32U)
4898 #define PWM_CMPB0_CMPB0_Msk (0xFFFFFFFFU)
4899 #define PWM_CMPB0_CMPB0 PWM_CMPB0_CMPB0_Msk
4900
4901 /******************* Bit definition for PWM_CMPB1 register ******************/
4902 #define PWM_CMPB1_CMPB1_Pos (0U)
4903 #define PWM_CMPB1_CMPB1_Len (32U)
4904 #define PWM_CMPB1_CMPB1_Msk (0xFFFFFFFFU)
4905 #define PWM_CMPB1_CMPB1 PWM_CMPB1_CMPB1_Msk
4906
4907 /******************* Bit definition for PWM_CMPC0 register ******************/
4908 #define PWM_CMPC0_CMPC0_Pos (0U)
4909 #define PWM_CMPC0_CMPC0_Len (32U)
4910 #define PWM_CMPC0_CMPC0_Msk (0xFFFFFFFFU)
4911 #define PWM_CMPC0_CMPC0 PWM_CMPC0_CMPC0_Msk
4912
4913 /******************* Bit definition for PWM_CMPC1 register ******************/
4914 #define PWM_CMPC1_CMPC1_Pos (0U)
4915 #define PWM_CMPC1_CMPC1_Len (32U)
4916 #define PWM_CMPC1_CMPC1_Msk (0xFFFFFFFFU)
4917 #define PWM_CMPC1_CMPC1 PWM_CMPC1_CMPC1_Msk
4918
4919 /******************* Bit definition for PWM_AQCTRL register *****************/
4920 #define PWM_AQCTRL_A0_Pos (0U)
4921 #define PWM_AQCTRL_A0_Len (2U)
4922 #define PWM_AQCTRL_A0_Msk (0x3U << PWM_AQCTRL_A0_Pos)
4923 #define PWM_AQCTRL_A0 PWM_AQCTRL_A0_Msk
4924
4925 #define PWM_AQCTRL_A1_Pos (2U)
4926 #define PWM_AQCTRL_A1_Len (2U)
4927 #define PWM_AQCTRL_A1_Msk (0x3U << PWM_AQCTRL_A1_Pos)
4928 #define PWM_AQCTRL_A1 PWM_AQCTRL_A1_Msk
4929
4930 #define PWM_AQCTRL_B0_Pos (4U)
4931 #define PWM_AQCTRL_B0_Len (2U)
4932 #define PWM_AQCTRL_B0_Msk (0x3U << PWM_AQCTRL_B0_Pos)
4933 #define PWM_AQCTRL_B0 PWM_AQCTRL_B0_Msk
4934
4935 #define PWM_AQCTRL_B1_Pos (6U)
4936 #define PWM_AQCTRL_B1_Len (2U)
4937 #define PWM_AQCTRL_B1_Msk (0x3U << PWM_AQCTRL_B1_Pos)
4938 #define PWM_AQCTRL_B1 PWM_AQCTRL_B1_Msk
4939
4940 #define PWM_AQCTRL_C0_Pos (8U)
4941 #define PWM_AQCTRL_C0_Len (2U)
4942 #define PWM_AQCTRL_C0_Msk (0x3U << PWM_AQCTRL_C0_Pos)
4943 #define PWM_AQCTRL_C0 PWM_AQCTRL_C0_Msk
4944
4945 #define PWM_AQCTRL_C1_Pos (10U)
4946 #define PWM_AQCTRL_C1_Len (2U)
4947 #define PWM_AQCTRL_C1_Msk (0x3U << PWM_AQCTRL_C1_Pos)
4948 #define PWM_AQCTRL_C1 PWM_AQCTRL_C1_Msk
4949
4950 /******************* Bit definition for PWM_BRPRD register ******************/
4951 #define PWM_BRPRD_BRPRD_Pos (0U)
4952 #define PWM_BRPRD_BRPRD_Len (32U)
4953 #define PWM_BRPRD_BRPRD_Msk (0xFFFFFFFFU)
4954 #define PWM_BRPRD_BRPRD PWM_BRPRD_BRPRD_Msk
4955
4956 /******************* Bit definition for PWM_HOLD register *******************/
4957 #define PWM_HOLD_HOLD_Pos (0U)
4958 #define PWM_HOLD_HOLD_Len (24U)
4959 #define PWM_HOLD_HOLD_Msk (0x00FFFFFFU)
4960 #define PWM_HOLD_HOLD PWM_HOLD_HOLD_Msk
4961
4962
4963 /* ================================================================================================================= */
4964 /* ================ SSI ================ */
4965 /* ================================================================================================================= */
4966 /******************* Bit definition for SSI_CTRL0 register ******************/
4967 #define SSI_CTRL0_SSTEN_Pos (24U)
4968 #define SSI_CTRL0_SSTEN_Len (1U)
4969 #define SSI_CTRL0_SSTEN_Msk (0x1U << SSI_CTRL0_SSTEN_Pos)
4970 #define SSI_CTRL0_SSTEN SSI_CTRL0_SSTEN_Msk
4971
4972 #define SSI_CTRL0_SPIFRF_Pos (21U)
4973 #define SSI_CTRL0_SPIFRF_Len (2U)
4974 #define SSI_CTRL0_SPIFRF_Msk (0x3U << SSI_CTRL0_SPIFRF_Pos)
4975 #define SSI_CTRL0_SPIFRF SSI_CTRL0_SPIFRF_Msk
4976
4977 #define SSI_CTRL0_DFS32_Pos (16U)
4978 #define SSI_CTRL0_DFS32_Len (5U)
4979 #define SSI_CTRL0_DFS32_Msk (0x1FU << SSI_CTRL0_DFS32_Pos)
4980 #define SSI_CTRL0_DFS32 SSI_CTRL0_DFS32_Msk
4981
4982 #define SSI_CTRL0_CFS_Pos (12U)
4983 #define SSI_CTRL0_CFS_Len (4U)
4984 #define SSI_CTRL0_CFS_Msk (0xFU << SSI_CTRL0_CFS_Pos)
4985 #define SSI_CTRL0_CFS SSI_CTRL0_CFS_Msk
4986
4987 #define SSI_CTRL0_SRL_Pos (11U)
4988 #define SSI_CTRL0_SRL_Len (1U)
4989 #define SSI_CTRL0_SRL_Msk (0x1U << SSI_CTRL0_SRL_Pos)
4990 #define SSI_CTRL0_SRL SSI_CTRL0_SRL_Msk
4991
4992 #define SSI_CTRL0_SLVOE_Pos (10U)
4993 #define SSI_CTRL0_SLVOE_Len (1U)
4994 #define SSI_CTRL0_SLVOE_Msk (0x1U << SSI_CTRL0_SLVOE_Pos)
4995 #define SSI_CTRL0_SLVOE SSI_CTRL0_SLVOE_Msk
4996
4997 #define SSI_CTRL0_TMOD_Pos (8U)
4998 #define SSI_CTRL0_TMOD_Len (2U)
4999 #define SSI_CTRL0_TMOD_Msk (0x3U << SSI_CTRL0_TMOD_Pos)
5000 #define SSI_CTRL0_TMOD SSI_CTRL0_TMOD_Msk
5001
5002 #define SSI_CTRL0_SCPOL_Pos (7U)
5003 #define SSI_CTRL0_SCPOL_Len (1U)
5004 #define SSI_CTRL0_SCPOL_Msk (0x1U << SSI_CTRL0_SCPOL_Pos)
5005 #define SSI_CTRL0_SCPOL SSI_CTRL0_SCPOL_Msk
5006
5007 #define SSI_CTRL0_SCPHA_Pos (6U)
5008 #define SSI_CTRL0_SCPHA_Len (1U)
5009 #define SSI_CTRL0_SCPHA_Msk (0x1U << SSI_CTRL0_SCPHA_Pos)
5010 #define SSI_CTRL0_SCPHA SSI_CTRL0_SCPHA_Msk
5011
5012 #define SSI_CTRL0_FRF_Pos (4U)
5013 #define SSI_CTRL0_FRF_Len (2U)
5014 #define SSI_CTRL0_FRF_Msk (0x3U << SSI_CTRL0_FRF_Pos)
5015 #define SSI_CTRL0_FRF SSI_CTRL0_FRF_Msk
5016
5017 #define SSI_CTRL1_NDF_Pos (0U)
5018 #define SSI_CTRL1_NDF_Len (16U)
5019 #define SSI_CTRL1_NDF_Msk (0xFFFFU << SSI_CTRL1_NDF_Pos)
5020 #define SSI_CTRL1_NDF SSI_CTRL1_NDF_Msk
5021
5022 /******************* Bit definition for SSI_SSIEN register ******************/
5023 #define SSI_SSIEN_EN_Pos (0U)
5024 #define SSI_SSIEN_EN_Len (1U)
5025 #define SSI_SSIEN_EN_Msk (0x1U << SSI_SSIEN_EN_Pos)
5026 #define SSI_SSIEN_EN SSI_SSIEN_EN_Msk
5027
5028 /******************* Bit definition for SSI_MWC register ********************/
5029 #define SSI_MWC_MHS_Pos (2U)
5030 #define SSI_MWC_MHS_Len (1U)
5031 #define SSI_MWC_MHS_Msk (0x1U << SSI_MWC_MHS_Pos)
5032 #define SSI_MWC_MHS SSI_MWC_MHS_Msk
5033
5034 #define SSI_MWC_MDD_Pos (1U)
5035 #define SSI_MWC_MDD_Len (1U)
5036 #define SSI_MWC_MDD_Msk (0x1U << SSI_MWC_MDD_Pos)
5037 #define SSI_MWC_MDD SSI_MWC_MDD_Msk
5038
5039 #define SSI_MWC_MWMOD_Pos (0U)
5040 #define SSI_MWC_MWMOD_Len (1U)
5041 #define SSI_MWC_MWMOD_Msk (0x1U << SSI_MWC_MWMOD_Pos)
5042 #define SSI_MWC_MWMOD SSI_MWC_MWMOD_Msk
5043
5044 /******************* Bit definition for SSI_SE register *********************/
5045 #define SSI_SE_SLAVE1_Pos (1U)
5046 #define SSI_SE_SLAVE1_Len (1U)
5047 #define SSI_SE_SLAVE1_Msk (0x1U << SSI_SE_SLAVE1_Pos)
5048 #define SSI_SE_SLAVE1 SSI_SE_SLAVE1_Msk
5049
5050 #define SSI_SE_SLAVE0_Pos (0U)
5051 #define SSI_SE_SLAVE0_Len (1U)
5052 #define SSI_SE_SLAVE0_Msk (0x1U << SSI_SE_SLAVE0_Pos)
5053 #define SSI_SE_SLAVE0 SSI_SE_SLAVE0_Msk
5054
5055 /******************* Bit definition for SSI_BAUD register *******************/
5056 #define SSI_BAUD_SCKDIV_Pos (0U)
5057 #define SSI_BAUD_SCKDIV_Len (16U)
5058 #define SSI_BAUD_SCKDIV_Msk (0xFFFFUL << SSI_BAUD_SCKDIV_Pos)
5059 #define SSI_BAUD_SCKDIV SSI_BAUD_SCKDIV_Msk
5060
5061 /******************* Bit definition for SSI_TXFTL register ******************/
5062 #define SSI_TXFTL_TFT_Pos (0U)
5063 #define SSI_TXFTL_TFT_Len (3U)
5064 #define SSI_TXFTL_TFT_Msk (0x7U << SSI_TXFTL_TFT_Pos)
5065 #define SSI_TXFTL_TFT SSI_TXFTL_TFT_Msk
5066
5067 /******************* Bit definition for SSI_RXFTL register ******************/
5068 #define SSI_RXFTL_RFT_Pos (0U)
5069 #define SSI_RXFTL_RFT_Len (3U)
5070 #define SSI_RXFTL_RFT_Msk (0x7U << SSI_RXFTL_RFT_Pos)
5071 #define SSI_RXFTL_RFT SSI_RXFTL_RFT_Msk
5072
5073 /******************* Bit definition for SSI_TXFL register *******************/
5074 #define SSI_TXFL_TXTFL_Pos (0U)
5075 #define SSI_TXFL_TXTFL_Len (4U)
5076 #define SSI_TXFL_TXTFL_Msk (0xFU << SSI_TXFL_TXTFL_Pos)
5077 #define SSI_TXFL_TXTFL SSI_TXFL_TXTFL_Msk
5078
5079 /******************* Bit definition for SSI_RXFL register *******************/
5080 #define SSI_RXFL_RXTFL_Pos (0U)
5081 #define SSI_RXFL_RXTFL_Len (4U)
5082 #define SSI_RXFL_RXTFL_Msk (0xFU << SSI_RXFL_RXTFL_Pos)
5083 #define SSI_RXFL_RXTFL SSI_RXFL_RXTFL_Msk
5084
5085 /******************* Bit definition for SSI_STAT register *******************/
5086 #define SSI_STAT_DCOL_Pos (6U)
5087 #define SSI_STAT_DCOL_Len (1U)
5088 #define SSI_STAT_DCOL_Msk (0x1U << SSI_STAT_DCOL_Pos)
5089 #define SSI_STAT_DCOL SSI_STAT_DCOL_Msk
5090
5091 #define SSI_STAT_TXE_Pos (5U)
5092 #define SSI_STAT_TXE_Len (1U)
5093 #define SSI_STAT_TXE_Msk (0x1U << SSI_STAT_TXE_Pos)
5094 #define SSI_STAT_TXE SSI_STAT_TXE_Msk
5095
5096 #define SSI_STAT_RFF_Pos (4U)
5097 #define SSI_STAT_RFF_Len (1U)
5098 #define SSI_STAT_RFF_Msk (0x1U << SSI_STAT_RFF_Pos)
5099 #define SSI_STAT_RFF SSI_STAT_RFF_Msk
5100
5101 #define SSI_STAT_RFNE_Pos (3U)
5102 #define SSI_STAT_RFNE_Len (1U)
5103 #define SSI_STAT_RFNE_Msk (0x1U << SSI_STAT_RFNE_Pos)
5104 #define SSI_STAT_RFNE SSI_STAT_RFNE_Msk
5105
5106 #define SSI_STAT_TFE_Pos (2U)
5107 #define SSI_STAT_TFE_Len (1U)
5108 #define SSI_STAT_TFE_Msk (0x1U << SSI_STAT_TFE_Pos)
5109 #define SSI_STAT_TFE SSI_STAT_TFE_Msk
5110
5111 #define SSI_STAT_TFNF_Pos (1U)
5112 #define SSI_STAT_TFNF_Len (1U)
5113 #define SSI_STAT_TFNF_Msk (0x1U << SSI_STAT_TFNF_Pos)
5114 #define SSI_STAT_TFNF SSI_STAT_TFNF_Msk
5115
5116 #define SSI_STAT_BUSY_Pos (0U)
5117 #define SSI_STAT_BUSY_Len (1U)
5118 #define SSI_STAT_BUSY_Msk (0x1U << SSI_STAT_BUSY_Pos)
5119 #define SSI_STAT_BUSY SSI_STAT_BUSY_Msk
5120
5121 /******************* Bit definition for SSI_INTMASK register ****************/
5122 #define SSI_INTMASK_MSTIM_Pos (5U)
5123 #define SSI_INTMASK_MSTIM_Len (1U)
5124 #define SSI_INTMASK_MSTIM_Msk (0x1U << SSI_INTMASK_MSTIM_Pos)
5125 #define SSI_INTMASK_MSTIM SSI_INTMASK_MSTIM_Msk
5126
5127 #define SSI_INTMASK_RXFIM_Pos (4U)
5128 #define SSI_INTMASK_RXFIM_Len (1U)
5129 #define SSI_INTMASK_RXFIM_Msk (0x1U << SSI_INTMASK_RXFIM_Pos)
5130 #define SSI_INTMASK_RXFIM SSI_INTMASK_RXFIM_Msk
5131
5132 #define SSI_INTMASK_RXOIM_Pos (3U)
5133 #define SSI_INTMASK_RXOIM_Len (1U)
5134 #define SSI_INTMASK_RXOIM_Msk (0x1U << SSI_INTMASK_RXOIM_Pos)
5135 #define SSI_INTMASK_RXOIM SSI_INTMASK_RXOIM_Msk
5136
5137 #define SSI_INTMASK_RXUIM_Pos (2U)
5138 #define SSI_INTMASK_RXUIM_Len (1U)
5139 #define SSI_INTMASK_RXUIM_Msk (0x1U << SSI_INTMASK_RXUIM_Pos)
5140 #define SSI_INTMASK_RXUIM SSI_INTMASK_RXUIM_Msk
5141
5142 #define SSI_INTMASK_TXOIM_Pos (1U)
5143 #define SSI_INTMASK_TXOIM_Len (1U)
5144 #define SSI_INTMASK_TXOIM_Msk (0x1U << SSI_INTMASK_TXOIM_Pos)
5145 #define SSI_INTMASK_TXOIM SSI_INTMASK_TXOIM_Msk
5146
5147 #define SSI_INTMASK_TXEIM_Pos (0U)
5148 #define SSI_INTMASK_TXEIM_Len (1U)
5149 #define SSI_INTMASK_TXEIM_Msk (0x1U << SSI_INTMASK_TXEIM_Pos)
5150 #define SSI_INTMASK_TXEIM SSI_INTMASK_TXEIM_Msk
5151
5152 /******************* Bit definition for SSI_INTSTAT register ****************/
5153 #define SSI_INTSTAT_MSTIS_Pos (5U)
5154 #define SSI_INTSTAT_MSTIS_Len (1U)
5155 #define SSI_INTSTAT_MSTIS_Msk (0x1U << SSI_INTSTAT_MSTIS_Pos)
5156 #define SSI_INTSTAT_MSTIS SSI_INTSTAT_MSTIS_Msk
5157
5158 #define SSI_INTSTAT_RXFIS_Pos (4U)
5159 #define SSI_INTSTAT_RXFIS_Len (1U)
5160 #define SSI_INTSTAT_RXFIS_Msk (0x1U << SSI_INTSTAT_RXFIS_Pos)
5161 #define SSI_INTSTAT_RXFIS SSI_INTSTAT_RXFIS_Msk
5162
5163 #define SSI_INTSTAT_RXOIS_Pos (3U)
5164 #define SSI_INTSTAT_RXOIS_Len (1U)
5165 #define SSI_INTSTAT_RXOIS_Msk (0x1U << SSI_INTSTAT_RXOIS_Pos)
5166 #define SSI_INTSTAT_RXOIS SSI_INTSTAT_RXOIS_Msk
5167
5168 #define SSI_INTSTAT_RXUIS_Pos (2U)
5169 #define SSI_INTSTAT_RXUIS_Len (1U)
5170 #define SSI_INTSTAT_RXUIS_Msk (0x1U << SSI_INTSTAT_RXUIS_Pos)
5171 #define SSI_INTSTAT_RXUIS SSI_INTSTAT_RXUIS_Msk
5172
5173 #define SSI_INTSTAT_TXOIS_Pos (1U)
5174 #define SSI_INTSTAT_TXOIS_Len (1U)
5175 #define SSI_INTSTAT_TXOIS_Msk (0x1U << SSI_INTSTAT_TXOIS_Pos)
5176 #define SSI_INTSTAT_TXOIS SSI_INTSTAT_TXOIS_Msk
5177
5178 #define SSI_INTSTAT_TXEIS_Pos (0U)
5179 #define SSI_INTSTAT_TXEIS_Len (1U)
5180 #define SSI_INTSTAT_TXEIS_Msk (0x1U << SSI_INTSTAT_TXEIS_Pos)
5181 #define SSI_INTSTAT_TXEIS SSI_INTSTAT_TXEIS_Msk
5182
5183 /******************* Bit definition for SSI_RAW_INTSTAT register ************/
5184 #define SSI_RAW_INTSTAT_MSTIR_Pos (5U)
5185 #define SSI_RAW_INTSTAT_MSTIR_Len (1U)
5186 #define SSI_RAW_INTSTAT_MSTIR_Msk (0x1U << SSI_RAW_INTSTAT_MSTIR_Pos)
5187 #define SSI_RAW_INTSTAT_MSTIR SSI_RAW_INTSTAT_MSTIR_Msk
5188
5189 #define SSI_RAW_INTSTAT_RXFIR_Pos (4U)
5190 #define SSI_RAW_INTSTAT_RXFIR_Len (1U)
5191 #define SSI_RAW_INTSTAT_RXFIR_Msk (0x1U << SSI_RAW_INTSTAT_RXFIR_Pos)
5192 #define SSI_RAW_INTSTAT_RXFIR SSI_RAW_INTSTAT_RXFIR_Msk
5193
5194 #define SSI_RAW_INTSTAT_RXOIR_Pos (3U)
5195 #define SSI_RAW_INTSTAT_RXOIR_Len (1U)
5196 #define SSI_RAW_INTSTAT_RXOIR_Msk (0x1U << SSI_RAW_INTSTAT_RXOIR_Pos)
5197 #define SSI_RAW_INTSTAT_RXOIR SSI_RAW_INTSTAT_RXOIR_Msk
5198
5199 #define SSI_RAW_INTSTAT_RXUIR_Pos (2U)
5200 #define SSI_RAW_INTSTAT_RXUIR_Len (1U)
5201 #define SSI_RAW_INTSTAT_RXUIR_Msk (0x1U << SSI_RAW_INTSTAT_RXUIR_Pos)
5202 #define SSI_RAW_INTSTAT_RXUIR SSI_RAW_INTSTAT_RXUIR_Msk
5203
5204 #define SSI_RAW_INTSTAT_TXOIR_Pos (1U)
5205 #define SSI_RAW_INTSTAT_TXOIR_Len (1U)
5206 #define SSI_RAW_INTSTAT_TXOIR_Msk (0x1U << SSI_RAW_INTSTAT_TXOIR_Pos)
5207 #define SSI_RAW_INTSTAT_TXOIR SSI_RAW_INTSTAT_TXOIR_Msk
5208
5209 #define SSI_RAW_INTSTAT_TXEIR_Pos (0U)
5210 #define SSI_RAW_INTSTAT_TXEIR_Len (1U)
5211 #define SSI_RAW_INTSTAT_TXEIR_Msk (0x1U << SSI_RAW_INTSTAT_TXEIR_Pos)
5212 #define SSI_RAW_INTSTAT_TXEIR SSI_RAW_INTSTAT_TXEIR_Msk
5213
5214 /******************* Bit definition for SSI_TXOIC register ******************/
5215 #define SSI_TXOIC_TXOIC_Pos (0U)
5216 #define SSI_TXOIC_TXOIC_Len (1U)
5217 #define SSI_TXOIC_TXOIC_Msk (0x1U << SSI_TXOIC_TXOIC_Pos)
5218 #define SSI_TXOIC_TXOIC SSI_TXOIC_TXOIC_Msk
5219
5220 /******************* Bit definition for SSI_RXOIC register ******************/
5221 #define SSI_RXOIC_RXOIC_Pos (0U)
5222 #define SSI_RXOIC_RXOIC_Len (1U)
5223 #define SSI_RXOIC_RXOIC_Msk (0x1U << SSI_RXOIC_RXOIC_Pos)
5224 #define SSI_RXOIC_RXOIC SSI_RXOIC_RXOIC_Msk
5225
5226 #define SSI_RXUIC_RXUIC_Pos (0U)
5227 #define SSI_RXUIC_RXUIC_Len (1U)
5228 #define SSI_RXUIC_RXUIC_Msk (0x1U << SSI_RXUIC_RXUIC_Pos)
5229 #define SSI_RXUIC_RXUIC SSI_RXUIC_RXUIC_Msk
5230
5231 /******************* Bit definition for SSI_MSTIC register ******************/
5232 #define SSI_MSTIC_MSTIC_Pos (0U)
5233 #define SSI_MSTIC_MSTIC_Len (1U)
5234 #define SSI_MSTIC_MSTIC_Msk (0x1U << SSI_MSTIC_MSTIC_Pos)
5235 #define SSI_MSTIC_MSTIC SSI_MSTIC_MSTIC_Msk
5236
5237 /******************* Bit definition for SSI_INTCLR register ******************/
5238 #define SSI_INTCLR_INTCLR_Pos (0U)
5239 #define SSI_INTCLR_INTCLR_Len (1U)
5240 #define SSI_INTCLR_INTCLR_Msk (0x1U << SSI_INTCLR_INTCLR_Pos)
5241 #define SSI_INTCLR_INTCLR SSI_INTCLR_INTCLR_Msk
5242
5243 /******************* Bit definition for SSI_DMAC register *******************/
5244 #define SSI_DMAC_TDMAE_Pos (1U)
5245 #define SSI_DMAC_TDMAE_Len (1U)
5246 #define SSI_DMAC_TDMAE_Msk (0x1U << SSI_DMAC_TDMAE_Pos)
5247 #define SSI_DMAC_TDMAE SSI_DMAC_TDMAE_Msk
5248
5249 #define SSI_DMAC_RDMAE_Pos (0U)
5250 #define SSI_DMAC_RDMAE_Len (1U)
5251 #define SSI_DMAC_RDMAE_Msk (0x1U << SSI_DMAC_RDMAE_Pos)
5252 #define SSI_DMAC_RDMAE SSI_DMAC_RDMAE_Msk
5253
5254 /******************* Bit definition for SSI_DMATDL register *****************/
5255 #define SSI_DMATDL_DMATDL_Pos (0U)
5256 #define SSI_DMATDL_DMATDL_Len (4U)
5257 #define SSI_DMATDL_DMATDL_Msk (0xFU << SSI_DMATDL_DMATDL_Pos)
5258 #define SSI_DMATDL_DMATDL SSI_DMATDL_DMATDL_Msk
5259
5260 #define SSI_DMARDL_DMARDL_Pos (0U)
5261 #define SSI_DMARDL_DMARDL_Len (4U)
5262 #define SSI_DMARDL_DMARDL_Msk (0xFU << SSI_DMARDL_DMARDL_Pos)
5263 #define SSI_DMARDL_DMARDL SSI_DMARDL_DMARDL_Msk
5264
5265 /******************* Bit definition for SSI_IDCODE register *****************/
5266 #define SSI_IDCODE_ID_Pos (0U)
5267 #define SSI_IDCODE_ID_Len (32U)
5268 #define SSI_IDCODE_ID_Msk (0xFFFFFFFFU)
5269 #define SSI_IDCODE_ID SSI_IDCODE_ID_Msk
5270
5271 /******************* Bit definition for SSI_COMP register *******************/
5272 #define SSI_COMP_VERSION_Pos (0U)
5273 #define SSI_COMP_VERSION_Len (32U)
5274 #define SSI_COMP_VERSION_Msk (0xFFFFFFFFU)
5275 #define SSI_COMP_VERSION SSI_COMP_VERSION_Msk
5276
5277 /******************* Bit definition for SSI_DATA register *******************/
5278 #define SSI_DATA_REG_Pos (0U)
5279 #define SSI_DATA_REG_Len (32U)
5280 #define SSI_DATA_REG_Msk (0xFFFFFFFFU)
5281 #define SSI_DATA_REG SSI_DATA_REG_Msk
5282
5283 /******************* Bit definition for SSI_RX register *********************/
5284 #define SSI_RX_SAMPLEDLY_Pos (0U)
5285 #define SSI_RX_SAMPLEDLY_Len (8U)
5286 #define SSI_RX_SAMPLEDLY_Msk (0xFFU << SSI_RX_SAMPLEDLY_Pos)
5287 #define SSI_RX_SAMPLEDLY SSI_RX_SAMPLEDLY_Msk
5288
5289 /******************* Bit definition for SSI_SCTRL0 register *****************/
5290 #define SSI_SCTRL0_WAITCYCLES_Pos (11U)
5291 #define SSI_SCTRL0_WAITCYCLES_Len (5U)
5292 #define SSI_SCTRL0_WAITCYCLES_Msk (0x1FU << SSI_SCTRL0_WAITCYCLES_Pos)
5293 #define SSI_SCTRL0_WAITCYCLES SSI_SCTRL0_WAITCYCLES_Msk
5294
5295 #define SSI_SCTRL0_INSTL_Pos (8U)
5296 #define SSI_SCTRL0_INSTL_Len (2U)
5297 #define SSI_SCTRL0_INSTL_Msk (0x03U << SSI_SCTRL0_INSTL_Pos)
5298 #define SSI_SCTRL0_INSTL SSI_SCTRL0_INSTL_Msk
5299
5300 #define SSI_SCTRL0_ADDRL_Pos (2U)
5301 #define SSI_SCTRL0_ADDRL_Len (4U)
5302 #define SSI_SCTRL0_ADDRL_Msk (0x0FU << SSI_SCTRL0_ADDRL_Pos)
5303 #define SSI_SCTRL0_ADDRL SSI_SCTRL0_ADDRL_Msk
5304
5305 #define SSI_SCTRL0_TRANSTYPE_Pos (0U)
5306 #define SSI_SCTRL0_TRANSTYPE_Len (2U)
5307 #define SSI_SCTRL0_TRANSTYPE_Msk (0x03U << SSI_SCTRL0_TRANSTYPE_Pos)
5308 #define SSI_SCTRL0_TRANSTYPE SSI_SCTRL0_TRANSTYPE_Msk
5309
5310
5311 /* ================================================================================================================= */
5312 /* ================ TIMER ================ */
5313 /* ================================================================================================================= */
5314 /******************* Bit definition for TIMER_CTRL register *******************/
5315 #define TIMER_CTRL_INTEN_Pos (3U)
5316 #define TIMER_CTRL_INTEN_Len (1U)
5317 #define TIMER_CTRL_INTEN_Msk (0x1U << TIMER_CTRL_INTEN_Pos)
5318 #define TIMER_CTRL_INTEN TIMER_CTRL_INTEN_Msk
5319
5320 #define TIMER_CTRL_EN_Pos (0U)
5321 #define TIMER_CTRL_EN_Len (1U)
5322 #define TIMER_CTRL_EN_Msk (0x1U << TIMER_CTRL_EN_Pos)
5323 #define TIMER_CTRL_EN TIMER_CTRL_EN_Msk
5324
5325 /******************* Bit definition for TIMER_VALUE register ******************/
5326 #define TIMER_VALUE_VALUE_Pos (0U)
5327 #define TIMER_VALUE_VALUE_Len (32U)
5328 #define TIMER_VALUE_VALUE_Msk (0xFFFFFFFFU)
5329 #define TIMER_VALUE_VALUE TIMER_VALUE_VALUE_Msk
5330
5331 /******************* Bit definition for TIMER_RELOAD register *****************/
5332 #define TIMER_RELOAD_RELOAD_Pos (0U)
5333 #define TIMER_RELOAD_RELOAD_Len (32U)
5334 #define TIMER_RELOAD_RELOAD_Msk (0xFFFFFFFFU)
5335 #define TIMER_RELOAD_RELOAD TIMER_RELOAD_RELOAD_Msk
5336
5337 /******************* Bit definition for TIMER_RELOAD register *****************/
5338 #define TIMER_INT_STAT_Pos (0U)
5339 #define TIMER_INT_STAT_Len (1U)
5340 #define TIMER_INT_STAT_Msk (0x1U << TIMER_INT_STAT_Pos)
5341 #define TIMER_INT_STAT TIMER_INT_STAT_Msk
5342
5343
5344 /* ================================================================================================================= */
5345 /* ================ UART ================ */
5346 /* ================================================================================================================= */
5347 /******************* Bit definition for UART_RBR register *******************/
5348 #define UART_RBR_RBR_Pos (0U)
5349 #define UART_RBR_RBR_Len (8U)
5350 #define UART_RBR_RBR_Msk (0xFFU << UART_RBR_RBR_Pos)
5351 #define UART_RBR_RBR UART_RBR_RBR_Msk /**< Receive Buffer Register */
5352
5353 /******************* Bit definition for UART_DLL register *******************/
5354 #define UART_DLL_DLL_Pos (0U)
5355 #define UART_DLL_DLL_Len (8U)
5356 #define UART_DLL_DLL_Msk (0xFFU << UART_DLL_DLL_Pos)
5357 #define UART_DLL_DLL UART_DLL_DLL_Msk /**< Divisor Latch (Low) */
5358
5359 /******************* Bit definition for UART_THR register *******************/
5360 #define UART_THR_THR_Pos (0U)
5361 #define UART_THR_THR_Len (8U)
5362 #define UART_THR_THR_Msk (0xFFU << UART_THR_THR_Pos)
5363 #define UART_THR_THR UART_THR_THR_Msk /**< Transmit Holding Register */
5364
5365 /******************* Bit definition for UART_DLH register *******************/
5366 #define UART_DLH_DLH_Pos (0U)
5367 #define UART_DLH_DLH_Len (8U)
5368 #define UART_DLH_DLH_Msk (0xFFU << UART_DLH_DLH_Pos)
5369 #define UART_DLH_DLH UART_DLH_DLH_Msk /**< Divisor Latch (High) */
5370
5371 /******************* Bit definition for UART_IER register *******************/
5372 #define UART_IER_PTIME_Pos (7U)
5373 #define UART_IER_PTIME_Len (1U)
5374 #define UART_IER_PTIME_Msk (0x1U << UART_IER_PTIME_Pos)
5375 #define UART_IER_PTIME UART_IER_PTIME_Msk /**< Programmable THRE Interrupt
5376 Mode Enable */
5377
5378 #define UART_IER_ELCOLR_Pos (4U)
5379 #define UART_IER_ELCOLR_Len (1U)
5380 #define UART_IER_ELCOLR_Msk (0x1U << UART_IER_ELCOLR_Pos)
5381 #define UART_IER_ELCOLR UART_IER_ELCOLR_Msk /**< Enable Auto Clear LSR Register
5382 by read RBR/LSR, read only */
5383
5384 #define UART_IER_EDSSI_Pos (3U)
5385 #define UART_IER_EDSSI_Len (1U)
5386 #define UART_IER_EDSSI_Msk (0x1U << UART_IER_EDSSI_Pos)
5387 #define UART_IER_EDSSI UART_IER_EDSSI_Msk /**< Enable Modem Status Interrupt */
5388
5389 #define UART_IER_ERLS_Pos (2U)
5390 #define UART_IER_ERLS_Len (1U)
5391 #define UART_IER_ERLS_Msk (0x1U << UART_IER_ERLS_Pos)
5392 #define UART_IER_ERLS UART_IER_ERLS_Msk /**< Enable Receiver Line Status
5393 Interrupt */
5394
5395 #define UART_IER_ETBEI_Pos (1U)
5396 #define UART_IER_ETBEI_Len (1U)
5397 #define UART_IER_ETBEI_Msk (0x1U << UART_IER_ETBEI_Pos)
5398 #define UART_IER_ETBEI UART_IER_ETBEI_Msk /**< Enable Transmit Holding Register
5399 Empty Interrupt */
5400
5401 #define UART_IER_ERBFI_Pos (0U)
5402 #define UART_IER_ERBFI_Len (1U)
5403 #define UART_IER_ERBFI_Msk (0x1U << UART_IER_ERBFI_Pos)
5404 #define UART_IER_ERBFI UART_IER_ERBFI_Msk /**< Enable Received Data
5405 Available Interrupt */
5406
5407 /******************* Bit definition for UART_FCR register *******************/
5408 #define UART_TXFIFO_SIZE 128
5409 #define UART_RXFIFO_SIZE 128
5410
5411 #define UART_FCR_RT_Pos (6U)
5412 #define UART_FCR_RT_Len (2U)
5413 #define UART_FCR_RT_Msk (0x3U << UART_FCR_RT_Pos)
5414 #define UART_FCR_RT UART_FCR_RT_Msk /**< RCVR Trigger */
5415 #define UART_FCR_RT_CHAR_1 (0x0U << UART_FCR_RT_Pos) /**< RX FIFO 1 Char */
5416 #define UART_FCR_RT_QUARTER_FULL (0x1U << UART_FCR_RT_Pos) /**< RX FIFO Quater Full*/
5417 #define UART_FCR_RT_HALF_FULL (0x2U << UART_FCR_RT_Pos) /**< RX FIFO Half Full */
5418 #define UART_FCR_RT_FULL_2 (0x3U << UART_FCR_RT_Pos) /**< RX FIFO 2 less than Full */
5419
5420 #define UART_FCR_TET_Pos (4U)
5421 #define UART_FCR_TET_Len (2U)
5422 #define UART_FCR_TET_Msk (0x3U << UART_FCR_TET_Pos)
5423 #define UART_FCR_TET UART_FCR_TET_Msk /**< TX Empty Trigger */
5424 #define UART_FCR_TET_EMPTY (0x0U << UART_FCR_TET_Pos) /**< TX FIFO Empty */
5425 #define UART_FCR_TET_CHAR_2 (0x1U << UART_FCR_TET_Pos) /**< TX FIFO 2 chars */
5426 #define UART_FCR_TET_QUARTER_FULL (0x2U << UART_FCR_TET_Pos) /**< TX FIFO Quater Full */
5427 #define UART_FCR_TET_HALF_FULL (0x3U << UART_FCR_TET_Pos) /**< TX FIFO Half Full */
5428
5429 #define UART_FCR_XFIFOR_Pos (2U)
5430 #define UART_FCR_XFIFOR_Len (1U)
5431 #define UART_FCR_XFIFOR_Msk (0x1U << UART_FCR_XFIFOR_Pos)
5432 #define UART_FCR_XFIFOR UART_FCR_XFIFOR_Msk /**< XMIT FIFO Reset */
5433
5434 #define UART_FCR_RFIFOR_Pos (1U)
5435 #define UART_FCR_RFIFOR_Len (1U)
5436 #define UART_FCR_RFIFOR_Msk (0x1U << UART_FCR_RFIFOR_Pos)
5437 #define UART_FCR_RFIFOR UART_FCR_RFIFOR_Msk /**< RCVR FIFO Reset */
5438
5439 #define UART_FCR_FIFOE_Pos (0U)
5440 #define UART_FCR_FIFOE_Len (1U)
5441 #define UART_FCR_FIFOE_Msk (0x1U << UART_FCR_FIFOE_Pos)
5442 #define UART_FCR_FIFOE UART_FCR_FIFOE_Msk /**< FIFO Enable */
5443
5444 /******************* Bit definition for UART_IIR register *******************/
5445 #define UART_IIR_IID_Pos (0U)
5446 #define UART_IIR_IID_Len (4U)
5447 #define UART_IIR_IID_Msk (0xFU << UART_IIR_IID_Pos)
5448 #define UART_IIR_IID UART_IIR_IID_Msk /**< Interrupt ID */
5449 #define UART_IIR_IID_MS (0x0U << UART_IIR_IID_Pos) /**< Modem Status */
5450 #define UART_IIR_IID_NIP (0x1U << UART_IIR_IID_Pos) /**< No Interrupt Pending */
5451 #define UART_IIR_IID_THRE (0x2U << UART_IIR_IID_Pos) /**< THR Empty */
5452 #define UART_IIR_IID_RDA (0x4U << UART_IIR_IID_Pos) /**< Received Data Available */
5453 #define UART_IIR_IID_RLS (0x6U << UART_IIR_IID_Pos) /**< Receiver Line Status */
5454 #define UART_IIR_IID_CTO (0xCU << UART_IIR_IID_Pos) /**< Character Timeout */
5455
5456 /******************* Bit definition for UART_LCR register *******************/
5457 #define UART_LCR_DLAB_Pos (7U)
5458 #define UART_LCR_DLAB_Len (1U)
5459 #define UART_LCR_DLAB_Msk (0x1U << UART_LCR_DLAB_Pos)
5460 #define UART_LCR_DLAB UART_LCR_DLAB_Msk /**< Divisor Latch Access */
5461
5462 #define UART_LCR_BC_Pos (6U)
5463 #define UART_LCR_BC_Len (1U)
5464 #define UART_LCR_BC_Msk (0x1U << UART_LCR_BC_Pos)
5465 #define UART_LCR_BC UART_LCR_BC_Msk /**< Break Control */
5466
5467 #define UART_LCR_PARITY_Pos (3U)
5468 #define UART_LCR_PARITY_Len (3U)
5469 #define UART_LCR_PARITY_Msk (0x7U << UART_LCR_PARITY_Pos)
5470 #define UART_LCR_PARITY UART_LCR_PARITY_Msk /**< Parity,SP,EPS,PEN bits */
5471 #define UART_LCR_PARITY_NONE (0x0U << UART_LCR_PARITY_Pos) /**< Parity none */
5472 #define UART_LCR_PARITY_ODD (0x1U << UART_LCR_PARITY_Pos) /**< Parity odd */
5473 #define UART_LCR_PARITY_EVEN (0x3U << UART_LCR_PARITY_Pos) /**< Parity even */
5474 #define UART_LCR_PARITY_SP0 (0x5U << UART_LCR_PARITY_Pos) /**< Parity stick 0 */
5475 #define UART_LCR_PARITY_SP1 (0x7U << UART_LCR_PARITY_Pos) /**< Parity stick 1 */
5476
5477 #define UART_LCR_STOP_Pos (2U)
5478 #define UART_LCR_STOP_Msk (0x1U << UART_LCR_STOP_Pos)
5479 #define UART_LCR_STOP UART_LCR_STOP_Msk /**< Stop bit */
5480 #define UART_LCR_STOP_1 (0x0U << UART_LCR_STOP_Pos) /**< Stop bit 1 */
5481 #define UART_LCR_STOP_1_5 (0x1U << UART_LCR_STOP_Pos) /**< Stop bit 1.5 (DLS = 0) */
5482 #define UART_LCR_STOP_2 (0x1U << UART_LCR_STOP_Pos) /**< Stop bit 2 (DLS != 0) */
5483
5484 #define UART_LCR_DLS_Pos (0U)
5485 #define UART_LCR_DLS_Msk (0x3U << UART_LCR_DLS_Pos)
5486 #define UART_LCR_DLS UART_LCR_DLS_Msk /**< Data Length Select */
5487 #define UART_LCR_DLS_5 (0x0U << UART_LCR_DLS_Pos) /**< Data bits 5 */
5488 #define UART_LCR_DLS_6 (0x1U << UART_LCR_DLS_Pos) /**< Data bits 6 */
5489 #define UART_LCR_DLS_7 (0x2U << UART_LCR_DLS_Pos) /**< Data bits 7 */
5490 #define UART_LCR_DLS_8 (0x3U << UART_LCR_DLS_Pos) /**< Data bits 8 */
5491
5492 /******************* Bit definition for UART_MCR register *******************/
5493 #define UART_MCR_AFCE_Pos (5U)
5494 #define UART_MCR_AFCE_Len (1U)
5495 #define UART_MCR_AFCE_Msk (0x1U << UART_MCR_AFCE_Pos)
5496 #define UART_MCR_AFCE UART_MCR_AFCE_Msk /**< Auto flow contrl enable */
5497
5498 #define UART_MCR_LOOPBACK_Pos (4U)
5499 #define UART_MCR_LOOPBACK_Len (1U)
5500 #define UART_MCR_LOOPBACK_Msk (0x1U << UART_MCR_LOOPBACK_Pos)
5501 #define UART_MCR_LOOPBACK UART_MCR_LOOPBACK_Msk /**< LoopBack */
5502
5503 #define UART_MCR_RTS_Pos (1U)
5504 #define UART_MCR_RTS_Len (1U)
5505 #define UART_MCR_RTS_Msk (0x1U << UART_MCR_RTS_Pos)
5506 #define UART_MCR_RTS UART_MCR_RTS_Msk /**< Request To Send */
5507
5508 /******************* Bit definition for UART_LSR register *******************/
5509 #define UART_LSR_RFE_Pos (7U)
5510 #define UART_LSR_RFE_Len (1U)
5511 #define UART_LSR_RFE_Msk (0x1U << UART_LSR_RFE_Pos)
5512 #define UART_LSR_RFE UART_LSR_RFE_Msk /**< Receiver FIFO Error */
5513
5514 #define UART_LSR_TEMT_Pos (6U)
5515 #define UART_LSR_TEMT_Len (1U)
5516 #define UART_LSR_TEMT_Msk (0x1U << UART_LSR_TEMT_Pos)
5517 #define UART_LSR_TEMT UART_LSR_TEMT_Msk /**< Transmitter Empty */
5518
5519 #define UART_LSR_THRE_Pos (5U)
5520 #define UART_LSR_THRE_Len (1U)
5521 #define UART_LSR_THRE_Msk (0x1U << UART_LSR_THRE_Pos)
5522 #define UART_LSR_THRE UART_LSR_THRE_Msk /**< Transmit Holding Register Empty */
5523
5524 #define UART_LSR_BI_Pos (4U)
5525 #define UART_LSR_BI_Len (1U)
5526 #define UART_LSR_BI_Msk (0x1U << UART_LSR_BI_Pos)
5527 #define UART_LSR_BI UART_LSR_BI_Msk /**< Break Interrupt */
5528
5529 #define UART_LSR_FE_Pos (3U)
5530 #define UART_LSR_FE_Len (1U)
5531 #define UART_LSR_FE_Msk (0x1U << UART_LSR_FE_Pos)
5532 #define UART_LSR_FE UART_LSR_FE_Msk /**< Framing Error */
5533
5534 #define UART_LSR_PE_Pos (2U)
5535 #define UART_LSR_PE_Len (1U)
5536 #define UART_LSR_PE_Msk (0x1U << UART_LSR_PE_Pos)
5537 #define UART_LSR_PE UART_LSR_PE_Msk /**< Parity Error */
5538
5539 #define UART_LSR_OE_Pos (1U)
5540 #define UART_LSR_OE_Len (1U)
5541 #define UART_LSR_OE_Msk (0x1U << UART_LSR_OE_Pos)
5542 #define UART_LSR_OE UART_LSR_OE_Msk /**< Overrun error */
5543
5544 #define UART_LSR_DR_Pos (0U)
5545 #define UART_LSR_DR_Msk (0x1U << UART_LSR_DR_Pos)
5546 #define UART_LSR_DR UART_LSR_DR_Msk /**< Data Ready */
5547
5548 /******************* Bit definition for UART_MSR register *******************/
5549 #define UART_MSR_CTS_Pos (4U)
5550 #define UART_MSR_CTS_Len (1U)
5551 #define UART_MSR_CTS_Msk (0x1U << UART_MSR_CTS_Pos)
5552 #define UART_MSR_CTS UART_MSR_CTS_Msk /**< Clear To Send */
5553
5554 #define UART_MSR_DCTS_Pos (0U)
5555 #define UART_MSR_DCTS_Len (1U)
5556 #define UART_MSR_DCTS_Msk (0x1U << UART_MSR_DCTS_Pos)
5557 #define UART_MSR_DCTS UART_MSR_DCTS_Msk /**< Delta Clear To Send */
5558
5559 /******************* Bit definition for UART_USR register *******************/
5560 #define UART_USR_RFF_Pos (4U)
5561 #define UART_USR_RFF_Len (1U)
5562 #define UART_USR_RFF_Msk (0x1U << UART_USR_RFF_Pos)
5563 #define UART_USR_RFF UART_USR_RFF_Msk /**< Receive FIFO Full */
5564
5565 #define UART_USR_RFNE_Pos (3U)
5566 #define UART_USR_RFNE_Len (1U)
5567 #define UART_USR_RFNE_Msk (0x1U << UART_USR_RFNE_Pos)
5568 #define UART_USR_RFNE UART_USR_RFNE_Msk /**< Receive FIFO Not Empty */
5569
5570 #define UART_USR_TFE_Pos (2U)
5571 #define UART_USR_TFE_Len (1U)
5572 #define UART_USR_TFE_Msk (0x1U << UART_USR_TFE_Pos)
5573 #define UART_USR_TFE UART_USR_TFE_Msk /**< Transmit FIFO Empty */
5574
5575 #define UART_USR_TFNF_Pos (1U)
5576 #define UART_USR_TFNF_Len (1U)
5577 #define UART_USR_TFNF_Msk (0x1U << UART_USR_TFNF_Pos)
5578 #define UART_USR_TFNF UART_USR_TFNF_Msk /**< Transmit FIFO Not Full */
5579
5580 /******************* Bit definition for UART_TFL register *******************/
5581 /* Transmit FIFO Level bits */
5582 #define UART_TFL_TFL_Pos (0U)
5583 #define UART_TFL_TFL_Len (7U)
5584 #define UART_TFL_TFL_Msk (0x7FU << UART_TFL_TFL_Pos)
5585 #define UART_TFL_TFL UART_TFL_TFL_Msk /**< Transmit FIFO Level */
5586
5587 /******************* Bit definition for UART_RFL register *******************/
5588 /* Receive FIFO Level bits */
5589 #define UART_RFL_RFL_Pos (0U)
5590 #define UART_RFL_RFL_Len (7U)
5591 #define UART_RFL_RFL_Msk (0x7FU << UART_RFL_RFL_Pos)
5592 #define UART_RFL_RFL UART_RFL_RFL_Msk /**< Receive FIFO Level */
5593
5594 /******************* Bit definition for UART_SRR register *******************/
5595 /* XMIT FIFO Reset bit */
5596 #define UART_SRR_XFR_Pos (2U)
5597 #define UART_SRR_XFR_Len (1U)
5598 #define UART_SRR_XFR_Msk (0x1U << UART_SRR_XFR_Pos)
5599 #define UART_SRR_XFR UART_SRR_XFR_Msk /**< XMIT FIFO Reset */
5600
5601 /* RCVR FIFO Reset bit */
5602 #define UART_SRR_RFR_Pos (1U)
5603 #define UART_SRR_RFR_Len (1U)
5604 #define UART_SRR_RFR_Msk (0x1U << UART_SRR_RFR_Pos)
5605 #define UART_SRR_RFR UART_SRR_RFR_Msk /**< RCVR FIFO Reset */
5606
5607 /* UART Reset Enable bit */
5608 #define UART_SRR_UR_Pos (0U)
5609 #define UART_SRR_UR_Len (1U)
5610 #define UART_SRR_UR_Msk (0x1U << UART_SRR_UR_Pos)
5611 #define UART_SRR_UR UART_SRR_UR_Msk /**< UART Reset */
5612
5613 /******************* Bit definition for UART_SRTS register *******************/
5614 #define UART_SRTS_SRTS_Pos (0U)
5615 #define UART_SRTS_SRTS_Len (1U)
5616 #define UART_SRTS_SRTS_Msk (0x1U << UART_SRTS_SRTS_Pos)
5617 #define UART_SRTS_SRTS UART_SRTS_SRTS_Msk /**< Shadow Request to Send */
5618
5619 /******************* Bit definition for UART_SBCR register *******************/
5620 #define UART_SBCR_SBCR_Pos (0U)
5621 #define UART_SBCR_SBCR_Len (1U)
5622 #define UART_SBCR_SBCR_Msk (0x1U << UART_SBCR_SBCR_Pos)
5623 #define UART_SBCR_SBCR UART_SBCR_SBCR_Msk /**< Shadow Break Control */
5624
5625 /******************* Bit definition for UART_SFE register *******************/
5626 #define UART_SFE_SFE_Pos (0U)
5627 #define UART_SFE_SFE_Len (1U)
5628 #define UART_SFE_SFE_Msk (0x1U << UART_SFE_SFE_Pos)
5629 #define UART_SFE_SFE UART_SFE_SFE_Msk /**< Shadow FIFO Enable */
5630
5631 /******************* Bit definition for UART_SRT register *******************/
5632 #define UART_SRT_SRT_Pos (0U)
5633 #define UART_SRT_SRT_Len (2U)
5634 #define UART_SRT_SRT_Msk (0x3U << UART_SRT_SRT_Pos)
5635 #define UART_SRT_SRT UART_SRT_SRT_Msk
5636 #define UART_SRT_SRT_CHAR_1 (0x0U << UART_SRT_SRT_Pos) /**< RX FIFO 1 Char */
5637 #define UART_SRT_SRT_QUARTER_FULL (0x1U << UART_SRT_SRT_Pos) /**< RX FIFO Quater Full*/
5638 #define UART_SRT_SRT_HALF_FULL (0x2U << UART_SRT_SRT_Pos) /**< RX FIFO Half Full */
5639 #define UART_SRT_SRT_FULL_2 (0x3U << UART_SRT_SRT_Pos) /**< RX FIFO 2 less than Full */
5640
5641 /******************* Bit definition for UART_STET register *******************/
5642 #define UART_STET_STET_Pos (0U)
5643 #define UART_STET_STET_Len (2U)
5644 #define UART_STET_STET_Msk (0x3U << UART_STET_STET_Pos)
5645 #define UART_STET_STET UART_STET_STET_Msk
5646 #define UART_STET_STET_EMPTY (0x0U << UART_STET_STET_Pos) /**< TX FIFO Empty */
5647 #define UART_STET_STET_CHAR_2 (0x1U << UART_STET_STET_Pos) /**< TX FIFO 2 chars */
5648 #define UART_STET_STET_QUARTER_FULL (0x2U << UART_STET_STET_Pos) /**< TX FIFO Quater Full */
5649 #define UART_STET_STET_HALF_FULL (0x3U << UART_STET_STET_Pos) /**< TX FIFO Half Full */
5650
5651 /******************* Bit definition for UART_HTX register *******************/
5652 #define UART_HTX_HTX_Pos (0U)
5653 #define UART_HTX_HTX_Len (1U)
5654 #define UART_HTX_HTX_Msk (0x1U << UART_HTX_HTX_Pos)
5655 #define UART_HTX_HTX UART_HTX_HTX_Msk /**< Halt TX */
5656
5657 /******************* Bit definition for UART_DLF register *******************/
5658 #define UART_DLF_DLF_Pos (0U)
5659 #define UART_DLF_DLF_Len (1U)
5660 #define UART_DLF_DLF_Msk (0x1U << UART_DLF_DLF_Pos)
5661 #define UART_DLF_DLF UART_DLF_DLF_Msk /**< Fractional part of divisor */
5662
5663
5664 /* ================================================================================================================= */
5665 /* ================ WDT ================ */
5666 /* ================================================================================================================= */
5667 /******************* Bit definition for WDT_CTRL register ********************/
5668 #define WDT_CTRL_INTEN_Pos (0U)
5669 #define WDT_CTRL_INTEN_Len (1U)
5670 #define WDT_CTRL_INTEN_Msk (0x1U << WDT_CTRL_INTEN_Pos)
5671 #define WDT_CTRL_INTEN WDT_CTRL_INTEN_Msk /**< Interrupt Enable */
5672
5673 #define WDT_CTRL_RSTEN_Pos (1U)
5674 #define WDT_CTRL_RSTEN_Len (1U)
5675 #define WDT_CTRL_RSTEN_Msk (0x1U << WDT_CTRL_RSTEN_Pos)
5676 #define WDT_CTRL_RSTEN WDT_CTRL_RSTEN_Msk /**< Reset Enable */
5677
5678 /******************* Bit definition for WDT_INTCLR register ********************/
5679 #define WDT_INTCLR_Pos (0U)
5680 #define WDT_INTCLR_Len (1U)
5681 #define WDT_INTCLR_Msk (0x1U << WDT_INTCLR_Pos)
5682 #define WDT_INTCLR WDT_INTCLR_Msk /**< Interrupt status clear */
5683
5684 /******************* Bit definition for WDT_MIS register ********************/
5685 #define WDT_MIS_INTSTAT_Pos (0U)
5686 #define WDT_MIS_INTSTAT_Len (1U)
5687 #define WDT_MIS_INTSTAT_Msk (0x1U << WDT_MIS_INTSTAT_Pos)
5688 #define WDT_MIS_INTSTAT WDT_MIS_INTSTAT_Msk /**< Interrupt status */
5689
5690
5691 /* ================================================================================================================= */
5692 /* ================ XQSPI ================ */
5693 /* ================================================================================================================= */
5694 /******************* Bit definition for XQSPI_CACHE_CTRL0 register **********/
5695 #define XQSPI_CACHE_CTRL0_CLK_FORCE_EN_Pos (7U)
5696 #define XQSPI_CACHE_CTRL0_CLK_FORCE_EN_Len (4U)
5697 #define XQSPI_CACHE_CTRL0_CLK_FORCE_EN_Msk (0xFU << XQSPI_CACHE_CTRL0_CLK_FORCE_EN_Pos)
5698 #define XQSPI_CACHE_CTRL0_CLK_FORCE_EN XQSPI_CACHE_CTRL0_CLK_FORCE_EN_Msk
5699
5700 #define XQSPI_CACHE_CTRL0_BUF_DIS_Pos (6U)
5701 #define XQSPI_CACHE_CTRL0_BUF_DIS_Len (1U)
5702 #define XQSPI_CACHE_CTRL0_BUF_DIS_Msk (0x1U << XQSPI_CACHE_CTRL0_BUF_DIS_Pos)
5703 #define XQSPI_CACHE_CTRL0_BUF_DIS XQSPI_CACHE_CTRL0_BUF_DIS_Msk
5704
5705 #define XQSPI_CACHE_CTRL0_DIS_SEQ_Pos (5U)
5706 #define XQSPI_CACHE_CTRL0_DIS_SEQ_Len (1U)
5707 #define XQSPI_CACHE_CTRL0_DIS_SEQ_Msk (0x1U << XQSPI_CACHE_CTRL0_DIS_SEQ_Pos)
5708 #define XQSPI_CACHE_CTRL0_DIS_SEQ XQSPI_CACHE_CTRL0_DIS_SEQ_Msk
5709
5710 #define XQSPI_CACHE_CTRL0_HITMISS_Pos (4U)
5711 #define XQSPI_CACHE_CTRL0_HITMISS_Len (1U)
5712 #define XQSPI_CACHE_CTRL0_HITMISS_Msk (0x1U << XQSPI_CACHE_CTRL0_HITMISS_Pos)
5713 #define XQSPI_CACHE_CTRL0_HITMISS XQSPI_CACHE_CTRL0_HITMISS_Msk
5714
5715 #define XQSPI_CACHE_CTRL0_FIFO_Pos (3U)
5716 #define XQSPI_CACHE_CTRL0_FIFO_Len (1U)
5717 #define XQSPI_CACHE_CTRL0_FIFO_Msk (0x1U << XQSPI_CACHE_CTRL0_FIFO_Pos)
5718 #define XQSPI_CACHE_CTRL0_FIFO XQSPI_CACHE_CTRL0_FIFO_Msk
5719
5720 #define XQSPI_CACHE_CTRL0_FLUSH_Pos (1U)
5721 #define XQSPI_CACHE_CTRL0_FLUSH_Len (1U)
5722 #define XQSPI_CACHE_CTRL0_FLUSH_Msk (0x1U << XQSPI_CACHE_CTRL0_FLUSH_Pos)
5723 #define XQSPI_CACHE_CTRL0_FLUSH XQSPI_CACHE_CTRL0_FLUSH_Msk
5724
5725 #define XQSPI_CACHE_CTRL0_DIS_Pos (0U)
5726 #define XQSPI_CACHE_CTRL0_DIS_Len (1U)
5727 #define XQSPI_CACHE_CTRL0_DIS_Msk (0x1U << XQSPI_CACHE_CTRL0_DIS_Pos)
5728 #define XQSPI_CACHE_CTRL0_DIS XQSPI_CACHE_CTRL0_DIS_Msk
5729
5730 /******************* Bit definition for XQSPI_CACHE_CTRL1 register **********/
5731 #define XQSPI_CACHE_CTRL1_DBGMUX_EN_Pos (4U)
5732 #define XQSPI_CACHE_CTRL1_DBGMUX_EN_Len (1U)
5733 #define XQSPI_CACHE_CTRL1_DBGMUX_EN_Msk (0x1U << XQSPI_CACHE_CTRL1_DBGMUX_EN_Pos)
5734 #define XQSPI_CACHE_CTRL1_DBGMUX_EN XQSPI_CACHE_CTRL1_DBGMUX_EN_Msk
5735
5736 #define XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos (0U)
5737 #define XQSPI_CACHE_CTRL1_DBGBUS_SEL_Len (4U)
5738 #define XQSPI_CACHE_CTRL1_DBGBUS_SEL_Msk (0xFU << XQSPI_CACHE_CTRL1_DBGBUS_SEL_Pos)
5739 #define XQSPI_CACHE_CTRL1_DBGBUS_SEL XQSPI_CACHE_CTRL1_DBGBUS_SEL_Msk
5740
5741 /******************* Bit definition for XQSPI_CACHE_HITCOUNT register *******/
5742 #define XQSPI_CACHE_HITCOUNT_Pos (0U)
5743 #define XQSPI_CACHE_HITCOUNT_Len (32U)
5744 #define XQSPI_CACHE_HITCOUNT_Msk (0xFFFFFFFFU)
5745 #define XQSPI_CACHE_HITCOUNT XQSPI_CACHE_HITCOUNT_Msk
5746
5747 /******************* Bit definition for XQSPI_CACHE_MISSCOUNT register ******/
5748 #define XQSPI_CACHE_MISSCOUNT_Pos (0U)
5749 #define XQSPI_CACHE_MISSCOUNT_Len (32U)
5750 #define XQSPI_CACHE_MISSCOUNT_Msk (0xFFFFFFFFU)
5751 #define XQSPI_CACHE_MISSCOUNT XQSPI_CACHE_MISSCOUNT_Msk
5752
5753 /******************* Bit definition for XQSPI_CACHE_STAT register ***********/
5754 #define XQSPI_CACHE_BUF_BUSY_Pos (2U)
5755 #define XQSPI_CACHE_BUF_BUSY_Len (1U)
5756 #define XQSPI_CACHE_BUF_BUSY_Msk (0x1U << XQSPI_CACHE_BUF_BUSY_Pos)
5757 #define XQSPI_CACHE_BUF_BUSY XQSPI_CACHE_BUF_BUSY_Msk
5758
5759 #define XQSPI_CACHE_BUF_ADDR_REACHED_Pos (1U)
5760 #define XQSPI_CACHE_BUF_ADDR_REACHED_Len (1U)
5761 #define XQSPI_CACHE_BUF_ADDR_REACHED_Msk (0x1U << XQSPI_CACHE_BUF_ADDR_REACHED_Pos)
5762 #define XQSPI_CACHE_BUF_ADDR_REACHED XQSPI_CACHE_BUF_ADDR_REACHED_Msk
5763
5764 #define XQSPI_CACHE_STAT_Pos (0U)
5765 #define XQSPI_CACHE_STAT_Len (1U)
5766 #define XQSPI_CACHE_STAT_Msk (0x1U << XQSPI_CACHE_STAT_Pos)
5767 #define XQSPI_CACHE_STAT XQSPI_CACHE_STAT_Msk
5768
5769 /******************* Bit definition for XQSPI_CACHE_BUF_FIRST_ADDR register ***********/
5770 #define XQSPI_CACHE_BUF_FISRT_ADDR_Pos (0U)
5771 #define XQSPI_CACHE_BUF_FISRT_ADDR_Len (32U)
5772 #define XQSPI_CACHE_BUF_FISRT_ADDR_Msk (0xFFFFFFFFU)
5773 #define XQSPI_CACHE_BUF_FISRT_ADDR XQSPI_CACHE_BUF_FISRT_ADDR_Msk
5774
5775 /******************* Bit definition for XQSPI_CACHE_BUF_LAST_ADDR register ***********/
5776 #define XQSPI_CACHE_BUF_LAST_ADDR_Pos (0U)
5777 #define XQSPI_CACHE_BUF_LAST_ADDR_Len (32U)
5778 #define XQSPI_CACHE_BUF_LAST_ADDR_Msk (0xFFFFFFFFU)
5779 #define XQSPI_CACHE_BUF_LAST_ADDR XQSPI_CACHE_BUF_LAST_ADDR_Msk
5780
5781 /******************* Bit definition for XQSPI_XIP_CFG register **************/
5782 #define XQSPI_XIP_CFG_CMD_Pos (0U)
5783 #define XQSPI_XIP_CFG_CMD_Len (8U)
5784 #define XQSPI_XIP_CFG_CMD_Msk (0xFFU << XQSPI_XIP_CFG_CMD_Pos)
5785 #define XQSPI_XIP_CFG_CMD XQSPI_XIP_CFG_CMD_Msk
5786
5787 #define XQSPI_XIP_CFG_LE32_Pos (8U)
5788 #define XQSPI_XIP_CFG_LE32_Len (1U)
5789 #define XQSPI_XIP_CFG_LE32_Msk (0x1U << XQSPI_XIP_CFG_LE32_Pos)
5790 #define XQSPI_XIP_CFG_LE32 XQSPI_XIP_CFG_LE32_Msk
5791
5792 #define XQSPI_XIP_CFG_ADDR4_Pos (7U)
5793 #define XQSPI_XIP_CFG_ADDR4_Len (1U)
5794 #define XQSPI_XIP_CFG_ADDR4_Msk (0x1U << XQSPI_XIP_CFG_ADDR4_Pos)
5795 #define XQSPI_XIP_CFG_ADDR4 XQSPI_XIP_CFG_ADDR4_Msk
5796
5797 #define XQSPI_XIP_CFG_CPOL_Pos (6U)
5798 #define XQSPI_XIP_CFG_CPOL_Len (1U)
5799 #define XQSPI_XIP_CFG_CPOL_Msk (0x1U << XQSPI_XIP_CFG_CPOL_Pos)
5800 #define XQSPI_XIP_CFG_CPOL XQSPI_XIP_CFG_CPOL_Msk
5801
5802 #define XQSPI_XIP_CFG_CPHA_Pos (5U)
5803 #define XQSPI_XIP_CFG_CPHA_Len (1U)
5804 #define XQSPI_XIP_CFG_CPHA_Msk (0x1U << XQSPI_XIP_CFG_CPHA_Pos)
5805 #define XQSPI_XIP_CFG_CPHA XQSPI_XIP_CFG_CPHA_Msk
5806
5807 #define XQSPI_XIP_CFG_SS_Pos (1U)
5808 #define XQSPI_XIP_CFG_SS_Len (4U)
5809 #define XQSPI_XIP_CFG_SS_Msk (0xFU << XQSPI_XIP_CFG_SS_Pos)
5810 #define XQSPI_XIP_CFG_SS XQSPI_XIP_CFG_SS_Msk
5811
5812 #define XQSPI_XIP_CFG_HPEN_Pos (0U)
5813 #define XQSPI_XIP_CFG_HPEN_Len (1U)
5814 #define XQSPI_XIP_CFG_HPEN_Msk (0x1U << XQSPI_XIP_CFG_HPEN_Pos)
5815 #define XQSPI_XIP_CFG_HPEN XQSPI_XIP_CFG_HPEN_Msk
5816
5817 #define XQSPI_XIP_CFG_ENDDUMMY_Pos (12U)
5818 #define XQSPI_XIP_CFG_ENDDUMMY_Len (2U)
5819 #define XQSPI_XIP_CFG_ENDDUMMY_Msk (0x3U << XQSPI_XIP_CFG_ENDDUMMY_Pos)
5820 #define XQSPI_XIP_CFG_ENDDUMMY XQSPI_XIP_CFG_ENDDUMMY_Msk
5821
5822 #define XQSPI_XIP_CFG_DUMMYCYCLES_Pos (8U)
5823 #define XQSPI_XIP_CFG_DUMMYCYCLES_Len (4U)
5824 #define XQSPI_XIP_CFG_DUMMYCYCLES_Msk (0xFU << XQSPI_XIP_CFG_DUMMYCYCLES_Pos)
5825 #define XQSPI_XIP_CFG_DUMMYCYCLES XQSPI_XIP_CFG_DUMMYCYCLES_Msk
5826
5827 #define XQSPI_XIP_CFG_HPMODE_Pos (0U)
5828 #define XQSPI_XIP_CFG_HPMODE_Len (8U)
5829 #define XQSPI_XIP_CFG_HPMODE_Msk (0xFFUL << XQSPI_XIP_CFG_HPMODE_Pos)
5830 #define XQSPI_XIP_CFG_HPMODE XQSPI_XIP_CFG_HPMODE_Msk
5831
5832 /******************* Bit definition for XQSPI_XIP_EN register ***************/
5833 #define XQSPI_XIP_EN_REQ_Pos (0U)
5834 #define XQSPI_XIP_EN_REQ_Len (1U)
5835 #define XQSPI_XIP_EN_REQ_Msk (0x1U << XQSPI_XIP_EN_REQ_Pos)
5836 #define XQSPI_XIP_EN_REQ XQSPI_XIP_EN_REQ_Msk
5837
5838 #define XQSPI_XIP_EN_OUT_Pos (0U)
5839 #define XQSPI_XIP_EN_OUT_Len (1U)
5840 #define XQSPI_XIP_EN_OUT_Msk (0x1U << XQSPI_XIP_EN_OUT_Pos)
5841 #define XQSPI_XIP_EN_OUT XQSPI_XIP_EN_OUT_Msk
5842
5843 /******************* Bit definition for XQSPI_XIP_INT0 register *************/
5844 #define XQSPI_XIP_INT_EN_Pos (0U)
5845 #define XQSPI_XIP_INT_EN_Len (1U)
5846 #define XQSPI_XIP_INT_EN_Msk (0x1U << XQSPI_XIP_INT_EN_Pos)
5847 #define XQSPI_XIP_INT_EN XQSPI_XIP_INT_EN_Msk
5848
5849 /******************* Bit definition for XQSPI_XIP_INT1 register *************/
5850 #define XQSPI_XIP_INT_STAT_Pos (0U)
5851 #define XQSPI_XIP_INT_STAT_Len (1U)
5852 #define XQSPI_XIP_INT_STAT_Msk (0x1U << XQSPI_XIP_INT_STAT_Pos)
5853 #define XQSPI_XIP_INT_STAT XQSPI_XIP_INT_STAT_Msk
5854
5855 /******************* Bit definition for XQSPI_XIP_INT2 register *************/
5856 #define XQSPI_XIP_INT_REQ_Pos (0U)
5857 #define XQSPI_XIP_INT_REQ_Len (1U)
5858 #define XQSPI_XIP_INT_REQ_Msk (0x1U << XQSPI_XIP_INT_REQ_Pos)
5859 #define XQSPI_XIP_INT_REQ XQSPI_XIP_INT_REQ_Msk
5860
5861 /******************* Bit definition for XQSPI_XIP_INT3 register *************/
5862 #define XQSPI_XIP_INT_SET_Pos (0U)
5863 #define XQSPI_XIP_INT_SET_Len (1U)
5864 #define XQSPI_XIP_INT_SET_Msk (0x1U << XQSPI_XIP_INT_SET_Pos)
5865 #define XQSPI_XIP_INT_SET XQSPI_XIP_INT_SET_Msk
5866
5867 /******************* Bit definition for XQSPI_XIP_INT4 register *************/
5868 #define XQSPI_XIP_INT_CLR_Pos (0U)
5869 #define XQSPI_XIP_INT_CLR_Len (1U)
5870 #define XQSPI_XIP_INT_CLR_Msk (0x1U << XQSPI_XIP_INT_CLR_Pos)
5871 #define XQSPI_XIP_INT_CLR XQSPI_XIP_INT_CLR_Msk
5872
5873 /******************* Bit definition for XQSPI_QSPI_STAT register ************/
5874 #define XQSPI_QSPI_STAT_RXFULL_Pos (7U)
5875 #define XQSPI_QSPI_STAT_RXFULL_Len (1U)
5876 #define XQSPI_QSPI_STAT_RXFULL_Msk (0x1U << XQSPI_QSPI_STAT_RXFULL_Pos)
5877 #define XQSPI_QSPI_STAT_RXFULL XQSPI_QSPI_STAT_RXFULL_Msk
5878
5879 #define XQSPI_QSPI_STAT_RXWMARK_Pos (6U)
5880 #define XQSPI_QSPI_STAT_RXWMARK_Len (1U)
5881 #define XQSPI_QSPI_STAT_RXWMARK_Msk (0x1U << XQSPI_QSPI_STAT_RXWMARK_Pos)
5882 #define XQSPI_QSPI_STAT_RXWMARK XQSPI_QSPI_STAT_RXWMARK_Msk
5883
5884 #define XQSPI_QSPI_STAT_RXEMPTY_Pos (5U)
5885 #define XQSPI_QSPI_STAT_RXEMPTY_Len (1U)
5886 #define XQSPI_QSPI_STAT_RXEMPTY_Msk (0x1U << XQSPI_QSPI_STAT_RXEMPTY_Pos)
5887 #define XQSPI_QSPI_STAT_RXEMPTY XQSPI_QSPI_STAT_RXEMPTY_Msk
5888
5889 #define XQSPI_QSPI_STAT_TXFULL_Pos (4U)
5890 #define XQSPI_QSPI_STAT_TXFULL_Len (1U)
5891 #define XQSPI_QSPI_STAT_TXFULL_Msk (0x1U << XQSPI_QSPI_STAT_TXFULL_Pos)
5892 #define XQSPI_QSPI_STAT_TXFULL XQSPI_QSPI_STAT_TXFULL_Msk
5893
5894 #define XQSPI_QSPI_STAT_TXWMARK_Pos (3U)
5895 #define XQSPI_QSPI_STAT_TXWMARK_Len (1U)
5896 #define XQSPI_QSPI_STAT_TXWMARK_Msk (0x1U << XQSPI_QSPI_STAT_TXWMARK_Pos)
5897 #define XQSPI_QSPI_STAT_TXWMARK XQSPI_QSPI_STAT_TXWMARK_Msk
5898
5899 #define XQSPI_QSPI_STAT_TXEMPTY_Pos (2U)
5900 #define XQSPI_QSPI_STAT_TXEMPTY_Len (1U)
5901 #define XQSPI_QSPI_STAT_TXEMPTY_Msk (0x1U << XQSPI_QSPI_STAT_TXEMPTY_Pos)
5902 #define XQSPI_QSPI_STAT_TXEMPTY XQSPI_QSPI_STAT_TXEMPTY_Msk
5903
5904 #define XQSPI_QSPI_STAT_XFERIP_Pos (0U)
5905 #define XQSPI_QSPI_STAT_XFERIP_Len (1U)
5906 #define XQSPI_QSPI_STAT_XFERIP_Msk (0x1U << XQSPI_QSPI_STAT_XFERIP_Pos)
5907 #define XQSPI_QSPI_STAT_XFERIP XQSPI_QSPI_STAT_XFERIP_Msk
5908
5909 /******************* Bit definition for XQSPI_QSPI_FIFO register ************/
5910 #define XQSPI_QSPI_FIFO_TX_Pos (0U)
5911 #define XQSPI_QSPI_FIFO_TX_Len (32U)
5912 #define XQSPI_QSPI_FIFO_TX_Msk (0xFFFFFFFFU)
5913 #define XQSPI_QSPI_FIFO_TX XQSPI_QSPI_FIFO_TX_Msk
5914
5915 #define XQSPI_QSPI_FIFO_RX_Pos (0U)
5916 #define XQSPI_QSPI_FIFO_RX_Len (32U)
5917 #define XQSPI_QSPI_FIFO_RX_Msk (0xFFFFFFFFU)
5918 #define XQSPI_QSPI_FIFO_RX XQSPI_QSPI_FIFO_RX_Msk
5919
5920 /******************* Bit definition for XQSPI_QSPI_CTRL register ************/
5921 #define XQSPI_QSPI_CTRL_TXWMARK_Pos (14U)
5922 #define XQSPI_QSPI_CTRL_TXWMARK_Len (2U)
5923 #define XQSPI_QSPI_CTRL_TXWMARK_Msk (0x3U << XQSPI_QSPI_CTRL_TXWMARK_Pos)
5924 #define XQSPI_QSPI_CTRL_TXWMARK XQSPI_QSPI_CTRL_TXWMARK_Msk
5925
5926 #define XQSPI_QSPI_CTRL_RXWMARK_Pos (12U)
5927 #define XQSPI_QSPI_CTRL_RXWMARK_Len (2U)
5928 #define XQSPI_QSPI_CTRL_RXWMARK_Msk (0x3U << XQSPI_QSPI_CTRL_RXWMARK_Pos)
5929 #define XQSPI_QSPI_CTRL_RXWMARK XQSPI_QSPI_CTRL_RXWMARK_Msk
5930
5931 #define XQSPI_QSPI_CTRL_MWAITEN_Pos (11U)
5932 #define XQSPI_QSPI_CTRL_MWAITEN_Len (1U)
5933 #define XQSPI_QSPI_CTRL_MWAITEN_Msk (0x1U << XQSPI_QSPI_CTRL_MWAITEN_Pos)
5934 #define XQSPI_QSPI_CTRL_MWAITEN XQSPI_QSPI_CTRL_MWAITEN_Msk
5935
5936 #define XQSPI_QSPI_CTRL_DMA_Pos (10U)
5937 #define XQSPI_QSPI_CTRL_DMA_Len (1U)
5938 #define XQSPI_QSPI_CTRL_DMA_Msk (0x1U << XQSPI_QSPI_CTRL_DMA_Pos)
5939 #define XQSPI_QSPI_CTRL_DMA XQSPI_QSPI_CTRL_DMA_Msk
5940
5941 #define XQSPI_QSPI_CTRL_MASTER_Pos (5U)
5942 #define XQSPI_QSPI_CTRL_MASTER_Len (1U)
5943 #define XQSPI_QSPI_CTRL_MASTER_Msk (0x1U << XQSPI_QSPI_CTRL_MASTER_Pos)
5944 #define XQSPI_QSPI_CTRL_MASTER XQSPI_QSPI_CTRL_MASTER_Msk
5945
5946 #define XQSPI_QSPI_CTRL_CPOL_Pos (4U)
5947 #define XQSPI_QSPI_CTRL_CPOL_Len (1U)
5948 #define XQSPI_QSPI_CTRL_CPOL_Msk (0x1U << XQSPI_QSPI_CTRL_CPOL_Pos)
5949 #define XQSPI_QSPI_CTRL_CPOL XQSPI_QSPI_CTRL_CPOL_Msk
5950
5951 #define XQSPI_QSPI_CTRL_CPHA_Pos (3U)
5952 #define XQSPI_QSPI_CTRL_CPHA_Len (1U)
5953 #define XQSPI_QSPI_CTRL_CPHA_Msk (0x1U << XQSPI_QSPI_CTRL_CPHA_Pos)
5954 #define XQSPI_QSPI_CTRL_CPHA XQSPI_QSPI_CTRL_CPHA_Msk
5955
5956 #define XQSPI_QSPI_CTRL_MSB1ST_Pos (2U)
5957 #define XQSPI_QSPI_CTRL_MSB1ST_Len (1U)
5958 #define XQSPI_QSPI_CTRL_MSB1ST_Msk (0x1U << XQSPI_QSPI_CTRL_MSB1ST_Pos)
5959 #define XQSPI_QSPI_CTRL_MSB1ST XQSPI_QSPI_CTRL_MSB1ST_Msk
5960
5961 #define XQSPI_QSPI_CTRL_CONTXFER_Pos (0U)
5962 #define XQSPI_QSPI_CTRL_CONTXFER_Len (1U)
5963 #define XQSPI_QSPI_CTRL_CONTXFER_Msk (0x1U << XQSPI_QSPI_CTRL_CONTXFER_Pos)
5964 #define XQSPI_QSPI_CTRL_CONTXFER XQSPI_QSPI_CTRL_CONTXFER_Msk
5965
5966 /******************* Bit definition for XQSPI_QSPI_AUXCTRL register *********/
5967 #define XQSPI_QSPI_AUXCTRL_CONTXFERX_Pos (7U)
5968 #define XQSPI_QSPI_AUXCTRL_CONTXFERX_Len (1U)
5969 #define XQSPI_QSPI_AUXCTRL_CONTXFERX_Msk (0x1U << XQSPI_QSPI_AUXCTRL_CONTXFERX_Pos)
5970 #define XQSPI_QSPI_AUXCTRL_CONTXFERX XQSPI_QSPI_AUXCTRL_CONTXFERX_Msk
5971
5972 #define XQSPI_QSPI_AUXCTRL_BITSIZE_Pos (4U)
5973 #define XQSPI_QSPI_AUXCTRL_BITSIZE_Len (3U)
5974 #define XQSPI_QSPI_AUXCTRL_BITSIZE_Msk (0x7U << XQSPI_QSPI_AUXCTRL_BITSIZE_Pos)
5975 #define XQSPI_QSPI_AUXCTRL_BITSIZE XQSPI_QSPI_AUXCTRL_BITSIZE_Msk
5976
5977 #define XQSPI_QSPI_AUXCTRL_INHIBITDIN_Pos (3U)
5978 #define XQSPI_QSPI_AUXCTRL_INHIBITDIN_Len (1U)
5979 #define XQSPI_QSPI_AUXCTRL_INHIBITDIN_Msk (0x1U << XQSPI_QSPI_AUXCTRL_INHIBITDIN_Pos)
5980 #define XQSPI_QSPI_AUXCTRL_INHIBITDIN XQSPI_QSPI_AUXCTRL_INHIBITDIN_Msk
5981
5982 #define XQSPI_QSPI_AUXCTRL_INHIBITDOUT_Pos (2U)
5983 #define XQSPI_QSPI_AUXCTRL_INHIBITDOUT_Len (1U)
5984 #define XQSPI_QSPI_AUXCTRL_INHIBITDOUT_Msk (0x1U << XQSPI_QSPI_AUXCTRL_INHIBITDOUT_Pos)
5985 #define XQSPI_QSPI_AUXCTRL_INHIBITDOUT XQSPI_QSPI_AUXCTRL_INHIBITDOUT_Msk
5986
5987 #define XQSPI_QSPI_AUXCTRL_QMODE_Pos (0U)
5988 #define XQSPI_QSPI_AUXCTRL_QMODE_Len (2U)
5989 #define XQSPI_QSPI_AUXCTRL_QMODE_Msk (0x3U << XQSPI_QSPI_AUXCTRL_QMODE_Pos)
5990 #define XQSPI_QSPI_AUXCTRL_QMODE XQSPI_QSPI_AUXCTRL_QMODE_Msk
5991
5992 /******************* Bit definition for XQSPI_QSPI_SS register **************/
5993 #define XQSPI_QSPI_SS_OUT3_Pos (3U)
5994 #define XQSPI_QSPI_SS_OUT3_Len (1U)
5995 #define XQSPI_QSPI_SS_OUT3_Msk (0x1U << XQSPI_QSPI_SS_OUT3_Pos)
5996 #define XQSPI_QSPI_SS_OUT3 XQSPI_QSPI_SS_OUT3_Msk
5997
5998 #define XQSPI_QSPI_SS_OUT2_Pos (2U)
5999 #define XQSPI_QSPI_SS_OUT2_Len (1U)
6000 #define XQSPI_QSPI_SS_OUT2_Msk (0x1U << XQSPI_QSPI_SS_OUT2_Pos)
6001 #define XQSPI_QSPI_SS_OUT2 XQSPI_QSPI_SS_OUT2_Msk
6002
6003 #define XQSPI_QSPI_SS_OUT1_Pos (1U)
6004 #define XQSPI_QSPI_SS_OUT1_Len (1U)
6005 #define XQSPI_QSPI_SS_OUT1_Msk (0x1U << XQSPI_QSPI_SS_OUT1_Pos)
6006 #define XQSPI_QSPI_SS_OUT1 XQSPI_QSPI_SS_OUT1_Msk
6007
6008 #define XQSPI_QSPI_SS_OUT0_Pos (0U)
6009 #define XQSPI_QSPI_SS_OUT0_Len (1U)
6010 #define XQSPI_QSPI_SS_OUT0_Msk (0x1U << XQSPI_QSPI_SS_OUT0_Pos)
6011 #define XQSPI_QSPI_SS_OUT0 XQSPI_QSPI_SS_OUT0_Msk
6012
6013 /******************* Bit definition for XQSPI_QSPI_SS_POL register **********/
6014 #define XQSPI_QSPI_SS_POL3_Pos (3U)
6015 #define XQSPI_QSPI_SS_POL3_Len (1U)
6016 #define XQSPI_QSPI_SS_POL3_Msk (0x1U << XQSPI_QSPI_SS_POL3_Pos)
6017 #define XQSPI_QSPI_SS_POL3 XQSPI_QSPI_SS_POL3_Msk
6018
6019 #define XQSPI_QSPI_SS_POL2_Pos (2U)
6020 #define XQSPI_QSPI_SS_POL2_Len (1U)
6021 #define XQSPI_QSPI_SS_POL2_Msk (0x1U << XQSPI_QSPI_SS_POL2_Pos)
6022 #define XQSPI_QSPI_SS_POL2 XQSPI_QSPI_SS_POL2_Msk
6023
6024 #define XQSPI_QSPI_SS_POL1_Pos (1U)
6025 #define XQSPI_QSPI_SS_POL1_Len (1U)
6026 #define XQSPI_QSPI_SS_POL1_Msk (0x1U << XQSPI_QSPI_SS_POL1_Pos)
6027 #define XQSPI_QSPI_SS_POL1 XQSPI_QSPI_SS_POL1_Msk
6028
6029 #define XQSPI_QSPI_SS_POL0_Pos (0U)
6030 #define XQSPI_QSPI_SS_POL0_Len (1U)
6031 #define XQSPI_QSPI_SS_POL0_Msk (0x1U << XQSPI_QSPI_SS_POL0_Pos)
6032 #define XQSPI_QSPI_SS_POL0 XQSPI_QSPI_SS_POL0_Msk
6033
6034 /******************* Bit definition for XQSPI_QSPI_INT_EN register **********/
6035 #define XQSPI_QSPI_INT_EN_Pos (0U)
6036 #define XQSPI_QSPI_INT_EN_Len (7U)
6037 #define XQSPI_QSPI_INT_EN_Msk (0x7FUL << XQSPI_QSPI_INT_EN_Pos)
6038 #define XQSPI_QSPI_INT_EN XQSPI_QSPI_INT_EN_Msk
6039
6040 /******************* Bit definition for XQSPI_QSPI_INT_STAT register ********/
6041 #define XQSPI_QSPI_INT_STAT_Pos (0U)
6042 #define XQSPI_QSPI_INT_STAT_Len (7U)
6043 #define XQSPI_QSPI_INT_STAT_Msk (0x7FUL << XQSPI_QSPI_INT_STAT_Pos)
6044 #define XQSPI_QSPI_INT_STAT XQSPI_QSPI_INT_STAT_Msk
6045
6046 /******************* Bit definition for XQSPI_QSPI_INT_CLR register *********/
6047 #define XQSPI_QSPI_INT_CLR_Pos (0U)
6048 #define XQSPI_QSPI_INT_CLR_Len (7U)
6049 #define XQSPI_QSPI_INT_CLR_Msk (0x7FUL << XQSPI_QSPI_INT_CLR_Pos)
6050 #define XQSPI_QSPI_INT_CLR XQSPI_QSPI_INT_CLR_Msk
6051
6052 /******************* Bit definition for XQSPI Interrupt Bit Mapping *********/
6053 #define XQSPI_QSPI_GPI_HI_PULSE1_Pos (6U)
6054 #define XQSPI_QSPI_GPI_HI_PULSE1_Len (1U)
6055 #define XQSPI_QSPI_GPI_HI_PULSE1_Msk (0x1U << XQSPI_QSPI_GPI_HI_PULSE1_Pos)
6056 #define XQSPI_QSPI_GPI_HI_PULSE0_Pos (5U)
6057 #define XQSPI_QSPI_GPI_HI_PULSE0_Len (1U)
6058 #define XQSPI_QSPI_GPI_HI_PULSE0_Msk (0x1U << XQSPI_QSPI_GPI_HI_PULSE0_Pos)
6059 #define XQSPI_QSPI_XFER_DPULSE_Pos (4U)
6060 #define XQSPI_QSPI_XFER_DPULSE_Len (1U)
6061 #define XQSPI_QSPI_XFER_DPULSE_Msk (0x1U << XQSPI_QSPI_XFER_DPULSE_Pos)
6062 #define XQSPI_QSPI_RX_FPULSE_Pos (3U)
6063 #define XQSPI_QSPI_RX_FPULSE_Len (1U)
6064 #define XQSPI_QSPI_RX_FPULSE_Msk (0x1U << XQSPI_QSPI_RX_FPULSE_Pos)
6065 #define XQSPI_QSPI_RX_WPULSE_Pos (2U)
6066 #define XQSPI_QSPI_RX_WPULSE_Len (1U)
6067 #define XQSPI_QSPI_RX_WPULSE_Msk (0x1U << XQSPI_QSPI_RX_WPULSE_Pos)
6068 #define XQSPI_QSPI_TX_WPULSE_Pos (1U)
6069 #define XQSPI_QSPI_TX_WPULSE_Len (1U)
6070 #define XQSPI_QSPI_TX_WPULSE_Msk (0x1U << XQSPI_QSPI_TX_WPULSE_Pos)
6071 #define XQSPI_QSPI_TX_EPULSE_Pos (0U)
6072 #define XQSPI_QSPI_TX_EPULSE_Len (1U)
6073 #define XQSPI_QSPI_TX_EPULSE_Msk (0x1U << XQSPI_QSPI_TX_EPULSE_Pos)
6074
6075 /******************* Bit definition for XQSPI_QSPI_TXFIFOLVL register *******/
6076 #define XQSPI_QSPI_TXFIFOLVL_Pos (0U)
6077 #define XQSPI_QSPI_TXFIFOLVL_Len (7U)
6078 #define XQSPI_QSPI_TXFIFOLVL_Msk (0x7FUL << XQSPI_QSPI_TXFIFOLVL_Pos)
6079 #define XQSPI_QSPI_TXFIFOLVL XQSPI_QSPI_TXFIFOLVL_Msk
6080
6081 /******************* Bit definition for XQSPI_QSPI_RXFIFOLVL register *******/
6082 #define XQSPI_QSPI_RXFIFOLVL_Pos (0U)
6083 #define XQSPI_QSPI_RXFIFOLVL_Len (7U)
6084 #define XQSPI_QSPI_RXFIFOLVL_Msk (0x7FUL << XQSPI_QSPI_RXFIFOLVL_Pos)
6085 #define XQSPI_QSPI_RXFIFOLVL XQSPI_QSPI_RXFIFOLVL_Msk
6086
6087 /******************* Bit definition for XQSPI_QSPI_MWAIT register ***********/
6088 #define XQSPI_QSPI_MWAIT_MWAIT_Pos (0U)
6089 #define XQSPI_QSPI_MWAIT_MWAIT_Len (8U)
6090 #define XQSPI_QSPI_MWAIT_MWAIT_Msk (0xFFUL << XQSPI_QSPI_MWAIT_MWAIT_Pos)
6091 #define XQSPI_QSPI_MWAIT_MWAIT XQSPI_QSPI_MWAIT_MWAIT_Msk
6092
6093 /******************* Bit definition for XQSPI_QSPI_EN register **************/
6094 #define XQSPI_QSPI_EN_EN_Pos (0U)
6095 #define XQSPI_QSPI_EN_EN_Len (1U)
6096 #define XQSPI_QSPI_EN_EN_Msk (0x1U << XQSPI_QSPI_EN_EN_Pos)
6097 #define XQSPI_QSPI_EN_EN XQSPI_QSPI_EN_EN_Msk
6098
6099 /******************* Bit definition for XQSPI_QSPI_GPOSET_GPOSET register ***/
6100 #define XQSPI_QSPI_GPOSET_GPOSET_Pos (0U)
6101 #define XQSPI_QSPI_GPOSET_GPOSET_Len (8U)
6102 #define XQSPI_QSPI_GPOSET_GPOSET_Msk (0xFFUL << XQSPI_QSPI_GPOSET_GPOSET_Pos)
6103 #define XQSPI_QSPI_GPOSET_GPOSET XQSPI_QSPI_GPOSET_GPOSET_Msk
6104
6105 /******************* Bit definition for XQSPI_QSPI_GPOCLR_GPOCLR register ***/
6106 #define XQSPI_QSPI_GPOCLR_GPOCLR_Pos (0U)
6107 #define XQSPI_QSPI_GPOCLR_GPOCLR_Len (8U)
6108 #define XQSPI_QSPI_GPOCLR_GPOCLR_Msk (0xFFUL << XQSPI_QSPI_GPOCLR_GPOCLR_Pos)
6109 #define XQSPI_QSPI_GPOCLR_GPOCLR XQSPI_QSPI_GPOCLR_GPOCLR_Msk
6110
6111 /******************* Bit definition for XQSPI_QSPI_FLASH_WRITE register ***/
6112 #define XQSPI_QSPI_FLASH_WRITE_Pos (0U)
6113 #define XQSPI_QSPI_FLASH_WRITE_Len (1U)
6114 #define XQSPI_QSPI_FLASH_WRITE_Msk (0xFFUL << XQSPI_QSPI_FLASH_WRITE_Pos)
6115 #define XQSPI_QSPI_FLASH_WRITE XQSPI_QSPI_FLASH_WRITE_Msk
6116
6117 /******************* Bit definition for XQSPI_QSPI_PRESENT_BYPASS register ***/
6118 #define XQSPI_QSPI_PRESENT_BYPASS_Pos (0U)
6119 #define XQSPI_QSPI_PRESENT_BYPASS_Len (1U)
6120 #define XQSPI_QSPI_PRESENT_BYPASS_Msk (0xFFUL << XQSPI_QSPI_PRESENT_BYPASS_Pos)
6121 #define XQSPI_QSPI_PRESENT_BYPASS XQSPI_QSPI_PRESENT_BYPASS_Msk
6122
6123 /* =============================================================================================================== */
6124 /* ================ EFUSE ================ */
6125 /* =============================================================================================================== */
6126 /******************* Bit definition for EFUSE_TPGM register **********/
6127 #define EFUSE_TPGM_TIME_Pos (0U)
6128 #define EFUSE_TPGM_TIME_Len (12U)
6129 #define EFUSE_TPGM_TIME_Msk (0xFFFUL << EFUSE_TPGM_TIME_Pos)
6130 #define EFUSE_TPGM_TIME EFUSE_TPGM_TIME_Msk
6131
6132 #define EFUSE_TPGM_MAIN_OR_BACKUP_Pos (12U)
6133 #define EFUSE_TPGM_MAIN_OR_BACKUP_Len (1U)
6134 #define EFUSE_TPGM_MAIN_OR_BACKUP_Msk (0x1UL << EFUSE_TPGM_MAIN_OR_BACKUP_Pos)
6135 #define EFUSE_TPGM_MAIN_OR_BACKUP EFUSE_TPGM_MAIN_OR_BACKUP_Msk
6136
6137 #define EFUSE_TPGM_CRC_CHECK_LEN_Pos (16U)
6138 #define EFUSE_TPGM_CRC_CHECK_LEN_Len (6U)
6139 #define EFUSE_TPGM_CRC_CHECK_LEN_Msk (0x3FUL << EFUSE_TPGM_CRC_CHECK_LEN_Pos)
6140 #define EFUSE_TPGM_CRC_CHECK_LEN EFUSE_TPGM_CRC_CHECK_LEN_Msk
6141
6142 #define EFUSE_TPGM_WRITE_INTERVAL_Pos (24U)
6143 #define EFUSE_TPGM_WRITE_INTERVAL_Len (8U)
6144 #define EFUSE_TPGM_WRITE_INTERVAL_Msk (0xFFUL << EFUSE_TPGM_WRITE_INTERVAL_Pos)
6145 #define EFUSE_TPGM_WRITE_INTERVAL EFUSE_TPGM_WRITE_INTERVAL_Msk
6146
6147 /******************* Bit definition for EFUSE_PGENB register **********/
6148 #define EFUSE_PGENB_SIG_Pos (0U)
6149 #define EFUSE_PGENB_SIG_Len (1U)
6150 #define EFUSE_PGENB_SIG_Msk (0x1UL << EFUSE_PGENB_SIG_Pos)
6151 #define EFUSE_PGENB_SIG EFUSE_PGENB_SIG_Msk
6152
6153 /******************* Bit definition for EFUSE_TEST_MODE register **********/
6154 #define EFUSE_TEST_MODE_Pos (0U)
6155 #define EFUSE_TEST_MODE_Len (16U)
6156 #define EFUSE_TEST_MODE_Msk (0xFFFFUL << EFUSE_TEST_MODE_Pos)
6157 #define EFUSE_TEST_MODE EFUSE_TEST_MODE_Msk
6158
6159 /******************* Bit definition for EFUSE_OPERATION register **********/
6160 #define EFUSE_OPER_WRITE_KEYRAM_Pos (0U)
6161 #define EFUSE_OPER_WRITE_KEYRAM_Len (1U)
6162 #define EFUSE_OPER_WRITE_KEYRAM_Msk (0x1UL << EFUSE_OPER_WRITE_KEYRAM_Pos)
6163 #define EFUSE_OPER_WRITE_KEYRAM EFUSE_OPER_WRITE_KEYRAM_Msk
6164
6165 #define EFUSE_OPER_INIT_CHECK_Pos (1U)
6166 #define EFUSE_OPER_INIT_CHECK_Len (1U)
6167 #define EFUSE_OPER_INIT_CHECK_Msk (0x1UL << EFUSE_OPER_INIT_CHECK_Pos)
6168 #define EFUSE_OPER_INIT_CHECK EFUSE_OPER_INIT_CHECK_Msk
6169
6170 #define EFUSE_OPER_CRC_CHECK_Pos (2U)
6171 #define EFUSE_OPER_CRC_CHECK_Len (1U)
6172 #define EFUSE_OPER_CRC_CHECK_Msk (0x1UL << EFUSE_OPER_CRC_CHECK_Pos)
6173 #define EFUSE_OPER_CRC_CHECK EFUSE_OPER_CRC_CHECK_Msk
6174
6175 #define EFUSE_OPER_READ_TRIM_Pos (3U)
6176 #define EFUSE_OPER_READ_TRIM_Len (1U)
6177 #define EFUSE_OPER_READ_TRIM_Msk (0x1UL << EFUSE_OPER_READ_TRIM_Pos)
6178 #define EFUSE_OPER_READ_TRIM EFUSE_OPER_READ_TRIM_Msk
6179
6180 #define EFUSE_OPER_RD_TEST_MODE_Pos (4U)
6181 #define EFUSE_OPER_RD_TEST_MODE_Len (1U)
6182 #define EFUSE_OPER_RD_TEST_MODE_Msk (0x1UL << EFUSE_OPER_RD_TEST_MODE_Pos)
6183 #define EFUSE_OPER_RD_TEST_MODE EFUSE_OPER_RD_TEST_MODE_Msk
6184
6185 /******************* Bit definition for EFUSE_STATUS register **********/
6186 #define EFUSE_STATUS_WRITE_KEYRAM_BUSY_Pos (0U)
6187 #define EFUSE_STATUS_WRITE_KEYRAM_BUSY_Len (1U)
6188 #define EFUSE_STATUS_WRITE_KEYRAM_BUSY_Msk (0x1UL << EFUSE_STATUS_WRITE_KEYRAM_BUSY_Pos)
6189 #define EFUSE_STATUS_WRITE_KEYRAM_BUSY EFUSE_STATUS_WRITE_KEYRAM_BUSY_Msk
6190
6191 #define EFUSE_STATUS_READ_TRIM_DONE_Pos (1U)
6192 #define EFUSE_STATUS_READ_TRIM_DONE_Len (1U)
6193 #define EFUSE_STATUS_READ_TRIM_DONE_Msk (0x1UL << EFUSE_STATUS_READ_TRIM_DONE_Pos)
6194 #define EFUSE_STATUS_READ_TRIM_DONE EFUSE_STATUS_READ_TRIM_DONE_Msk
6195
6196 #define EFUSE_STATUS_TRIM_CRC_SUCCESS_Pos (2U)
6197 #define EFUSE_STATUS_TRIM_CRC_SUCCESS_Len (1U)
6198 #define EFUSE_STATUS_TRIM_CRC_SUCCESS_Msk (0x1UL << EFUSE_STATUS_TRIM_CRC_SUCCESS_Pos)
6199 #define EFUSE_STATUS_TRIM_CRC_SUCCESS EFUSE_STATUS_TRIM_CRC_SUCCESS_Msk
6200
6201 #define EFUSE_STATUS_INIT_DONE_Pos (3U)
6202 #define EFUSE_STATUS_INIT_DONE_Len (1U)
6203 #define EFUSE_STATUS_INIT_DONE_Msk (0x1UL << EFUSE_STATUS_INIT_DONE_Pos)
6204 #define EFUSE_STATUS_INIT_DONE EFUSE_STATUS_INIT_DONE_Msk
6205
6206 #define EFUSE_STATUS_INIT_SUCCESS_Pos (4U)
6207 #define EFUSE_STATUS_INIT_SUCCESS_Len (1U)
6208 #define EFUSE_STATUS_INIT_SUCCESS_Msk (0x1UL << EFUSE_STATUS_INIT_SUCCESS_Pos)
6209 #define EFUSE_STATUS_INIT_SUCCESS EFUSE_STATUS_INIT_SUCCESS_Msk
6210
6211 #define EFUSE_STATUS_CRC_CHECK_DONE_Pos (5U)
6212 #define EFUSE_STATUS_CRC_CHECK_DONE_Len (1U)
6213 #define EFUSE_STATUS_CRC_CHECK_DONE_Msk (0x1UL << EFUSE_STATUS_CRC_CHECK_DONE_Pos)
6214 #define EFUSE_STATUS_CRC_CHECK_DONE EFUSE_STATUS_CRC_CHECK_DONE_Msk
6215
6216 #define EFUSE_STATUS_WRITE_DONE_Pos (6U)
6217 #define EFUSE_STATUS_WRITE_DONE_Len (1U)
6218 #define EFUSE_STATUS_WRITE_DONE_Msk (0x1UL << EFUSE_STATUS_WRITE_DONE_Pos)
6219 #define EFUSE_STATUS_WRITE_DONE EFUSE_STATUS_WRITE_DONE_Msk
6220
6221 #define EFUSE_STATUS_TEST_MODE_DONE_Pos (7U)
6222 #define EFUSE_STATUS_TEST_MODE_DONE_Len (1U)
6223 #define EFUSE_STATUS_TEST_MODE_DONE_Msk (0x1UL << EFUSE_STATUS_TEST_MODE_DONE_Pos)
6224 #define EFUSE_STATUS_TEST_MODE_DONE EFUSE_STATUS_TEST_MODE_DONE_Msk
6225
6226 /******************* Bit definition for EFUSE_KEY_MASK register **********/
6227 #define EFUSE_KEY_MASK_Pos (0U)
6228 #define EFUSE_KEY_MASK_Len (32U)
6229 #define EFUSE_KEY_MASK_Msk (0x1UL << EFUSE_KEY_MASK_Pos)
6230 #define EFUSE_KEY_MASK EFUSE_KEY_MASK_Msk
6231
6232 /******************* Bit definition for EFUSE_CRC_START_ADDR register **********/
6233 #define EFUSE_CRC_START_CHECK_ADDR_Pos (0U)
6234 #define EFUSE_CRC_START_CHECK_ADDR_Len (32U)
6235 #define EFUSE_CRC_START_CHECK_ADDR_Msk (0xFFFFFFFFU)
6236 #define EFUSE_CRC_START_CHECK_ADDR EFUSE_CRC_START_CHECK_ADDR_Msk
6237
6238 /******************* Bit definition for EFUSE_CRC_OUTPUT register **********/
6239 #define EFUSE_CRC_OUTPUT_VALUE_Pos (0U)
6240 #define EFUSE_CRC_OUTPUT_VALUE_Len (32U)
6241 #define EFUSE_CRC_OUTPUT_VALUE_Msk (0xFFFFFFFFU)
6242 #define EFUSE_CRC_OUTPUT_VALUE EFUSE_CRC_OUTPUT_VALUE_Msk
6243
6244 /******************* Bit definition for EFUSE_TRIM_ADDR register **********/
6245 #define EFUSE_TRIM_START_ADDR_Pos (0U)
6246 #define EFUSE_TRIM_START_ADDR_Len (32U)
6247 #define EFUSE_TRIM_START_ADDR_Msk (0xFFFFFFFFU)
6248 #define EFUSE_TRIM_START_ADDR EFUSE_TRIM_START_ADDR_Msk
6249
6250 /******************* Bit definition for EFUSE_TRIM_LEN register **********/
6251 #define EFUSE_TRIM_LENGTH_Pos (0U)
6252 #define EFUSE_TRIM_LENGTH_Len (5U)
6253 #define EFUSE_TRIM_LENGTH_Msk (0x1FU << EFUSE_TRIM_LENGTH_Pos)
6254 #define EFUSE_TRIM_LENGTH EFUSE_TRIM_LENGTH_Msk
6255
6256 /******************* Bit definition for EFUSE_TRIM register **************/
6257 #define EFUSE_TRIM_Pos (0U)
6258 #define EFUSE_TRIM_Len (32U)
6259 #define EFUSE_TRIM_Msk (0xFFFFFFFFU)
6260 #define EFUSE_TRIM EFUSE_TRIM_Msk
6261
6262 /* =============================================================================================================== */
6263 /* ================ RNG ================ */
6264 /* =============================================================================================================== */
6265 /******************* Bit definition for RNG_CTRL register **********/
6266 #define RNG_CTRL_RUN_EN_Pos (0U)
6267 #define RNG_CTRL_RUN_EN_Len (1U)
6268 #define RNG_CTRL_RUN_EN_Msk (0x1UL << RNG_CTRL_RUN_EN_Pos)
6269 #define RNG_CTRL_RUN_EN RNG_CTRL_RUN_EN_Msk
6270
6271 /******************* Bit definition for RNG_STATUS register **********/
6272 #define RNG_STATUS_READY_Pos (0U)
6273 #define RNG_STATUS_READY_Len (1U)
6274 #define RNG_STATUS_READY_Msk (0x1UL << RNG_STATUS_READY_Pos)
6275 #define RNG_STATUS_READY RNG_STATUS_READY_Msk
6276
6277 /******************* Bit definition for RNG_DATA register **********/
6278 #define RNG_DATA_VALUE_Pos (0U)
6279 #define RNG_DATA_VALUE_Len (32U)
6280 #define RNG_DATA_VALUE_Msk (0xFFFFFFFF)
6281 #define RNG_DATA_VALUE RNG_DATA_VALUE_Msk
6282
6283 /******************* Bit definition for RNG_LR_STATUS register *********/
6284 #define RNG_LR_STATUS_FLAG_Pos (0U)
6285 #define RNG_LR_STATUS_FLAG_Len (1U)
6286 #define RNG_LR_STATUS_FLAG_Msk (0x1UL << RNG_LR_STATUS_FLAG_Pos)
6287 #define RNG_LR_STATUS_FLAG RNG_LR_STATUS_FLAG_Msk
6288 #define RNG_LR_STATUS_CNT_Pos (1U)
6289 #define RNG_LR_STATUS_CNT_Len (8U)
6290 #define RNG_LR_STATUS_CNT_Msk (0xFFUL << RNG_LR_STATUS_CNT_Pos)
6291 #define RNG_LR_STATUS_CNT RNG_LR_STATUS_CNT_Msk
6292
6293 /******************* Bit definition for RNG_CONFIG register ************/
6294 #define RNG_CONFIG_OUT_MODE_Pos (0U)
6295 #define RNG_CONFIG_OUT_MODE_Len (4U)
6296 #define RNG_CONFIG_OUT_MODE_Msk (0xFUL << RNG_CONFIG_OUT_MODE_Pos)
6297 #define RNG_CONFIG_OUT_MODE RNG_CONFIG_OUT_MODE_Msk
6298 #define RNG_CONFIG_LFSR_XOR_SEL_Pos (4U)
6299 #define RNG_CONFIG_LFSR_XOR_SEL_Len (3U)
6300 #define RNG_CONFIG_LFSR_XOR_SEL_Msk (0x7UL << RNG_CONFIG_LFSR_XOR_SEL_Pos)
6301 #define RNG_CONFIG_LFSR_XOR_SEL RNG_CONFIG_LFSR_XOR_SEL_Msk
6302 #define RNG_CONFIG_POST_MODE_Pos (7U)
6303 #define RNG_CONFIG_POST_MODE_Len (2U)
6304 #define RNG_CONFIG_POST_MODE_Msk (0x3UL << RNG_CONFIG_POST_MODE_Pos)
6305 #define RNG_CONFIG_POST_MODE RNG_CONFIG_POST_MODE_Msk
6306 #define RNG_CONFIG_LFSR_MODE_Pos (9U)
6307 #define RNG_CONFIG_LFSR_MODE_Len (1U)
6308 #define RNG_CONFIG_LFSR_MODE_Msk (0x1UL << RNG_CONFIG_LFSR_MODE_Pos)
6309 #define RNG_CONFIG_LFSR_MODE RNG_CONFIG_LFSR_MODE_Msk
6310 #define RNG_CONFIG_LFSR_SEED_SEL_Pos (10U)
6311 #define RNG_CONFIG_LFSR_SEED_SEL_Len (3U)
6312 #define RNG_CONFIG_LFSR_SEED_SEL_Msk (0x7UL << RNG_CONFIG_LFSR_SEED_SEL_Pos)
6313 #define RNG_CONFIG_LFSR_SEED_SEL RNG_CONFIG_LFSR_SEED_SEL_Msk
6314 #define RNG_CONFIG_IRQ_EN_Pos (13U)
6315 #define RNG_CONFIG_IRQ_EN_Len (1U)
6316 #define RNG_CONFIG_IRQ_EN_Msk (0x1UL << RNG_CONFIG_IRQ_EN_Pos)
6317 #define RNG_CONFIG_IRQ_EN RNG_CONFIG_IRQ_EN_Msk
6318 #define RNG_CONFIG_FRO_EN_Pos (15U)
6319 #define RNG_CONFIG_FRO_EN_Len (1U)
6320 #define RNG_CONFIG_FRO_EN_Msk (0x1UL << RNG_CONFIG_FRO_EN_Pos)
6321 #define RNG_CONFIG_FRO_EN RNG_CONFIG_FRO_EN_Msk
6322
6323 /******************* Bit definition for RNG_TSCON register *************/
6324 #define RNG_TSCON_TRDY_TIME_Pos (0U)
6325 #define RNG_TSCON_TRDY_TIME_Len (8U)
6326 #define RNG_TSCON_TRDY_TIME_Msk (0xFUL << RNG_TSCON_TRDY_TIME_Pos)
6327 #define RNG_TSCON_TRDY_TIME RNG_TSCON_TRDY_TIME_Msk
6328 #define RNG_TSCON_FRO_CHAIN_Pos (11U)
6329 #define RNG_TSCON_FRO_CHAIN_Len (4U)
6330 #define RNG_TSCON_FRO_CHAIN_Msk (0xFUL << RNG_TSCON_FRO_CHAIN_Pos)
6331 #define RNG_TSCON_FRO_CHAIN RNG_TSCON_FRO_CHAIN_Msk
6332
6333 /******************* Bit definition for RNG_FROCFG register *************/
6334 #define RNG_FROCFG_CHAINE_EN_Pos (0U)
6335 #define RNG_FROCFG_CHAINE_EN_Len (8U)
6336 #define RNG_FROCFG_CHAINE_EN_Msk (0xFFUL << RNG_FROCFG_CHAINE_EN_Pos)
6337 #define RNG_FROCFG_CHAINE_EN RNG_FROCFG_CHAINE_EN_Msk
6338 #define RNG_FROCFG_TEST_IN_Pos (8U)
6339 #define RNG_FROCFG_TEST_IN_Len (8U)
6340 #define RNG_FROCFG_TEST_IN_Msk (0xFFUL << RNG_FROCFG_TEST_IN_Pos)
6341 #define RNG_FROCFG_TEST_IN RNG_FROCFG_TEST_IN_Msk
6342
6343 /******************* Bit definition for RNG_USER_SEED register *************/
6344 #define RNG_USER_SEED_Pos (0U)
6345 #define RNG_USER_SEED_Len (16U)
6346 #define RNG_USER_SEED_Msk (0xFFUL << RNG_USER_SEED_Pos)
6347 #define RNG_USER_SEED RNG_USER_SEED_Msk
6348
6349 /******************* Bit definition for RNG_LRCON register *****************/
6350 #define RNG_LRCON_TEST_EN_Pos (0U)
6351 #define RNG_LRCON_TEST_EN_Len (1U)
6352 #define RNG_LRCON_TEST_EN_Msk (0x1UL << RNG_LRCON_TEST_EN_Pos)
6353 #define RNG_LRCON_TEST_EN RNG_LRCON_TEST_EN_Msk
6354 #define RNG_LRCON_TEST_LIMIT_Pos (1U)
6355 #define RNG_LRCON_TEST_LIMIT_Len (5U)
6356 #define RNG_LRCON_TEST_LIMIT_Msk (0x1FUL << RNG_LRCON_TEST_LIMIT_Pos)
6357 #define RNG_LRCON_TEST_LIMIT RNG_LRCON_TEST_LIMIT_Msk
6358
6359 /** @} */ /* End of group Peripheral_Registers_Bits_Definition */
6360
6361 /** @addtogroup Exported_macros
6362 * @{
6363 */
6364 /****************************** GPIO instances ********************************/
IS_GPIO_ALL_INSTANCE(gpio_regs_t * __INSTANCE__)6365 static inline uint32_t IS_GPIO_ALL_INSTANCE(gpio_regs_t *__INSTANCE__)
6366 {
6367 return (((__INSTANCE__) == GPIO0) || ((__INSTANCE__) == GPIO1));
6368 }
6369
6370 /****************************** I2C instances *********************************/
IS_I2C_ALL_INSTANCE(i2c_regs_t * __INSTANCE__)6371 static inline uint32_t IS_I2C_ALL_INSTANCE(i2c_regs_t *__INSTANCE__)
6372 {
6373 return (((__INSTANCE__) == I2C0) || ((__INSTANCE__) == I2C1));
6374 }
6375
6376 /****************************** I2S instances *********************************/
IS_I2S_ALL_INSTANCE(i2s_regs_t * __INSTANCE__)6377 static inline uint32_t IS_I2S_ALL_INSTANCE(i2s_regs_t *__INSTANCE__)
6378 {
6379 return (((__INSTANCE__) == I2S_M) || ((__INSTANCE__) == I2S_S));
6380 }
6381
6382 /****************************** UART instances ********************************/
IS_UART_ALL_INSTANCE(uart_regs_t * __INSTANCE__)6383 static inline uint32_t IS_UART_ALL_INSTANCE(uart_regs_t *__INSTANCE__)
6384 {
6385 return (((__INSTANCE__) == UART0) || ((__INSTANCE__) == UART1));
6386 }
6387
6388 /******************** UART instances : Support of DMA *************************/
IS_UART_DMA_INSTANCE(uart_regs_t * __INSTANCE__)6389 static inline uint32_t IS_UART_DMA_INSTANCE(uart_regs_t *__INSTANCE__)
6390 {
6391 return (((__INSTANCE__) == UART0));
6392 }
6393
6394 /****************************** TIM instances *********************************/
IS_UART_TIM_INSTANCE(timer_regs_t * __INSTANCE__)6395 static inline uint32_t IS_UART_TIM_INSTANCE(timer_regs_t *__INSTANCE__)
6396 {
6397 return (((__INSTANCE__) == TIMER0) || ((__INSTANCE__) == TIMER1));
6398 }
6399
6400 /****************************** DUAL TIM instances ****************************/
IS_DUAL_TIM_ALL_INSTANCE(dual_timer_regs_t * __INSTANCE__)6401 static inline uint32_t IS_DUAL_TIM_ALL_INSTANCE(dual_timer_regs_t *__INSTANCE__)
6402 {
6403 return (((__INSTANCE__) == DUAL_TIMER0) || ((__INSTANCE__) == DUAL_TIMER1));
6404 }
6405
6406 /****************************** PWM instances *********************************/
IS_PWM_ALL_INSTANCE(pwm_regs_t * __INSTANCE__)6407 static inline uint32_t IS_PWM_ALL_INSTANCE(pwm_regs_t *__INSTANCE__)
6408 {
6409 return (((__INSTANCE__) == PWM0) || ((__INSTANCE__) == PWM1));
6410 }
6411
6412 /****************************** WDT instances *********************************/
IS_WDT_ALL_INSTANCE(wdt_regs_t * __INSTANCE__)6413 static inline uint32_t IS_WDT_ALL_INSTANCE(wdt_regs_t *__INSTANCE__)
6414 {
6415 return (((__INSTANCE__) == WDT));
6416 }
6417
6418 /****************************** SPI instances *********************************/
IS_SPI_ALL_INSTANCE(ssi_regs_t * __INSTANCE__)6419 static inline uint32_t IS_SPI_ALL_INSTANCE(ssi_regs_t *__INSTANCE__)
6420 {
6421 return (((__INSTANCE__) == SPIM) || ((__INSTANCE__) == SPIS));
6422 }
6423
6424 /****************************** QSPI instances ********************************/
IS_QSPI_ALL_INSTANCE(ssi_regs_t * __INSTANCE__)6425 static inline uint32_t IS_QSPI_ALL_INSTANCE(ssi_regs_t *__INSTANCE__)
6426 {
6427 return (((__INSTANCE__) == QSPI0) || ((__INSTANCE__) == QSPI1));
6428 }
6429
6430 /****************************** PKC instances *********************************/
IS_PKC_ALL_INSTANCE(pkc_regs_t * __INSTANCE__)6431 static inline uint32_t IS_PKC_ALL_INSTANCE(pkc_regs_t *__INSTANCE__)
6432 {
6433 return (((__INSTANCE__) == PKC));
6434 }
6435
6436 /****************************** AES Instances *********************************/
IS_AES_ALL_INSTANCE(aes_regs_t * __INSTANCE__)6437 static inline uint32_t IS_AES_ALL_INSTANCE(aes_regs_t *__INSTANCE__)
6438 {
6439 return (((__INSTANCE__) == AES));
6440 }
6441
6442 /****************************** HMAC Instances ********************************/
IS_HMAC_ALL_INSTANCE(hmac_regs_t * __INSTANCE__)6443 static inline uint32_t IS_HMAC_ALL_INSTANCE(hmac_regs_t *__INSTANCE__)
6444 {
6445 return (((__INSTANCE__) == HMAC));
6446 }
6447
6448 /****************************** XQSPI Instances *******************************/
IS_XQSPI_ALL_INSTANCE(xqspi_regs_t * __INSTANCE__)6449 static inline uint32_t IS_XQSPI_ALL_INSTANCE(xqspi_regs_t *__INSTANCE__)
6450 {
6451 return (((__INSTANCE__) == XQSPI));
6452 }
6453
6454 /****************************** EFUSE Instances *******************************/
IS_EFUSE_ALL_INSTANCE(efuse_regs_t * __INSTANCE__)6455 static inline uint32_t IS_EFUSE_ALL_INSTANCE(efuse_regs_t *__INSTANCE__)
6456 {
6457 return (((__INSTANCE__) == EFUSE));
6458 }
6459
6460 /****************************** RNG Instances *******************************/
IS_RNG_ALL_INSTANCE(rng_regs_t * __INSTANCE__)6461 static inline uint32_t IS_RNG_ALL_INSTANCE(rng_regs_t *__INSTANCE__)
6462 {
6463 return (((__INSTANCE__) == RNG));
6464 }
6465
6466 /** @} */ /* End of group Exported_macros */
6467
6468 #ifdef __cplusplus
6469 }
6470 #endif
6471
6472 #endif /* __GR551xx_H__ */
6473
6474 /** @} */ /* End of group GR551xx */
6475
6476 /** @} */ /* End of group CMSIS_Device */
6477