1 /****************************************************************************** 2 * @file gd32vf103.h 3 * @brief NMSIS Core Peripheral Access Layer Header File for GD32VF103 series 4 * 5 * @version V1.00 6 * @date 4. Jan 2020 7 ******************************************************************************/ 8 /* 9 * Copyright (c) 2019 Nuclei Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 #ifndef __GD32VF103_H__ 27 #define __GD32VF103_H__ 28 29 #include <stddef.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /** @addtogroup gd32 36 * @{ 37 */ 38 39 40 /** @addtogroup gd32vf103 41 * @{ 42 */ 43 44 45 /** @addtogroup Configuration_of_NMSIS 46 * @{ 47 */ 48 49 50 51 52 /* =========================================================================================================================== */ 53 /* ================ Interrupt Number Definition ================ */ 54 /* =========================================================================================================================== */ 55 56 typedef enum IRQn 57 { 58 /* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */ 59 60 Reserved0_IRQn = 0, /*!< Internal reserved */ 61 Reserved1_IRQn = 1, /*!< Internal reserved */ 62 Reserved2_IRQn = 2, /*!< Internal reserved */ 63 SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */ 64 Reserved3_IRQn = 4, /*!< Internal reserved */ 65 Reserved4_IRQn = 5, /*!< Internal reserved */ 66 Reserved5_IRQn = 6, /*!< Internal reserved */ 67 SysTimer_IRQn = 7, /*!< System Timer Interrupt */ 68 Reserved6_IRQn = 8, /*!< Internal reserved */ 69 Reserved7_IRQn = 9, /*!< Internal reserved */ 70 Reserved8_IRQn = 10, /*!< Internal reserved */ 71 Reserved9_IRQn = 11, /*!< Internal reserved */ 72 Reserved10_IRQn = 12, /*!< Internal reserved */ 73 Reserved11_IRQn = 13, /*!< Internal reserved */ 74 Reserved12_IRQn = 14, /*!< Internal reserved */ 75 Reserved13_IRQn = 15, /*!< Internal reserved */ 76 Reserved14_IRQn = 16, /*!< Internal reserved */ 77 BusError_IRQn = 17, /*!< Bus Error interrupt */ 78 PerfMon_IRQn = 18, /*!< Performance Monitor */ 79 80 /* =========================================== GD32VF103 Specific Interrupt Numbers ========================================= */ 81 /* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported 82 could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s 83 eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ 84 /* interruput numbers */ 85 WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */ 86 LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */ 87 TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */ 88 RTC_IRQn = 22, /*!< RTC alarm interrupt */ 89 FMC_IRQn = 23, /*!< FMC interrupt */ 90 RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */ 91 EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */ 92 EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */ 93 EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */ 94 EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */ 95 EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */ 96 DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */ 97 DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */ 98 DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */ 99 DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */ 100 DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */ 101 DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */ 102 DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */ 103 ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */ 104 CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */ 105 CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */ 106 CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */ 107 CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */ 108 EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */ 109 TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */ 110 TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */ 111 TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */ 112 TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */ 113 TIMER1_IRQn = 47, /*!< TIMER1 interrupt */ 114 TIMER2_IRQn = 48, /*!< TIMER2 interrupt */ 115 TIMER3_IRQn = 49, /*!< TIMER3 interrupts */ 116 I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */ 117 I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */ 118 I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */ 119 I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */ 120 SPI0_IRQn = 54, /*!< SPI0 interrupt */ 121 SPI1_IRQn = 55, /*!< SPI1 interrupt */ 122 USART0_IRQn = 56, /*!< USART0 interrupt */ 123 USART1_IRQn = 57, /*!< USART1 interrupt */ 124 USART2_IRQn = 58, /*!< USART2 interrupt */ 125 EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */ 126 RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */ 127 USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */ 128 129 EXMC_IRQn = 67, /*!< EXMC global interrupt */ 130 131 TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */ 132 SPI2_IRQn = 70, /*!< SPI2 global interrupt */ 133 UART3_IRQn = 71, /*!< UART3 global interrupt */ 134 UART4_IRQn = 72, /*!< UART4 global interrupt */ 135 TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */ 136 TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */ 137 DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */ 138 DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */ 139 DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */ 140 DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */ 141 DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */ 142 143 CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */ 144 CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */ 145 CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */ 146 CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ 147 USBFS_IRQn = 86, /*!< USBFS global interrupt */ 148 149 SOC_INT_MAX, 150 151 } IRQn_Type; 152 153 /* =========================================================================================================================== */ 154 /* ================ Exception Code Definition ================ */ 155 /* =========================================================================================================================== */ 156 157 typedef enum EXCn { 158 /* ======================================= Nuclei N/NX Specific Exception Code ======================================== */ 159 InsUnalign_EXCn = 0, /*!< Instruction address misaligned */ 160 InsAccFault_EXCn = 1, /*!< Instruction access fault */ 161 IlleIns_EXCn = 2, /*!< Illegal instruction */ 162 Break_EXCn = 3, /*!< Beakpoint */ 163 LdAddrUnalign_EXCn = 4, /*!< Load address misaligned */ 164 LdFault_EXCn = 5, /*!< Load access fault */ 165 StAddrUnalign_EXCn = 6, /*!< Store or AMO address misaligned */ 166 StAccessFault_EXCn = 7, /*!< Store or AMO access fault */ 167 UmodeEcall_EXCn = 8, /*!< Environment call from User mode */ 168 MmodeEcall_EXCn = 11, /*!< Environment call from Machine mode */ 169 NMI_EXCn = 0xfff, /*!< NMI interrupt*/ 170 } EXCn_Type; 171 172 /* =========================================================================================================================== */ 173 /* ================ Processor and Core Peripheral Section ================ */ 174 /* =========================================================================================================================== */ 175 176 /* ToDo: set the defines according your Device */ 177 /* ToDo: define the correct core revision */ 178 #define __NUCLEI_N_REV 0x0100 /*!< Core Revision r1p0 */ 179 180 /* ToDo: define the correct core features for the nuclei_soc */ 181 #define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */ 182 #define __ECLIC_BASEADDR 0xD2000000UL /*!< Set to ECLIC baseaddr of your device */ 183 184 #define __ECLIC_INTCTLBITS 4 /*!< Set to 1 - 8, the number of hardware bits are actually implemented in the clicintctl registers. */ 185 #define __ECLIC_INTNUM 86 /*!< Set to 1 - 1005, the external interrupt number of ECLIC Unit */ 186 #define __SYSTIMER_PRESENT 1 /*!< Set to 1 if System Timer is present */ 187 #define __SYSTIMER_BASEADDR 0xD1000000UL /*!< Set to SysTimer baseaddr of your device */ 188 189 /*!< Set to 0, 1, or 2, 0 not present, 1 single floating point unit present, 2 double floating point unit present */ 190 #define __FPU_PRESENT 0 191 192 #define __DSP_PRESENT 0 /*!< Set to 1 if DSP is present */ 193 #define __PMP_PRESENT 1 /*!< Set to 1 if PMP is present */ 194 #define __PMP_ENTRY_NUM 8 /*!< Set to 8 or 16, the number of PMP entries */ 195 #define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ 196 #define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ 197 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 198 #define __Vendor_EXCEPTION 0 /*!< Set to 1 if vendor exception hander is present */ 199 200 /** @} */ /* End of group Configuration_of_CMSIS */ 201 202 203 204 #include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */ 205 /* ToDo: include your system_nuclei_soc.h file 206 replace 'Device' with your device name */ 207 #include "system_gd32vf103.h" /*!< gd32vf103 System */ 208 209 210 /* ======================================== Start of section using anonymous unions ======================================== */ 211 #if defined (__GNUC__) 212 /* anonymous unions are enabled by default */ 213 #else 214 #warning Not supported compiler type 215 #endif 216 217 218 /* system frequency define */ 219 #define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ 220 #define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ 221 #define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ 222 223 #define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) 224 225 226 #define RTC_FREQ LXTAL_VALUE 227 // The TIMER frequency is just the RTC frequency 228 #define SOC_TIMER_FREQ ((uint32_t)SystemCoreClock/4) //LXTAL_VALUE units HZ 229 230 231 /* enum definitions */ 232 typedef enum { 233 DISABLE = 0, 234 ENABLE = !DISABLE 235 } EventStatus, ControlStatus; 236 237 // Already defined 238 // typedef enum { 239 // FALSE = 0, 240 // TRUE = !FALSE 241 // } BOOL; 242 243 typedef enum { 244 RESET = 0, 245 SET = 1, 246 MAX = 0X7FFFFFFF 247 } FlagStatus; 248 249 typedef enum { 250 ERROR = 0, 251 SUCCESS = !ERROR 252 } ErrStatus; 253 254 /* =========================================================================================================================== */ 255 /* ================ Device Specific Peripheral Section ================ */ 256 /* =========================================================================================================================== */ 257 258 259 /** @addtogroup Device_Peripheral_peripherals 260 * @{ 261 */ 262 263 /**************************************************************************** 264 * Platform definitions 265 *****************************************************************************/ 266 267 268 269 270 271 /* ToDo: add here your device specific peripheral access structure typedefs 272 following is an example for Systick Timer*/ 273 274 /* =========================================================================================================================== */ 275 /* ================ SysTick Timer ================ */ 276 /* =========================================================================================================================== */ 277 278 /*@}*/ /* end of group nuclei_soc_Peripherals */ 279 280 281 /* ========================================= End of section using anonymous unions ========================================= */ 282 #if defined (__GNUC__) 283 /* anonymous unions are enabled by default */ 284 #else 285 #warning Not supported compiler type 286 #endif 287 288 289 /* =========================================================================================================================== */ 290 /* ================ Device Specific Peripheral Address Map ================ */ 291 /* =========================================================================================================================== */ 292 293 294 /* ToDo: add here your device peripherals base addresses 295 following is an example for timer */ 296 /** @addtogroup Device_Peripheral_peripheralAddr 297 * @{ 298 */ 299 /* main flash and SRAM memory map */ 300 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ 301 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ 302 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ 303 #define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ 304 #define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ 305 306 /* peripheral memory map */ 307 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ 308 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ 309 #define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ 310 #define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ 311 312 /* advanced peripheral bus 1 memory map */ 313 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ 314 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ 315 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ 316 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ 317 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ 318 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ 319 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ 320 #define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ 321 #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ 322 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ 323 #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ 324 325 /* advanced peripheral bus 2 memory map */ 326 #define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ 327 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ 328 #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ 329 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ 330 331 /* advanced high performance bus 1 memory map */ 332 #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ 333 #define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ 334 #define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ 335 #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ 336 #define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ 337 338 339 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 340 341 342 /* =========================================================================================================================== */ 343 /* ================ Peripheral declaration ================ */ 344 /* =========================================================================================================================== */ 345 346 347 /* ToDo: add here your device peripherals pointer definitions 348 following is an example for timer */ 349 /** @addtogroup Device_Peripheral_declaration 350 * @{ 351 */ 352 /* bit operations */ 353 #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) 354 #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) 355 #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) 356 #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) 357 #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 358 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) 359 360 // Interrupt Numbers 361 #define SOC_ECLIC_NUM_INTERRUPTS 86 362 #define SOC_ECLIC_INT_GPIO_BASE 19 363 364 365 // Interrupt Handler Definitions 366 #define SOC_MTIMER_HANDLER eclic_mtip_handler 367 #define SOC_SOFTINT_HANDLER eclic_msip_handler 368 369 #define NUM_GPIO 32 370 371 extern uint32_t get_cpu_freq(void); 372 373 /** 374 * \brief delay a time in milliseconds 375 * \param[in] count: count in milliseconds 376 * \param[out] none 377 * \retval none 378 */ 379 extern void delay_1ms(uint32_t count); 380 381 382 /** @} */ /* End of group gd32vf103_soc */ 383 384 /** @} */ /* End of group gd32vf103 */ 385 386 #ifdef __cplusplus 387 } 388 #endif 389 390 #endif /* __GD32VF103_SOC_H__ */ 391