1 /**
2 *****************************************************************************************
3 *
4 * @file interrupt_gr55xx.c
5 *
6 * @brief Interrupt Service Routines.
7 *
8 *****************************************************************************************
9
10 * @attention
11 #####Copyright (c) 2019 GOODIX
12 All rights reserved.
13
14 Redistribution and use in source and binary forms, with or without
15 modification, are permitted provided that the following conditions are met:
16 * Redistributions of source code must retain the above copyright
17 notice, this list of conditions and the following disclaimer.
18 * Redistributions in binary form must reproduce the above copyright
19 notice, this list of conditions and the following disclaimer in the
20 documentation and/or other materials provided with the distribution.
21 * Neither the name of GOODIX nor the names of its contributors may be used
22 to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 POSSIBILITY OF SUCH DAMAGE.
36 *****************************************************************************************
37 */
38
39 /*
40 * INCLUDE FILES
41 *****************************************************************************************
42 */
43 #include "gr55xx_sys.h"
44 #include "gr55xx_hal.h"
45 #include "custom_config.h"
46 #include "gr55xx_rom_symbol.h"
47
48 /******************************************************************************/
49 /* Cortex-M4F Processor Interruption and Exception Handlers */
50 /* Add here the Interrupt Handler for the BLE peripheral(s) */
51 /******************************************************************************/
52
53 /**
54 ****************************************************************************************
55 * @brief SVC Interrupt Handler
56 * @retval void
57 ****************************************************************************************
58 */
59 #if defined ( __CC_ARM )
60 #ifndef GR5515_E
SVC_Handler(void)61 SECTION_RAM_CODE __asm void SVC_Handler (void)
62 {
63 PRESERVE8
64 IMPORT SVC_handler_proc
65
66 TST LR, #4 ;
67 Called from Handler Mode?
68 MRSNE R12, PSP ;
69 Yes, use PSP
70 MOVEQ R12, SP ;
71 No, use MSP
72 PUSH {R0-R3, LR}
73 MOV R0, R12
74 BL SVC_handler_proc
75 MOV R12, R0
76 POP {R0-R3, LR}
77 CMP R12, #0
78 BLXNE R12
79 BX LR ;
80 RETI
81 SVC_Dead
82 B SVC_Dead ;
83 None Existing SVC
84 ALIGN
85 }
86 #endif
87 #elif defined ( __GNUC__ )
88 #elif defined (__ICCARM__)
89
SVC_handler_proc(uint32_t * svc_args)90 SECTION_RAM_CODE uint32_t SVC_handler_proc(uint32_t *svc_args)
91 {
92 uint16_t svc_cmd;
93 uint32_t svc_func_addr;
94 uint32_t func_addr = 0;
95 svc_func_addr = svc_args[ITEM_6];
96 svc_cmd = *((uint16_t*)svc_func_addr-1);
97 if ((svc_cmd<=0xDFFF)&&(svc_cmd>=0xDF00)) {
98 func_addr = (uint32_t)SVC_Table[svc_cmd&(0xFF)];
99 return func_addr ;
100 } else {
101 func_addr=get_patch_rep_addr(svc_func_addr);
102 svc_args[ITEM_6] = func_addr;
103 return 0;
104 }
105 }
106
SVC_Handler(void)107 SECTION_RAM_CODE void __attribute__((naked))SVC_Handler (void)
108 {
109 asm volatile (
110 "TST R14,#4\n\t"
111 "IT NE\n\t"
112 "MRSNE R12, PSP\n\t"
113 "IT EQ\n"
114 "MOVEQ R12, SP \n\t"
115 "PUSH {R0-R3,LR} \n\t"
116 "MOV R0, R12 \n\t"
117 "BL SVC_handler_proc \n\t"
118 "MOV R12, R0 \n\t"
119 "POP {R0-R3, LR} \n\t"
120 "CMP R12, #0\n\t"
121 "IT NE\n\t"
122 "BLXNE R12\n\t"
123 "BX LR\n\t");
124 }
125 #endif
126
127 /**
128 ****************************************************************************************
129 * @brief hardfault Interrupt Handler
130 * @retval void
131 ****************************************************************************************
132 */
133 #if defined ( __CC_ARM )
134
cortex_backtrace_fault_handler(void)135 SECTION_RAM_CODE __WEAK void cortex_backtrace_fault_handler(void)
136 {
137 while (1) {}
138 }
139
HardFault_Handler(void)140 SECTION_RAM_CODE __asm void HardFault_Handler (void)
141 {
142 #if SYS_FAULT_TRACE_ENABLE
143 PRESERVE8
144 IMPORT cortex_backtrace_fault_handler
145 MOV r0, lr
146 MOV r1, sp
147 BL cortex_backtrace_fault_handler
148 #endif
149 Fault_Loop
150 BL Fault_Loop
151 ALIGN
152 }
153
154 #if DEBUG_MONITOR
155 uint32_t __R4_R11_REG[8];
print_callstack_handler(uint32_t sp)156 void print_callstack_handler(uint32_t sp)
157 {
158 printf("================================\r\n");
159 printf(" r0: %08x r1: %08x\r\n", ((uint32_t *)sp)[ITEM_0], ((uint32_t *)sp)[ITEM_1]);
160 printf(" r2: %08x r3: %08x\r\n", ((uint32_t *)sp)[ITEM_2], ((uint32_t *)sp)[ITEM_3]);
161 printf(" r4: %08x r5: %08x\r\n", __R4_R11_REG[ITEM_0], __R4_R11_REG[ITEM_1]);
162 printf(" r6: %08x r7: %08x\r\n", __R4_R11_REG[ITEM_2], __R4_R11_REG[ITEM_3]);
163 printf(" r8: %08x r9: %08x\r\n", __R4_R11_REG[ITEM_4], __R4_R11_REG[ITEM_5]);
164 printf(" r10:%08x r11:%08x\r\n", __R4_R11_REG[ITEM_6], __R4_R11_REG[ITEM_7]);
165 printf(" r12:%08x lr: %08x\r\n", ((uint32_t *)sp)[ITEM_4], ((uint32_t *)sp)[ITEM_5]);
166 printf(" pc: %08x xpsr: %08x\r\n", ((uint32_t *)sp)[ITEM_6], ((uint32_t *)sp)[ITEM_7]);
167 printf("================================\r\n");
168 }
169
DebugMon_Handler(void)170 __asm void DebugMon_Handler(void)
171 {
172 PRESERVE8
173 IMPORT print_callstack_handler
174 IMPORT __R4_R11_REG
175 LDR R0, = __R4_R11_REG
176 STMIA R0!, {R4-R11}
177 MOV R0, SP
178 MOV r12, lr
179 BL print_callstack_handler
180 BX r12
181 ALIGN
182 }
183 #endif
184
185 #elif defined ( __GNUC__ )
186
hardfault_trace_handler(unsigned int * args)187 SECTION_RAM_CODE __WEAK void hardfault_trace_handler(unsigned int *args)
188 {
189 while (1) {}
190 }
191
HardFault_Handler(void)192 SECTION_RAM_CODE void __attribute__((naked))HardFault_Handler (void)
193 {
194 __asm("TST LR, #4\n");
195 __asm("ITE EQ\n");
196 __asm("MRSEQ R0, MSP\n");
197 __asm("MRSNE R0, PSP\n");
198 __asm("BL hardfault_trace_handler\n");
199 while (1) {}
200 }
201
202 #endif
203
204 /**
205 ****************************************************************************************
206 * @brief MemManage fault Interrupt Handler
207 * @retval void
208 ****************************************************************************************
209 */
MemManage_Handler(void)210 SECTION_RAM_CODE void MemManage_Handler(void)
211 {
212 while (1) {}
213 }
214
215 /**
216 ****************************************************************************************
217 * @brief Bus Fault Interrupt Handler
218 * @retval void
219 ****************************************************************************************
220 */
BusFault_Handler(void)221 SECTION_RAM_CODE void BusFault_Handler(void)
222 {
223 while (1) {}
224 }
225
226 /**
227 ****************************************************************************************
228 * @brief UsageFault Interrupt Handler
229 * @retval void
230 ****************************************************************************************
231 */
UsageFault_Handler(void)232 SECTION_RAM_CODE void UsageFault_Handler(void)
233 {
234 while (1) {}
235 }
236
237 /**
238 ****************************************************************************************
239 * @brief sleep timer Interrupt Handler
240 * @retval void
241 ****************************************************************************************
242 */
SLPTIMER_IRQHandler(void)243 SECTION_RAM_CODE void SLPTIMER_IRQHandler(void)
244 {
245 hal_pwr_sleep_timer_irq_handler();
246 }
247