| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64InstPrinter.cpp | 1282 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1284 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1286 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 375 unsigned FirstReg = 0; in CreateRegs() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3337 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3354 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3408 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3473 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToFPR() local
4314 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
5174 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
5221 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandStoreDM1Macro() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 505 unsigned FirstReg = 0; in ScanInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2149 unsigned &FirstReg, in CanFormLdStDWord()
2316 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 4307 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4360 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4507 unsigned FirstReg = 0; in HandleByVal() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1512 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3343 unsigned FirstReg; in tryParseVectorList() local
5604 unsigned FirstReg; in tryParseGPRSeqPair() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 1895 const auto FirstReg = in legalizeMov() local
1967 const auto FirstReg = in legalizeMov() local
2054 const auto FirstReg = in legalizeMov() local
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| D | IceTargetLoweringARM32.cpp | 396 const auto FirstReg = in copyRegAllocFromInfWeightVariable64On32() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 855 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 4569 unsigned FirstReg = Reg; in parseVectorList() local
|