1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __HAL_CMU_BEST2003_H__ 16 #define __HAL_CMU_BEST2003_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #ifdef FPGA 23 #define HAL_CMU_DEFAULT_CRYSTAL_FREQ 26000000 24 #define HAL_CMU_VALID_CRYSTAL_FREQ { HAL_CMU_DEFAULT_CRYSTAL_FREQ, } 25 #else 26 #define HAL_CMU_DEFAULT_CRYSTAL_FREQ 24000000 27 #define HAL_CMU_VALID_CRYSTAL_FREQ { 24000000, 40000000, } 28 #endif 29 30 enum HAL_CMU_MOD_ID_T { 31 // HCLK/HRST 32 HAL_CMU_MOD_H_MCU, // 0 33 HAL_CMU_MOD_H_CACHE0, // 1 34 HAL_CMU_MOD_H_CP, // 2 35 HAL_CMU_MOD_H_CACHE1, // 3 36 HAL_CMU_MOD_H_ADMA, // 4 37 HAL_CMU_MOD_H_GDMA, // 5 38 HAL_CMU_MOD_H_SEC_ENG, // 6 39 HAL_CMU_MOD_H_USBC, // 7 40 HAL_CMU_MOD_H_USBH, // 8 41 HAL_CMU_MOD_H_I2C_SLAVE, // 9 42 HAL_CMU_MOD_H_AX2H_A7, // 10 43 HAL_CMU_MOD_H_AH2H_WF, // 11 44 HAL_CMU_MOD_H_AH2H_BT, // 12 45 HAL_CMU_MOD_H_CODEC, // 13 46 HAL_CMU_MOD_H_AHB1, // 14 47 HAL_CMU_MOD_H_AHB0, // 15 48 HAL_CMU_MOD_H_PSRAM1G, // 16 49 HAL_CMU_MOD_H_PSRAM200, // 17 50 HAL_CMU_MOD_H_FLASH, // 18 51 HAL_CMU_MOD_H_RAM5, // 19 52 HAL_CMU_MOD_H_RAM4, // 20 53 HAL_CMU_MOD_H_RAM3, // 21 54 HAL_CMU_MOD_H_RAM2, // 22 55 HAL_CMU_MOD_H_RAM1, // 23 56 HAL_CMU_MOD_H_RAM0, // 24 57 HAL_CMU_MOD_H_ROM0, // 25 58 HAL_CMU_MOD_H_BT_DUMP, // 26 59 HAL_CMU_MOD_H_WF_DUMP, // 27 60 HAL_CMU_MOD_H_SDMMC, // 28 61 HAL_CMU_MOD_H_CHECKSUM, // 29 62 HAL_CMU_MOD_H_CRC, // 30 63 HAL_CMU_MOD_H_FLASH1, // 31 64 // PCLK/PRST 65 HAL_CMU_MOD_P_CMU, // 0 66 HAL_CMU_MOD_P_WDT, // 1 67 HAL_CMU_MOD_P_TIMER0, // 2 68 HAL_CMU_MOD_P_TIMER1, // 3 69 HAL_CMU_MOD_P_TIMER2, // 4 70 HAL_CMU_MOD_P_I2C0, // 5 71 HAL_CMU_MOD_P_I2C1, // 6 72 HAL_CMU_MOD_P_SPI, // 7 73 HAL_CMU_MOD_P_SLCD, // 8 74 HAL_CMU_MOD_P_SPI_ITN, // 9 75 HAL_CMU_MOD_P_SPI_PHY, // 10 76 HAL_CMU_MOD_P_UART0, // 11 77 HAL_CMU_MOD_P_UART1, // 12 78 HAL_CMU_MOD_P_UART2, // 13 79 HAL_CMU_MOD_P_PCM, // 14 80 HAL_CMU_MOD_P_I2S0, // 15 81 HAL_CMU_MOD_P_SPDIF0, // 16 82 HAL_CMU_MOD_P_TRANSQ0, // 17 83 HAL_CMU_MOD_P_TRANSQ1, // 18 84 HAL_CMU_MOD_P_TRNG, // 19 85 HAL_CMU_MOD_P_SEC_ENG, // 20 86 HAL_CMU_MOD_P_TZC, // 21 87 HAL_CMU_MOD_P_IR, // 22 88 HAL_CMU_MOD_P_I2C2, // 23 89 HAL_CMU_MOD_P_UART3, // 24 90 HAL_CMU_MOD_P_I2S1, // 25 91 // OCLK/ORST 92 HAL_CMU_MOD_O_SLEEP, // 0 93 HAL_CMU_MOD_O_USB, // 1 94 HAL_CMU_MOD_O_USB32K, // 2 95 HAL_CMU_MOD_O_PSRAM1G, // 3 96 HAL_CMU_MOD_O_PSRAM200, // 4 97 HAL_CMU_MOD_O_FLASH, // 5 98 HAL_CMU_MOD_O_SDMMC, // 6 99 HAL_CMU_MOD_O_WDT, // 7 100 HAL_CMU_MOD_O_TIMER0, // 8 101 HAL_CMU_MOD_O_TIMER1, // 9 102 HAL_CMU_MOD_O_TIMER2, // 10 103 HAL_CMU_MOD_O_I2C0, // 11 104 HAL_CMU_MOD_O_I2C1, // 12 105 HAL_CMU_MOD_O_SPI, // 13 106 HAL_CMU_MOD_O_SLCD, // 14 107 HAL_CMU_MOD_O_SPI_ITN, // 15 108 HAL_CMU_MOD_O_SPI_PHY, // 16 109 HAL_CMU_MOD_O_UART0, // 17 110 HAL_CMU_MOD_O_UART1, // 18 111 HAL_CMU_MOD_O_UART2, // 19 112 HAL_CMU_MOD_O_PCM, // 20 113 HAL_CMU_MOD_O_I2S0, // 21 114 HAL_CMU_MOD_O_SPDIF0, // 22 115 HAL_CMU_MOD_O_I2S1, // 23 116 HAL_CMU_MOD_O_A7, // 24 117 HAL_CMU_MOD_O_TSF, // 25 118 HAL_CMU_MOD_O_WDT_AP, // 26 119 HAL_CMU_MOD_O_TIMER0_AP, // 27 120 HAL_CMU_MOD_O_TIMER1_AP, // 28 121 HAL_CMU_MOD_O_FLASH1, // 29 122 HAL_CMU_MOD_O_I2C2, // 30 123 HAL_CMU_MOD_O_UART3, // 31 124 // QCLK/QRST 125 HAL_CMU_MOD_Q_NULL, // 0 126 HAL_CMU_MOD_Q_DSI_32K, // 1 127 HAL_CMU_MOD_Q_DSI_PN, // 2 128 HAL_CMU_MOD_Q_DSI_TV, // 3 129 HAL_CMU_MOD_Q_DSI_PIX, // 4 130 HAL_CMU_MOD_Q_DSI_DSI, // 5 131 HAL_CMU_MOD_Q_CSI_LANE, // 6 132 HAL_CMU_MOD_Q_CSI_PIX, // 7 133 HAL_CMU_MOD_Q_CSI_LANG, // 8 134 HAL_CMU_MOD_Q_IR, // 9 135 136 // AON ACLK/ARST 137 HAL_CMU_AON_A_CMU, // 0 138 HAL_CMU_AON_A_GPIO, // 1 139 HAL_CMU_AON_A_GPIO_INT, // 2 140 HAL_CMU_AON_A_WDT, // 3 141 HAL_CMU_AON_A_PWM, // 4 142 HAL_CMU_AON_A_TIMER, // 5 143 HAL_CMU_AON_A_IOMUX, // 6 144 HAL_CMU_AON_A_SPIDPD, // 7 145 HAL_CMU_AON_A_APBC, // 8 146 HAL_CMU_AON_A_H2H_MCU, // 9 147 HAL_CMU_AON_A_PSC, // 10 148 HAL_CMU_AON_A_PWM1, // 11 149 HAL_CMU_AON_A_WLAN_SLEEP, // 12 150 // AON OCLK/ORST 151 HAL_CMU_AON_O_WDT, // 13 152 HAL_CMU_AON_O_TIMER, // 14 153 HAL_CMU_AON_O_GPIO, // 15 154 HAL_CMU_AON_O_PWM0, // 16 155 HAL_CMU_AON_O_PWM1, // 17 156 HAL_CMU_AON_O_PWM2, // 18 157 HAL_CMU_AON_O_PWM3, // 19 158 HAL_CMU_AON_O_IOMUX, // 20 159 HAL_CMU_AON_O_SLP32K, // 21 160 HAL_CMU_AON_O_SLP26M, // 22 161 HAL_CMU_AON_O_SPIDPD, // 23 162 HAL_CMU_AON_O_WLAN32K, // 24 163 HAL_CMU_AON_O_WLAN26M, // 25 164 HAL_CMU_AON_O_BTAON, // 26 165 HAL_CMU_AON_O_PWM4, // 27 166 HAL_CMU_AON_O_PWM5, // 28 167 HAL_CMU_AON_O_PWM6, // 29 168 HAL_CMU_AON_O_PWM7, // 30 169 170 // AON SUBSYS 171 HAL_CMU_AON_A7, // 0 172 HAL_CMU_AON_A7CPU, // 1 173 HAL_CMU_AON_MCU, // 2 174 HAL_CMU_AON_CODEC, // 3 175 HAL_CMU_AON_WF, // 4 176 HAL_CMU_AON_BT, // 5 177 HAL_CMU_AON_MCUCPU, // 6 178 HAL_CMU_AON_WFCPU, // 7 179 HAL_CMU_AON_BTCPU, // 8 180 HAL_CMU_AON_GLOBAL, // 9 181 182 HAL_CMU_MOD_QTY, 183 184 HAL_CMU_MOD_GLOBAL = HAL_CMU_AON_GLOBAL, 185 HAL_CMU_MOD_BT = HAL_CMU_AON_BT, 186 HAL_CMU_MOD_BTCPU = HAL_CMU_AON_BTCPU, 187 HAL_CMU_MOD_WF = HAL_CMU_AON_WF, 188 HAL_CMU_MOD_WFCPU = HAL_CMU_AON_WFCPU, 189 190 HAL_CMU_MOD_P_PWM = HAL_CMU_AON_A_PWM, 191 HAL_CMU_MOD_P_PWM1 = HAL_CMU_AON_A_PWM1, 192 HAL_CMU_MOD_O_PWM0 = HAL_CMU_AON_O_PWM0, 193 HAL_CMU_MOD_O_PWM1 = HAL_CMU_AON_O_PWM1, 194 HAL_CMU_MOD_O_PWM2 = HAL_CMU_AON_O_PWM2, 195 HAL_CMU_MOD_O_PWM3 = HAL_CMU_AON_O_PWM3, 196 HAL_CMU_MOD_O_PWM4 = HAL_CMU_AON_O_PWM4, 197 HAL_CMU_MOD_O_PWM5 = HAL_CMU_AON_O_PWM5, 198 HAL_CMU_MOD_O_PWM6 = HAL_CMU_AON_O_PWM6, 199 HAL_CMU_MOD_O_PWM7 = HAL_CMU_AON_O_PWM7, 200 201 HAL_CMU_H_DCACHE = HAL_CMU_MOD_H_CACHE0, 202 HAL_CMU_H_ICACHE = HAL_CMU_MOD_H_CACHE1, 203 204 HAL_CMU_MOD_P_SPI_DPD = HAL_CMU_AON_A_SPIDPD, 205 HAL_CMU_MOD_O_SPI_DPD = HAL_CMU_AON_O_SPIDPD, 206 HAL_CMU_MOD_H_PSRAM = HAL_CMU_MOD_H_PSRAM200, 207 HAL_CMU_MOD_O_PSRAM = HAL_CMU_MOD_O_PSRAM200, 208 HAL_CMU_MOD_H_PSRAMUHS = HAL_CMU_MOD_H_PSRAM1G, 209 HAL_CMU_MOD_O_PSRAMUHS = HAL_CMU_MOD_O_PSRAM1G, 210 }; 211 212 enum HAL_CMU_CLOCK_OUT_ID_T { 213 HAL_CMU_CLOCK_OUT_AON_32K = 0x00, 214 HAL_CMU_CLOCK_OUT_AON_OSC = 0x01, 215 HAL_CMU_CLOCK_OUT_AON_OSCX2 = 0x02, 216 HAL_CMU_CLOCK_OUT_AON_DIG_OSCX2 = 0x03, 217 HAL_CMU_CLOCK_OUT_AON_DIG_OSCX4 = 0x04, 218 HAL_CMU_CLOCK_OUT_AON_PER = 0x05, 219 HAL_CMU_CLOCK_OUT_AON_USB = 0x06, 220 HAL_CMU_CLOCK_OUT_AON_DCDC0 = 0x07, 221 HAL_CMU_CLOCK_OUT_AON_CHCLK = 0x08, 222 HAL_CMU_CLOCK_OUT_AON_SPDIF0 = 0x09, 223 HAL_CMU_CLOCK_OUT_AON_MCU = 0x0A, 224 HAL_CMU_CLOCK_OUT_AON_FLASH = 0x0B, 225 HAL_CMU_CLOCK_OUT_AON_PSRAM = 0x0C, 226 HAL_CMU_CLOCK_OUT_AON_DDR = 0x0D, 227 HAL_CMU_CLOCK_OUT_AON_A7 = 0x0E, 228 HAL_CMU_CLOCK_OUT_AON_DCDC1 = 0x0F, 229 HAL_CMU_CLOCK_OUT_AON_OSCX4 = 0x10, 230 HAL_CMU_CLOCK_OUT_AON_DSI = 0x11, 231 HAL_CMU_CLOCK_OUT_AON_CSI = 0x12, 232 HAL_CMU_CLOCK_OUT_AON_PIX_DSI = 0x13, 233 HAL_CMU_CLOCK_OUT_AON_PIX_CSI = 0x14, 234 HAL_CMU_CLOCK_OUT_AON_PSRAMX2 = 0x15, 235 HAL_CMU_CLOCK_OUT_AON_DCDC2 = 0x16, 236 HAL_CMU_CLOCK_OUT_AON_SYS = 0x17, 237 238 HAL_CMU_CLOCK_OUT_WF_32K = 0x20, 239 HAL_CMU_CLOCK_OUT_WF_HCLK = 0x21, 240 HAL_CMU_CLOCK_OUT_WF_PCLK = 0x22, 241 HAL_CMU_CLOCK_OUT_WF_MAC = 0x23, 242 HAL_CMU_CLOCK_OUT_WF_PHY = 0x24, 243 HAL_CMU_CLOCK_OUT_WF_OSC = 0x25, 244 HAL_CMU_CLOCK_OUT_WF_40M = 0x26, 245 HAL_CMU_CLOCK_OUT_WF_80M = 0x27, 246 HAL_CMU_CLOCK_OUT_WF_160M = 0x28, 247 HAL_CMU_CLOCK_OUT_WF_UART = 0x29, 248 HAL_CMU_CLOCK_OUT_WF_SPI = 0x2A, 249 HAL_CMU_CLOCK_OUT_WF_SDIO = 0x2B, 250 HAL_CMU_CLOCK_OUT_WF_ADC = 0x2C, 251 HAL_CMU_CLOCK_OUT_WF_TX_DAC = 0x2D, 252 HAL_CMU_CLOCK_OUT_WF_BBDIGFIFO = 0x2E, 253 254 HAL_CMU_CLOCK_OUT_BT_NONE = 0x40, 255 HAL_CMU_CLOCK_OUT_BT_32K = 0x41, 256 HAL_CMU_CLOCK_OUT_BT_SYS = 0x42, 257 HAL_CMU_CLOCK_OUT_BT_OSCX2 = 0x43, 258 HAL_CMU_CLOCK_OUT_BT_OSC_2 = 0x44, 259 HAL_CMU_CLOCK_OUT_BT_ADC = 0x45, 260 HAL_CMU_CLOCK_OUT_BT_ADCD3 = 0x46, 261 HAL_CMU_CLOCK_OUT_BT_DAC = 0x47, 262 HAL_CMU_CLOCK_OUT_BT_DACD2 = 0x48, 263 HAL_CMU_CLOCK_OUT_BT_DACD4 = 0x49, 264 HAL_CMU_CLOCK_OUT_BT_DACD8 = 0x4A, 265 266 HAL_CMU_CLOCK_OUT_MCU_32K = 0x60, 267 HAL_CMU_CLOCK_OUT_MCU_SYS = 0x61, 268 HAL_CMU_CLOCK_OUT_MCU_FLASH = 0x62, 269 HAL_CMU_CLOCK_OUT_MCU_USB = 0x63, 270 HAL_CMU_CLOCK_OUT_MCU_PCLK = 0x64, 271 HAL_CMU_CLOCK_OUT_MCU_I2S0 = 0x65, 272 HAL_CMU_CLOCK_OUT_MCU_PCM = 0x66, 273 HAL_CMU_CLOCK_OUT_MCU_SPDIF0 = 0x67, 274 HAL_CMU_CLOCK_OUT_MCU_SDMMC = 0x68, 275 HAL_CMU_CLOCK_OUT_MCU_SPI2 = 0x69, 276 HAL_CMU_CLOCK_OUT_MCU_SPI0 = 0x6A, 277 HAL_CMU_CLOCK_OUT_MCU_SPI1 = 0x6B, 278 HAL_CMU_CLOCK_OUT_MCU_XCLK = 0x6C, 279 HAL_CMU_CLOCK_OUT_MCU_APCLK = 0x6D, 280 HAL_CMU_CLOCK_OUT_MCU_I2S1 = 0x6E, 281 282 HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA = 0x80, 283 HAL_CMU_CLOCK_OUT_CODEC_CODEC = 0x81, 284 HAL_CMU_CLOCK_OUT_CODEC_IIR = 0x82, 285 HAL_CMU_CLOCK_OUT_CODEC_RS_DAC = 0x83, 286 HAL_CMU_CLOCK_OUT_CODEC_RS_ADC = 0x84, 287 HAL_CMU_CLOCK_OUT_CODEC_HCLK = 0x85, 288 }; 289 290 enum HAL_CMU_I2S_MCLK_ID_T { 291 HAL_CMU_I2S_MCLK_PLLCODEC = 0x00, 292 HAL_CMU_I2S_MCLK_CODEC = 0x01, 293 HAL_CMU_I2S_MCLK_PLLIIR = 0x02, 294 HAL_CMU_I2S_MCLK_PLLRS = 0x03, 295 HAL_CMU_I2S_MCLK_PLLSPDIF0 = 0x04, 296 HAL_CMU_I2S_MCLK_PLLPCM = 0x05, 297 HAL_CMU_I2S_MCLK_PER = 0x06, 298 HAL_CMU_I2S_MCLK_CLK_OUT = 0x07, 299 }; 300 301 enum HAL_PWM_ID_T { 302 HAL_PWM_ID_0, 303 HAL_PWM_ID_1, 304 HAL_PWM_ID_2, 305 HAL_PWM_ID_3, 306 HAL_PWM1_ID_0, 307 HAL_PWM1_ID_1, 308 HAL_PWM1_ID_2, 309 HAL_PWM1_ID_3, 310 311 HAL_PWM_ID_QTY 312 }; 313 #define HAL_PWM_ID_T HAL_PWM_ID_T 314 315 enum HAL_I2S_ID_T { 316 HAL_I2S_ID_0 = 0, 317 HAL_I2S_ID_1, 318 319 HAL_I2S_ID_QTY, 320 }; 321 #define HAL_I2S_ID_T HAL_I2S_ID_T 322 323 enum HAL_CMU_FREQ_T { 324 HAL_CMU_FREQ_32K, 325 HAL_CMU_FREQ_6P5M, 326 HAL_CMU_FREQ_13M, 327 HAL_CMU_FREQ_26M, 328 HAL_CMU_FREQ_52M, 329 HAL_CMU_FREQ_78M, 330 HAL_CMU_FREQ_104M, 331 HAL_CMU_FREQ_156M, 332 HAL_CMU_FREQ_208M, 333 HAL_CMU_FREQ_260M, 334 HAL_CMU_FREQ_390M, 335 HAL_CMU_FREQ_780M, 336 337 HAL_CMU_FREQ_QTY 338 }; 339 #define HAL_CMU_FREQ_T HAL_CMU_FREQ_T 340 #define HAL_CMU_FREQ_390M HAL_CMU_FREQ_390M 341 342 enum HAL_CMU_PLL_T { 343 HAL_CMU_PLL_USB, 344 HAL_CMU_PLL_AUD = HAL_CMU_PLL_USB, 345 HAL_CMU_PLL_DDR, 346 HAL_CMU_PLL_DSP, 347 HAL_CMU_PLL_BB, 348 HAL_CMU_PLL_BB_PSRAM, 349 HAL_CMU_PLL_DSI, 350 351 HAL_CMU_PLL_QTY 352 }; 353 #define HAL_CMU_PLL_T HAL_CMU_PLL_T 354 355 enum HAL_CMU_PLL_USER_T { 356 HAL_CMU_PLL_USER_SYS, 357 HAL_CMU_PLL_USER_AUD, 358 HAL_CMU_PLL_USER_USB, 359 HAL_CMU_PLL_USER_FLASH, 360 HAL_CMU_PLL_USER_PSRAM, 361 HAL_CMU_PLL_USER_DSP, 362 HAL_CMU_PLL_USER_DSI, 363 364 HAL_CMU_PLL_USER_QTY, 365 HAL_CMU_PLL_USER_ALL = HAL_CMU_PLL_USER_QTY, 366 }; 367 #define HAL_CMU_PLL_USER_T HAL_CMU_PLL_USER_T 368 369 #define HAL_CMU_USB_ROM_SELECT_CLOCK_SOURCE 370 371 #define HAL_CMU_SYS_REBOOT 372 373 enum HAL_FLASH0_SIZE_CFG { 374 HAL_FLASH0_SIZE_0M = 0x1, 375 HAL_FLASH0_SIZE_8M = 0x2, 376 HAL_FLASH0_SIZE_16M = 0x0, 377 HAL_FLASH0_SIZE_32M = 0x4, 378 HAL_FLASH0_SIZE_64M = 0x8, 379 }; 380 381 enum HAL_CMU_JTAG_SEL_T { 382 HAL_CMU_JTAG_SEL_MAIN, 383 HAL_CMU_JTAG_SEL_CP, 384 HAL_CMU_JTAG_SEL_A7, 385 386 HAL_CMU_JTAG_SEL_QTY 387 }; 388 389 int hal_cmu_fast_timer_offline(void); 390 391 int hal_cmu_ddr_clock_enable(); 392 393 void hal_cmu_ddr_clock_disable(); 394 395 void hal_cmu_ddr_reset_set(); 396 397 void hal_cmu_ddr_reset_clear(); 398 399 uint32_t hal_cmu_get_aon_chip_id(void); 400 401 uint32_t hal_cmu_get_aon_revision_id(void); 402 403 void hal_cmu_cp_enable(uint32_t sp, uint32_t entry); 404 405 void hal_cmu_cp_disable(void); 406 407 uint32_t hal_cmu_cp_get_entry_addr(void); 408 409 void hal_cmu_wifi_clock_enable(void); 410 411 void hal_cmu_wifi_clock_disable(void); 412 413 void hal_cmu_wifi_reset_set(void); 414 415 void hal_cmu_wifi_reset_clear(void); 416 417 void hal_cmu_dsp_clock_enable(void); 418 419 void hal_cmu_dsp_clock_disable(void); 420 421 void hal_cmu_dsp_reset_set(void); 422 423 void hal_cmu_dsp_reset_clear(void); 424 425 void hal_cmu_dsp_init_boot_reg(uint32_t entry); 426 427 void hal_cmu_dsp_start_cpu(void); 428 429 void hal_cmu_dsp_setup(void); 430 431 void hal_cmu_dsp_stop_cpu(void); 432 433 void hal_cmu_jtag_set_cp(void); 434 435 void hal_cmu_jtag_set_a7(void); 436 437 void hal_cmu_cp_boot(uint32_t entry); 438 439 void hal_cmu_jtag_sel(enum HAL_CMU_JTAG_SEL_T sel); 440 441 void hal_cmu_dma_req_init(void); 442 443 void hal_cmu_flash0_dual_die(); 444 445 void hal_cmu_set_flash0_x8_mode(uint32_t en); 446 447 void hal_cmu_set_flash0_size(enum HAL_FLASH0_SIZE_CFG cfg); 448 449 void hal_cmu_flash1_enable(); 450 451 void hal_cmu_wlan_set_sleep_allow(uint32_t auto_mode); 452 453 uint32_t hal_cmu_get_osc_ready_cycle_cnt(void); 454 455 uint32_t hal_cmu_get_osc_switch_overhead(void); 456 457 void hal_cmu_dsi_clock_enable(void); 458 459 void hal_cmu_dsi_clock_enable_v2(uint8_t pixel_div); 460 461 void hal_cmu_dsi_clock_disable(void); 462 463 void hal_cmu_dsi_reset_set(void); 464 465 void hal_cmu_dsi_reset_clear(void); 466 467 void hal_cmu_csi_clock_enable(void); 468 469 void hal_cmu_csi_clock_disable(void); 470 471 void hal_cmu_csi_reset_set(void); 472 473 void hal_cmu_csi_reset_clear(void); 474 475 void hal_cmu_lcdc_clock_enable(void); 476 477 void hal_cmu_lcdc_clock_disable(void); 478 479 void hal_cmu_lcdc_reset_set(void); 480 481 void hal_cmu_lcdc_reset_clear(void); 482 483 void hal_cmu_shutdown_hook(void); 484 485 #ifdef __cplusplus 486 } 487 #endif 488 489 #endif 490 491