1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __REG_DMA_H__ 16 #define __REG_DMA_H__ 17 18 #include "plat_types.h" 19 #include "stdint.h" 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 // Number of channels on GPDMA and AUDMA 26 #define DMA_NUMBER_CHANNELS 8 27 28 // DMA Channel register block structure 29 struct DMA_CH_T { 30 __IO uint32_t SRCADDR; // 0x100+N*0x20 DMA Channel Source Address Register 31 __IO uint32_t DSTADDR; // 0x104+N*0x20 DMA Channel Destination Address Register 32 __IO uint32_t LLI; // 0x108+N*0x20 DMA Channel Linked List Item Register 33 __IO uint32_t CONTROL; // 0x10C+N*0x20 DMA Channel Control Register 34 __IO uint32_t CONFIG; // 0x110+N*0x20 DMA Channel Configuration Register 35 uint32_t RESERVED1[3]; // 0x114+N*0x20 36 }; 37 38 struct DMA_2D_CFG_T { 39 __IO uint32_t SRCX; // 0x200+N*0x20 DMA 2D Source X Axis Register 40 __IO uint32_t SRCY; // 0x204+N*0x20 DMA 2D Source Y Axis Register 41 __IO uint32_t DSTX; // 0x208+N*0x20 DMA 2D Destination X Axis Register 42 __IO uint32_t DSTY; // 0x20C+N*0x20 DMA 2D Destination Y Axis Register 43 __IO uint32_t CTRL; // 0x210+N*0x20 DMA 2D Control Register 44 __IO uint32_t SRC_INC; // 0x214+N*0x20 DMA source address increment (signed value) in burst mode 45 __IO uint32_t DST_INC; // 0x218+N*0x20 DMA destination address increment (signed value) in burst mode 46 uint32_t RESERVED2; // 0x21C+N*0x20 47 }; 48 49 // DMA register block 50 struct DMA_T { 51 __I uint32_t INTSTAT; // 0x000 DMA Interrupt Status Register 52 __I uint32_t INTTCSTAT; // 0x004 DMA Interrupt Terminal Count Request Status Register 53 __O uint32_t INTTCCLR; // 0x008 DMA Interrupt Terminal Count Request Clear Register 54 __I uint32_t INTERRSTAT; // 0x00C DMA Interrupt Error Status Register 55 __O uint32_t INTERRCLR; // 0x010 DMA Interrupt Error Clear Register 56 __I uint32_t RAWINTTCSTAT; // 0x014 DMA Raw Interrupt Terminal Count Status Register 57 __I uint32_t RAWINTERRSTAT; // 0x018 DMA Raw Error Interrupt Status Register 58 __I uint32_t ENBLDCHNS; // 0x01C DMA Enabled Channel Register 59 __IO uint32_t SOFTBREQ; // 0x020 DMA Software Burst Request Register 60 __IO uint32_t SOFTSREQ; // 0x024 DMA Software Single Request Register 61 __IO uint32_t SOFTLBREQ; // 0x028 DMA Software Last Burst Request Register 62 __IO uint32_t SOFTLSREQ; // 0x02C DMA Software Last Single Request Register 63 __IO uint32_t DMACONFIG; // 0x030 DMA Configuration Register 64 __IO uint32_t SYNC; // 0x034 DMA Synchronization Register 65 uint32_t RESERVED0[50]; // 0x038 66 struct DMA_CH_T CH[DMA_NUMBER_CHANNELS]; // 0x100 67 struct DMA_2D_CFG_T _2D[DMA_NUMBER_CHANNELS]; // 0x200 68 }; 69 70 // Macro defines for DMA channel control registers 71 72 #define DMA_CONTROL_TRANSFERSIZE(n) ((((n) & 0xFFF) << 0)) // Transfer size 73 #define DMA_CONTROL_TRANSFERSIZE_MASK (0xFFF << 0) 74 #define DMA_CONTROL_TRANSFERSIZE_SHIFT (0) 75 #define DMA_CONTROL_SBSIZE(n) ((((n) & 0x07) << 12)) // Source burst size 76 #define DMA_CONTROL_DBSIZE(n) ((((n) & 0x07) << 15)) // Destination burst size 77 #define DMA_CONTROL_SWIDTH(n) ((((n) & 0x07) << 18)) // Source transfer width 78 #define DMA_CONTROL_SWIDTH_MASK (0x07 << 18) 79 #define DMA_CONTROL_SWIDTH_SHIFT (18) 80 #define DMA_CONTROL_DWIDTH(n) ((((n) & 0x07) << 21)) // Destination transfer width 81 #define DMA_CONTROL_BURST_SI ((1UL << 24)) // Source increment in burst mode 82 #define DMA_CONTROL_BURST_DI ((1UL << 25)) // Destination increment in burst mode 83 #define DMA_CONTROL_SI ((1UL << 26)) // Source increment 84 #define DMA_CONTROL_DI ((1UL << 27)) // Destination increment 85 #define DMA_CONTROL_SRCAHB1 0 86 #define DMA_CONTROL_DSTAHB1 0 87 #define DMA_CONTROL_PROT1 ((1UL << 28)) // Indicates that the access is in user mode or privileged mode 88 #define DMA_CONTROL_PROT2 ((1UL << 29)) // Indicates that the access is bufferable or not bufferable 89 #define DMA_CONTROL_PROT3 ((1UL << 30)) // Indicates that the access is cacheable or not cacheable 90 #define DMA_CONTROL_TC_IRQ ((1UL << 31)) // Terminal count interrupt enable bit 91 92 // Macro defines for DMA Channel Configuration registers 93 94 #define DMA_CONFIG_EN ((1UL << 0)) // DMA control enable 95 #define DMA_CONFIG_SRCPERIPH(n) ((((n) & 0x1F) << 1)) // Source peripheral 96 #define DMA_CONFIG_DSTPERIPH(n) ((((n) & 0x1F) << 6)) // Destination peripheral 97 #define DMA_CONFIG_TRANSFERTYPE(n) ((((n) & 0x7) << 11)) // This value indicates the type of transfer 98 #define DMA_CONFIG_ERR_IRQMASK ((1UL << 14)) // Interrupt error mask 99 #define DMA_CONFIG_TC_IRQMASK ((1UL << 15)) // Terminal count interrupt mask 100 #define DMA_CONFIG_LOCK ((1UL << 16)) // Lock 101 #define DMA_CONFIG_ACTIVE ((1UL << 17)) // Active 102 #define DMA_CONFIG_HALT ((1UL << 18)) // Halt 103 #define DMA_CONFIG_TRY_BURST ((1UL << 19)) // Try burst 104 105 #define DMA_STAT_CHAN(n) ((1 << (n)) & 0xFF) 106 #define DMA_STAT_CHAN_ALL (0xFF) 107 108 // Macro defines for DMA Configuration register 109 110 #define DMA_DMACONFIG_EN (1 << 0) // DMA Controller enable 111 #define DMA_DMACONFIG_AHB1_BIGENDIAN (1 << 1) // AHB Master endianness configuration 112 #define DMA_DMACONFIG_AHB2_BIGENDIAN (1 << 2) // AHB Master endianness configuration 113 #define DMA_DMACONFIG_CROSS_1KB_EN (1 << 3) 114 #define DMA_DMACONFIG_TC_IRQ_EN(n) (((n) & 0xFF) << 4) 115 #define DMA_DMACONFIG_TC_IRQ_EN_MASK (0xFF << 4) 116 #define DMA_DMACONFIG_TC_IRQ_EN_SHIFT (4) 117 118 #define DMA_DMACONFIG_CLK_EN_SHIFT 12 119 #define DMA_DMACONFIG_CLK_EN_MASK (0xFF << DMA_DMACONFIG_CLK_EN_SHIFT) 120 #define DMA_DMACONFIG_CLK_EN(n) BITFIELD_VAL(DMA_DMACONFIG_CLK_EN, n) 121 122 // Macro defines for DMA 2D Configuration registers 123 124 #define DMA_2D_MODIFY_SHIFT 11 125 #define DMA_2D_MODIFY_MASK (0x1FFFFF << DMA_2D_MODIFY_SHIFT) 126 #define DMA_2D_MODIFY(n) BITFIELD_VAL(DMA_2D_MODIFY, n) 127 #define DMA_2D_COUNT_SHIFT 0 128 #define DMA_2D_COUNT_MASK (0x7FF << DMA_2D_COUNT_SHIFT) 129 #define DMA_2D_COUNT(n) BITFIELD_VAL(DMA_2D_COUNT, n) 130 131 #define DMA_2D_CTRL_DST_EN (1 << 1) 132 #define DMA_2D_CTRL_SRC_EN (1 << 0) 133 134 // Macro defines for DMA Burst Address Inc registers 135 136 #define DMA_BURST_SRC_INC_VAL_SHIFT 0 137 #define DMA_BURST_SRC_INC_VAL_MASK (0xFFFF << DMA_BURST_SRC_INC_VAL_SHIFT) 138 #define DMA_BURST_SRC_INC_VAL(n) BITFIELD_VAL(DMA_BURST_SRC_INC_VAL, n) 139 #define DMA_BURST_DST_INC_VAL_SHIFT 0 140 #define DMA_BURST_DST_INC_VAL_MASK (0xFFFF << DMA_BURST_DST_INC_VAL_SHIFT) 141 #define DMA_BURST_DST_INC_VAL(n) BITFIELD_VAL(DMA_BURST_DST_INC_VAL, n) 142 143 #ifdef __cplusplus 144 } 145 #endif 146 147 #endif 148 149