1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018-2019 NXP 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 */ 7 8 #ifndef _ASM_ARCH_IMX8MM_CLOCK_H 9 #define _ASM_ARCH_IMX8MM_CLOCK_H 10 11 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ 12 { \ 13 .rate = (_rate), \ 14 .mdiv = (_m), \ 15 .pdiv = (_p), \ 16 .sdiv = (_s), \ 17 .kdiv = (_k), \ 18 } 19 20 #define LOCK_STATUS BIT(31) 21 #define LOCK_SEL_MASK BIT(29) 22 #define CLKE_MASK BIT(11) 23 #define RST_MASK BIT(9) 24 #define BYPASS_MASK BIT(4) 25 #define MDIV_SHIFT 12 26 #define MDIV_MASK GENMASK(21, 12) 27 #define PDIV_SHIFT 4 28 #define PDIV_MASK GENMASK(9, 4) 29 #define SDIV_SHIFT 0 30 #define SDIV_MASK GENMASK(2, 0) 31 #define KDIV_SHIFT 0 32 #define KDIV_MASK GENMASK(15, 0) 33 34 struct imx_int_pll_rate_table { 35 u32 rate; 36 int mdiv; 37 int pdiv; 38 int sdiv; 39 int kdiv; 40 }; 41 42 enum pll_clocks { 43 ANATOP_ARM_PLL, 44 ANATOP_VPU_PLL, 45 ANATOP_GPU_PLL, 46 ANATOP_SYSTEM_PLL1, 47 ANATOP_SYSTEM_PLL2, 48 ANATOP_SYSTEM_PLL3, 49 ANATOP_AUDIO_PLL1, 50 ANATOP_AUDIO_PLL2, 51 ANATOP_VIDEO_PLL, 52 ANATOP_DRAM_PLL, 53 }; 54 55 #ifdef CONFIG_IMX8MN 56 enum clk_root_index { 57 ARM_A53_CLK_ROOT = 0, 58 ARM_M7_CLK_ROOT = 1, 59 GPU_CORE_CLK_ROOT = 3, 60 GPU_SHADER_CLK_ROOT = 4, 61 MAIN_AXI_CLK_ROOT = 16, 62 ENET_AXI_CLK_ROOT = 17, 63 NAND_USDHC_BUS_CLK_ROOT = 18, 64 DISPLAY_AXI_CLK_ROOT = 20, 65 DISPLAY_APB_CLK_ROOT = 21, 66 USB_BUS_CLK_ROOT = 23, 67 GPU_AXI_CLK_ROOT = 24, 68 GPU_AHB_CLK_ROOT = 25, 69 NOC_CLK_ROOT = 26, 70 AHB_CLK_ROOT = 32, 71 IPG_CLK_ROOT = 33, 72 AUDIO_AHB_CLK_ROOT = 34, 73 DRAM_SEL_CFG = 48, 74 CORE_SEL_CFG = 49, 75 DRAM_ALT_CLK_ROOT = 64, 76 DRAM_APB_CLK_ROOT = 65, 77 DISPLAY_PIXEL_CLK_ROOT = 74, 78 SAI2_CLK_ROOT = 76, 79 SAI3_CLK_ROOT = 77, 80 SAI5_CLK_ROOT = 79, 81 SAI6_CLK_ROOT = 80, 82 SPDIF1_CLK_ROOT = 81, 83 ENET_REF_CLK_ROOT = 83, 84 ENET_TIMER_CLK_ROOT = 84, 85 ENET_PHY_REF_CLK_ROOT = 85, 86 NAND_CLK_ROOT = 86, 87 QSPI_CLK_ROOT = 87, 88 USDHC1_CLK_ROOT = 88, 89 USDHC2_CLK_ROOT = 89, 90 I2C1_CLK_ROOT = 90, 91 I2C2_CLK_ROOT = 91, 92 I2C3_CLK_ROOT = 92, 93 I2C4_CLK_ROOT = 93, 94 UART1_CLK_ROOT = 94, 95 UART2_CLK_ROOT = 95, 96 UART3_CLK_ROOT = 96, 97 UART4_CLK_ROOT = 97, 98 USB_CORE_REF_CLK_ROOT = 98, 99 USB_PHY_REF_CLK_ROOT = 99, 100 GIC_CLK_ROOT = 100, 101 ECSPI1_CLK_ROOT = 101, 102 ECSPI2_CLK_ROOT = 102, 103 PWM1_CLK_ROOT = 103, 104 PWM2_CLK_ROOT = 104, 105 PWM3_CLK_ROOT = 105, 106 PWM4_CLK_ROOT = 106, 107 GPT1_CLK_ROOT = 107, 108 GPT2_CLK_ROOT = 108, 109 GPT3_CLK_ROOT = 109, 110 GPT4_CLK_ROOT = 110, 111 GPT5_CLK_ROOT = 111, 112 GPT6_CLK_ROOT = 112, 113 TRACE_CLK_ROOT = 113, 114 WDOG_CLK_ROOT = 114, 115 WRCLK_CLK_ROOT = 115, 116 IPP_DO_CLKO1 = 116, 117 IPP_DO_CLKO2 = 117, 118 MIPI_DSI_CORE_CLK_ROOT = 118, 119 DISPLAY_DSI_PHY_REF_CLK_ROOT = 119, 120 MIPI_DSI_DBI_CLK_ROOT = 120, 121 USDHC3_CLK_ROOT = 121, 122 DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122, 123 MIPI_CSI1_PHY_REF_CLK_ROOT = 123, 124 MIPI_CSI2_PHY_REF_CLK_ROOT = 126, 125 MIPI_CSI2_ESC_CLK_ROOT = 127, 126 ECSPI3_CLK_ROOT = 131, 127 PDM_CLK_ROOT = 132, 128 SAI7_CLK_ROOT = 134, 129 CLK_ROOT_MAX, 130 }; 131 #else 132 enum clk_root_index { 133 ARM_A53_CLK_ROOT = 0, 134 ARM_M4_CLK_ROOT = 1, 135 VPU_A53_CLK_ROOT = 2, 136 GPU3D_CLK_ROOT = 3, 137 GPU2D_CLK_ROOT = 4, 138 MAIN_AXI_CLK_ROOT = 16, 139 ENET_AXI_CLK_ROOT = 17, 140 NAND_USDHC_BUS_CLK_ROOT = 18, 141 VPU_BUS_CLK_ROOT = 19, 142 DISPLAY_AXI_CLK_ROOT = 20, 143 DISPLAY_APB_CLK_ROOT = 21, 144 DISPLAY_RTRM_CLK_ROOT = 22, 145 USB_BUS_CLK_ROOT = 23, 146 GPU_AXI_CLK_ROOT = 24, 147 GPU_AHB_CLK_ROOT = 25, 148 NOC_CLK_ROOT = 26, 149 NOC_APB_CLK_ROOT = 27, 150 AHB_CLK_ROOT = 32, 151 IPG_CLK_ROOT = 33, 152 AUDIO_AHB_CLK_ROOT = 34, 153 MIPI_DSI_ESC_RX_CLK_ROOT = 36, 154 DRAM_SEL_CFG = 48, 155 CORE_SEL_CFG = 49, 156 DRAM_ALT_CLK_ROOT = 64, 157 DRAM_APB_CLK_ROOT = 65, 158 VPU_G1_CLK_ROOT = 66, 159 VPU_G2_CLK_ROOT = 67, 160 DISPLAY_DTRC_CLK_ROOT = 68, 161 DISPLAY_DC8000_CLK_ROOT = 69, 162 PCIE_CTRL_CLK_ROOT = 70, 163 PCIE_PHY_CLK_ROOT = 71, 164 PCIE_AUX_CLK_ROOT = 72, 165 DC_PIXEL_CLK_ROOT = 73, 166 LCDIF_PIXEL_CLK_ROOT = 74, 167 SAI1_CLK_ROOT = 75, 168 SAI2_CLK_ROOT = 76, 169 SAI3_CLK_ROOT = 77, 170 SAI4_CLK_ROOT = 78, 171 SAI5_CLK_ROOT = 79, 172 SAI6_CLK_ROOT = 80, 173 SPDIF1_CLK_ROOT = 81, 174 SPDIF2_CLK_ROOT = 82, 175 ENET_REF_CLK_ROOT = 83, 176 ENET_TIMER_CLK_ROOT = 84, 177 ENET_PHY_REF_CLK_ROOT = 85, 178 NAND_CLK_ROOT = 86, 179 QSPI_CLK_ROOT = 87, 180 USDHC1_CLK_ROOT = 88, 181 USDHC2_CLK_ROOT = 89, 182 I2C1_CLK_ROOT = 90, 183 I2C2_CLK_ROOT = 91, 184 I2C3_CLK_ROOT = 92, 185 I2C4_CLK_ROOT = 93, 186 UART1_CLK_ROOT = 94, 187 UART2_CLK_ROOT = 95, 188 UART3_CLK_ROOT = 96, 189 UART4_CLK_ROOT = 97, 190 USB_CORE_REF_CLK_ROOT = 98, 191 USB_PHY_REF_CLK_ROOT = 99, 192 GIC_CLK_ROOT = 100, 193 ECSPI1_CLK_ROOT = 101, 194 ECSPI2_CLK_ROOT = 102, 195 PWM1_CLK_ROOT = 103, 196 PWM2_CLK_ROOT = 104, 197 PWM3_CLK_ROOT = 105, 198 PWM4_CLK_ROOT = 106, 199 GPT1_CLK_ROOT = 107, 200 GPT2_CLK_ROOT = 108, 201 GPT3_CLK_ROOT = 109, 202 GPT4_CLK_ROOT = 110, 203 GPT5_CLK_ROOT = 111, 204 GPT6_CLK_ROOT = 112, 205 TRACE_CLK_ROOT = 113, 206 WDOG_CLK_ROOT = 114, 207 WRCLK_CLK_ROOT = 115, 208 IPP_DO_CLKO1 = 116, 209 IPP_DO_CLKO2 = 117, 210 MIPI_DSI_CORE_CLK_ROOT = 118, 211 MIPI_DSI_PHY_REF_CLK_ROOT = 119, 212 MIPI_DSI_DBI_CLK_ROOT = 120, 213 USDHC3_CLK_ROOT = 121, 214 MIPI_CSI1_CORE_CLK_ROOT = 122, 215 MIPI_CSI1_PHY_REF_CLK_ROOT = 123, 216 MIPI_CSI1_ESC_CLK_ROOT = 124, 217 MIPI_CSI2_CORE_CLK_ROOT = 125, 218 MIPI_CSI2_PHY_REF_CLK_ROOT = 126, 219 MIPI_CSI2_ESC_CLK_ROOT = 127, 220 PCIE2_CTRL_CLK_ROOT = 128, 221 PCIE2_PHY_CLK_ROOT = 129, 222 PCIE2_AUX_CLK_ROOT = 130, 223 ECSPI3_CLK_ROOT = 131, 224 PDM_CLK_ROOT = 132, 225 VPU_H1_CLK_ROOT = 133, 226 CLK_ROOT_MAX, 227 }; 228 #endif 229 230 enum clk_root_src { 231 OSC_24M_CLK, 232 ARM_PLL_CLK, 233 DRAM_PLL1_CLK, 234 VIDEO_PLL2_CLK, 235 VPU_PLL_CLK, 236 GPU_PLL_CLK, 237 SYSTEM_PLL1_800M_CLK, 238 SYSTEM_PLL1_400M_CLK, 239 SYSTEM_PLL1_266M_CLK, 240 SYSTEM_PLL1_200M_CLK, 241 SYSTEM_PLL1_160M_CLK, 242 SYSTEM_PLL1_133M_CLK, 243 SYSTEM_PLL1_100M_CLK, 244 SYSTEM_PLL1_80M_CLK, 245 SYSTEM_PLL1_40M_CLK, 246 SYSTEM_PLL2_1000M_CLK, 247 SYSTEM_PLL2_500M_CLK, 248 SYSTEM_PLL2_333M_CLK, 249 SYSTEM_PLL2_250M_CLK, 250 SYSTEM_PLL2_200M_CLK, 251 SYSTEM_PLL2_166M_CLK, 252 SYSTEM_PLL2_125M_CLK, 253 SYSTEM_PLL2_100M_CLK, 254 SYSTEM_PLL2_50M_CLK, 255 SYSTEM_PLL3_CLK, 256 AUDIO_PLL1_CLK, 257 AUDIO_PLL2_CLK, 258 VIDEO_PLL_CLK, 259 OSC_32K_CLK, 260 EXT_CLK_1, 261 EXT_CLK_2, 262 EXT_CLK_3, 263 EXT_CLK_4, 264 OSC_HDMI_CLK 265 }; 266 267 enum clk_ccgr_index { 268 CCGR_DVFS = 0, 269 CCGR_ANAMIX = 1, 270 CCGR_CPU = 2, 271 CCGR_CSU = 3, 272 CCGR_DEBUG = 4, 273 CCGR_DDR1 = 5, 274 CCGR_ECSPI1 = 7, 275 CCGR_ECSPI2 = 8, 276 CCGR_ECSPI3 = 9, 277 CCGR_ENET1 = 10, 278 CCGR_GPIO1 = 11, 279 CCGR_GPIO2 = 12, 280 CCGR_GPIO3 = 13, 281 CCGR_GPIO4 = 14, 282 CCGR_GPIO5 = 15, 283 CCGR_GPT1 = 16, 284 CCGR_GPT2 = 17, 285 CCGR_GPT3 = 18, 286 CCGR_GPT4 = 19, 287 CCGR_GPT5 = 20, 288 CCGR_GPT6 = 21, 289 CCGR_HS = 22, 290 CCGR_I2C1 = 23, 291 CCGR_I2C2 = 24, 292 CCGR_I2C3 = 25, 293 CCGR_I2C4 = 26, 294 CCGR_IOMUX = 27, 295 CCGR_IOMUX1 = 28, 296 CCGR_IOMUX2 = 29, 297 CCGR_IOMUX3 = 30, 298 CCGR_IOMUX4 = 31, 299 CCGR_SNVSMIX_IPG_CLK = 32, 300 CCGR_MU = 33, 301 CCGR_OCOTP = 34, 302 CCGR_OCRAM = 35, 303 CCGR_OCRAM_S = 36, 304 CCGR_PCIE = 37, 305 CCGR_PERFMON1 = 38, 306 CCGR_PERFMON2 = 39, 307 CCGR_PWM1 = 40, 308 CCGR_PWM2 = 41, 309 CCGR_PWM3 = 42, 310 CCGR_PWM4 = 43, 311 CCGR_QOS = 44, 312 CCGR_QOS_DISPMIX = 45, 313 CCGR_QOS_ETHENET = 46, 314 CCGR_QSPI = 47, 315 CCGR_RAWNAND = 48, 316 CCGR_RDC = 49, 317 CCGR_ROM = 50, 318 CCGR_SAI1 = 51, 319 CCGR_SAI2 = 52, 320 CCGR_SAI3 = 53, 321 CCGR_SAI4 = 54, 322 CCGR_SAI5 = 55, 323 CCGR_SAI6 = 56, 324 CCGR_SCTR = 57, 325 CCGR_SDMA1 = 58, 326 CCGR_SDMA2 = 59, 327 CCGR_SEC_DEBUG = 60, 328 CCGR_SEMA1 = 61, 329 CCGR_SEMA2 = 62, 330 CCGR_SIM_DISPLAY = 63, 331 CCGR_SIM_ENET = 64, 332 CCGR_SIM_M = 65, 333 CCGR_SIM_MAIN = 66, 334 CCGR_SIM_S = 67, 335 CCGR_SIM_WAKEUP = 68, 336 CCGR_SIM_HSIO = 69, 337 CCGR_SIM_VPU = 70, 338 CCGR_SNVS = 71, 339 CCGR_TRACE = 72, 340 CCGR_UART1 = 73, 341 CCGR_UART2 = 74, 342 CCGR_UART3 = 75, 343 CCGR_UART4 = 76, 344 CCGR_USB_MSCALE_PL301 = 77, 345 CCGR_GPU3D = 79, 346 CCGR_USDHC1 = 81, 347 CCGR_USDHC2 = 82, 348 CCGR_WDOG1 = 83, 349 CCGR_WDOG2 = 84, 350 CCGR_WDOG3 = 85, 351 CCGR_VPUG1 = 86, 352 CCGR_GPU_BUS = 87, 353 CCGR_VPUH1 = 89, 354 CCGR_VPUG2 = 90, 355 CCGR_PDM = 91, 356 CCGR_GIC = 92, 357 CCGR_DISPMIX = 93, 358 CCGR_USDHC3 = 94, 359 CCGR_SDMA3 = 95, 360 CCGR_XTAL = 96, 361 CCGR_PLL = 97, 362 CCGR_TEMP_SENSOR = 98, 363 CCGR_VPUMIX_BUS = 99, 364 CCGR_GPU2D = 102, 365 CCGR_MAX 366 }; 367 368 enum clk_src_index { 369 CLK_SRC_CKIL_SYNC_REQ = 0, 370 CLK_SRC_ARM_PLL_EN = 1, 371 CLK_SRC_GPU_PLL_EN = 2, 372 CLK_SRC_VPU_PLL_EN = 3, 373 CLK_SRC_DRAM_PLL_EN = 4, 374 CLK_SRC_SYSTEM_PLL1_EN = 5, 375 CLK_SRC_SYSTEM_PLL2_EN = 6, 376 CLK_SRC_SYSTEM_PLL3_EN = 7, 377 CLK_SRC_AUDIO_PLL1_EN = 8, 378 CLK_SRC_AUDIO_PLL2_EN = 9, 379 CLK_SRC_VIDEO_PLL1_EN = 10, 380 CLK_SRC_RESERVED = 11, 381 CLK_SRC_ARM_PLL = 12, 382 CLK_SRC_GPU_PLL = 13, 383 CLK_SRC_VPU_PLL = 14, 384 CLK_SRC_DRAM_PLL = 15, 385 CLK_SRC_SYSTEM_PLL1_800M = 16, 386 CLK_SRC_SYSTEM_PLL1_400M = 17, 387 CLK_SRC_SYSTEM_PLL1_266M = 18, 388 CLK_SRC_SYSTEM_PLL1_200M = 19, 389 CLK_SRC_SYSTEM_PLL1_160M = 20, 390 CLK_SRC_SYSTEM_PLL1_133M = 21, 391 CLK_SRC_SYSTEM_PLL1_100M = 22, 392 CLK_SRC_SYSTEM_PLL1_80M = 23, 393 CLK_SRC_SYSTEM_PLL1_40M = 24, 394 CLK_SRC_SYSTEM_PLL2_1000M = 25, 395 CLK_SRC_SYSTEM_PLL2_500M = 26, 396 CLK_SRC_SYSTEM_PLL2_333M = 27, 397 CLK_SRC_SYSTEM_PLL2_250M = 28, 398 CLK_SRC_SYSTEM_PLL2_200M = 29, 399 CLK_SRC_SYSTEM_PLL2_166M = 30, 400 CLK_SRC_SYSTEM_PLL2_125M = 31, 401 CLK_SRC_SYSTEM_PLL2_100M = 32, 402 CLK_SRC_SYSTEM_PLL2_50M = 33, 403 CLK_SRC_SYSTEM_PLL3 = 34, 404 CLK_SRC_AUDIO_PLL1 = 35, 405 CLK_SRC_AUDIO_PLL2 = 36, 406 CLK_SRC_VIDEO_PLL1 = 37, 407 }; 408 409 #define INTPLL_LOCK_MASK BIT(31) 410 #define INTPLL_LOCK_SEL_MASK BIT(29) 411 #define INTPLL_EXT_BYPASS_MASK BIT(28) 412 #define INTPLL_DIV20_CLKE_MASK BIT(27) 413 #define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26) 414 #define INTPLL_DIV10_CLKE_MASK BIT(25) 415 #define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24) 416 #define INTPLL_DIV8_CLKE_MASK BIT(23) 417 #define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22) 418 #define INTPLL_DIV6_CLKE_MASK BIT(21) 419 #define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20) 420 #define INTPLL_DIV5_CLKE_MASK BIT(19) 421 #define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18) 422 #define INTPLL_DIV4_CLKE_MASK BIT(17) 423 #define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16) 424 #define INTPLL_DIV3_CLKE_MASK BIT(15) 425 #define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14) 426 #define INTPLL_DIV2_CLKE_MASK BIT(13) 427 #define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12) 428 #define INTPLL_CLKE_MASK BIT(11) 429 #define INTPLL_CLKE_OVERRIDE_MASK BIT(10) 430 #define INTPLL_RST_MASK BIT(9) 431 #define INTPLL_RST_OVERRIDE_MASK BIT(8) 432 #define INTPLL_BYPASS_MASK BIT(4) 433 #define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2) 434 #define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0) 435 436 #define INTPLL_MAIN_DIV_MASK GENMASK(21, 12) 437 #define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12)) 438 #define INTPLL_MAIN_DIV_SHIFT 12 439 #define INTPLL_PRE_DIV_MASK GENMASK(9, 4) 440 #define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4)) 441 #define INTPLL_PRE_DIV_SHIFT 4 442 #define INTPLL_POST_DIV_MASK GENMASK(2, 0) 443 #define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0)) 444 #define INTPLL_POST_DIV_SHIFT 0 445 446 #define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4) 447 #define INTPLL_LOCK_CON_DLY_SHIFT 4 448 #define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2) 449 #define INTPLL_LOCK_CON_OUT_SHIFT 2 450 #define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0) 451 #define INTPLL_LOCK_CON_IN_SHIFT 0 452 453 #define INTPLL_LRD_EN_MASK BIT(21) 454 #define INTPLL_FOUT_MASK BIT(20) 455 #define INTPLL_AFC_SEL_MASK BIT(19) 456 #define INTPLL_PBIAS_CTRL_MASK BIT(18) 457 #define INTPLL_PBIAS_CTRL_EN_MASK BIT(17) 458 #define INTPLL_AFCINIT_SEL_MASK BIT(16) 459 #define INTPLL_FSEL_MASK BIT(14) 460 #define INTPLL_FEED_EN_MASK BIT(13) 461 #define INTPLL_EXTAFC_MASK GENMASK(7, 3) 462 #define INTPLL_AFC_EN_MASK BIT(2) 463 #define INTPLL_ICP_MASK GENMASK(1, 0) 464 465 #endif 466