1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2008,2010 Freescale Semiconductor, Inc
4 * Andy Fleming
5 *
6 * Based (loosely) on the Linux code
7 */
8
9 #ifndef _MMC_H_
10 #define _MMC_H_
11
12 #include <linux/list.h>
13 #include <linux/sizes.h>
14 #include <linux/compiler.h>
15 #include <part.h>
16
17 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
18 #define MMC_SUPPORTS_TUNING
19 #endif
20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
21 #define MMC_SUPPORTS_TUNING
22 #endif
23
24 /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
25 #define SD_VERSION_SD (1U << 31)
26 #define MMC_VERSION_MMC (1U << 30)
27
28 #define MAKE_SDMMC_VERSION(a, b, c) \
29 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
30 #define MAKE_SD_VERSION(a, b, c) \
31 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
32 #define MAKE_MMC_VERSION(a, b, c) \
33 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
34
35 #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
36 (((u32)(x) >> 16) & 0xff)
37 #define EXTRACT_SDMMC_MINOR_VERSION(x) \
38 (((u32)(x) >> 8) & 0xff)
39 #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
40 ((u32)(x) & 0xff)
41
42 #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
43 #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
44 #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
45 #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
46
47 #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
48 #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
49 #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
50 #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
51 #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
52 #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
53 #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
54 #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
55 #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
56 #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
57 #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
58 #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
59 #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
60 #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
61
62 #define MMC_CAP(mode) (1 << mode)
63 #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
64 #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
65 #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
66 #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
67 #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
68 #define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
69
70 #define MMC_CAP_NONREMOVABLE BIT(14)
71 #define MMC_CAP_NEEDS_POLL BIT(15)
72 #define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
73
74 #define MMC_MODE_8BIT BIT(30)
75 #define MMC_MODE_4BIT BIT(29)
76 #define MMC_MODE_1BIT BIT(28)
77 #define MMC_MODE_SPI BIT(27)
78
79
80 #define SD_DATA_4BIT 0x00040000
81
82 #define IS_SD(x) ((x)->version & SD_VERSION_SD)
83 #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
84
85 #define MMC_DATA_READ 1
86 #define MMC_DATA_WRITE 2
87
88 #define MMC_CMD_GO_IDLE_STATE 0
89 #define MMC_CMD_SEND_OP_COND 1
90 #define MMC_CMD_ALL_SEND_CID 2
91 #define MMC_CMD_SET_RELATIVE_ADDR 3
92 #define MMC_CMD_SET_DSR 4
93 #define MMC_CMD_SWITCH 6
94 #define MMC_CMD_SELECT_CARD 7
95 #define MMC_CMD_SEND_EXT_CSD 8
96 #define MMC_CMD_SEND_CSD 9
97 #define MMC_CMD_SEND_CID 10
98 #define MMC_CMD_STOP_TRANSMISSION 12
99 #define MMC_CMD_SEND_STATUS 13
100 #define MMC_CMD_SET_BLOCKLEN 16
101 #define MMC_CMD_READ_SINGLE_BLOCK 17
102 #define MMC_CMD_READ_MULTIPLE_BLOCK 18
103 #define MMC_CMD_SEND_TUNING_BLOCK 19
104 #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
105 #define MMC_CMD_SET_BLOCK_COUNT 23
106 #define MMC_CMD_WRITE_SINGLE_BLOCK 24
107 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
108 #define MMC_CMD_ERASE_GROUP_START 35
109 #define MMC_CMD_ERASE_GROUP_END 36
110 #define MMC_CMD_ERASE 38
111 #define MMC_CMD_APP_CMD 55
112 #define MMC_CMD_SPI_READ_OCR 58
113 #define MMC_CMD_SPI_CRC_ON_OFF 59
114 #define MMC_CMD_RES_MAN 62
115
116 #define MMC_CMD62_ARG1 0xefac62ec
117 #define MMC_CMD62_ARG2 0xcbaea7
118
119
120 #define SD_CMD_SEND_RELATIVE_ADDR 3
121 #define SD_CMD_SWITCH_FUNC 6
122 #define SD_CMD_SEND_IF_COND 8
123 #define SD_CMD_SWITCH_UHS18V 11
124
125 #define SD_CMD_APP_SET_BUS_WIDTH 6
126 #define SD_CMD_APP_SD_STATUS 13
127 #define SD_CMD_ERASE_WR_BLK_START 32
128 #define SD_CMD_ERASE_WR_BLK_END 33
129 #define SD_CMD_APP_SEND_OP_COND 41
130 #define SD_CMD_APP_SEND_SCR 51
131
mmc_is_tuning_cmd(uint cmdidx)132 static inline bool mmc_is_tuning_cmd(uint cmdidx)
133 {
134 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
135 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
136 return true;
137 return false;
138 }
139
140 /* SCR definitions in different words */
141 #define SD_HIGHSPEED_BUSY 0x00020000
142 #define SD_HIGHSPEED_SUPPORTED 0x00020000
143
144 #define UHS_SDR12_BUS_SPEED 0
145 #define HIGH_SPEED_BUS_SPEED 1
146 #define UHS_SDR25_BUS_SPEED 1
147 #define UHS_SDR50_BUS_SPEED 2
148 #define UHS_SDR104_BUS_SPEED 3
149 #define UHS_DDR50_BUS_SPEED 4
150
151 #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
152 #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
153 #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
154 #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
155 #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
156
157 #define OCR_BUSY 0x80000000
158 #define OCR_HCS 0x40000000
159 #define OCR_S18R 0x1000000
160 #define OCR_VOLTAGE_MASK 0x007FFF80
161 #define OCR_ACCESS_MODE 0x60000000
162
163 #define MMC_ERASE_ARG 0x00000000
164 #define MMC_SECURE_ERASE_ARG 0x80000000
165 #define MMC_TRIM_ARG 0x00000001
166 #define MMC_DISCARD_ARG 0x00000003
167 #define MMC_SECURE_TRIM1_ARG 0x80000001
168 #define MMC_SECURE_TRIM2_ARG 0x80008000
169
170 #define MMC_STATUS_MASK (~0x0206BF7F)
171 #define MMC_STATUS_SWITCH_ERROR (1 << 7)
172 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
173 #define MMC_STATUS_CURR_STATE (0xf << 9)
174 #define MMC_STATUS_ERROR (1 << 19)
175
176 #define MMC_STATE_PRG (7 << 9)
177
178 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
179 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
180 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
181 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
182 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
183 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
184 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
185 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
186 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
187 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
188 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
189 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
190 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
191 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
192 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
193 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
194 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
195
196 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
197 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
198 addressed by index which are
199 1 in value field */
200 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
201 addressed by index, which are
202 1 in value field */
203 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
204
205 #define SD_SWITCH_CHECK 0
206 #define SD_SWITCH_SWITCH 1
207
208 /*
209 * EXT_CSD fields
210 */
211 #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
212 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
213 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
214 #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
215 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
216 #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
217 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
218 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
219 #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
220 #define EXT_CSD_WR_REL_PARAM 166 /* R */
221 #define EXT_CSD_WR_REL_SET 167 /* R/W */
222 #define EXT_CSD_RPMB_MULT 168 /* RO */
223 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
224 #define EXT_CSD_BOOT_BUS_WIDTH 177
225 #define EXT_CSD_PART_CONF 179 /* R/W */
226 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
227 #define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
228 #define EXT_CSD_HS_TIMING 185 /* R/W */
229 #define EXT_CSD_REV 192 /* RO */
230 #define EXT_CSD_CARD_TYPE 196 /* RO */
231 #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
232 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
233 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
234 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
235 #define EXT_CSD_BOOT_MULT 226 /* RO */
236 #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
237 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
238
239 /*
240 * EXT_CSD field definitions
241 */
242 #define EXT_CSD_WR_REL_VALUE (0x1f)
243 #define EXT_CSD_RST_N_EN_MASK 0x3
244 #define EXT_CSD_RST_N_ENABLED (1 << 0) /* RST_n is enabled on card */
245
246 #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
247 #define EXT_CSD_CMD_SET_SECURE (1 << 1)
248 #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
249
250 #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
251 #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
252 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
253 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
254 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
255 | EXT_CSD_CARD_TYPE_DDR_1_2V)
256
257 #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
258 /* SDR mode @1.8V I/O */
259 #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
260 /* SDR mode @1.2V I/O */
261 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
262 EXT_CSD_CARD_TYPE_HS200_1_2V)
263 #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
264 #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
265 #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
266 EXT_CSD_CARD_TYPE_HS400_1_2V)
267
268 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
269 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
270 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
271 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
272 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
273 #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
274 #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
275
276 #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
277 #define EXT_CSD_TIMING_HS 1 /* HS */
278 #define EXT_CSD_TIMING_HS200 2 /* HS200 */
279 #define EXT_CSD_TIMING_HS400 3 /* HS400 */
280 #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
281
282 #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
283 #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
284 #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
285 #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
286
287 #define EXT_CSD_BOOT_ACK(x) (x << 6)
288 #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
289 #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
290
291 #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
292 #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
293 #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
294
295 #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
296 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
297 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
298
299 #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
300
301 #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
302 #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
303
304 #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
305
306 #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
307 #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
308
309 #define R1_ILLEGAL_COMMAND (1 << 22)
310 #define R1_APP_CMD (1 << 5)
311
312 #define MMC_RSP_PRESENT (1 << 0)
313 #define MMC_RSP_136 (1 << 1) /* 136 bit response */
314 #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
315 #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
316 #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
317
318 #define MMC_RSP_NONE (0)
319 #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
320 #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
321 MMC_RSP_BUSY)
322 #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
323 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
324 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
325 #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
326 #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
327 #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
328
329 #define MMCPART_NOAVAILABLE (0xff)
330 #define PART_ACCESS_MASK (0x7)
331 #define PART_SUPPORT (0x1)
332 #define ENHNCD_SUPPORT (0x2)
333 #define PART_ENH_ATTRIB (0x1f)
334
335 #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
336 #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
337
338 enum mmc_voltage {
339 MMC_SIGNAL_VOLTAGE_000 = 0,
340 MMC_SIGNAL_VOLTAGE_120 = 1,
341 MMC_SIGNAL_VOLTAGE_180 = 2,
342 MMC_SIGNAL_VOLTAGE_330 = 4,
343 };
344
345 #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
346 MMC_SIGNAL_VOLTAGE_180 |\
347 MMC_SIGNAL_VOLTAGE_330)
348
349 /* Maximum block size for MMC */
350 #define MMC_MAX_BLOCK_LEN 512
351
352 /* The number of MMC physical partitions. These consist of:
353 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
354 */
355 #define MMC_NUM_BOOT_PARTITION 2
356 #define MMC_PART_RPMB 3 /* RPMB partition number */
357
358 /* Driver model support */
359
360 /**
361 * struct mmc_uclass_priv - Holds information about a device used by the uclass
362 */
363 struct mmc_uclass_priv {
364 struct mmc *mmc;
365 };
366
367 /**
368 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
369 *
370 * Provided that the device is already probed and ready for use, this value
371 * will be available.
372 *
373 * @dev: Device
374 * @return associated mmc struct pointer if available, else NULL
375 */
376 struct mmc *mmc_get_mmc_dev(struct udevice *dev);
377
378 /* End of driver model support */
379
380 struct mmc_cid {
381 unsigned long psn;
382 unsigned short oid;
383 unsigned char mid;
384 unsigned char prv;
385 unsigned char mdt;
386 char pnm[7];
387 };
388
389 struct mmc_cmd {
390 ushort cmdidx;
391 uint resp_type;
392 uint cmdarg;
393 uint response[4];
394 };
395
396 struct mmc_data {
397 union {
398 char *dest;
399 const char *src; /* src buffers don't get written to */
400 };
401 uint flags;
402 uint blocks;
403 uint blocksize;
404 };
405
406 /* forward decl. */
407 struct mmc;
408
409 #if CONFIG_IS_ENABLED(DM_MMC)
410 struct dm_mmc_ops {
411 /**
412 * send_cmd() - Send a command to the MMC device
413 *
414 * @dev: Device to receive the command
415 * @cmd: Command to send
416 * @data: Additional data to send/receive
417 * @return 0 if OK, -ve on error
418 */
419 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
420 struct mmc_data *data);
421
422 /**
423 * set_ios() - Set the I/O speed/width for an MMC device
424 *
425 * @dev: Device to update
426 * @return 0 if OK, -ve on error
427 */
428 int (*set_ios)(struct udevice *dev);
429
430 /**
431 * get_cd() - See whether a card is present
432 *
433 * @dev: Device to check
434 * @return 0 if not present, 1 if present, -ve on error
435 */
436 int (*get_cd)(struct udevice *dev);
437
438 /**
439 * get_wp() - See whether a card has write-protect enabled
440 *
441 * @dev: Device to check
442 * @return 0 if write-enabled, 1 if write-protected, -ve on error
443 */
444 int (*get_wp)(struct udevice *dev);
445
446 #ifdef MMC_SUPPORTS_TUNING
447 /**
448 * execute_tuning() - Start the tuning process
449 *
450 * @dev: Device to start the tuning
451 * @opcode: Command opcode to send
452 * @return 0 if OK, -ve on error
453 */
454 int (*execute_tuning)(struct udevice *dev, uint opcode);
455 #endif
456
457 /**
458 * wait_dat0() - wait until dat0 is in the target state
459 * (CLK must be running during the wait)
460 *
461 * @dev: Device to check
462 * @state: target state
463 * @timeout_us: timeout in us
464 * @return 0 if dat0 is in the target state, -ve on error
465 */
466 int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
467
468 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
469 /* set_enhanced_strobe() - set HS400 enhanced strobe */
470 int (*set_enhanced_strobe)(struct udevice *dev);
471 #endif
472
473 /**
474 * host_power_cycle - host specific tasks in power cycle sequence
475 * Called between mmc_power_off() and
476 * mmc_power_on()
477 *
478 * @dev: Device to check
479 * @return 0 if not present, 1 if present, -ve on error
480 */
481 int (*host_power_cycle)(struct udevice *dev);
482 };
483
484 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
485
486 int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
487 struct mmc_data *data);
488 int dm_mmc_set_ios(struct udevice *dev);
489 int dm_mmc_get_cd(struct udevice *dev);
490 int dm_mmc_get_wp(struct udevice *dev);
491 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
492 int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
493 int dm_mmc_host_power_cycle(struct udevice *dev);
494
495 /* Transition functions for compatibility */
496 int mmc_set_ios(struct mmc *mmc);
497 int mmc_getcd(struct mmc *mmc);
498 int mmc_getwp(struct mmc *mmc);
499 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
500 int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
501 int mmc_set_enhanced_strobe(struct mmc *mmc);
502 int mmc_host_power_cycle(struct mmc *mmc);
503
504 #else
505 struct mmc_ops {
506 int (*send_cmd)(struct mmc *mmc,
507 struct mmc_cmd *cmd, struct mmc_data *data);
508 int (*set_ios)(struct mmc *mmc);
509 int (*init)(struct mmc *mmc);
510 int (*getcd)(struct mmc *mmc);
511 int (*getwp)(struct mmc *mmc);
512 int (*host_power_cycle)(struct mmc *mmc);
513 int (*execute_tuning)(struct mmc *mmc, u32 opcode);
514 void (*hs400_enable_es)(struct mmc *mmc, bool enable);
515 int (*card_busy)(struct mmc *mmc);
516 };
517 #endif
518
519 struct mmc_config {
520 const char *name;
521 #if !CONFIG_IS_ENABLED(DM_MMC)
522 const struct mmc_ops *ops;
523 #endif
524 uint host_caps;
525 uint voltages;
526 uint f_min;
527 uint f_max;
528 uint b_max;
529 unsigned char part_type;
530 };
531
532 struct sd_ssr {
533 unsigned int au; /* In sectors */
534 unsigned int erase_timeout; /* In milliseconds */
535 unsigned int erase_offset; /* In milliseconds */
536 };
537
538 enum bus_mode {
539 MMC_LEGACY,
540 SD_LEGACY,
541 MMC_HS,
542 SD_HS,
543 MMC_HS_52,
544 MMC_DDR_52,
545 UHS_SDR12,
546 UHS_SDR25,
547 UHS_SDR50,
548 UHS_DDR50,
549 UHS_SDR104,
550 MMC_HS_200,
551 MMC_HS_400,
552 MMC_HS_400_ES,
553 MMC_MODES_END
554 };
555
556 const char *mmc_mode_name(enum bus_mode mode);
557 void mmc_dump_capabilities(const char *text, uint caps);
558
mmc_is_mode_ddr(enum bus_mode mode)559 static inline bool mmc_is_mode_ddr(enum bus_mode mode)
560 {
561 if (mode == MMC_DDR_52)
562 return true;
563 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
564 else if (mode == UHS_DDR50)
565 return true;
566 #endif
567 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
568 else if (mode == MMC_HS_400)
569 return true;
570 #endif
571 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
572 else if (mode == MMC_HS_400_ES)
573 return true;
574 #endif
575 else
576 return false;
577 }
578
579 #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
580 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
581 MMC_CAP(UHS_DDR50))
582
supports_uhs(uint caps)583 static inline bool supports_uhs(uint caps)
584 {
585 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
586 return (caps & UHS_CAPS) ? true : false;
587 #else
588 return false;
589 #endif
590 }
591
592 /*
593 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
594 * with mmc_get_mmc_dev().
595 *
596 * TODO struct mmc should be in mmc_private but it's hard to fix right now
597 */
598 struct mmc {
599 #if !CONFIG_IS_ENABLED(BLK)
600 struct list_head link;
601 #endif
602 const struct mmc_config *cfg; /* provided configuration */
603 uint version;
604 void *priv;
605 uint has_init;
606 int high_capacity;
607 bool clk_disable; /* true if the clock can be turned off */
608 uint bus_width;
609 uint clock;
610 #define MMC_HIGH_52_MAX_DTR 52000000
611 enum mmc_voltage signal_voltage;
612 uint card_caps;
613 uint host_caps;
614 uint ocr;
615 uint dsr;
616 uint dsr_imp;
617 uint scr[2];
618 uint csd[4];
619 uint cid[4];
620 ushort rca;
621 u8 part_support;
622 u8 part_attr;
623 u8 wr_rel_set;
624 u8 part_config;
625 u8 gen_cmd6_time; /* units: 10 ms */
626 u8 part_switch_time; /* units: 10 ms */
627 uint tran_speed;
628 uint legacy_speed; /* speed for the legacy mode provided by the card */
629 uint read_bl_len;
630 #if CONFIG_IS_ENABLED(MMC_WRITE)
631 uint write_bl_len;
632 uint erase_grp_size; /* in 512-byte sectors */
633 #endif
634 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
635 uint hc_wp_grp_size; /* in 512-byte sectors */
636 #endif
637 #if CONFIG_IS_ENABLED(MMC_WRITE)
638 struct sd_ssr ssr; /* SD status register */
639 #endif
640 u64 capacity;
641 u64 capacity_user;
642 u64 capacity_boot;
643 u64 capacity_rpmb;
644 u64 capacity_gp[4];
645 #ifndef CONFIG_SPL_BUILD
646 u64 enh_user_start;
647 u64 enh_user_size;
648 #endif
649 #if !CONFIG_IS_ENABLED(BLK)
650 struct blk_desc block_dev;
651 #endif
652 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
653 char init_in_progress; /* 1 if we have done mmc_start_init() */
654 char preinit; /* start init as early as possible */
655 int ddr_mode;
656 #if CONFIG_IS_ENABLED(DM_MMC)
657 struct udevice *dev; /* Device for this MMC controller */
658 #if CONFIG_IS_ENABLED(DM_REGULATOR)
659 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
660 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
661 #endif
662 #endif
663 u8 strobe_enhanced;
664 u8 dev_num;
665 u32 ocr_from_bootrom;
666 u8 *ext_csd;
667 u32 cardtype; /* cardtype read from the MMC */
668 enum mmc_voltage current_voltage;
669 enum bus_mode selected_mode; /* mode currently used */
670 enum bus_mode best_mode; /* best mode is the supported mode with the
671 * highest bandwidth. It may not always be the
672 * operating mode due to limitations when
673 * accessing the boot partitions
674 */
675 u32 quirks;
676 };
677
678 struct mmc_hwpart_conf {
679 struct {
680 uint enh_start; /* in 512-byte sectors */
681 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
682 unsigned wr_rel_change : 1;
683 unsigned wr_rel_set : 1;
684 } user;
685 struct {
686 uint size; /* in 512-byte sectors */
687 unsigned enhanced : 1;
688 unsigned wr_rel_change : 1;
689 unsigned wr_rel_set : 1;
690 } gp_part[4];
691 };
692
693 enum mmc_hwpart_conf_mode {
694 MMC_HWPART_CONF_CHECK,
695 MMC_HWPART_CONF_SET,
696 MMC_HWPART_CONF_COMPLETE,
697 };
698
699 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
700
701 /**
702 * mmc_bind() - Set up a new MMC device ready for probing
703 *
704 * A child block device is bound with the IF_TYPE_MMC interface type. This
705 * allows the device to be used with CONFIG_BLK
706 *
707 * @dev: MMC device to set up
708 * @mmc: MMC struct
709 * @cfg: MMC configuration
710 * @return 0 if OK, -ve on error
711 */
712 int mmc_bind(struct udevice *dev, struct mmc *mmc,
713 const struct mmc_config *cfg);
714 void mmc_destroy(struct mmc *mmc);
715
716 /**
717 * mmc_unbind() - Unbind a MMC device's child block device
718 *
719 * @dev: MMC device
720 * @return 0 if OK, -ve on error
721 */
722 int mmc_unbind(struct udevice *dev);
723 int mmc_initialize(bd_t *bis);
724 int mmc_init_device(int num);
725 int mmc_init(struct mmc *mmc);
726 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
727
728 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
729 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
730 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
731 int mmc_deinit(struct mmc *mmc);
732 #endif
733
734 /**
735 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
736 *
737 * @dev: MMC device
738 * @cfg: MMC configuration
739 * @return 0 if OK, -ve on error
740 */
741 int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
742
743 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
744
745 /**
746 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
747 *
748 * @voltage: The mmc_voltage to convert
749 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
750 */
751 int mmc_voltage_to_mv(enum mmc_voltage voltage);
752
753 /**
754 * mmc_set_clock() - change the bus clock
755 * @mmc: MMC struct
756 * @clock: bus frequency in Hz
757 * @disable: flag indicating if the clock must on or off
758 * @return 0 if OK, -ve on error
759 */
760 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
761
762 #define MMC_CLK_ENABLE false
763 #define MMC_CLK_DISABLE true
764
765 struct mmc *find_mmc_device(int dev_num);
766 int mmc_set_dev(int dev_num);
767 void print_mmc_devices(char separator);
768
769 /**
770 * get_mmc_num() - get the total MMC device number
771 *
772 * @return 0 if there is no MMC device, else the number of devices
773 */
774 int get_mmc_num(void);
775 int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
776 int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
777 enum mmc_hwpart_conf_mode mode);
778
779 #if !CONFIG_IS_ENABLED(DM_MMC)
780 int mmc_getcd(struct mmc *mmc);
781 int board_mmc_getcd(struct mmc *mmc);
782 int mmc_getwp(struct mmc *mmc);
783 int board_mmc_getwp(struct mmc *mmc);
784 #endif
785
786 int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
787 int mmc_set_boot_config(struct mmc *mmc);
788 int mmc_set_dsr(struct mmc *mmc, u16 val);
789 /* Function to change the size of boot partition and rpmb partitions */
790 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
791 unsigned long rpmbsize);
792 /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
793 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
794 /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
795 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
796 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
797 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
798 /* Functions to read / write the RPMB partition */
799 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
800 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
801 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
802 unsigned short cnt, unsigned char *key);
803 int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
804 unsigned short cnt, unsigned char *key);
805
806 /**
807 * mmc_rpmb_route_frames() - route RPMB data frames
808 * @mmc Pointer to a MMC device struct
809 * @req Request data frames
810 * @reqlen Length of data frames in bytes
811 * @rsp Supplied buffer for response data frames
812 * @rsplen Length of supplied buffer for response data frames
813 *
814 * The RPMB data frames are routed to/from some external entity, for
815 * example a Trusted Exectuion Environment in an arm TrustZone protected
816 * secure world. It's expected that it's the external entity who is in
817 * control of the RPMB key.
818 *
819 * Returns 0 on success, < 0 on error.
820 */
821 int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
822 void *rsp, unsigned long rsplen);
823
824 #ifdef CONFIG_CMD_BKOPS_ENABLE
825 int mmc_set_bkops_enable(struct mmc *mmc);
826 #endif
827
828 /**
829 * Start device initialization and return immediately; it does not block on
830 * polling OCR (operation condition register) status. Useful for checking
831 * the presence of SD/eMMC when no card detect logic is available.
832 *
833 * @param mmc Pointer to a MMC device struct
834 * @return 0 on success, <0 on error.
835 */
836 int mmc_get_op_cond(struct mmc *mmc);
837
838 /**
839 * Start device initialization and return immediately; it does not block on
840 * polling OCR (operation condition register) status. Then you should call
841 * mmc_init, which would block on polling OCR status and complete the device
842 * initializatin.
843 *
844 * @param mmc Pointer to a MMC device struct
845 * @return 0 on success, <0 on error.
846 */
847 int mmc_start_init(struct mmc *mmc);
848
849 /**
850 * Set preinit flag of mmc device.
851 *
852 * This will cause the device to be pre-inited during mmc_initialize(),
853 * which may save boot time if the device is not accessed until later.
854 * Some eMMC devices take 200-300ms to init, but unfortunately they
855 * must be sent a series of commands to even get them to start preparing
856 * for operation.
857 *
858 * @param mmc Pointer to a MMC device struct
859 * @param preinit preinit flag value
860 */
861 void mmc_set_preinit(struct mmc *mmc, int preinit);
862
863 #ifdef CONFIG_MMC_SPI
864 #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
865 #else
866 #define mmc_host_is_spi(mmc) 0
867 #endif
868
869 void board_mmc_power_init(void);
870 int board_mmc_init(bd_t *bis);
871 int cpu_mmc_init(bd_t *bis);
872 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
873 # ifdef CONFIG_SYS_MMC_ENV_PART
874 extern uint mmc_get_env_part(struct mmc *mmc);
875 # endif
876 int mmc_get_env_dev(void);
877
878 /* Minimum partition switch timeout in units of 10-milliseconds */
879 #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
880
881 /* Set block count limit because of 16 bit register limit on some hardware*/
882 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
883 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
884 #endif
885
886 /**
887 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
888 *
889 * @mmc: MMC device
890 * @return block device if found, else NULL
891 */
892 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
893
894 #endif /* _MMC_H_ */
895