1 /* 2 * himci_reg.h 3 * 4 * The himci head File. 5 * 6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 * 21 */ 22 23 #ifndef _HIMCI_REG_H_ 24 #define _HIMCI_REG_H_ 25 #include <config.h> 26 27 #define MCI_CTRL 0x00 28 #define MCI_PWREN 0x04 29 #define MCI_CLKDIV 0x08 30 #define MCI_CLKSRC 0x0C 31 #define MCI_CLKENA 0x10 32 #define MCI_TIMEOUT 0x14 33 #define MCI_CTYPE 0x18 34 #define MCI_BLKSIZ 0x1c 35 #define MCI_BYTCNT 0x20 36 #define MCI_INTMASK 0x24 37 #define MCI_CMDARG 0x28 38 #define MCI_CMD 0x2C 39 #define MCI_RESP0 0x30 40 #define MCI_RESP1 0x34 41 #define MCI_RESP2 0x38 42 #define MCI_RESP3 0x3C 43 #define MCI_MINTSTS 0x40 44 #define MCI_RINTSTS 0x44 45 #define MCI_STATUS 0x48 46 #define MCI_FIFOTH 0x4C 47 #define MCI_CDETECT 0x50 48 #define MCI_WRTPRT 0x54 49 #define MCI_GPIO 0x58 50 #define MCI_TCBCNT 0x5C 51 #define MCI_TBBCNT 0x60 52 #define MCI_DEBNCE 0x64 53 #define MCI_USRID 0x68 54 #define MCI_VERID 0x6C 55 #define MCI_HCON 0x70 56 #define MCI_UHS_REG 0x74 57 #define MCI_RESET_N 0x78 58 #define MCI_BMOD 0x80 59 #define MCI_DBADDR 0x88 60 #define MCI_IDSTS 0x8C 61 #define MCI_IDINTEN 0x90 62 #define MCI_DSCADDR 0x94 63 #define MCI_BUFADDR 0x98 64 #define MMC_CARDTHRCTL 0x100 65 #define MCI_UHS_REG_EXT 0x108 66 67 /* MCI_UHS_REG_EXT(0x108) details */ 68 /* bit[19:16] sampling phase */ 69 #define CLK_SMPL_PHS_SHIFT 16 70 #define CLK_SMPL_PHS_MASK (0x7<<16) 71 #define CLK_DRV_PHS_MASK (0x7<<23) 72 73 #define MCI_TUNING_CTRL 0x118 74 75 /* MCI_TUNING_CTRL(0x118) details */ 76 #define HW_TUNING_EN (0x1 << 0) 77 #define EDGE_CTRL (0x1 << 1) 78 #define FOUND_EDGE (0x1 << 5) 79 80 #define MCI_FIFO_START 0x200 81 82 /* IDMAC DEST1 details */ 83 #define DMA_BUFFER 0x2000 84 #define MAX_DMA_DES 20480 85 86 /* IDMAC DEST0 details */ 87 #define DMA_DES_OWN (0x1<<31) 88 #define DMA_DES_NEXT_DES (0x1<<4) 89 #define DMA_DES_FIRST_DES (0x1<<3) 90 #define DMA_DES_LAST_DES (0x1<<2) 91 92 /* MCI_CTRL(0x00) details */ 93 #define USE_INTERNAL_DMA (0x1<<25) 94 #define INTR_EN (0x1<<4) 95 #define DMA_RESET (0x1<<2) 96 #define FIFO_RESET (0x1<<1) 97 #define CTRL_RESET (0x1<<0) 98 99 /* MCI_CLKENA(0x10) details */ 100 /* bit 0: enable of card clk */ 101 #define CCLK_ENABLE (0x1<<0) 102 103 /* MCI_TIMEOUT(0x14) details: */ 104 #define DATA_TIMEOUT (0xffffff<<8) /* bit 31-8: data read timeout param */ 105 #define RESPONSE_TIMEOUT 0xff /* bit 7-0: response timeout param */ 106 107 /* MCI_CTYPE(0x18) details */ 108 #define CARD_WIDTH_MASK 0x10001UL 109 #define CARD_WIDTH_8BIT 0x10000UL 110 #define CARD_WIDTH_4BIT 0x01UL 111 #define CARD_WIDTH_1BIT 0x00UL 112 113 /* MCI_INTMASK(0x24) details: 114 bit 16-1: mask MMC host controller each interrupt 115 */ 116 #define ALL_INT_MASK 0x1fffe 117 118 /* MCI_CMD(0x2c) details: 119 bit 31: cmd execute or load start param of interface clk bit 120 */ 121 #define MCI_CMD_MASK 0x803FFFFFUL 122 #define START_CMD (0x1<<31) 123 #define USE_HOLD_REG (0x1<<29) 124 #define DISABLE_BOOT (0x1<<26) 125 #define ENABLE_BOOT (0x1<<24) 126 #define UP_CLK_ONLY (0x1<<21) 127 #define CARD_NUM (0x1<<16) 128 #define SEND_INIT (0x1<<15) 129 #define STOP_ABORT_CMD (0x1<<14) 130 #define WT_PD_CPT (0x1<<13) 131 #define SEND_AUTO_STOP (0x1<<12) 132 #define DATA_EXPECT (0x1<<9) 133 #define CHECK_RESP_CRC (0x1<<8) 134 #define RESP_LENGTH (0x1<<7) 135 #define RESP_EXPECT (0x1<<6) 136 137 /* MCI_INTSTS(0x44) details */ 138 /* ************************************************************* */ 139 /* bit 16: sdio interrupt status */ 140 #define SDIO_INT_STATUS (0x1<<16) 141 142 /* bit 15: end-bit error (read)/write no CRC interrupt status */ 143 #define EBE_INT_STATUS (0x1<<15) 144 145 /* bit 14: auto command done interrupt status */ 146 #define ACD_INT_STATUS (0x1<<14) 147 148 /* bit 13: start bit error interrupt status */ 149 #define SBE_INT_STATUS (0x1<<13) 150 151 /* bit 12: hardware locked write error interrupt status */ 152 #define HLE_INT_STATUS (0x1<<12) 153 154 /* bit 11: FIFO underrun/overrun error interrupt status */ 155 #define FRUN_INT_STATUS (0x1<<11) 156 157 /* bit 10: data starvation-by-host timeout interrupt status */ 158 #define HTO_INT_STATUS (0x1<<10) 159 160 /* bit 9: data read timeout interrupt status */ 161 #define DRTO_INT_STATUS (0x1<<9) 162 #define BDS_INT_STATUS (0x1<<9) 163 164 /* bit 8: response timeout interrupt status */ 165 #define RTO_INT_STATUS (0x1<<8) 166 167 /* bit 7: data CRC error interrupt status */ 168 #define DCRC_INT_STATUS (0x1<<7) 169 170 /* bit 6: response CRC error interrupt status */ 171 #define RCRC_INT_STATUS (0x1<<6) 172 173 /* bit 5: receive FIFO data request interrupt status */ 174 #define RXDR_INT_STATUS (0x1<<5) 175 176 /* bit 4: transmit FIFO data request interrupt status */ 177 #define TXDR_INT_STATUS (0x1<<4) 178 179 /* bit 3: data transfer Over interrupt status */ 180 #define DTO_INT_STATUS (0x1<<3) 181 182 /* bit 2: command done interrupt status */ 183 #define CD_INT_STATUS (0x1<<2) 184 185 /* bit 1: response error interrupt status */ 186 #define RE_INT_STATUS (0x1<<1) 187 /* ************************************************************* */ 188 189 /* MCI_RINTSTS(0x44) details:bit 16-1: clear 190 MMC host controller each interrupt but 191 hardware locked write error interrupt 192 */ 193 #define ALL_INT_CLR 0x1affe 194 195 /* MCI_STATUS(0x48) details */ 196 #define DATA_BUSY (0x1<<9) 197 198 /* MCI_FIFOTH(0x4c) details */ 199 #define BURST_SIZE (0x2<<28) 200 #define RX_WMARK (0x7<<16) 201 #define TX_WMARK 0x8 202 203 /* MCI_CDETECT(0x50) details */ 204 #define HIMCI_CARD0 (0x1<<0) 205 206 /* MCI_GPIO(0x58) details */ 207 #define DTO_FIX_BYPASS (0x1 << 23) 208 #define CMD_OUT_EN_FIX_BYPASS (0x1 << 8) 209 210 /* MCI_VERID(0x6c) details */ 211 #define MCI_VERID_VALUE 0x5342250A 212 #define MCI_VERID_VALUE2 0x5342270A 213 #define MCI_VERID_VALUE3 0x5342290A 214 215 /* MCI_BMOD(0x80) details */ 216 #define BURST_16 (0x3<<8) 217 #define BURST_8 (0x2<<8) 218 #define BMOD_DMA_EN (0x1<<7) 219 #define BURST_INCR (0x1<<1) 220 #define BMOD_SWR (0x1<<0) 221 222 /* MCI_IDINTEN(0x90) details */ 223 #define MCI_IDINTEN_MASK 0x00000337UL 224 #define TI (0x1<<0) 225 #define RI (0x1<<1) 226 #define NI (0x1<<8) 227 228 /* MCI MMC_CARDTHRCTL(0x100) details */ 229 #define RW_THRESHOLD_SIZE 0x2000005 230 231 /* MCI_UHS_REG_EXT(0x108) details */ 232 #define DRV_PHASE_MASK (0x7<<23) 233 #define DRV_PHASE_SHIFT (0x4<<23) 234 #define SMPL_PHASE_MASK (0x7<<16) 235 #define SMPL_PHASE_SHIFT (0x1<<16) 236 237 /* MCI_FIFO_START(0x200) details */ 238 #define FIFO_COUNT 17 /* fifo count [bit 17] */ 239 #define FIFO_COUNT_MASK 0x1fff /* fifo count [bit 29:17]>>17 */ 240 241 #endif 242