1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4 #ifndef _MLXSW_REG_H
5 #define _MLXSW_REG_H
6
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/bitops.h>
10 #include <linux/if_vlan.h>
11
12 #include "item.h"
13 #include "port.h"
14
15 struct mlxsw_reg_info {
16 u16 id;
17 u16 len; /* In u8 */
18 const char *name;
19 };
20
21 #define MLXSW_REG_DEFINE(_name, _id, _len) \
22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
23 .id = _id, \
24 .len = _len, \
25 .name = #_name, \
26 }
27
28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
34 * This register is used for configuration of the switch capabilities.
35 */
36 #define MLXSW_REG_SGCR_ID 0x2000
37 #define MLXSW_REG_SGCR_LEN 0x10
38
39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40
41 /* reg_sgcr_llb
42 * Link Local Broadcast (Default=0)
43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
44 * packets and ignore the IGMP snooping entries.
45 * Access: RW
46 */
47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48
mlxsw_reg_sgcr_pack(char * payload,bool llb)49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50 {
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
53 }
54
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
57 * The SPAD register configures the switch physical MAC address.
58 */
59 #define MLXSW_REG_SPAD_ID 0x2002
60 #define MLXSW_REG_SPAD_LEN 0x10
61
62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63
64 /* reg_spad_base_mac
65 * Base MAC address for the switch partitions.
66 * Per switch partition MAC address is equal to:
67 * base_mac + swid
68 * Access: RW
69 */
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71
72 /* SMID - Switch Multicast ID
73 * --------------------------
74 * The MID record maps from a MID (Multicast ID), which is a unique identifier
75 * of the multicast group within the stacking domain, into a list of local
76 * ports into which the packet is replicated.
77 */
78 #define MLXSW_REG_SMID_ID 0x2007
79 #define MLXSW_REG_SMID_LEN 0x240
80
81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
82
83 /* reg_smid_swid
84 * Switch partition ID.
85 * Access: Index
86 */
87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
88
89 /* reg_smid_mid
90 * Multicast identifier - global identifier that represents the multicast group
91 * across all devices.
92 * Access: Index
93 */
94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
95
96 /* reg_smid_port
97 * Local port memebership (1 bit per port).
98 * Access: RW
99 */
100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
101
102 /* reg_smid_port_mask
103 * Local port mask (1 bit per port).
104 * Access: W
105 */
106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
107
mlxsw_reg_smid_pack(char * payload,u16 mid,u8 port,bool set)108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
109 u8 port, bool set)
110 {
111 MLXSW_REG_ZERO(smid, payload);
112 mlxsw_reg_smid_swid_set(payload, 0);
113 mlxsw_reg_smid_mid_set(payload, mid);
114 mlxsw_reg_smid_port_set(payload, port, set);
115 mlxsw_reg_smid_port_mask_set(payload, port, 1);
116 }
117
118 /* SSPR - Switch System Port Record Register
119 * -----------------------------------------
120 * Configures the system port to local port mapping.
121 */
122 #define MLXSW_REG_SSPR_ID 0x2008
123 #define MLXSW_REG_SSPR_LEN 0x8
124
125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
126
127 /* reg_sspr_m
128 * Master - if set, then the record describes the master system port.
129 * This is needed in case a local port is mapped into several system ports
130 * (for multipathing). That number will be reported as the source system
131 * port when packets are forwarded to the CPU. Only one master port is allowed
132 * per local port.
133 *
134 * Note: Must be set for Spectrum.
135 * Access: RW
136 */
137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
138
139 /* reg_sspr_local_port
140 * Local port number.
141 *
142 * Access: RW
143 */
144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
145
146 /* reg_sspr_sub_port
147 * Virtual port within the physical port.
148 * Should be set to 0 when virtual ports are not enabled on the port.
149 *
150 * Access: RW
151 */
152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
153
154 /* reg_sspr_system_port
155 * Unique identifier within the stacking domain that represents all the ports
156 * that are available in the system (external ports).
157 *
158 * Currently, only single-ASIC configurations are supported, so we default to
159 * 1:1 mapping between system ports and local ports.
160 * Access: Index
161 */
162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163
mlxsw_reg_sspr_pack(char * payload,u8 local_port)164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
165 {
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
171 }
172
173 /* SFDAT - Switch Filtering Database Aging Time
174 * --------------------------------------------
175 * Controls the Switch aging time. Aging time is able to be set per Switch
176 * Partition.
177 */
178 #define MLXSW_REG_SFDAT_ID 0x2009
179 #define MLXSW_REG_SFDAT_LEN 0x8
180
181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
182
183 /* reg_sfdat_swid
184 * Switch partition ID.
185 * Access: Index
186 */
187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
188
189 /* reg_sfdat_age_time
190 * Aging time in seconds
191 * Min - 10 seconds
192 * Max - 1,000,000 seconds
193 * Default is 300 seconds.
194 * Access: RW
195 */
196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
197
mlxsw_reg_sfdat_pack(char * payload,u32 age_time)198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
199 {
200 MLXSW_REG_ZERO(sfdat, payload);
201 mlxsw_reg_sfdat_swid_set(payload, 0);
202 mlxsw_reg_sfdat_age_time_set(payload, age_time);
203 }
204
205 /* SFD - Switch Filtering Database
206 * -------------------------------
207 * The following register defines the access to the filtering database.
208 * The register supports querying, adding, removing and modifying the database.
209 * The access is optimized for bulk updates in which case more than one
210 * FDB record is present in the same command.
211 */
212 #define MLXSW_REG_SFD_ID 0x200A
213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
218
219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
220
221 /* reg_sfd_swid
222 * Switch partition ID for queries. Reserved on Write.
223 * Access: Index
224 */
225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
226
227 enum mlxsw_reg_sfd_op {
228 /* Dump entire FDB a (process according to record_locator) */
229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230 /* Query records by {MAC, VID/FID} value */
231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232 /* Query and clear activity. Query records by {MAC, VID/FID} value */
233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234 /* Test. Response indicates if each of the records could be
235 * added to the FDB.
236 */
237 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238 /* Add/modify. Aged-out records cannot be added. This command removes
239 * the learning notification of the {MAC, VID/FID}. Response includes
240 * the entries that were added to the FDB.
241 */
242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243 /* Remove record by {MAC, VID/FID}. This command also removes
244 * the learning notification and aged-out notifications
245 * of the {MAC, VID/FID}. The response provides current (pre-removal)
246 * entries as non-aged-out.
247 */
248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249 /* Remove learned notification by {MAC, VID/FID}. The response provides
250 * the removed learning notification.
251 */
252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
253 };
254
255 /* reg_sfd_op
256 * Operation.
257 * Access: OP
258 */
259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
260
261 /* reg_sfd_record_locator
262 * Used for querying the FDB. Use record_locator=0 to initiate the
263 * query. When a record is returned, a new record_locator is
264 * returned to be used in the subsequent query.
265 * Reserved for database update.
266 * Access: Index
267 */
268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
269
270 /* reg_sfd_num_rec
271 * Request: Number of records to read/add/modify/remove
272 * Response: Number of records read/added/replaced/removed
273 * See above description for more details.
274 * Ranges 0..64
275 * Access: RW
276 */
277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
278
mlxsw_reg_sfd_pack(char * payload,enum mlxsw_reg_sfd_op op,u32 record_locator)279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
280 u32 record_locator)
281 {
282 MLXSW_REG_ZERO(sfd, payload);
283 mlxsw_reg_sfd_op_set(payload, op);
284 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
285 }
286
287 /* reg_sfd_rec_swid
288 * Switch partition ID.
289 * Access: Index
290 */
291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 MLXSW_REG_SFD_REC_LEN, 0x00, false);
293
294 enum mlxsw_reg_sfd_rec_type {
295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 };
299
300 /* reg_sfd_rec_type
301 * FDB record type.
302 * Access: RW
303 */
304 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
305 MLXSW_REG_SFD_REC_LEN, 0x00, false);
306
307 enum mlxsw_reg_sfd_rec_policy {
308 /* Replacement disabled, aging disabled. */
309 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
310 /* (mlag remote): Replacement enabled, aging disabled,
311 * learning notification enabled on this port.
312 */
313 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
314 /* (ingress device): Replacement enabled, aging enabled. */
315 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
316 };
317
318 /* reg_sfd_rec_policy
319 * Policy.
320 * Access: RW
321 */
322 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
323 MLXSW_REG_SFD_REC_LEN, 0x00, false);
324
325 /* reg_sfd_rec_a
326 * Activity. Set for new static entries. Set for static entries if a frame SMAC
327 * lookup hits on the entry.
328 * To clear the a bit, use "query and clear activity" op.
329 * Access: RO
330 */
331 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
332 MLXSW_REG_SFD_REC_LEN, 0x00, false);
333
334 /* reg_sfd_rec_mac
335 * MAC address.
336 * Access: Index
337 */
338 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
339 MLXSW_REG_SFD_REC_LEN, 0x02);
340
341 enum mlxsw_reg_sfd_rec_action {
342 /* forward */
343 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
344 /* forward and trap, trap_id is FDB_TRAP */
345 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
346 /* trap and do not forward, trap_id is FDB_TRAP */
347 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
348 /* forward to IP router */
349 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
350 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
351 };
352
353 /* reg_sfd_rec_action
354 * Action to apply on the packet.
355 * Note: Dynamic entries can only be configured with NOP action.
356 * Access: RW
357 */
358 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
359 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
360
361 /* reg_sfd_uc_sub_port
362 * VEPA channel on local port.
363 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
364 * VEPA is not enabled.
365 * Access: RW
366 */
367 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
368 MLXSW_REG_SFD_REC_LEN, 0x08, false);
369
370 /* reg_sfd_uc_fid_vid
371 * Filtering ID or VLAN ID
372 * For SwitchX and SwitchX-2:
373 * - Dynamic entries (policy 2,3) use FID
374 * - Static entries (policy 0) use VID
375 * - When independent learning is configured, VID=FID
376 * For Spectrum: use FID for both Dynamic and Static entries.
377 * VID should not be used.
378 * Access: Index
379 */
380 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
381 MLXSW_REG_SFD_REC_LEN, 0x08, false);
382
383 /* reg_sfd_uc_system_port
384 * Unique port identifier for the final destination of the packet.
385 * Access: RW
386 */
387 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
388 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
389
mlxsw_reg_sfd_rec_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_type rec_type,const char * mac,enum mlxsw_reg_sfd_rec_action action)390 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
391 enum mlxsw_reg_sfd_rec_type rec_type,
392 const char *mac,
393 enum mlxsw_reg_sfd_rec_action action)
394 {
395 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
396
397 if (rec_index >= num_rec)
398 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
399 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
400 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
401 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
402 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
403 }
404
mlxsw_reg_sfd_uc_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid_vid,enum mlxsw_reg_sfd_rec_action action,u8 local_port)405 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
406 enum mlxsw_reg_sfd_rec_policy policy,
407 const char *mac, u16 fid_vid,
408 enum mlxsw_reg_sfd_rec_action action,
409 u8 local_port)
410 {
411 mlxsw_reg_sfd_rec_pack(payload, rec_index,
412 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
413 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
414 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
415 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
416 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
417 }
418
mlxsw_reg_sfd_uc_unpack(char * payload,int rec_index,char * mac,u16 * p_fid_vid,u8 * p_local_port)419 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
420 char *mac, u16 *p_fid_vid,
421 u8 *p_local_port)
422 {
423 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
424 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
425 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
426 }
427
428 /* reg_sfd_uc_lag_sub_port
429 * LAG sub port.
430 * Must be 0 if multichannel VEPA is not enabled.
431 * Access: RW
432 */
433 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
434 MLXSW_REG_SFD_REC_LEN, 0x08, false);
435
436 /* reg_sfd_uc_lag_fid_vid
437 * Filtering ID or VLAN ID
438 * For SwitchX and SwitchX-2:
439 * - Dynamic entries (policy 2,3) use FID
440 * - Static entries (policy 0) use VID
441 * - When independent learning is configured, VID=FID
442 * For Spectrum: use FID for both Dynamic and Static entries.
443 * VID should not be used.
444 * Access: Index
445 */
446 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
447 MLXSW_REG_SFD_REC_LEN, 0x08, false);
448
449 /* reg_sfd_uc_lag_lag_vid
450 * Indicates VID in case of vFIDs. Reserved for FIDs.
451 * Access: RW
452 */
453 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
454 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
455
456 /* reg_sfd_uc_lag_lag_id
457 * LAG Identifier - pointer into the LAG descriptor table.
458 * Access: RW
459 */
460 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
461 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
462
463 static inline void
mlxsw_reg_sfd_uc_lag_pack(char * payload,int rec_index,enum mlxsw_reg_sfd_rec_policy policy,const char * mac,u16 fid_vid,enum mlxsw_reg_sfd_rec_action action,u16 lag_vid,u16 lag_id)464 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
465 enum mlxsw_reg_sfd_rec_policy policy,
466 const char *mac, u16 fid_vid,
467 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
468 u16 lag_id)
469 {
470 mlxsw_reg_sfd_rec_pack(payload, rec_index,
471 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
472 mac, action);
473 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
474 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
475 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
476 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
477 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
478 }
479
mlxsw_reg_sfd_uc_lag_unpack(char * payload,int rec_index,char * mac,u16 * p_vid,u16 * p_lag_id)480 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
481 char *mac, u16 *p_vid,
482 u16 *p_lag_id)
483 {
484 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
485 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
486 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
487 }
488
489 /* reg_sfd_mc_pgi
490 *
491 * Multicast port group index - index into the port group table.
492 * Value 0x1FFF indicates the pgi should point to the MID entry.
493 * For Spectrum this value must be set to 0x1FFF
494 * Access: RW
495 */
496 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
497 MLXSW_REG_SFD_REC_LEN, 0x08, false);
498
499 /* reg_sfd_mc_fid_vid
500 *
501 * Filtering ID or VLAN ID
502 * Access: Index
503 */
504 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
505 MLXSW_REG_SFD_REC_LEN, 0x08, false);
506
507 /* reg_sfd_mc_mid
508 *
509 * Multicast identifier - global identifier that represents the multicast
510 * group across all devices.
511 * Access: RW
512 */
513 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
514 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
515
516 static inline void
mlxsw_reg_sfd_mc_pack(char * payload,int rec_index,const char * mac,u16 fid_vid,enum mlxsw_reg_sfd_rec_action action,u16 mid)517 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
518 const char *mac, u16 fid_vid,
519 enum mlxsw_reg_sfd_rec_action action, u16 mid)
520 {
521 mlxsw_reg_sfd_rec_pack(payload, rec_index,
522 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
523 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
524 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
525 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
526 }
527
528 /* SFN - Switch FDB Notification Register
529 * -------------------------------------------
530 * The switch provides notifications on newly learned FDB entries and
531 * aged out entries. The notifications can be polled by software.
532 */
533 #define MLXSW_REG_SFN_ID 0x200B
534 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
535 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
536 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
537 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
538 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
539
540 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
541
542 /* reg_sfn_swid
543 * Switch partition ID.
544 * Access: Index
545 */
546 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
547
548 /* reg_sfn_end
549 * Forces the current session to end.
550 * Access: OP
551 */
552 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
553
554 /* reg_sfn_num_rec
555 * Request: Number of learned notifications and aged-out notification
556 * records requested.
557 * Response: Number of notification records returned (must be smaller
558 * than or equal to the value requested)
559 * Ranges 0..64
560 * Access: OP
561 */
562 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
563
mlxsw_reg_sfn_pack(char * payload)564 static inline void mlxsw_reg_sfn_pack(char *payload)
565 {
566 MLXSW_REG_ZERO(sfn, payload);
567 mlxsw_reg_sfn_swid_set(payload, 0);
568 mlxsw_reg_sfn_end_set(payload, 1);
569 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
570 }
571
572 /* reg_sfn_rec_swid
573 * Switch partition ID.
574 * Access: RO
575 */
576 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
577 MLXSW_REG_SFN_REC_LEN, 0x00, false);
578
579 enum mlxsw_reg_sfn_rec_type {
580 /* MAC addresses learned on a regular port. */
581 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
582 /* MAC addresses learned on a LAG port. */
583 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
584 /* Aged-out MAC address on a regular port. */
585 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
586 /* Aged-out MAC address on a LAG port. */
587 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
588 };
589
590 /* reg_sfn_rec_type
591 * Notification record type.
592 * Access: RO
593 */
594 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
595 MLXSW_REG_SFN_REC_LEN, 0x00, false);
596
597 /* reg_sfn_rec_mac
598 * MAC address.
599 * Access: RO
600 */
601 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
602 MLXSW_REG_SFN_REC_LEN, 0x02);
603
604 /* reg_sfn_mac_sub_port
605 * VEPA channel on the local port.
606 * 0 if multichannel VEPA is not enabled.
607 * Access: RO
608 */
609 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
610 MLXSW_REG_SFN_REC_LEN, 0x08, false);
611
612 /* reg_sfn_mac_fid
613 * Filtering identifier.
614 * Access: RO
615 */
616 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
617 MLXSW_REG_SFN_REC_LEN, 0x08, false);
618
619 /* reg_sfn_mac_system_port
620 * Unique port identifier for the final destination of the packet.
621 * Access: RO
622 */
623 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
624 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
625
mlxsw_reg_sfn_mac_unpack(char * payload,int rec_index,char * mac,u16 * p_vid,u8 * p_local_port)626 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
627 char *mac, u16 *p_vid,
628 u8 *p_local_port)
629 {
630 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
631 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
632 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
633 }
634
635 /* reg_sfn_mac_lag_lag_id
636 * LAG ID (pointer into the LAG descriptor table).
637 * Access: RO
638 */
639 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
640 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
641
mlxsw_reg_sfn_mac_lag_unpack(char * payload,int rec_index,char * mac,u16 * p_vid,u16 * p_lag_id)642 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
643 char *mac, u16 *p_vid,
644 u16 *p_lag_id)
645 {
646 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
647 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
648 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
649 }
650
651 /* SPMS - Switch Port MSTP/RSTP State Register
652 * -------------------------------------------
653 * Configures the spanning tree state of a physical port.
654 */
655 #define MLXSW_REG_SPMS_ID 0x200D
656 #define MLXSW_REG_SPMS_LEN 0x404
657
658 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
659
660 /* reg_spms_local_port
661 * Local port number.
662 * Access: Index
663 */
664 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
665
666 enum mlxsw_reg_spms_state {
667 MLXSW_REG_SPMS_STATE_NO_CHANGE,
668 MLXSW_REG_SPMS_STATE_DISCARDING,
669 MLXSW_REG_SPMS_STATE_LEARNING,
670 MLXSW_REG_SPMS_STATE_FORWARDING,
671 };
672
673 /* reg_spms_state
674 * Spanning tree state of each VLAN ID (VID) of the local port.
675 * 0 - Do not change spanning tree state (used only when writing).
676 * 1 - Discarding. No learning or forwarding to/from this port (default).
677 * 2 - Learning. Port is learning, but not forwarding.
678 * 3 - Forwarding. Port is learning and forwarding.
679 * Access: RW
680 */
681 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
682
mlxsw_reg_spms_pack(char * payload,u8 local_port)683 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
684 {
685 MLXSW_REG_ZERO(spms, payload);
686 mlxsw_reg_spms_local_port_set(payload, local_port);
687 }
688
mlxsw_reg_spms_vid_pack(char * payload,u16 vid,enum mlxsw_reg_spms_state state)689 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
690 enum mlxsw_reg_spms_state state)
691 {
692 mlxsw_reg_spms_state_set(payload, vid, state);
693 }
694
695 /* SPVID - Switch Port VID
696 * -----------------------
697 * The switch port VID configures the default VID for a port.
698 */
699 #define MLXSW_REG_SPVID_ID 0x200E
700 #define MLXSW_REG_SPVID_LEN 0x08
701
702 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
703
704 /* reg_spvid_local_port
705 * Local port number.
706 * Access: Index
707 */
708 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
709
710 /* reg_spvid_sub_port
711 * Virtual port within the physical port.
712 * Should be set to 0 when virtual ports are not enabled on the port.
713 * Access: Index
714 */
715 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
716
717 /* reg_spvid_pvid
718 * Port default VID
719 * Access: RW
720 */
721 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
722
mlxsw_reg_spvid_pack(char * payload,u8 local_port,u16 pvid)723 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
724 {
725 MLXSW_REG_ZERO(spvid, payload);
726 mlxsw_reg_spvid_local_port_set(payload, local_port);
727 mlxsw_reg_spvid_pvid_set(payload, pvid);
728 }
729
730 /* SPVM - Switch Port VLAN Membership
731 * ----------------------------------
732 * The Switch Port VLAN Membership register configures the VLAN membership
733 * of a port in a VLAN denoted by VID. VLAN membership is managed per
734 * virtual port. The register can be used to add and remove VID(s) from a port.
735 */
736 #define MLXSW_REG_SPVM_ID 0x200F
737 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
738 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
739 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
740 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
741 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
742
743 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
744
745 /* reg_spvm_pt
746 * Priority tagged. If this bit is set, packets forwarded to the port with
747 * untagged VLAN membership (u bit is set) will be tagged with priority tag
748 * (VID=0)
749 * Access: RW
750 */
751 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
752
753 /* reg_spvm_pte
754 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
755 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
756 * Access: WO
757 */
758 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
759
760 /* reg_spvm_local_port
761 * Local port number.
762 * Access: Index
763 */
764 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
765
766 /* reg_spvm_sub_port
767 * Virtual port within the physical port.
768 * Should be set to 0 when virtual ports are not enabled on the port.
769 * Access: Index
770 */
771 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
772
773 /* reg_spvm_num_rec
774 * Number of records to update. Each record contains: i, e, u, vid.
775 * Access: OP
776 */
777 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
778
779 /* reg_spvm_rec_i
780 * Ingress membership in VLAN ID.
781 * Access: Index
782 */
783 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
784 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
785 MLXSW_REG_SPVM_REC_LEN, 0, false);
786
787 /* reg_spvm_rec_e
788 * Egress membership in VLAN ID.
789 * Access: Index
790 */
791 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
792 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
793 MLXSW_REG_SPVM_REC_LEN, 0, false);
794
795 /* reg_spvm_rec_u
796 * Untagged - port is an untagged member - egress transmission uses untagged
797 * frames on VID<n>
798 * Access: Index
799 */
800 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
801 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
802 MLXSW_REG_SPVM_REC_LEN, 0, false);
803
804 /* reg_spvm_rec_vid
805 * Egress membership in VLAN ID.
806 * Access: Index
807 */
808 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
809 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
810 MLXSW_REG_SPVM_REC_LEN, 0, false);
811
mlxsw_reg_spvm_pack(char * payload,u8 local_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)812 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
813 u16 vid_begin, u16 vid_end,
814 bool is_member, bool untagged)
815 {
816 int size = vid_end - vid_begin + 1;
817 int i;
818
819 MLXSW_REG_ZERO(spvm, payload);
820 mlxsw_reg_spvm_local_port_set(payload, local_port);
821 mlxsw_reg_spvm_num_rec_set(payload, size);
822
823 for (i = 0; i < size; i++) {
824 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
825 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
826 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
827 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
828 }
829 }
830
831 /* SPAFT - Switch Port Acceptable Frame Types
832 * ------------------------------------------
833 * The Switch Port Acceptable Frame Types register configures the frame
834 * admittance of the port.
835 */
836 #define MLXSW_REG_SPAFT_ID 0x2010
837 #define MLXSW_REG_SPAFT_LEN 0x08
838
839 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
840
841 /* reg_spaft_local_port
842 * Local port number.
843 * Access: Index
844 *
845 * Note: CPU port is not supported (all tag types are allowed).
846 */
847 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
848
849 /* reg_spaft_sub_port
850 * Virtual port within the physical port.
851 * Should be set to 0 when virtual ports are not enabled on the port.
852 * Access: RW
853 */
854 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
855
856 /* reg_spaft_allow_untagged
857 * When set, untagged frames on the ingress are allowed (default).
858 * Access: RW
859 */
860 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
861
862 /* reg_spaft_allow_prio_tagged
863 * When set, priority tagged frames on the ingress are allowed (default).
864 * Access: RW
865 */
866 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
867
868 /* reg_spaft_allow_tagged
869 * When set, tagged frames on the ingress are allowed (default).
870 * Access: RW
871 */
872 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
873
mlxsw_reg_spaft_pack(char * payload,u8 local_port,bool allow_untagged)874 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
875 bool allow_untagged)
876 {
877 MLXSW_REG_ZERO(spaft, payload);
878 mlxsw_reg_spaft_local_port_set(payload, local_port);
879 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
880 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
881 mlxsw_reg_spaft_allow_tagged_set(payload, true);
882 }
883
884 /* SFGC - Switch Flooding Group Configuration
885 * ------------------------------------------
886 * The following register controls the association of flooding tables and MIDs
887 * to packet types used for flooding.
888 */
889 #define MLXSW_REG_SFGC_ID 0x2011
890 #define MLXSW_REG_SFGC_LEN 0x10
891
892 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
893
894 enum mlxsw_reg_sfgc_type {
895 MLXSW_REG_SFGC_TYPE_BROADCAST,
896 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
897 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
898 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
899 MLXSW_REG_SFGC_TYPE_RESERVED,
900 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
901 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
902 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
903 MLXSW_REG_SFGC_TYPE_MAX,
904 };
905
906 /* reg_sfgc_type
907 * The traffic type to reach the flooding table.
908 * Access: Index
909 */
910 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
911
912 enum mlxsw_reg_sfgc_bridge_type {
913 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
914 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
915 };
916
917 /* reg_sfgc_bridge_type
918 * Access: Index
919 *
920 * Note: SwitchX-2 only supports 802.1Q mode.
921 */
922 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
923
924 enum mlxsw_flood_table_type {
925 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
926 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
927 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
928 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
929 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
930 };
931
932 /* reg_sfgc_table_type
933 * See mlxsw_flood_table_type
934 * Access: RW
935 *
936 * Note: FID offset and FID types are not supported in SwitchX-2.
937 */
938 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
939
940 /* reg_sfgc_flood_table
941 * Flooding table index to associate with the specific type on the specific
942 * switch partition.
943 * Access: RW
944 */
945 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
946
947 /* reg_sfgc_mid
948 * The multicast ID for the swid. Not supported for Spectrum
949 * Access: RW
950 */
951 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
952
953 /* reg_sfgc_counter_set_type
954 * Counter Set Type for flow counters.
955 * Access: RW
956 */
957 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
958
959 /* reg_sfgc_counter_index
960 * Counter Index for flow counters.
961 * Access: RW
962 */
963 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
964
965 static inline void
mlxsw_reg_sfgc_pack(char * payload,enum mlxsw_reg_sfgc_type type,enum mlxsw_reg_sfgc_bridge_type bridge_type,enum mlxsw_flood_table_type table_type,unsigned int flood_table)966 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
967 enum mlxsw_reg_sfgc_bridge_type bridge_type,
968 enum mlxsw_flood_table_type table_type,
969 unsigned int flood_table)
970 {
971 MLXSW_REG_ZERO(sfgc, payload);
972 mlxsw_reg_sfgc_type_set(payload, type);
973 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
974 mlxsw_reg_sfgc_table_type_set(payload, table_type);
975 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
976 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
977 }
978
979 /* SFTR - Switch Flooding Table Register
980 * -------------------------------------
981 * The switch flooding table is used for flooding packet replication. The table
982 * defines a bit mask of ports for packet replication.
983 */
984 #define MLXSW_REG_SFTR_ID 0x2012
985 #define MLXSW_REG_SFTR_LEN 0x420
986
987 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
988
989 /* reg_sftr_swid
990 * Switch partition ID with which to associate the port.
991 * Access: Index
992 */
993 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
994
995 /* reg_sftr_flood_table
996 * Flooding table index to associate with the specific type on the specific
997 * switch partition.
998 * Access: Index
999 */
1000 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1001
1002 /* reg_sftr_index
1003 * Index. Used as an index into the Flooding Table in case the table is
1004 * configured to use VID / FID or FID Offset.
1005 * Access: Index
1006 */
1007 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1008
1009 /* reg_sftr_table_type
1010 * See mlxsw_flood_table_type
1011 * Access: RW
1012 */
1013 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1014
1015 /* reg_sftr_range
1016 * Range of entries to update
1017 * Access: Index
1018 */
1019 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1020
1021 /* reg_sftr_port
1022 * Local port membership (1 bit per port).
1023 * Access: RW
1024 */
1025 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1026
1027 /* reg_sftr_cpu_port_mask
1028 * CPU port mask (1 bit per port).
1029 * Access: W
1030 */
1031 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1032
mlxsw_reg_sftr_pack(char * payload,unsigned int flood_table,unsigned int index,enum mlxsw_flood_table_type table_type,unsigned int range,u8 port,bool set)1033 static inline void mlxsw_reg_sftr_pack(char *payload,
1034 unsigned int flood_table,
1035 unsigned int index,
1036 enum mlxsw_flood_table_type table_type,
1037 unsigned int range, u8 port, bool set)
1038 {
1039 MLXSW_REG_ZERO(sftr, payload);
1040 mlxsw_reg_sftr_swid_set(payload, 0);
1041 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1042 mlxsw_reg_sftr_index_set(payload, index);
1043 mlxsw_reg_sftr_table_type_set(payload, table_type);
1044 mlxsw_reg_sftr_range_set(payload, range);
1045 mlxsw_reg_sftr_port_set(payload, port, set);
1046 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1047 }
1048
1049 /* SFDF - Switch Filtering DB Flush
1050 * --------------------------------
1051 * The switch filtering DB flush register is used to flush the FDB.
1052 * Note that FDB notifications are flushed as well.
1053 */
1054 #define MLXSW_REG_SFDF_ID 0x2013
1055 #define MLXSW_REG_SFDF_LEN 0x14
1056
1057 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1058
1059 /* reg_sfdf_swid
1060 * Switch partition ID.
1061 * Access: Index
1062 */
1063 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1064
1065 enum mlxsw_reg_sfdf_flush_type {
1066 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1067 MLXSW_REG_SFDF_FLUSH_PER_FID,
1068 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1069 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1070 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1071 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1072 };
1073
1074 /* reg_sfdf_flush_type
1075 * Flush type.
1076 * 0 - All SWID dynamic entries are flushed.
1077 * 1 - All FID dynamic entries are flushed.
1078 * 2 - All dynamic entries pointing to port are flushed.
1079 * 3 - All FID dynamic entries pointing to port are flushed.
1080 * 4 - All dynamic entries pointing to LAG are flushed.
1081 * 5 - All FID dynamic entries pointing to LAG are flushed.
1082 * Access: RW
1083 */
1084 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1085
1086 /* reg_sfdf_flush_static
1087 * Static.
1088 * 0 - Flush only dynamic entries.
1089 * 1 - Flush both dynamic and static entries.
1090 * Access: RW
1091 */
1092 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1093
mlxsw_reg_sfdf_pack(char * payload,enum mlxsw_reg_sfdf_flush_type type)1094 static inline void mlxsw_reg_sfdf_pack(char *payload,
1095 enum mlxsw_reg_sfdf_flush_type type)
1096 {
1097 MLXSW_REG_ZERO(sfdf, payload);
1098 mlxsw_reg_sfdf_flush_type_set(payload, type);
1099 mlxsw_reg_sfdf_flush_static_set(payload, true);
1100 }
1101
1102 /* reg_sfdf_fid
1103 * FID to flush.
1104 * Access: RW
1105 */
1106 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1107
1108 /* reg_sfdf_system_port
1109 * Port to flush.
1110 * Access: RW
1111 */
1112 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1113
1114 /* reg_sfdf_port_fid_system_port
1115 * Port to flush, pointed to by FID.
1116 * Access: RW
1117 */
1118 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1119
1120 /* reg_sfdf_lag_id
1121 * LAG ID to flush.
1122 * Access: RW
1123 */
1124 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1125
1126 /* reg_sfdf_lag_fid_lag_id
1127 * LAG ID to flush, pointed to by FID.
1128 * Access: RW
1129 */
1130 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1131
1132 /* SLDR - Switch LAG Descriptor Register
1133 * -----------------------------------------
1134 * The switch LAG descriptor register is populated by LAG descriptors.
1135 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1136 * max_lag-1.
1137 */
1138 #define MLXSW_REG_SLDR_ID 0x2014
1139 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1140
1141 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1142
1143 enum mlxsw_reg_sldr_op {
1144 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1145 MLXSW_REG_SLDR_OP_LAG_CREATE,
1146 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1147 /* Ports that appear in the list have the Distributor enabled */
1148 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1149 /* Removes ports from the disributor list */
1150 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1151 };
1152
1153 /* reg_sldr_op
1154 * Operation.
1155 * Access: RW
1156 */
1157 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1158
1159 /* reg_sldr_lag_id
1160 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1161 * Access: Index
1162 */
1163 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1164
mlxsw_reg_sldr_lag_create_pack(char * payload,u8 lag_id)1165 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1166 {
1167 MLXSW_REG_ZERO(sldr, payload);
1168 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1169 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1170 }
1171
mlxsw_reg_sldr_lag_destroy_pack(char * payload,u8 lag_id)1172 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1173 {
1174 MLXSW_REG_ZERO(sldr, payload);
1175 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1176 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1177 }
1178
1179 /* reg_sldr_num_ports
1180 * The number of member ports of the LAG.
1181 * Reserved for Create / Destroy operations
1182 * For Add / Remove operations - indicates the number of ports in the list.
1183 * Access: RW
1184 */
1185 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1186
1187 /* reg_sldr_system_port
1188 * System port.
1189 * Access: RW
1190 */
1191 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1192
mlxsw_reg_sldr_lag_add_port_pack(char * payload,u8 lag_id,u8 local_port)1193 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1194 u8 local_port)
1195 {
1196 MLXSW_REG_ZERO(sldr, payload);
1197 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1198 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1199 mlxsw_reg_sldr_num_ports_set(payload, 1);
1200 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1201 }
1202
mlxsw_reg_sldr_lag_remove_port_pack(char * payload,u8 lag_id,u8 local_port)1203 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1204 u8 local_port)
1205 {
1206 MLXSW_REG_ZERO(sldr, payload);
1207 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1208 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1209 mlxsw_reg_sldr_num_ports_set(payload, 1);
1210 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1211 }
1212
1213 /* SLCR - Switch LAG Configuration 2 Register
1214 * -------------------------------------------
1215 * The Switch LAG Configuration register is used for configuring the
1216 * LAG properties of the switch.
1217 */
1218 #define MLXSW_REG_SLCR_ID 0x2015
1219 #define MLXSW_REG_SLCR_LEN 0x10
1220
1221 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1222
1223 enum mlxsw_reg_slcr_pp {
1224 /* Global Configuration (for all ports) */
1225 MLXSW_REG_SLCR_PP_GLOBAL,
1226 /* Per port configuration, based on local_port field */
1227 MLXSW_REG_SLCR_PP_PER_PORT,
1228 };
1229
1230 /* reg_slcr_pp
1231 * Per Port Configuration
1232 * Note: Reading at Global mode results in reading port 1 configuration.
1233 * Access: Index
1234 */
1235 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1236
1237 /* reg_slcr_local_port
1238 * Local port number
1239 * Supported from CPU port
1240 * Not supported from router port
1241 * Reserved when pp = Global Configuration
1242 * Access: Index
1243 */
1244 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1245
1246 enum mlxsw_reg_slcr_type {
1247 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1248 MLXSW_REG_SLCR_TYPE_XOR,
1249 MLXSW_REG_SLCR_TYPE_RANDOM,
1250 };
1251
1252 /* reg_slcr_type
1253 * Hash type
1254 * Access: RW
1255 */
1256 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1257
1258 /* Ingress port */
1259 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1260 /* SMAC - for IPv4 and IPv6 packets */
1261 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1262 /* SMAC - for non-IP packets */
1263 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1264 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1265 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1266 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1267 /* DMAC - for IPv4 and IPv6 packets */
1268 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1269 /* DMAC - for non-IP packets */
1270 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1271 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1272 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1273 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1274 /* Ethertype - for IPv4 and IPv6 packets */
1275 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1276 /* Ethertype - for non-IP packets */
1277 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1278 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1279 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1280 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1281 /* VLAN ID - for IPv4 and IPv6 packets */
1282 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1283 /* VLAN ID - for non-IP packets */
1284 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1285 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1286 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1287 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1288 /* Source IP address (can be IPv4 or IPv6) */
1289 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1290 /* Destination IP address (can be IPv4 or IPv6) */
1291 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1292 /* TCP/UDP source port */
1293 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1294 /* TCP/UDP destination port*/
1295 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1296 /* IPv4 Protocol/IPv6 Next Header */
1297 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1298 /* IPv6 Flow label */
1299 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1300 /* SID - FCoE source ID */
1301 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1302 /* DID - FCoE destination ID */
1303 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1304 /* OXID - FCoE originator exchange ID */
1305 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1306 /* Destination QP number - for RoCE packets */
1307 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1308
1309 /* reg_slcr_lag_hash
1310 * LAG hashing configuration. This is a bitmask, in which each set
1311 * bit includes the corresponding item in the LAG hash calculation.
1312 * The default lag_hash contains SMAC, DMAC, VLANID and
1313 * Ethertype (for all packet types).
1314 * Access: RW
1315 */
1316 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1317
mlxsw_reg_slcr_pack(char * payload,u16 lag_hash)1318 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1319 {
1320 MLXSW_REG_ZERO(slcr, payload);
1321 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1322 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1323 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1324 }
1325
1326 /* SLCOR - Switch LAG Collector Register
1327 * -------------------------------------
1328 * The Switch LAG Collector register controls the Local Port membership
1329 * in a LAG and enablement of the collector.
1330 */
1331 #define MLXSW_REG_SLCOR_ID 0x2016
1332 #define MLXSW_REG_SLCOR_LEN 0x10
1333
1334 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1335
1336 enum mlxsw_reg_slcor_col {
1337 /* Port is added with collector disabled */
1338 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1339 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1340 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1341 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1342 };
1343
1344 /* reg_slcor_col
1345 * Collector configuration
1346 * Access: RW
1347 */
1348 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1349
1350 /* reg_slcor_local_port
1351 * Local port number
1352 * Not supported for CPU port
1353 * Access: Index
1354 */
1355 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1356
1357 /* reg_slcor_lag_id
1358 * LAG Identifier. Index into the LAG descriptor table.
1359 * Access: Index
1360 */
1361 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1362
1363 /* reg_slcor_port_index
1364 * Port index in the LAG list. Only valid on Add Port to LAG col.
1365 * Valid range is from 0 to cap_max_lag_members-1
1366 * Access: RW
1367 */
1368 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1369
mlxsw_reg_slcor_pack(char * payload,u8 local_port,u16 lag_id,enum mlxsw_reg_slcor_col col)1370 static inline void mlxsw_reg_slcor_pack(char *payload,
1371 u8 local_port, u16 lag_id,
1372 enum mlxsw_reg_slcor_col col)
1373 {
1374 MLXSW_REG_ZERO(slcor, payload);
1375 mlxsw_reg_slcor_col_set(payload, col);
1376 mlxsw_reg_slcor_local_port_set(payload, local_port);
1377 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1378 }
1379
mlxsw_reg_slcor_port_add_pack(char * payload,u8 local_port,u16 lag_id,u8 port_index)1380 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1381 u8 local_port, u16 lag_id,
1382 u8 port_index)
1383 {
1384 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1385 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1386 mlxsw_reg_slcor_port_index_set(payload, port_index);
1387 }
1388
mlxsw_reg_slcor_port_remove_pack(char * payload,u8 local_port,u16 lag_id)1389 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1390 u8 local_port, u16 lag_id)
1391 {
1392 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1393 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1394 }
1395
mlxsw_reg_slcor_col_enable_pack(char * payload,u8 local_port,u16 lag_id)1396 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1397 u8 local_port, u16 lag_id)
1398 {
1399 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1400 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1401 }
1402
mlxsw_reg_slcor_col_disable_pack(char * payload,u8 local_port,u16 lag_id)1403 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1404 u8 local_port, u16 lag_id)
1405 {
1406 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1407 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1408 }
1409
1410 /* SPMLR - Switch Port MAC Learning Register
1411 * -----------------------------------------
1412 * Controls the Switch MAC learning policy per port.
1413 */
1414 #define MLXSW_REG_SPMLR_ID 0x2018
1415 #define MLXSW_REG_SPMLR_LEN 0x8
1416
1417 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1418
1419 /* reg_spmlr_local_port
1420 * Local port number.
1421 * Access: Index
1422 */
1423 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1424
1425 /* reg_spmlr_sub_port
1426 * Virtual port within the physical port.
1427 * Should be set to 0 when virtual ports are not enabled on the port.
1428 * Access: Index
1429 */
1430 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1431
1432 enum mlxsw_reg_spmlr_learn_mode {
1433 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1434 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1435 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1436 };
1437
1438 /* reg_spmlr_learn_mode
1439 * Learning mode on the port.
1440 * 0 - Learning disabled.
1441 * 2 - Learning enabled.
1442 * 3 - Security mode.
1443 *
1444 * In security mode the switch does not learn MACs on the port, but uses the
1445 * SMAC to see if it exists on another ingress port. If so, the packet is
1446 * classified as a bad packet and is discarded unless the software registers
1447 * to receive port security error packets usign HPKT.
1448 */
1449 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1450
mlxsw_reg_spmlr_pack(char * payload,u8 local_port,enum mlxsw_reg_spmlr_learn_mode mode)1451 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1452 enum mlxsw_reg_spmlr_learn_mode mode)
1453 {
1454 MLXSW_REG_ZERO(spmlr, payload);
1455 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1456 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1457 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1458 }
1459
1460 /* SVFA - Switch VID to FID Allocation Register
1461 * --------------------------------------------
1462 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1463 * virtualized ports.
1464 */
1465 #define MLXSW_REG_SVFA_ID 0x201C
1466 #define MLXSW_REG_SVFA_LEN 0x10
1467
1468 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1469
1470 /* reg_svfa_swid
1471 * Switch partition ID.
1472 * Access: Index
1473 */
1474 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1475
1476 /* reg_svfa_local_port
1477 * Local port number.
1478 * Access: Index
1479 *
1480 * Note: Reserved for 802.1Q FIDs.
1481 */
1482 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1483
1484 enum mlxsw_reg_svfa_mt {
1485 MLXSW_REG_SVFA_MT_VID_TO_FID,
1486 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1487 };
1488
1489 /* reg_svfa_mapping_table
1490 * Mapping table:
1491 * 0 - VID to FID
1492 * 1 - {Port, VID} to FID
1493 * Access: Index
1494 *
1495 * Note: Reserved for SwitchX-2.
1496 */
1497 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1498
1499 /* reg_svfa_v
1500 * Valid.
1501 * Valid if set.
1502 * Access: RW
1503 *
1504 * Note: Reserved for SwitchX-2.
1505 */
1506 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1507
1508 /* reg_svfa_fid
1509 * Filtering ID.
1510 * Access: RW
1511 */
1512 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1513
1514 /* reg_svfa_vid
1515 * VLAN ID.
1516 * Access: Index
1517 */
1518 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1519
1520 /* reg_svfa_counter_set_type
1521 * Counter set type for flow counters.
1522 * Access: RW
1523 *
1524 * Note: Reserved for SwitchX-2.
1525 */
1526 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1527
1528 /* reg_svfa_counter_index
1529 * Counter index for flow counters.
1530 * Access: RW
1531 *
1532 * Note: Reserved for SwitchX-2.
1533 */
1534 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1535
mlxsw_reg_svfa_pack(char * payload,u8 local_port,enum mlxsw_reg_svfa_mt mt,bool valid,u16 fid,u16 vid)1536 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1537 enum mlxsw_reg_svfa_mt mt, bool valid,
1538 u16 fid, u16 vid)
1539 {
1540 MLXSW_REG_ZERO(svfa, payload);
1541 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1542 mlxsw_reg_svfa_swid_set(payload, 0);
1543 mlxsw_reg_svfa_local_port_set(payload, local_port);
1544 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1545 mlxsw_reg_svfa_v_set(payload, valid);
1546 mlxsw_reg_svfa_fid_set(payload, fid);
1547 mlxsw_reg_svfa_vid_set(payload, vid);
1548 }
1549
1550 /* SVPE - Switch Virtual-Port Enabling Register
1551 * --------------------------------------------
1552 * Enables port virtualization.
1553 */
1554 #define MLXSW_REG_SVPE_ID 0x201E
1555 #define MLXSW_REG_SVPE_LEN 0x4
1556
1557 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1558
1559 /* reg_svpe_local_port
1560 * Local port number
1561 * Access: Index
1562 *
1563 * Note: CPU port is not supported (uses VLAN mode only).
1564 */
1565 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1566
1567 /* reg_svpe_vp_en
1568 * Virtual port enable.
1569 * 0 - Disable, VLAN mode (VID to FID).
1570 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1571 * Access: RW
1572 */
1573 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1574
mlxsw_reg_svpe_pack(char * payload,u8 local_port,bool enable)1575 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1576 bool enable)
1577 {
1578 MLXSW_REG_ZERO(svpe, payload);
1579 mlxsw_reg_svpe_local_port_set(payload, local_port);
1580 mlxsw_reg_svpe_vp_en_set(payload, enable);
1581 }
1582
1583 /* SFMR - Switch FID Management Register
1584 * -------------------------------------
1585 * Creates and configures FIDs.
1586 */
1587 #define MLXSW_REG_SFMR_ID 0x201F
1588 #define MLXSW_REG_SFMR_LEN 0x18
1589
1590 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1591
1592 enum mlxsw_reg_sfmr_op {
1593 MLXSW_REG_SFMR_OP_CREATE_FID,
1594 MLXSW_REG_SFMR_OP_DESTROY_FID,
1595 };
1596
1597 /* reg_sfmr_op
1598 * Operation.
1599 * 0 - Create or edit FID.
1600 * 1 - Destroy FID.
1601 * Access: WO
1602 */
1603 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1604
1605 /* reg_sfmr_fid
1606 * Filtering ID.
1607 * Access: Index
1608 */
1609 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1610
1611 /* reg_sfmr_fid_offset
1612 * FID offset.
1613 * Used to point into the flooding table selected by SFGC register if
1614 * the table is of type FID-Offset. Otherwise, this field is reserved.
1615 * Access: RW
1616 */
1617 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1618
1619 /* reg_sfmr_vtfp
1620 * Valid Tunnel Flood Pointer.
1621 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1622 * Access: RW
1623 *
1624 * Note: Reserved for 802.1Q FIDs.
1625 */
1626 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1627
1628 /* reg_sfmr_nve_tunnel_flood_ptr
1629 * Underlay Flooding and BC Pointer.
1630 * Used as a pointer to the first entry of the group based link lists of
1631 * flooding or BC entries (for NVE tunnels).
1632 * Access: RW
1633 */
1634 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1635
1636 /* reg_sfmr_vv
1637 * VNI Valid.
1638 * If not set, then vni is reserved.
1639 * Access: RW
1640 *
1641 * Note: Reserved for 802.1Q FIDs.
1642 */
1643 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1644
1645 /* reg_sfmr_vni
1646 * Virtual Network Identifier.
1647 * Access: RW
1648 *
1649 * Note: A given VNI can only be assigned to one FID.
1650 */
1651 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1652
mlxsw_reg_sfmr_pack(char * payload,enum mlxsw_reg_sfmr_op op,u16 fid,u16 fid_offset)1653 static inline void mlxsw_reg_sfmr_pack(char *payload,
1654 enum mlxsw_reg_sfmr_op op, u16 fid,
1655 u16 fid_offset)
1656 {
1657 MLXSW_REG_ZERO(sfmr, payload);
1658 mlxsw_reg_sfmr_op_set(payload, op);
1659 mlxsw_reg_sfmr_fid_set(payload, fid);
1660 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1661 mlxsw_reg_sfmr_vtfp_set(payload, false);
1662 mlxsw_reg_sfmr_vv_set(payload, false);
1663 }
1664
1665 /* SPVMLR - Switch Port VLAN MAC Learning Register
1666 * -----------------------------------------------
1667 * Controls the switch MAC learning policy per {Port, VID}.
1668 */
1669 #define MLXSW_REG_SPVMLR_ID 0x2020
1670 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1671 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1672 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1673 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1674 MLXSW_REG_SPVMLR_REC_LEN * \
1675 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1676
1677 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1678
1679 /* reg_spvmlr_local_port
1680 * Local ingress port.
1681 * Access: Index
1682 *
1683 * Note: CPU port is not supported.
1684 */
1685 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1686
1687 /* reg_spvmlr_num_rec
1688 * Number of records to update.
1689 * Access: OP
1690 */
1691 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1692
1693 /* reg_spvmlr_rec_learn_enable
1694 * 0 - Disable learning for {Port, VID}.
1695 * 1 - Enable learning for {Port, VID}.
1696 * Access: RW
1697 */
1698 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1699 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1700
1701 /* reg_spvmlr_rec_vid
1702 * VLAN ID to be added/removed from port or for querying.
1703 * Access: Index
1704 */
1705 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1706 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1707
mlxsw_reg_spvmlr_pack(char * payload,u8 local_port,u16 vid_begin,u16 vid_end,bool learn_enable)1708 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1709 u16 vid_begin, u16 vid_end,
1710 bool learn_enable)
1711 {
1712 int num_rec = vid_end - vid_begin + 1;
1713 int i;
1714
1715 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1716
1717 MLXSW_REG_ZERO(spvmlr, payload);
1718 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1719 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1720
1721 for (i = 0; i < num_rec; i++) {
1722 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1723 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1724 }
1725 }
1726
1727 /* CWTP - Congetion WRED ECN TClass Profile
1728 * ----------------------------------------
1729 * Configures the profiles for queues of egress port and traffic class
1730 */
1731 #define MLXSW_REG_CWTP_ID 0x2802
1732 #define MLXSW_REG_CWTP_BASE_LEN 0x28
1733 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1734 #define MLXSW_REG_CWTP_LEN 0x40
1735
1736 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1737
1738 /* reg_cwtp_local_port
1739 * Local port number
1740 * Not supported for CPU port
1741 * Access: Index
1742 */
1743 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1744
1745 /* reg_cwtp_traffic_class
1746 * Traffic Class to configure
1747 * Access: Index
1748 */
1749 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1750
1751 /* reg_cwtp_profile_min
1752 * Minimum Average Queue Size of the profile in cells.
1753 * Access: RW
1754 */
1755 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1756 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1757
1758 /* reg_cwtp_profile_percent
1759 * Percentage of WRED and ECN marking for maximum Average Queue size
1760 * Range is 0 to 100, units of integer percentage
1761 * Access: RW
1762 */
1763 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1764 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1765
1766 /* reg_cwtp_profile_max
1767 * Maximum Average Queue size of the profile in cells
1768 * Access: RW
1769 */
1770 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1771 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1772
1773 #define MLXSW_REG_CWTP_MIN_VALUE 64
1774 #define MLXSW_REG_CWTP_MAX_PROFILE 2
1775 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1776
mlxsw_reg_cwtp_pack(char * payload,u8 local_port,u8 traffic_class)1777 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1778 u8 traffic_class)
1779 {
1780 int i;
1781
1782 MLXSW_REG_ZERO(cwtp, payload);
1783 mlxsw_reg_cwtp_local_port_set(payload, local_port);
1784 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1785
1786 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1787 mlxsw_reg_cwtp_profile_min_set(payload, i,
1788 MLXSW_REG_CWTP_MIN_VALUE);
1789 mlxsw_reg_cwtp_profile_max_set(payload, i,
1790 MLXSW_REG_CWTP_MIN_VALUE);
1791 }
1792 }
1793
1794 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1795
1796 static inline void
mlxsw_reg_cwtp_profile_pack(char * payload,u8 profile,u32 min,u32 max,u32 probability)1797 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1798 u32 probability)
1799 {
1800 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1801
1802 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1803 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1804 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1805 }
1806
1807 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1808 * ---------------------------------------------------
1809 * The CWTPM register maps each egress port and traffic class to profile num.
1810 */
1811 #define MLXSW_REG_CWTPM_ID 0x2803
1812 #define MLXSW_REG_CWTPM_LEN 0x44
1813
1814 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1815
1816 /* reg_cwtpm_local_port
1817 * Local port number
1818 * Not supported for CPU port
1819 * Access: Index
1820 */
1821 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1822
1823 /* reg_cwtpm_traffic_class
1824 * Traffic Class to configure
1825 * Access: Index
1826 */
1827 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1828
1829 /* reg_cwtpm_ew
1830 * Control enablement of WRED for traffic class:
1831 * 0 - Disable
1832 * 1 - Enable
1833 * Access: RW
1834 */
1835 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1836
1837 /* reg_cwtpm_ee
1838 * Control enablement of ECN for traffic class:
1839 * 0 - Disable
1840 * 1 - Enable
1841 * Access: RW
1842 */
1843 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1844
1845 /* reg_cwtpm_tcp_g
1846 * TCP Green Profile.
1847 * Index of the profile within {port, traffic class} to use.
1848 * 0 for disabling both WRED and ECN for this type of traffic.
1849 * Access: RW
1850 */
1851 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1852
1853 /* reg_cwtpm_tcp_y
1854 * TCP Yellow Profile.
1855 * Index of the profile within {port, traffic class} to use.
1856 * 0 for disabling both WRED and ECN for this type of traffic.
1857 * Access: RW
1858 */
1859 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1860
1861 /* reg_cwtpm_tcp_r
1862 * TCP Red Profile.
1863 * Index of the profile within {port, traffic class} to use.
1864 * 0 for disabling both WRED and ECN for this type of traffic.
1865 * Access: RW
1866 */
1867 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
1868
1869 /* reg_cwtpm_ntcp_g
1870 * Non-TCP Green Profile.
1871 * Index of the profile within {port, traffic class} to use.
1872 * 0 for disabling both WRED and ECN for this type of traffic.
1873 * Access: RW
1874 */
1875 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
1876
1877 /* reg_cwtpm_ntcp_y
1878 * Non-TCP Yellow Profile.
1879 * Index of the profile within {port, traffic class} to use.
1880 * 0 for disabling both WRED and ECN for this type of traffic.
1881 * Access: RW
1882 */
1883 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
1884
1885 /* reg_cwtpm_ntcp_r
1886 * Non-TCP Red Profile.
1887 * Index of the profile within {port, traffic class} to use.
1888 * 0 for disabling both WRED and ECN for this type of traffic.
1889 * Access: RW
1890 */
1891 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
1892
1893 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
1894
mlxsw_reg_cwtpm_pack(char * payload,u8 local_port,u8 traffic_class,u8 profile,bool wred,bool ecn)1895 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
1896 u8 traffic_class, u8 profile,
1897 bool wred, bool ecn)
1898 {
1899 MLXSW_REG_ZERO(cwtpm, payload);
1900 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
1901 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
1902 mlxsw_reg_cwtpm_ew_set(payload, wred);
1903 mlxsw_reg_cwtpm_ee_set(payload, ecn);
1904 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
1905 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
1906 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
1907 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
1908 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
1909 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
1910 }
1911
1912 /* PGCR - Policy-Engine General Configuration Register
1913 * ---------------------------------------------------
1914 * This register configures general Policy-Engine settings.
1915 */
1916 #define MLXSW_REG_PGCR_ID 0x3001
1917 #define MLXSW_REG_PGCR_LEN 0x20
1918
1919 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
1920
1921 /* reg_pgcr_default_action_pointer_base
1922 * Default action pointer base. Each region has a default action pointer
1923 * which is equal to default_action_pointer_base + region_id.
1924 * Access: RW
1925 */
1926 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
1927
mlxsw_reg_pgcr_pack(char * payload,u32 pointer_base)1928 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
1929 {
1930 MLXSW_REG_ZERO(pgcr, payload);
1931 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
1932 }
1933
1934 /* PPBT - Policy-Engine Port Binding Table
1935 * ---------------------------------------
1936 * This register is used for configuration of the Port Binding Table.
1937 */
1938 #define MLXSW_REG_PPBT_ID 0x3002
1939 #define MLXSW_REG_PPBT_LEN 0x14
1940
1941 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
1942
1943 enum mlxsw_reg_pxbt_e {
1944 MLXSW_REG_PXBT_E_IACL,
1945 MLXSW_REG_PXBT_E_EACL,
1946 };
1947
1948 /* reg_ppbt_e
1949 * Access: Index
1950 */
1951 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
1952
1953 enum mlxsw_reg_pxbt_op {
1954 MLXSW_REG_PXBT_OP_BIND,
1955 MLXSW_REG_PXBT_OP_UNBIND,
1956 };
1957
1958 /* reg_ppbt_op
1959 * Access: RW
1960 */
1961 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
1962
1963 /* reg_ppbt_local_port
1964 * Local port. Not including CPU port.
1965 * Access: Index
1966 */
1967 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
1968
1969 /* reg_ppbt_g
1970 * group - When set, the binding is of an ACL group. When cleared,
1971 * the binding is of an ACL.
1972 * Must be set to 1 for Spectrum.
1973 * Access: RW
1974 */
1975 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
1976
1977 /* reg_ppbt_acl_info
1978 * ACL/ACL group identifier. If the g bit is set, this field should hold
1979 * the acl_group_id, else it should hold the acl_id.
1980 * Access: RW
1981 */
1982 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
1983
mlxsw_reg_ppbt_pack(char * payload,enum mlxsw_reg_pxbt_e e,enum mlxsw_reg_pxbt_op op,u8 local_port,u16 acl_info)1984 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
1985 enum mlxsw_reg_pxbt_op op,
1986 u8 local_port, u16 acl_info)
1987 {
1988 MLXSW_REG_ZERO(ppbt, payload);
1989 mlxsw_reg_ppbt_e_set(payload, e);
1990 mlxsw_reg_ppbt_op_set(payload, op);
1991 mlxsw_reg_ppbt_local_port_set(payload, local_port);
1992 mlxsw_reg_ppbt_g_set(payload, true);
1993 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
1994 }
1995
1996 /* PACL - Policy-Engine ACL Register
1997 * ---------------------------------
1998 * This register is used for configuration of the ACL.
1999 */
2000 #define MLXSW_REG_PACL_ID 0x3004
2001 #define MLXSW_REG_PACL_LEN 0x70
2002
2003 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2004
2005 /* reg_pacl_v
2006 * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2007 * while the ACL is bounded to either a port, VLAN or ACL rule.
2008 * Access: RW
2009 */
2010 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2011
2012 /* reg_pacl_acl_id
2013 * An identifier representing the ACL (managed by software)
2014 * Range 0 .. cap_max_acl_regions - 1
2015 * Access: Index
2016 */
2017 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2018
2019 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2020
2021 /* reg_pacl_tcam_region_info
2022 * Opaque object that represents a TCAM region.
2023 * Obtained through PTAR register.
2024 * Access: RW
2025 */
2026 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2027 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2028
mlxsw_reg_pacl_pack(char * payload,u16 acl_id,bool valid,const char * tcam_region_info)2029 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2030 bool valid, const char *tcam_region_info)
2031 {
2032 MLXSW_REG_ZERO(pacl, payload);
2033 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2034 mlxsw_reg_pacl_v_set(payload, valid);
2035 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2036 }
2037
2038 /* PAGT - Policy-Engine ACL Group Table
2039 * ------------------------------------
2040 * This register is used for configuration of the ACL Group Table.
2041 */
2042 #define MLXSW_REG_PAGT_ID 0x3005
2043 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2044 #define MLXSW_REG_PAGT_ACL_LEN 4
2045 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2046 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2047 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2048
2049 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2050
2051 /* reg_pagt_size
2052 * Number of ACLs in the group.
2053 * Size 0 invalidates a group.
2054 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2055 * Total number of ACLs in all groups must be lower or equal
2056 * to cap_max_acl_tot_groups
2057 * Note: a group which is binded must not be invalidated
2058 * Access: Index
2059 */
2060 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2061
2062 /* reg_pagt_acl_group_id
2063 * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2064 * the ACL Group identifier (managed by software).
2065 * Access: Index
2066 */
2067 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2068
2069 /* reg_pagt_acl_id
2070 * ACL identifier
2071 * Access: RW
2072 */
2073 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2074
mlxsw_reg_pagt_pack(char * payload,u16 acl_group_id)2075 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2076 {
2077 MLXSW_REG_ZERO(pagt, payload);
2078 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2079 }
2080
mlxsw_reg_pagt_acl_id_pack(char * payload,int index,u16 acl_id)2081 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2082 u16 acl_id)
2083 {
2084 u8 size = mlxsw_reg_pagt_size_get(payload);
2085
2086 if (index >= size)
2087 mlxsw_reg_pagt_size_set(payload, index + 1);
2088 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2089 }
2090
2091 /* PTAR - Policy-Engine TCAM Allocation Register
2092 * ---------------------------------------------
2093 * This register is used for allocation of regions in the TCAM.
2094 * Note: Query method is not supported on this register.
2095 */
2096 #define MLXSW_REG_PTAR_ID 0x3006
2097 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2098 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2099 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2100 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2101 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2102
2103 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2104
2105 enum mlxsw_reg_ptar_op {
2106 /* allocate a TCAM region */
2107 MLXSW_REG_PTAR_OP_ALLOC,
2108 /* resize a TCAM region */
2109 MLXSW_REG_PTAR_OP_RESIZE,
2110 /* deallocate TCAM region */
2111 MLXSW_REG_PTAR_OP_FREE,
2112 /* test allocation */
2113 MLXSW_REG_PTAR_OP_TEST,
2114 };
2115
2116 /* reg_ptar_op
2117 * Access: OP
2118 */
2119 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2120
2121 /* reg_ptar_action_set_type
2122 * Type of action set to be used on this region.
2123 * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2124 * Access: WO
2125 */
2126 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2127
2128 enum mlxsw_reg_ptar_key_type {
2129 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2130 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2131 };
2132
2133 /* reg_ptar_key_type
2134 * TCAM key type for the region.
2135 * Access: WO
2136 */
2137 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2138
2139 /* reg_ptar_region_size
2140 * TCAM region size. When allocating/resizing this is the requested size,
2141 * the response is the actual size. Note that actual size may be
2142 * larger than requested.
2143 * Allowed range 1 .. cap_max_rules-1
2144 * Reserved during op deallocate.
2145 * Access: WO
2146 */
2147 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2148
2149 /* reg_ptar_region_id
2150 * Region identifier
2151 * Range 0 .. cap_max_regions-1
2152 * Access: Index
2153 */
2154 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2155
2156 /* reg_ptar_tcam_region_info
2157 * Opaque object that represents the TCAM region.
2158 * Returned when allocating a region.
2159 * Provided by software for ACL generation and region deallocation and resize.
2160 * Access: RW
2161 */
2162 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2163 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2164
2165 /* reg_ptar_flexible_key_id
2166 * Identifier of the Flexible Key.
2167 * Only valid if key_type == "FLEX_KEY"
2168 * The key size will be rounded up to one of the following values:
2169 * 9B, 18B, 36B, 54B.
2170 * This field is reserved for in resize operation.
2171 * Access: WO
2172 */
2173 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2174 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2175
mlxsw_reg_ptar_pack(char * payload,enum mlxsw_reg_ptar_op op,enum mlxsw_reg_ptar_key_type key_type,u16 region_size,u16 region_id,const char * tcam_region_info)2176 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2177 enum mlxsw_reg_ptar_key_type key_type,
2178 u16 region_size, u16 region_id,
2179 const char *tcam_region_info)
2180 {
2181 MLXSW_REG_ZERO(ptar, payload);
2182 mlxsw_reg_ptar_op_set(payload, op);
2183 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2184 mlxsw_reg_ptar_key_type_set(payload, key_type);
2185 mlxsw_reg_ptar_region_size_set(payload, region_size);
2186 mlxsw_reg_ptar_region_id_set(payload, region_id);
2187 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2188 }
2189
mlxsw_reg_ptar_key_id_pack(char * payload,int index,u16 key_id)2190 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2191 u16 key_id)
2192 {
2193 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2194 }
2195
mlxsw_reg_ptar_unpack(char * payload,char * tcam_region_info)2196 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2197 {
2198 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2199 }
2200
2201 /* PPBS - Policy-Engine Policy Based Switching Register
2202 * ----------------------------------------------------
2203 * This register retrieves and sets Policy Based Switching Table entries.
2204 */
2205 #define MLXSW_REG_PPBS_ID 0x300C
2206 #define MLXSW_REG_PPBS_LEN 0x14
2207
2208 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2209
2210 /* reg_ppbs_pbs_ptr
2211 * Index into the PBS table.
2212 * For Spectrum, the index points to the KVD Linear.
2213 * Access: Index
2214 */
2215 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2216
2217 /* reg_ppbs_system_port
2218 * Unique port identifier for the final destination of the packet.
2219 * Access: RW
2220 */
2221 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2222
mlxsw_reg_ppbs_pack(char * payload,u32 pbs_ptr,u16 system_port)2223 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2224 u16 system_port)
2225 {
2226 MLXSW_REG_ZERO(ppbs, payload);
2227 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2228 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2229 }
2230
2231 /* PRCR - Policy-Engine Rules Copy Register
2232 * ----------------------------------------
2233 * This register is used for accessing rules within a TCAM region.
2234 */
2235 #define MLXSW_REG_PRCR_ID 0x300D
2236 #define MLXSW_REG_PRCR_LEN 0x40
2237
2238 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2239
2240 enum mlxsw_reg_prcr_op {
2241 /* Move rules. Moves the rules from "tcam_region_info" starting
2242 * at offset "offset" to "dest_tcam_region_info"
2243 * at offset "dest_offset."
2244 */
2245 MLXSW_REG_PRCR_OP_MOVE,
2246 /* Copy rules. Copies the rules from "tcam_region_info" starting
2247 * at offset "offset" to "dest_tcam_region_info"
2248 * at offset "dest_offset."
2249 */
2250 MLXSW_REG_PRCR_OP_COPY,
2251 };
2252
2253 /* reg_prcr_op
2254 * Access: OP
2255 */
2256 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2257
2258 /* reg_prcr_offset
2259 * Offset within the source region to copy/move from.
2260 * Access: Index
2261 */
2262 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2263
2264 /* reg_prcr_size
2265 * The number of rules to copy/move.
2266 * Access: WO
2267 */
2268 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2269
2270 /* reg_prcr_tcam_region_info
2271 * Opaque object that represents the source TCAM region.
2272 * Access: Index
2273 */
2274 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2275 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2276
2277 /* reg_prcr_dest_offset
2278 * Offset within the source region to copy/move to.
2279 * Access: Index
2280 */
2281 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2282
2283 /* reg_prcr_dest_tcam_region_info
2284 * Opaque object that represents the destination TCAM region.
2285 * Access: Index
2286 */
2287 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2288 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2289
mlxsw_reg_prcr_pack(char * payload,enum mlxsw_reg_prcr_op op,const char * src_tcam_region_info,u16 src_offset,const char * dest_tcam_region_info,u16 dest_offset,u16 size)2290 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2291 const char *src_tcam_region_info,
2292 u16 src_offset,
2293 const char *dest_tcam_region_info,
2294 u16 dest_offset, u16 size)
2295 {
2296 MLXSW_REG_ZERO(prcr, payload);
2297 mlxsw_reg_prcr_op_set(payload, op);
2298 mlxsw_reg_prcr_offset_set(payload, src_offset);
2299 mlxsw_reg_prcr_size_set(payload, size);
2300 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2301 src_tcam_region_info);
2302 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2303 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2304 dest_tcam_region_info);
2305 }
2306
2307 /* PEFA - Policy-Engine Extended Flexible Action Register
2308 * ------------------------------------------------------
2309 * This register is used for accessing an extended flexible action entry
2310 * in the central KVD Linear Database.
2311 */
2312 #define MLXSW_REG_PEFA_ID 0x300F
2313 #define MLXSW_REG_PEFA_LEN 0xB0
2314
2315 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2316
2317 /* reg_pefa_index
2318 * Index in the KVD Linear Centralized Database.
2319 * Access: Index
2320 */
2321 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2322
2323 /* reg_pefa_a
2324 * Index in the KVD Linear Centralized Database.
2325 * Activity
2326 * For a new entry: set if ca=0, clear if ca=1
2327 * Set if a packet lookup has hit on the specific entry
2328 * Access: RO
2329 */
2330 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2331
2332 /* reg_pefa_ca
2333 * Clear activity
2334 * When write: activity is according to this field
2335 * When read: after reading the activity is cleared according to ca
2336 * Access: OP
2337 */
2338 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2339
2340 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2341
2342 /* reg_pefa_flex_action_set
2343 * Action-set to perform when rule is matched.
2344 * Must be zero padded if action set is shorter.
2345 * Access: RW
2346 */
2347 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2348
mlxsw_reg_pefa_pack(char * payload,u32 index,bool ca,const char * flex_action_set)2349 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2350 const char *flex_action_set)
2351 {
2352 MLXSW_REG_ZERO(pefa, payload);
2353 mlxsw_reg_pefa_index_set(payload, index);
2354 mlxsw_reg_pefa_ca_set(payload, ca);
2355 if (flex_action_set)
2356 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2357 flex_action_set);
2358 }
2359
mlxsw_reg_pefa_unpack(char * payload,bool * p_a)2360 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2361 {
2362 *p_a = mlxsw_reg_pefa_a_get(payload);
2363 }
2364
2365 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2366 * -----------------------------------------------------
2367 * This register is used for accessing rules within a TCAM region.
2368 * It is a new version of PTCE in order to support wider key,
2369 * mask and action within a TCAM region. This register is not supported
2370 * by SwitchX and SwitchX-2.
2371 */
2372 #define MLXSW_REG_PTCE2_ID 0x3017
2373 #define MLXSW_REG_PTCE2_LEN 0x1D8
2374
2375 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2376
2377 /* reg_ptce2_v
2378 * Valid.
2379 * Access: RW
2380 */
2381 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2382
2383 /* reg_ptce2_a
2384 * Activity. Set if a packet lookup has hit on the specific entry.
2385 * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2386 * Access: RO
2387 */
2388 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2389
2390 enum mlxsw_reg_ptce2_op {
2391 /* Read operation. */
2392 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2393 /* clear on read operation. Used to read entry
2394 * and clear Activity bit.
2395 */
2396 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2397 /* Write operation. Used to write a new entry to the table.
2398 * All R/W fields are relevant for new entry. Activity bit is set
2399 * for new entries - Note write with v = 0 will delete the entry.
2400 */
2401 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2402 /* Update action. Only action set will be updated. */
2403 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2404 /* Clear activity. A bit is cleared for the entry. */
2405 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2406 };
2407
2408 /* reg_ptce2_op
2409 * Access: OP
2410 */
2411 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2412
2413 /* reg_ptce2_offset
2414 * Access: Index
2415 */
2416 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2417
2418 /* reg_ptce2_priority
2419 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2420 * Note: priority does not have to be unique per rule.
2421 * Within a region, higher priority should have lower offset (no limitation
2422 * between regions in a multi-region).
2423 * Access: RW
2424 */
2425 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2426
2427 /* reg_ptce2_tcam_region_info
2428 * Opaque object that represents the TCAM region.
2429 * Access: Index
2430 */
2431 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2432 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2433
2434 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2435
2436 /* reg_ptce2_flex_key_blocks
2437 * ACL Key.
2438 * Access: RW
2439 */
2440 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2441 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2442
2443 /* reg_ptce2_mask
2444 * mask- in the same size as key. A bit that is set directs the TCAM
2445 * to compare the corresponding bit in key. A bit that is clear directs
2446 * the TCAM to ignore the corresponding bit in key.
2447 * Access: RW
2448 */
2449 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2450 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2451
2452 /* reg_ptce2_flex_action_set
2453 * ACL action set.
2454 * Access: RW
2455 */
2456 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2457 MLXSW_REG_FLEX_ACTION_SET_LEN);
2458
mlxsw_reg_ptce2_pack(char * payload,bool valid,enum mlxsw_reg_ptce2_op op,const char * tcam_region_info,u16 offset,u32 priority)2459 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2460 enum mlxsw_reg_ptce2_op op,
2461 const char *tcam_region_info,
2462 u16 offset, u32 priority)
2463 {
2464 MLXSW_REG_ZERO(ptce2, payload);
2465 mlxsw_reg_ptce2_v_set(payload, valid);
2466 mlxsw_reg_ptce2_op_set(payload, op);
2467 mlxsw_reg_ptce2_offset_set(payload, offset);
2468 mlxsw_reg_ptce2_priority_set(payload, priority);
2469 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2470 }
2471
2472 /* PERPT - Policy-Engine ERP Table Register
2473 * ----------------------------------------
2474 * This register adds and removes eRPs from the eRP table.
2475 */
2476 #define MLXSW_REG_PERPT_ID 0x3021
2477 #define MLXSW_REG_PERPT_LEN 0x80
2478
2479 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2480
2481 /* reg_perpt_erpt_bank
2482 * eRP table bank.
2483 * Range 0 .. cap_max_erp_table_banks - 1
2484 * Access: Index
2485 */
2486 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2487
2488 /* reg_perpt_erpt_index
2489 * Index to eRP table within the eRP bank.
2490 * Range is 0 .. cap_max_erp_table_bank_size - 1
2491 * Access: Index
2492 */
2493 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2494
2495 enum mlxsw_reg_perpt_key_size {
2496 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2497 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2498 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2499 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2500 };
2501
2502 /* reg_perpt_key_size
2503 * Access: OP
2504 */
2505 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2506
2507 /* reg_perpt_bf_bypass
2508 * 0 - The eRP is used only if bloom filter state is set for the given
2509 * rule.
2510 * 1 - The eRP is used regardless of bloom filter state.
2511 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2512 * Access: RW
2513 */
2514 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2515
2516 /* reg_perpt_erp_id
2517 * eRP ID for use by the rules.
2518 * Access: RW
2519 */
2520 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2521
2522 /* reg_perpt_erpt_base_bank
2523 * Base eRP table bank, points to head of erp_vector
2524 * Range is 0 .. cap_max_erp_table_banks - 1
2525 * Access: OP
2526 */
2527 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2528
2529 /* reg_perpt_erpt_base_index
2530 * Base index to eRP table within the eRP bank
2531 * Range is 0 .. cap_max_erp_table_bank_size - 1
2532 * Access: OP
2533 */
2534 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2535
2536 /* reg_perpt_erp_index_in_vector
2537 * eRP index in the vector.
2538 * Access: OP
2539 */
2540 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2541
2542 /* reg_perpt_erp_vector
2543 * eRP vector.
2544 * Access: OP
2545 */
2546 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2547
2548 /* reg_perpt_mask
2549 * Mask
2550 * 0 - A-TCAM will ignore the bit in key
2551 * 1 - A-TCAM will compare the bit in key
2552 * Access: RW
2553 */
2554 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2555
mlxsw_reg_perpt_erp_vector_pack(char * payload,unsigned long * erp_vector,unsigned long size)2556 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2557 unsigned long *erp_vector,
2558 unsigned long size)
2559 {
2560 unsigned long bit;
2561
2562 for_each_set_bit(bit, erp_vector, size)
2563 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2564 }
2565
2566 static inline void
mlxsw_reg_perpt_pack(char * payload,u8 erpt_bank,u8 erpt_index,enum mlxsw_reg_perpt_key_size key_size,u8 erp_id,u8 erpt_base_bank,u8 erpt_base_index,u8 erp_index,char * mask)2567 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2568 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2569 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2570 char *mask)
2571 {
2572 MLXSW_REG_ZERO(perpt, payload);
2573 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2574 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2575 mlxsw_reg_perpt_key_size_set(payload, key_size);
2576 mlxsw_reg_perpt_bf_bypass_set(payload, true);
2577 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2578 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2579 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2580 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2581 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2582 }
2583
2584 /* PERAR - Policy-Engine Region Association Register
2585 * -------------------------------------------------
2586 * This register associates a hw region for region_id's. Changing on the fly
2587 * is supported by the device.
2588 */
2589 #define MLXSW_REG_PERAR_ID 0x3026
2590 #define MLXSW_REG_PERAR_LEN 0x08
2591
2592 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2593
2594 /* reg_perar_region_id
2595 * Region identifier
2596 * Range 0 .. cap_max_regions-1
2597 * Access: Index
2598 */
2599 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2600
2601 static inline unsigned int
mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)2602 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2603 {
2604 return DIV_ROUND_UP(block_num, 4);
2605 }
2606
2607 /* reg_perar_hw_region
2608 * HW Region
2609 * Range 0 .. cap_max_regions-1
2610 * Default: hw_region = region_id
2611 * For a 8 key block region, 2 consecutive regions are used
2612 * For a 12 key block region, 3 consecutive regions are used
2613 * Access: RW
2614 */
2615 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2616
mlxsw_reg_perar_pack(char * payload,u16 region_id,u16 hw_region)2617 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2618 u16 hw_region)
2619 {
2620 MLXSW_REG_ZERO(perar, payload);
2621 mlxsw_reg_perar_region_id_set(payload, region_id);
2622 mlxsw_reg_perar_hw_region_set(payload, hw_region);
2623 }
2624
2625 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2626 * -----------------------------------------------------
2627 * This register is a new version of PTCE-V2 in order to support the
2628 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2629 */
2630 #define MLXSW_REG_PTCE3_ID 0x3027
2631 #define MLXSW_REG_PTCE3_LEN 0xF0
2632
2633 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2634
2635 /* reg_ptce3_v
2636 * Valid.
2637 * Access: RW
2638 */
2639 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2640
2641 enum mlxsw_reg_ptce3_op {
2642 /* Write operation. Used to write a new entry to the table.
2643 * All R/W fields are relevant for new entry. Activity bit is set
2644 * for new entries. Write with v = 0 will delete the entry. Must
2645 * not be used if an entry exists.
2646 */
2647 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2648 /* Update operation */
2649 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2650 /* Read operation */
2651 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2652 };
2653
2654 /* reg_ptce3_op
2655 * Access: OP
2656 */
2657 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2658
2659 /* reg_ptce3_priority
2660 * Priority of the rule. Higher values win.
2661 * For Spectrum-2 range is 1..cap_kvd_size - 1
2662 * Note: Priority does not have to be unique per rule.
2663 * Access: RW
2664 */
2665 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2666
2667 /* reg_ptce3_tcam_region_info
2668 * Opaque object that represents the TCAM region.
2669 * Access: Index
2670 */
2671 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2672 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2673
2674 /* reg_ptce3_flex2_key_blocks
2675 * ACL key. The key must be masked according to eRP (if exists) or
2676 * according to master mask.
2677 * Access: Index
2678 */
2679 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2680 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2681
2682 /* reg_ptce3_erp_id
2683 * eRP ID.
2684 * Access: Index
2685 */
2686 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2687
2688 /* reg_ptce3_delta_start
2689 * Start point of delta_value and delta_mask, in bits. Must not exceed
2690 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2691 * Access: Index
2692 */
2693 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2694
2695 /* reg_ptce3_delta_mask
2696 * Delta mask.
2697 * 0 - Ignore relevant bit in delta_value
2698 * 1 - Compare relevant bit in delta_value
2699 * Delta mask must not be set for reserved fields in the key blocks.
2700 * Note: No delta when no eRPs. Thus, for regions with
2701 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2702 * Access: Index
2703 */
2704 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2705
2706 /* reg_ptce3_delta_value
2707 * Delta value.
2708 * Bits which are masked by delta_mask must be 0.
2709 * Access: Index
2710 */
2711 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2712
2713 /* reg_ptce3_prune_vector
2714 * Pruning vector relative to the PERPT.erp_id.
2715 * Used for reducing lookups.
2716 * 0 - NEED: Do a lookup using the eRP.
2717 * 1 - PRUNE: Do not perform a lookup using the eRP.
2718 * Maybe be modified by PEAPBL and PEAPBM.
2719 * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2720 * all 1's or all 0's.
2721 * Access: RW
2722 */
2723 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2724
2725 /* reg_ptce3_prune_ctcam
2726 * Pruning on C-TCAM. Used for reducing lookups.
2727 * 0 - NEED: Do a lookup in the C-TCAM.
2728 * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2729 * Access: RW
2730 */
2731 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2732
2733 /* reg_ptce3_large_exists
2734 * Large entry key ID exists.
2735 * Within the region:
2736 * 0 - SINGLE: The large_entry_key_id is not currently in use.
2737 * For rule insert: The MSB of the key (blocks 6..11) will be added.
2738 * For rule delete: The MSB of the key will be removed.
2739 * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2740 * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2741 * For rule delete: The MSB of the key will not be removed.
2742 * Access: WO
2743 */
2744 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2745
2746 /* reg_ptce3_large_entry_key_id
2747 * Large entry key ID.
2748 * A key for 12 key blocks rules. Reserved when region has less than 12 key
2749 * blocks. Must be different for different keys which have the same common
2750 * 6 key blocks (MSB, blocks 6..11) key within a region.
2751 * Range is 0..cap_max_pe_large_key_id - 1
2752 * Access: RW
2753 */
2754 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2755
2756 /* reg_ptce3_action_pointer
2757 * Pointer to action.
2758 * Range is 0..cap_max_kvd_action_sets - 1
2759 * Access: RW
2760 */
2761 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2762
mlxsw_reg_ptce3_pack(char * payload,bool valid,enum mlxsw_reg_ptce3_op op,u32 priority,const char * tcam_region_info,const char * key,u8 erp_id,bool large_exists,u32 lkey_id,u32 action_pointer)2763 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2764 enum mlxsw_reg_ptce3_op op,
2765 u32 priority,
2766 const char *tcam_region_info,
2767 const char *key, u8 erp_id,
2768 bool large_exists, u32 lkey_id,
2769 u32 action_pointer)
2770 {
2771 MLXSW_REG_ZERO(ptce3, payload);
2772 mlxsw_reg_ptce3_v_set(payload, valid);
2773 mlxsw_reg_ptce3_op_set(payload, op);
2774 mlxsw_reg_ptce3_priority_set(payload, priority);
2775 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2776 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2777 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2778 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2779 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2780 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2781 }
2782
2783 /* PERCR - Policy-Engine Region Configuration Register
2784 * ---------------------------------------------------
2785 * This register configures the region parameters. The region_id must be
2786 * allocated.
2787 */
2788 #define MLXSW_REG_PERCR_ID 0x302A
2789 #define MLXSW_REG_PERCR_LEN 0x80
2790
2791 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2792
2793 /* reg_percr_region_id
2794 * Region identifier.
2795 * Range 0..cap_max_regions-1
2796 * Access: Index
2797 */
2798 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2799
2800 /* reg_percr_atcam_ignore_prune
2801 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2802 * Access: RW
2803 */
2804 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2805
2806 /* reg_percr_ctcam_ignore_prune
2807 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2808 * Access: RW
2809 */
2810 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2811
2812 /* reg_percr_bf_bypass
2813 * Bloom filter bypass.
2814 * 0 - Bloom filter is used (default)
2815 * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2816 * region_id or eRP. See PERPT.bf_bypass
2817 * Access: RW
2818 */
2819 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
2820
2821 /* reg_percr_master_mask
2822 * Master mask. Logical OR mask of all masks of all rules of a region
2823 * (both A-TCAM and C-TCAM). When there are no eRPs
2824 * (erpt_pointer_valid = 0), then this provides the mask.
2825 * Access: RW
2826 */
2827 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
2828
mlxsw_reg_percr_pack(char * payload,u16 region_id)2829 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
2830 {
2831 MLXSW_REG_ZERO(percr, payload);
2832 mlxsw_reg_percr_region_id_set(payload, region_id);
2833 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
2834 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
2835 mlxsw_reg_percr_bf_bypass_set(payload, true);
2836 }
2837
2838 /* PERERP - Policy-Engine Region eRP Register
2839 * ------------------------------------------
2840 * This register configures the region eRP. The region_id must be
2841 * allocated.
2842 */
2843 #define MLXSW_REG_PERERP_ID 0x302B
2844 #define MLXSW_REG_PERERP_LEN 0x1C
2845
2846 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
2847
2848 /* reg_pererp_region_id
2849 * Region identifier.
2850 * Range 0..cap_max_regions-1
2851 * Access: Index
2852 */
2853 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
2854
2855 /* reg_pererp_ctcam_le
2856 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
2857 * Access: RW
2858 */
2859 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
2860
2861 /* reg_pererp_erpt_pointer_valid
2862 * erpt_pointer is valid.
2863 * Access: RW
2864 */
2865 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
2866
2867 /* reg_pererp_erpt_bank_pointer
2868 * Pointer to eRP table bank. May be modified at any time.
2869 * Range 0..cap_max_erp_table_banks-1
2870 * Reserved when erpt_pointer_valid = 0
2871 */
2872 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
2873
2874 /* reg_pererp_erpt_pointer
2875 * Pointer to eRP table within the eRP bank. Can be changed for an
2876 * existing region.
2877 * Range 0..cap_max_erp_table_size-1
2878 * Reserved when erpt_pointer_valid = 0
2879 * Access: RW
2880 */
2881 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
2882
2883 /* reg_pererp_erpt_vector
2884 * Vector of allowed eRP indexes starting from erpt_pointer within the
2885 * erpt_bank_pointer. Next entries will be in next bank.
2886 * Note that eRP index is used and not eRP ID.
2887 * Reserved when erpt_pointer_valid = 0
2888 * Access: RW
2889 */
2890 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
2891
2892 /* reg_pererp_master_rp_id
2893 * Master RP ID. When there are no eRPs, then this provides the eRP ID
2894 * for the lookup. Can be changed for an existing region.
2895 * Reserved when erpt_pointer_valid = 1
2896 * Access: RW
2897 */
2898 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
2899
mlxsw_reg_pererp_erp_vector_pack(char * payload,unsigned long * erp_vector,unsigned long size)2900 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
2901 unsigned long *erp_vector,
2902 unsigned long size)
2903 {
2904 unsigned long bit;
2905
2906 for_each_set_bit(bit, erp_vector, size)
2907 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
2908 }
2909
mlxsw_reg_pererp_pack(char * payload,u16 region_id,bool ctcam_le,bool erpt_pointer_valid,u8 erpt_bank_pointer,u8 erpt_pointer,u8 master_rp_id)2910 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
2911 bool ctcam_le, bool erpt_pointer_valid,
2912 u8 erpt_bank_pointer, u8 erpt_pointer,
2913 u8 master_rp_id)
2914 {
2915 MLXSW_REG_ZERO(pererp, payload);
2916 mlxsw_reg_pererp_region_id_set(payload, region_id);
2917 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
2918 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
2919 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
2920 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
2921 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
2922 }
2923
2924 /* IEDR - Infrastructure Entry Delete Register
2925 * ----------------------------------------------------
2926 * This register is used for deleting entries from the entry tables.
2927 * It is legitimate to attempt to delete a nonexisting entry (the device will
2928 * respond as a good flow).
2929 */
2930 #define MLXSW_REG_IEDR_ID 0x3804
2931 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
2932 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
2933 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
2934 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
2935 MLXSW_REG_IEDR_REC_LEN * \
2936 MLXSW_REG_IEDR_REC_MAX_COUNT)
2937
2938 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
2939
2940 /* reg_iedr_num_rec
2941 * Number of records.
2942 * Access: OP
2943 */
2944 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
2945
2946 /* reg_iedr_rec_type
2947 * Resource type.
2948 * Access: OP
2949 */
2950 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
2951 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
2952
2953 /* reg_iedr_rec_size
2954 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
2955 * Access: OP
2956 */
2957 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
2958 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
2959
2960 /* reg_iedr_rec_index_start
2961 * Resource index start.
2962 * Access: OP
2963 */
2964 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
2965 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
2966
mlxsw_reg_iedr_pack(char * payload)2967 static inline void mlxsw_reg_iedr_pack(char *payload)
2968 {
2969 MLXSW_REG_ZERO(iedr, payload);
2970 }
2971
mlxsw_reg_iedr_rec_pack(char * payload,int rec_index,u8 rec_type,u16 rec_size,u32 rec_index_start)2972 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
2973 u8 rec_type, u16 rec_size,
2974 u32 rec_index_start)
2975 {
2976 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
2977
2978 if (rec_index >= num_rec)
2979 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
2980 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
2981 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
2982 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
2983 }
2984
2985 /* QPTS - QoS Priority Trust State Register
2986 * ----------------------------------------
2987 * This register controls the port policy to calculate the switch priority and
2988 * packet color based on incoming packet fields.
2989 */
2990 #define MLXSW_REG_QPTS_ID 0x4002
2991 #define MLXSW_REG_QPTS_LEN 0x8
2992
2993 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
2994
2995 /* reg_qpts_local_port
2996 * Local port number.
2997 * Access: Index
2998 *
2999 * Note: CPU port is supported.
3000 */
3001 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3002
3003 enum mlxsw_reg_qpts_trust_state {
3004 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3005 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3006 };
3007
3008 /* reg_qpts_trust_state
3009 * Trust state for a given port.
3010 * Access: RW
3011 */
3012 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3013
mlxsw_reg_qpts_pack(char * payload,u8 local_port,enum mlxsw_reg_qpts_trust_state ts)3014 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3015 enum mlxsw_reg_qpts_trust_state ts)
3016 {
3017 MLXSW_REG_ZERO(qpts, payload);
3018
3019 mlxsw_reg_qpts_local_port_set(payload, local_port);
3020 mlxsw_reg_qpts_trust_state_set(payload, ts);
3021 }
3022
3023 /* QPCR - QoS Policer Configuration Register
3024 * -----------------------------------------
3025 * The QPCR register is used to create policers - that limit
3026 * the rate of bytes or packets via some trap group.
3027 */
3028 #define MLXSW_REG_QPCR_ID 0x4004
3029 #define MLXSW_REG_QPCR_LEN 0x28
3030
3031 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3032
3033 enum mlxsw_reg_qpcr_g {
3034 MLXSW_REG_QPCR_G_GLOBAL = 2,
3035 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3036 };
3037
3038 /* reg_qpcr_g
3039 * The policer type.
3040 * Access: Index
3041 */
3042 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3043
3044 /* reg_qpcr_pid
3045 * Policer ID.
3046 * Access: Index
3047 */
3048 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3049
3050 /* reg_qpcr_color_aware
3051 * Is the policer aware of colors.
3052 * Must be 0 (unaware) for cpu port.
3053 * Access: RW for unbounded policer. RO for bounded policer.
3054 */
3055 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3056
3057 /* reg_qpcr_bytes
3058 * Is policer limit is for bytes per sec or packets per sec.
3059 * 0 - packets
3060 * 1 - bytes
3061 * Access: RW for unbounded policer. RO for bounded policer.
3062 */
3063 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3064
3065 enum mlxsw_reg_qpcr_ir_units {
3066 MLXSW_REG_QPCR_IR_UNITS_M,
3067 MLXSW_REG_QPCR_IR_UNITS_K,
3068 };
3069
3070 /* reg_qpcr_ir_units
3071 * Policer's units for cir and eir fields (for bytes limits only)
3072 * 1 - 10^3
3073 * 0 - 10^6
3074 * Access: OP
3075 */
3076 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3077
3078 enum mlxsw_reg_qpcr_rate_type {
3079 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3080 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3081 };
3082
3083 /* reg_qpcr_rate_type
3084 * Policer can have one limit (single rate) or 2 limits with specific operation
3085 * for packets that exceed the lower rate but not the upper one.
3086 * (For cpu port must be single rate)
3087 * Access: RW for unbounded policer. RO for bounded policer.
3088 */
3089 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3090
3091 /* reg_qpc_cbs
3092 * Policer's committed burst size.
3093 * The policer is working with time slices of 50 nano sec. By default every
3094 * slice is granted the proportionate share of the committed rate. If we want to
3095 * allow a slice to exceed that share (while still keeping the rate per sec) we
3096 * can allow burst. The burst size is between the default proportionate share
3097 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3098 * committed rate will result in exceeding the rate). The burst size must be a
3099 * log of 2 and will be determined by 2^cbs.
3100 * Access: RW
3101 */
3102 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3103
3104 /* reg_qpcr_cir
3105 * Policer's committed rate.
3106 * The rate used for sungle rate, the lower rate for double rate.
3107 * For bytes limits, the rate will be this value * the unit from ir_units.
3108 * (Resolution error is up to 1%).
3109 * Access: RW
3110 */
3111 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3112
3113 /* reg_qpcr_eir
3114 * Policer's exceed rate.
3115 * The higher rate for double rate, reserved for single rate.
3116 * Lower rate for double rate policer.
3117 * For bytes limits, the rate will be this value * the unit from ir_units.
3118 * (Resolution error is up to 1%).
3119 * Access: RW
3120 */
3121 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3122
3123 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3124
3125 /* reg_qpcr_exceed_action.
3126 * What to do with packets between the 2 limits for double rate.
3127 * Access: RW for unbounded policer. RO for bounded policer.
3128 */
3129 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3130
3131 enum mlxsw_reg_qpcr_action {
3132 /* Discard */
3133 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3134 /* Forward and set color to red.
3135 * If the packet is intended to cpu port, it will be dropped.
3136 */
3137 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3138 };
3139
3140 /* reg_qpcr_violate_action
3141 * What to do with packets that cross the cir limit (for single rate) or the eir
3142 * limit (for double rate).
3143 * Access: RW for unbounded policer. RO for bounded policer.
3144 */
3145 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3146
mlxsw_reg_qpcr_pack(char * payload,u16 pid,enum mlxsw_reg_qpcr_ir_units ir_units,bool bytes,u32 cir,u16 cbs)3147 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3148 enum mlxsw_reg_qpcr_ir_units ir_units,
3149 bool bytes, u32 cir, u16 cbs)
3150 {
3151 MLXSW_REG_ZERO(qpcr, payload);
3152 mlxsw_reg_qpcr_pid_set(payload, pid);
3153 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3154 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3155 mlxsw_reg_qpcr_violate_action_set(payload,
3156 MLXSW_REG_QPCR_ACTION_DISCARD);
3157 mlxsw_reg_qpcr_cir_set(payload, cir);
3158 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3159 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3160 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3161 }
3162
3163 /* QTCT - QoS Switch Traffic Class Table
3164 * -------------------------------------
3165 * Configures the mapping between the packet switch priority and the
3166 * traffic class on the transmit port.
3167 */
3168 #define MLXSW_REG_QTCT_ID 0x400A
3169 #define MLXSW_REG_QTCT_LEN 0x08
3170
3171 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3172
3173 /* reg_qtct_local_port
3174 * Local port number.
3175 * Access: Index
3176 *
3177 * Note: CPU port is not supported.
3178 */
3179 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3180
3181 /* reg_qtct_sub_port
3182 * Virtual port within the physical port.
3183 * Should be set to 0 when virtual ports are not enabled on the port.
3184 * Access: Index
3185 */
3186 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3187
3188 /* reg_qtct_switch_prio
3189 * Switch priority.
3190 * Access: Index
3191 */
3192 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3193
3194 /* reg_qtct_tclass
3195 * Traffic class.
3196 * Default values:
3197 * switch_prio 0 : tclass 1
3198 * switch_prio 1 : tclass 0
3199 * switch_prio i : tclass i, for i > 1
3200 * Access: RW
3201 */
3202 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3203
mlxsw_reg_qtct_pack(char * payload,u8 local_port,u8 switch_prio,u8 tclass)3204 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3205 u8 switch_prio, u8 tclass)
3206 {
3207 MLXSW_REG_ZERO(qtct, payload);
3208 mlxsw_reg_qtct_local_port_set(payload, local_port);
3209 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3210 mlxsw_reg_qtct_tclass_set(payload, tclass);
3211 }
3212
3213 /* QEEC - QoS ETS Element Configuration Register
3214 * ---------------------------------------------
3215 * Configures the ETS elements.
3216 */
3217 #define MLXSW_REG_QEEC_ID 0x400D
3218 #define MLXSW_REG_QEEC_LEN 0x20
3219
3220 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3221
3222 /* reg_qeec_local_port
3223 * Local port number.
3224 * Access: Index
3225 *
3226 * Note: CPU port is supported.
3227 */
3228 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3229
3230 enum mlxsw_reg_qeec_hr {
3231 MLXSW_REG_QEEC_HIERARCY_PORT,
3232 MLXSW_REG_QEEC_HIERARCY_GROUP,
3233 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3234 MLXSW_REG_QEEC_HIERARCY_TC,
3235 };
3236
3237 /* reg_qeec_element_hierarchy
3238 * 0 - Port
3239 * 1 - Group
3240 * 2 - Subgroup
3241 * 3 - Traffic Class
3242 * Access: Index
3243 */
3244 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3245
3246 /* reg_qeec_element_index
3247 * The index of the element in the hierarchy.
3248 * Access: Index
3249 */
3250 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3251
3252 /* reg_qeec_next_element_index
3253 * The index of the next (lower) element in the hierarchy.
3254 * Access: RW
3255 *
3256 * Note: Reserved for element_hierarchy 0.
3257 */
3258 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3259
3260 /* reg_qeec_mise
3261 * Min shaper configuration enable. Enables configuration of the min
3262 * shaper on this ETS element
3263 * 0 - Disable
3264 * 1 - Enable
3265 * Access: RW
3266 */
3267 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3268
3269 enum {
3270 MLXSW_REG_QEEC_BYTES_MODE,
3271 MLXSW_REG_QEEC_PACKETS_MODE,
3272 };
3273
3274 /* reg_qeec_pb
3275 * Packets or bytes mode.
3276 * 0 - Bytes mode
3277 * 1 - Packets mode
3278 * Access: RW
3279 *
3280 * Note: Used for max shaper configuration. For Spectrum, packets mode
3281 * is supported only for traffic classes of CPU port.
3282 */
3283 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3284
3285 /* The smallest permitted min shaper rate. */
3286 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */
3287
3288 /* reg_qeec_min_shaper_rate
3289 * Min shaper information rate.
3290 * For CPU port, can only be configured for port hierarchy.
3291 * When in bytes mode, value is specified in units of 1000bps.
3292 * Access: RW
3293 */
3294 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3295
3296 /* reg_qeec_mase
3297 * Max shaper configuration enable. Enables configuration of the max
3298 * shaper on this ETS element.
3299 * 0 - Disable
3300 * 1 - Enable
3301 * Access: RW
3302 */
3303 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3304
3305 /* A large max rate will disable the max shaper. */
3306 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
3307
3308 /* reg_qeec_max_shaper_rate
3309 * Max shaper information rate.
3310 * For CPU port, can only be configured for port hierarchy.
3311 * When in bytes mode, value is specified in units of 1000bps.
3312 * Access: RW
3313 */
3314 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3315
3316 /* reg_qeec_de
3317 * DWRR configuration enable. Enables configuration of the dwrr and
3318 * dwrr_weight.
3319 * 0 - Disable
3320 * 1 - Enable
3321 * Access: RW
3322 */
3323 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3324
3325 /* reg_qeec_dwrr
3326 * Transmission selection algorithm to use on the link going down from
3327 * the ETS element.
3328 * 0 - Strict priority
3329 * 1 - DWRR
3330 * Access: RW
3331 */
3332 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3333
3334 /* reg_qeec_dwrr_weight
3335 * DWRR weight on the link going down from the ETS element. The
3336 * percentage of bandwidth guaranteed to an ETS element within
3337 * its hierarchy. The sum of all weights across all ETS elements
3338 * within one hierarchy should be equal to 100. Reserved when
3339 * transmission selection algorithm is strict priority.
3340 * Access: RW
3341 */
3342 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3343
mlxsw_reg_qeec_pack(char * payload,u8 local_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index)3344 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3345 enum mlxsw_reg_qeec_hr hr, u8 index,
3346 u8 next_index)
3347 {
3348 MLXSW_REG_ZERO(qeec, payload);
3349 mlxsw_reg_qeec_local_port_set(payload, local_port);
3350 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3351 mlxsw_reg_qeec_element_index_set(payload, index);
3352 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3353 }
3354
3355 /* QRWE - QoS ReWrite Enable
3356 * -------------------------
3357 * This register configures the rewrite enable per receive port.
3358 */
3359 #define MLXSW_REG_QRWE_ID 0x400F
3360 #define MLXSW_REG_QRWE_LEN 0x08
3361
3362 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3363
3364 /* reg_qrwe_local_port
3365 * Local port number.
3366 * Access: Index
3367 *
3368 * Note: CPU port is supported. No support for router port.
3369 */
3370 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3371
3372 /* reg_qrwe_dscp
3373 * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3374 * Access: RW
3375 */
3376 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3377
3378 /* reg_qrwe_pcp
3379 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3380 * Access: RW
3381 */
3382 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3383
mlxsw_reg_qrwe_pack(char * payload,u8 local_port,bool rewrite_pcp,bool rewrite_dscp)3384 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3385 bool rewrite_pcp, bool rewrite_dscp)
3386 {
3387 MLXSW_REG_ZERO(qrwe, payload);
3388 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3389 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3390 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3391 }
3392
3393 /* QPDSM - QoS Priority to DSCP Mapping
3394 * ------------------------------------
3395 * QoS Priority to DSCP Mapping Register
3396 */
3397 #define MLXSW_REG_QPDSM_ID 0x4011
3398 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3399 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3400 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3401 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3402 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3403 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3404
3405 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3406
3407 /* reg_qpdsm_local_port
3408 * Local Port. Supported for data packets from CPU port.
3409 * Access: Index
3410 */
3411 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3412
3413 /* reg_qpdsm_prio_entry_color0_e
3414 * Enable update of the entry for color 0 and a given port.
3415 * Access: WO
3416 */
3417 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3418 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3419 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3420
3421 /* reg_qpdsm_prio_entry_color0_dscp
3422 * DSCP field in the outer label of the packet for color 0 and a given port.
3423 * Reserved when e=0.
3424 * Access: RW
3425 */
3426 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3427 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3428 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3429
3430 /* reg_qpdsm_prio_entry_color1_e
3431 * Enable update of the entry for color 1 and a given port.
3432 * Access: WO
3433 */
3434 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3435 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3436 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3437
3438 /* reg_qpdsm_prio_entry_color1_dscp
3439 * DSCP field in the outer label of the packet for color 1 and a given port.
3440 * Reserved when e=0.
3441 * Access: RW
3442 */
3443 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3444 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3445 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3446
3447 /* reg_qpdsm_prio_entry_color2_e
3448 * Enable update of the entry for color 2 and a given port.
3449 * Access: WO
3450 */
3451 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3452 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3453 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3454
3455 /* reg_qpdsm_prio_entry_color2_dscp
3456 * DSCP field in the outer label of the packet for color 2 and a given port.
3457 * Reserved when e=0.
3458 * Access: RW
3459 */
3460 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3461 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3462 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3463
mlxsw_reg_qpdsm_pack(char * payload,u8 local_port)3464 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3465 {
3466 MLXSW_REG_ZERO(qpdsm, payload);
3467 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3468 }
3469
3470 static inline void
mlxsw_reg_qpdsm_prio_pack(char * payload,unsigned short prio,u8 dscp)3471 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3472 {
3473 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3474 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3475 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3476 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3477 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3478 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3479 }
3480
3481 /* QPDPM - QoS Port DSCP to Priority Mapping Register
3482 * --------------------------------------------------
3483 * This register controls the mapping from DSCP field to
3484 * Switch Priority for IP packets.
3485 */
3486 #define MLXSW_REG_QPDPM_ID 0x4013
3487 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3488 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3489 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3490 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
3491 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
3492 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3493
3494 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3495
3496 /* reg_qpdpm_local_port
3497 * Local Port. Supported for data packets from CPU port.
3498 * Access: Index
3499 */
3500 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3501
3502 /* reg_qpdpm_dscp_e
3503 * Enable update of the specific entry. When cleared, the switch_prio and color
3504 * fields are ignored and the previous switch_prio and color values are
3505 * preserved.
3506 * Access: WO
3507 */
3508 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3509 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3510
3511 /* reg_qpdpm_dscp_prio
3512 * The new Switch Priority value for the relevant DSCP value.
3513 * Access: RW
3514 */
3515 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3516 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3517 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3518
mlxsw_reg_qpdpm_pack(char * payload,u8 local_port)3519 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3520 {
3521 MLXSW_REG_ZERO(qpdpm, payload);
3522 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3523 }
3524
3525 static inline void
mlxsw_reg_qpdpm_dscp_pack(char * payload,unsigned short dscp,u8 prio)3526 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3527 {
3528 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3529 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3530 }
3531
3532 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3533 * ------------------------------------------------------------------
3534 * This register configures if the Switch Priority to Traffic Class mapping is
3535 * based on Multicast packet indication. If so, then multicast packets will get
3536 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3537 * QTCT.
3538 * By default, Switch Priority to Traffic Class mapping is not based on
3539 * Multicast packet indication.
3540 */
3541 #define MLXSW_REG_QTCTM_ID 0x401A
3542 #define MLXSW_REG_QTCTM_LEN 0x08
3543
3544 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3545
3546 /* reg_qtctm_local_port
3547 * Local port number.
3548 * No support for CPU port.
3549 * Access: Index
3550 */
3551 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3552
3553 /* reg_qtctm_mc
3554 * Multicast Mode
3555 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3556 * indication (default is 0, not based on Multicast packet indication).
3557 */
3558 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3559
3560 static inline void
mlxsw_reg_qtctm_pack(char * payload,u8 local_port,bool mc)3561 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3562 {
3563 MLXSW_REG_ZERO(qtctm, payload);
3564 mlxsw_reg_qtctm_local_port_set(payload, local_port);
3565 mlxsw_reg_qtctm_mc_set(payload, mc);
3566 }
3567
3568 /* PMLP - Ports Module to Local Port Register
3569 * ------------------------------------------
3570 * Configures the assignment of modules to local ports.
3571 */
3572 #define MLXSW_REG_PMLP_ID 0x5002
3573 #define MLXSW_REG_PMLP_LEN 0x40
3574
3575 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3576
3577 /* reg_pmlp_rxtx
3578 * 0 - Tx value is used for both Tx and Rx.
3579 * 1 - Rx value is taken from a separte field.
3580 * Access: RW
3581 */
3582 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3583
3584 /* reg_pmlp_local_port
3585 * Local port number.
3586 * Access: Index
3587 */
3588 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3589
3590 /* reg_pmlp_width
3591 * 0 - Unmap local port.
3592 * 1 - Lane 0 is used.
3593 * 2 - Lanes 0 and 1 are used.
3594 * 4 - Lanes 0, 1, 2 and 3 are used.
3595 * Access: RW
3596 */
3597 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3598
3599 /* reg_pmlp_module
3600 * Module number.
3601 * Access: RW
3602 */
3603 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3604
3605 /* reg_pmlp_tx_lane
3606 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3607 * Access: RW
3608 */
3609 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3610
3611 /* reg_pmlp_rx_lane
3612 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3613 * equal to Tx lane.
3614 * Access: RW
3615 */
3616 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3617
mlxsw_reg_pmlp_pack(char * payload,u8 local_port)3618 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3619 {
3620 MLXSW_REG_ZERO(pmlp, payload);
3621 mlxsw_reg_pmlp_local_port_set(payload, local_port);
3622 }
3623
3624 /* PMTU - Port MTU Register
3625 * ------------------------
3626 * Configures and reports the port MTU.
3627 */
3628 #define MLXSW_REG_PMTU_ID 0x5003
3629 #define MLXSW_REG_PMTU_LEN 0x10
3630
3631 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
3632
3633 /* reg_pmtu_local_port
3634 * Local port number.
3635 * Access: Index
3636 */
3637 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
3638
3639 /* reg_pmtu_max_mtu
3640 * Maximum MTU.
3641 * When port type (e.g. Ethernet) is configured, the relevant MTU is
3642 * reported, otherwise the minimum between the max_mtu of the different
3643 * types is reported.
3644 * Access: RO
3645 */
3646 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
3647
3648 /* reg_pmtu_admin_mtu
3649 * MTU value to set port to. Must be smaller or equal to max_mtu.
3650 * Note: If port type is Infiniband, then port must be disabled, when its
3651 * MTU is set.
3652 * Access: RW
3653 */
3654 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
3655
3656 /* reg_pmtu_oper_mtu
3657 * The actual MTU configured on the port. Packets exceeding this size
3658 * will be dropped.
3659 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
3660 * oper_mtu might be smaller than admin_mtu.
3661 * Access: RO
3662 */
3663 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
3664
mlxsw_reg_pmtu_pack(char * payload,u8 local_port,u16 new_mtu)3665 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
3666 u16 new_mtu)
3667 {
3668 MLXSW_REG_ZERO(pmtu, payload);
3669 mlxsw_reg_pmtu_local_port_set(payload, local_port);
3670 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
3671 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
3672 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
3673 }
3674
3675 /* PTYS - Port Type and Speed Register
3676 * -----------------------------------
3677 * Configures and reports the port speed type.
3678 *
3679 * Note: When set while the link is up, the changes will not take effect
3680 * until the port transitions from down to up state.
3681 */
3682 #define MLXSW_REG_PTYS_ID 0x5004
3683 #define MLXSW_REG_PTYS_LEN 0x40
3684
3685 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
3686
3687 /* an_disable_admin
3688 * Auto negotiation disable administrative configuration
3689 * 0 - Device doesn't support AN disable.
3690 * 1 - Device supports AN disable.
3691 * Access: RW
3692 */
3693 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
3694
3695 /* reg_ptys_local_port
3696 * Local port number.
3697 * Access: Index
3698 */
3699 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
3700
3701 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
3702 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
3703
3704 /* reg_ptys_proto_mask
3705 * Protocol mask. Indicates which protocol is used.
3706 * 0 - Infiniband.
3707 * 1 - Fibre Channel.
3708 * 2 - Ethernet.
3709 * Access: Index
3710 */
3711 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
3712
3713 enum {
3714 MLXSW_REG_PTYS_AN_STATUS_NA,
3715 MLXSW_REG_PTYS_AN_STATUS_OK,
3716 MLXSW_REG_PTYS_AN_STATUS_FAIL,
3717 };
3718
3719 /* reg_ptys_an_status
3720 * Autonegotiation status.
3721 * Access: RO
3722 */
3723 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
3724
3725 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
3726 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
3727 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
3728 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
3729 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
3730 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
3731 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
3732 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
3733 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
3734 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
3735 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
3736 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
3737 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
3738 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
3739 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
3740 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
3741 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
3742 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
3743 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
3744 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
3745 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
3746 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
3747 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
3748 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
3749 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
3750 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
3751 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
3752 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
3753
3754 /* reg_ptys_eth_proto_cap
3755 * Ethernet port supported speeds and protocols.
3756 * Access: RO
3757 */
3758 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
3759
3760 /* reg_ptys_ib_link_width_cap
3761 * IB port supported widths.
3762 * Access: RO
3763 */
3764 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
3765
3766 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
3767 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
3768 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
3769 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
3770 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
3771 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
3772
3773 /* reg_ptys_ib_proto_cap
3774 * IB port supported speeds and protocols.
3775 * Access: RO
3776 */
3777 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
3778
3779 /* reg_ptys_eth_proto_admin
3780 * Speed and protocol to set port to.
3781 * Access: RW
3782 */
3783 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
3784
3785 /* reg_ptys_ib_link_width_admin
3786 * IB width to set port to.
3787 * Access: RW
3788 */
3789 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
3790
3791 /* reg_ptys_ib_proto_admin
3792 * IB speeds and protocols to set port to.
3793 * Access: RW
3794 */
3795 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
3796
3797 /* reg_ptys_eth_proto_oper
3798 * The current speed and protocol configured for the port.
3799 * Access: RO
3800 */
3801 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
3802
3803 /* reg_ptys_ib_link_width_oper
3804 * The current IB width to set port to.
3805 * Access: RO
3806 */
3807 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
3808
3809 /* reg_ptys_ib_proto_oper
3810 * The current IB speed and protocol.
3811 * Access: RO
3812 */
3813 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
3814
3815 /* reg_ptys_eth_proto_lp_advertise
3816 * The protocols that were advertised by the link partner during
3817 * autonegotiation.
3818 * Access: RO
3819 */
3820 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32);
3821
mlxsw_reg_ptys_eth_pack(char * payload,u8 local_port,u32 proto_admin,bool autoneg)3822 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
3823 u32 proto_admin, bool autoneg)
3824 {
3825 MLXSW_REG_ZERO(ptys, payload);
3826 mlxsw_reg_ptys_local_port_set(payload, local_port);
3827 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
3828 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
3829 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
3830 }
3831
mlxsw_reg_ptys_eth_unpack(char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_adm,u32 * p_eth_proto_oper)3832 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
3833 u32 *p_eth_proto_cap,
3834 u32 *p_eth_proto_adm,
3835 u32 *p_eth_proto_oper)
3836 {
3837 if (p_eth_proto_cap)
3838 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
3839 if (p_eth_proto_adm)
3840 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
3841 if (p_eth_proto_oper)
3842 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
3843 }
3844
mlxsw_reg_ptys_ib_pack(char * payload,u8 local_port,u16 proto_admin,u16 link_width)3845 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
3846 u16 proto_admin, u16 link_width)
3847 {
3848 MLXSW_REG_ZERO(ptys, payload);
3849 mlxsw_reg_ptys_local_port_set(payload, local_port);
3850 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
3851 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
3852 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
3853 }
3854
mlxsw_reg_ptys_ib_unpack(char * payload,u16 * p_ib_proto_cap,u16 * p_ib_link_width_cap,u16 * p_ib_proto_oper,u16 * p_ib_link_width_oper)3855 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
3856 u16 *p_ib_link_width_cap,
3857 u16 *p_ib_proto_oper,
3858 u16 *p_ib_link_width_oper)
3859 {
3860 if (p_ib_proto_cap)
3861 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
3862 if (p_ib_link_width_cap)
3863 *p_ib_link_width_cap =
3864 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
3865 if (p_ib_proto_oper)
3866 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
3867 if (p_ib_link_width_oper)
3868 *p_ib_link_width_oper =
3869 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
3870 }
3871
3872 /* PPAD - Port Physical Address Register
3873 * -------------------------------------
3874 * The PPAD register configures the per port physical MAC address.
3875 */
3876 #define MLXSW_REG_PPAD_ID 0x5005
3877 #define MLXSW_REG_PPAD_LEN 0x10
3878
3879 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
3880
3881 /* reg_ppad_single_base_mac
3882 * 0: base_mac, local port should be 0 and mac[7:0] is
3883 * reserved. HW will set incremental
3884 * 1: single_mac - mac of the local_port
3885 * Access: RW
3886 */
3887 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
3888
3889 /* reg_ppad_local_port
3890 * port number, if single_base_mac = 0 then local_port is reserved
3891 * Access: RW
3892 */
3893 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
3894
3895 /* reg_ppad_mac
3896 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
3897 * If single_base_mac = 1 - the per port MAC address
3898 * Access: RW
3899 */
3900 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
3901
mlxsw_reg_ppad_pack(char * payload,bool single_base_mac,u8 local_port)3902 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
3903 u8 local_port)
3904 {
3905 MLXSW_REG_ZERO(ppad, payload);
3906 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
3907 mlxsw_reg_ppad_local_port_set(payload, local_port);
3908 }
3909
3910 /* PAOS - Ports Administrative and Operational Status Register
3911 * -----------------------------------------------------------
3912 * Configures and retrieves per port administrative and operational status.
3913 */
3914 #define MLXSW_REG_PAOS_ID 0x5006
3915 #define MLXSW_REG_PAOS_LEN 0x10
3916
3917 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
3918
3919 /* reg_paos_swid
3920 * Switch partition ID with which to associate the port.
3921 * Note: while external ports uses unique local port numbers (and thus swid is
3922 * redundant), router ports use the same local port number where swid is the
3923 * only indication for the relevant port.
3924 * Access: Index
3925 */
3926 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
3927
3928 /* reg_paos_local_port
3929 * Local port number.
3930 * Access: Index
3931 */
3932 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
3933
3934 /* reg_paos_admin_status
3935 * Port administrative state (the desired state of the port):
3936 * 1 - Up.
3937 * 2 - Down.
3938 * 3 - Up once. This means that in case of link failure, the port won't go
3939 * into polling mode, but will wait to be re-enabled by software.
3940 * 4 - Disabled by system. Can only be set by hardware.
3941 * Access: RW
3942 */
3943 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
3944
3945 /* reg_paos_oper_status
3946 * Port operational state (the current state):
3947 * 1 - Up.
3948 * 2 - Down.
3949 * 3 - Down by port failure. This means that the device will not let the
3950 * port up again until explicitly specified by software.
3951 * Access: RO
3952 */
3953 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
3954
3955 /* reg_paos_ase
3956 * Admin state update enabled.
3957 * Access: WO
3958 */
3959 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
3960
3961 /* reg_paos_ee
3962 * Event update enable. If this bit is set, event generation will be
3963 * updated based on the e field.
3964 * Access: WO
3965 */
3966 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
3967
3968 /* reg_paos_e
3969 * Event generation on operational state change:
3970 * 0 - Do not generate event.
3971 * 1 - Generate Event.
3972 * 2 - Generate Single Event.
3973 * Access: RW
3974 */
3975 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
3976
mlxsw_reg_paos_pack(char * payload,u8 local_port,enum mlxsw_port_admin_status status)3977 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
3978 enum mlxsw_port_admin_status status)
3979 {
3980 MLXSW_REG_ZERO(paos, payload);
3981 mlxsw_reg_paos_swid_set(payload, 0);
3982 mlxsw_reg_paos_local_port_set(payload, local_port);
3983 mlxsw_reg_paos_admin_status_set(payload, status);
3984 mlxsw_reg_paos_oper_status_set(payload, 0);
3985 mlxsw_reg_paos_ase_set(payload, 1);
3986 mlxsw_reg_paos_ee_set(payload, 1);
3987 mlxsw_reg_paos_e_set(payload, 1);
3988 }
3989
3990 /* PFCC - Ports Flow Control Configuration Register
3991 * ------------------------------------------------
3992 * Configures and retrieves the per port flow control configuration.
3993 */
3994 #define MLXSW_REG_PFCC_ID 0x5007
3995 #define MLXSW_REG_PFCC_LEN 0x20
3996
3997 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
3998
3999 /* reg_pfcc_local_port
4000 * Local port number.
4001 * Access: Index
4002 */
4003 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4004
4005 /* reg_pfcc_pnat
4006 * Port number access type. Determines the way local_port is interpreted:
4007 * 0 - Local port number.
4008 * 1 - IB / label port number.
4009 * Access: Index
4010 */
4011 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4012
4013 /* reg_pfcc_shl_cap
4014 * Send to higher layers capabilities:
4015 * 0 - No capability of sending Pause and PFC frames to higher layers.
4016 * 1 - Device has capability of sending Pause and PFC frames to higher
4017 * layers.
4018 * Access: RO
4019 */
4020 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4021
4022 /* reg_pfcc_shl_opr
4023 * Send to higher layers operation:
4024 * 0 - Pause and PFC frames are handled by the port (default).
4025 * 1 - Pause and PFC frames are handled by the port and also sent to
4026 * higher layers. Only valid if shl_cap = 1.
4027 * Access: RW
4028 */
4029 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4030
4031 /* reg_pfcc_ppan
4032 * Pause policy auto negotiation.
4033 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4034 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4035 * based on the auto-negotiation resolution.
4036 * Access: RW
4037 *
4038 * Note: The auto-negotiation advertisement is set according to pptx and
4039 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4040 */
4041 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4042
4043 /* reg_pfcc_prio_mask_tx
4044 * Bit per priority indicating if Tx flow control policy should be
4045 * updated based on bit pfctx.
4046 * Access: WO
4047 */
4048 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4049
4050 /* reg_pfcc_prio_mask_rx
4051 * Bit per priority indicating if Rx flow control policy should be
4052 * updated based on bit pfcrx.
4053 * Access: WO
4054 */
4055 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4056
4057 /* reg_pfcc_pptx
4058 * Admin Pause policy on Tx.
4059 * 0 - Never generate Pause frames (default).
4060 * 1 - Generate Pause frames according to Rx buffer threshold.
4061 * Access: RW
4062 */
4063 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4064
4065 /* reg_pfcc_aptx
4066 * Active (operational) Pause policy on Tx.
4067 * 0 - Never generate Pause frames.
4068 * 1 - Generate Pause frames according to Rx buffer threshold.
4069 * Access: RO
4070 */
4071 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4072
4073 /* reg_pfcc_pfctx
4074 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4075 * 0 - Never generate priority Pause frames on the specified priority
4076 * (default).
4077 * 1 - Generate priority Pause frames according to Rx buffer threshold on
4078 * the specified priority.
4079 * Access: RW
4080 *
4081 * Note: pfctx and pptx must be mutually exclusive.
4082 */
4083 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4084
4085 /* reg_pfcc_pprx
4086 * Admin Pause policy on Rx.
4087 * 0 - Ignore received Pause frames (default).
4088 * 1 - Respect received Pause frames.
4089 * Access: RW
4090 */
4091 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4092
4093 /* reg_pfcc_aprx
4094 * Active (operational) Pause policy on Rx.
4095 * 0 - Ignore received Pause frames.
4096 * 1 - Respect received Pause frames.
4097 * Access: RO
4098 */
4099 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4100
4101 /* reg_pfcc_pfcrx
4102 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4103 * 0 - Ignore incoming priority Pause frames on the specified priority
4104 * (default).
4105 * 1 - Respect incoming priority Pause frames on the specified priority.
4106 * Access: RW
4107 */
4108 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4109
4110 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4111
mlxsw_reg_pfcc_prio_pack(char * payload,u8 pfc_en)4112 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4113 {
4114 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4115 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4116 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4117 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4118 }
4119
mlxsw_reg_pfcc_pack(char * payload,u8 local_port)4120 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4121 {
4122 MLXSW_REG_ZERO(pfcc, payload);
4123 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4124 }
4125
4126 /* PPCNT - Ports Performance Counters Register
4127 * -------------------------------------------
4128 * The PPCNT register retrieves per port performance counters.
4129 */
4130 #define MLXSW_REG_PPCNT_ID 0x5008
4131 #define MLXSW_REG_PPCNT_LEN 0x100
4132 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4133
4134 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4135
4136 /* reg_ppcnt_swid
4137 * For HCA: must be always 0.
4138 * Switch partition ID to associate port with.
4139 * Switch partitions are numbered from 0 to 7 inclusively.
4140 * Switch partition 254 indicates stacking ports.
4141 * Switch partition 255 indicates all switch partitions.
4142 * Only valid on Set() operation with local_port=255.
4143 * Access: Index
4144 */
4145 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4146
4147 /* reg_ppcnt_local_port
4148 * Local port number.
4149 * 255 indicates all ports on the device, and is only allowed
4150 * for Set() operation.
4151 * Access: Index
4152 */
4153 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4154
4155 /* reg_ppcnt_pnat
4156 * Port number access type:
4157 * 0 - Local port number
4158 * 1 - IB port number
4159 * Access: Index
4160 */
4161 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4162
4163 enum mlxsw_reg_ppcnt_grp {
4164 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4165 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4166 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4167 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4168 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4169 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4170 };
4171
4172 /* reg_ppcnt_grp
4173 * Performance counter group.
4174 * Group 63 indicates all groups. Only valid on Set() operation with
4175 * clr bit set.
4176 * 0x0: IEEE 802.3 Counters
4177 * 0x1: RFC 2863 Counters
4178 * 0x2: RFC 2819 Counters
4179 * 0x3: RFC 3635 Counters
4180 * 0x5: Ethernet Extended Counters
4181 * 0x8: Link Level Retransmission Counters
4182 * 0x10: Per Priority Counters
4183 * 0x11: Per Traffic Class Counters
4184 * 0x12: Physical Layer Counters
4185 * 0x13: Per Traffic Class Congestion Counters
4186 * Access: Index
4187 */
4188 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4189
4190 /* reg_ppcnt_clr
4191 * Clear counters. Setting the clr bit will reset the counter value
4192 * for all counters in the counter group. This bit can be set
4193 * for both Set() and Get() operation.
4194 * Access: OP
4195 */
4196 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4197
4198 /* reg_ppcnt_prio_tc
4199 * Priority for counter set that support per priority, valid values: 0-7.
4200 * Traffic class for counter set that support per traffic class,
4201 * valid values: 0- cap_max_tclass-1 .
4202 * For HCA: cap_max_tclass is always 8.
4203 * Otherwise must be 0.
4204 * Access: Index
4205 */
4206 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4207
4208 /* Ethernet IEEE 802.3 Counter Group */
4209
4210 /* reg_ppcnt_a_frames_transmitted_ok
4211 * Access: RO
4212 */
4213 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4214 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4215
4216 /* reg_ppcnt_a_frames_received_ok
4217 * Access: RO
4218 */
4219 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4220 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4221
4222 /* reg_ppcnt_a_frame_check_sequence_errors
4223 * Access: RO
4224 */
4225 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4226 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4227
4228 /* reg_ppcnt_a_alignment_errors
4229 * Access: RO
4230 */
4231 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4232 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4233
4234 /* reg_ppcnt_a_octets_transmitted_ok
4235 * Access: RO
4236 */
4237 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4238 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4239
4240 /* reg_ppcnt_a_octets_received_ok
4241 * Access: RO
4242 */
4243 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4244 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4245
4246 /* reg_ppcnt_a_multicast_frames_xmitted_ok
4247 * Access: RO
4248 */
4249 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4250 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4251
4252 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
4253 * Access: RO
4254 */
4255 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4256 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4257
4258 /* reg_ppcnt_a_multicast_frames_received_ok
4259 * Access: RO
4260 */
4261 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4262 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4263
4264 /* reg_ppcnt_a_broadcast_frames_received_ok
4265 * Access: RO
4266 */
4267 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4268 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4269
4270 /* reg_ppcnt_a_in_range_length_errors
4271 * Access: RO
4272 */
4273 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4274 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4275
4276 /* reg_ppcnt_a_out_of_range_length_field
4277 * Access: RO
4278 */
4279 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4280 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4281
4282 /* reg_ppcnt_a_frame_too_long_errors
4283 * Access: RO
4284 */
4285 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4286 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4287
4288 /* reg_ppcnt_a_symbol_error_during_carrier
4289 * Access: RO
4290 */
4291 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4292 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4293
4294 /* reg_ppcnt_a_mac_control_frames_transmitted
4295 * Access: RO
4296 */
4297 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4298 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4299
4300 /* reg_ppcnt_a_mac_control_frames_received
4301 * Access: RO
4302 */
4303 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4304 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4305
4306 /* reg_ppcnt_a_unsupported_opcodes_received
4307 * Access: RO
4308 */
4309 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4310 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4311
4312 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
4313 * Access: RO
4314 */
4315 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4316 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4317
4318 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4319 * Access: RO
4320 */
4321 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4322 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4323
4324 /* Ethernet RFC 2819 Counter Group */
4325
4326 /* reg_ppcnt_ether_stats_pkts64octets
4327 * Access: RO
4328 */
4329 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4330 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4331
4332 /* reg_ppcnt_ether_stats_pkts65to127octets
4333 * Access: RO
4334 */
4335 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4336 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4337
4338 /* reg_ppcnt_ether_stats_pkts128to255octets
4339 * Access: RO
4340 */
4341 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4342 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4343
4344 /* reg_ppcnt_ether_stats_pkts256to511octets
4345 * Access: RO
4346 */
4347 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4348 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4349
4350 /* reg_ppcnt_ether_stats_pkts512to1023octets
4351 * Access: RO
4352 */
4353 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4354 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4355
4356 /* reg_ppcnt_ether_stats_pkts1024to1518octets
4357 * Access: RO
4358 */
4359 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4360 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4361
4362 /* reg_ppcnt_ether_stats_pkts1519to2047octets
4363 * Access: RO
4364 */
4365 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4366 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4367
4368 /* reg_ppcnt_ether_stats_pkts2048to4095octets
4369 * Access: RO
4370 */
4371 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4372 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4373
4374 /* reg_ppcnt_ether_stats_pkts4096to8191octets
4375 * Access: RO
4376 */
4377 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4378 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4379
4380 /* reg_ppcnt_ether_stats_pkts8192to10239octets
4381 * Access: RO
4382 */
4383 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4384 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4385
4386 /* Ethernet Extended Counter Group Counters */
4387
4388 /* reg_ppcnt_ecn_marked
4389 * Access: RO
4390 */
4391 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4392 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4393
4394 /* Ethernet Per Priority Group Counters */
4395
4396 /* reg_ppcnt_rx_octets
4397 * Access: RO
4398 */
4399 MLXSW_ITEM64(reg, ppcnt, rx_octets,
4400 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4401
4402 /* reg_ppcnt_rx_frames
4403 * Access: RO
4404 */
4405 MLXSW_ITEM64(reg, ppcnt, rx_frames,
4406 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4407
4408 /* reg_ppcnt_tx_octets
4409 * Access: RO
4410 */
4411 MLXSW_ITEM64(reg, ppcnt, tx_octets,
4412 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4413
4414 /* reg_ppcnt_tx_frames
4415 * Access: RO
4416 */
4417 MLXSW_ITEM64(reg, ppcnt, tx_frames,
4418 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4419
4420 /* reg_ppcnt_rx_pause
4421 * Access: RO
4422 */
4423 MLXSW_ITEM64(reg, ppcnt, rx_pause,
4424 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4425
4426 /* reg_ppcnt_rx_pause_duration
4427 * Access: RO
4428 */
4429 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
4430 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4431
4432 /* reg_ppcnt_tx_pause
4433 * Access: RO
4434 */
4435 MLXSW_ITEM64(reg, ppcnt, tx_pause,
4436 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4437
4438 /* reg_ppcnt_tx_pause_duration
4439 * Access: RO
4440 */
4441 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
4442 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4443
4444 /* reg_ppcnt_rx_pause_transition
4445 * Access: RO
4446 */
4447 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
4448 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4449
4450 /* Ethernet Per Traffic Group Counters */
4451
4452 /* reg_ppcnt_tc_transmit_queue
4453 * Contains the transmit queue depth in cells of traffic class
4454 * selected by prio_tc and the port selected by local_port.
4455 * The field cannot be cleared.
4456 * Access: RO
4457 */
4458 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
4459 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4460
4461 /* reg_ppcnt_tc_no_buffer_discard_uc
4462 * The number of unicast packets dropped due to lack of shared
4463 * buffer resources.
4464 * Access: RO
4465 */
4466 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
4467 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4468
4469 /* Ethernet Per Traffic Class Congestion Group Counters */
4470
4471 /* reg_ppcnt_wred_discard
4472 * Access: RO
4473 */
4474 MLXSW_ITEM64(reg, ppcnt, wred_discard,
4475 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4476
mlxsw_reg_ppcnt_pack(char * payload,u8 local_port,enum mlxsw_reg_ppcnt_grp grp,u8 prio_tc)4477 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
4478 enum mlxsw_reg_ppcnt_grp grp,
4479 u8 prio_tc)
4480 {
4481 MLXSW_REG_ZERO(ppcnt, payload);
4482 mlxsw_reg_ppcnt_swid_set(payload, 0);
4483 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
4484 mlxsw_reg_ppcnt_pnat_set(payload, 0);
4485 mlxsw_reg_ppcnt_grp_set(payload, grp);
4486 mlxsw_reg_ppcnt_clr_set(payload, 0);
4487 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
4488 }
4489
4490 /* PLIB - Port Local to InfiniBand Port
4491 * ------------------------------------
4492 * The PLIB register performs mapping from Local Port into InfiniBand Port.
4493 */
4494 #define MLXSW_REG_PLIB_ID 0x500A
4495 #define MLXSW_REG_PLIB_LEN 0x10
4496
4497 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
4498
4499 /* reg_plib_local_port
4500 * Local port number.
4501 * Access: Index
4502 */
4503 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
4504
4505 /* reg_plib_ib_port
4506 * InfiniBand port remapping for local_port.
4507 * Access: RW
4508 */
4509 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
4510
4511 /* PPTB - Port Prio To Buffer Register
4512 * -----------------------------------
4513 * Configures the switch priority to buffer table.
4514 */
4515 #define MLXSW_REG_PPTB_ID 0x500B
4516 #define MLXSW_REG_PPTB_LEN 0x10
4517
4518 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
4519
4520 enum {
4521 MLXSW_REG_PPTB_MM_UM,
4522 MLXSW_REG_PPTB_MM_UNICAST,
4523 MLXSW_REG_PPTB_MM_MULTICAST,
4524 };
4525
4526 /* reg_pptb_mm
4527 * Mapping mode.
4528 * 0 - Map both unicast and multicast packets to the same buffer.
4529 * 1 - Map only unicast packets.
4530 * 2 - Map only multicast packets.
4531 * Access: Index
4532 *
4533 * Note: SwitchX-2 only supports the first option.
4534 */
4535 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
4536
4537 /* reg_pptb_local_port
4538 * Local port number.
4539 * Access: Index
4540 */
4541 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
4542
4543 /* reg_pptb_um
4544 * Enables the update of the untagged_buf field.
4545 * Access: RW
4546 */
4547 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
4548
4549 /* reg_pptb_pm
4550 * Enables the update of the prio_to_buff field.
4551 * Bit <i> is a flag for updating the mapping for switch priority <i>.
4552 * Access: RW
4553 */
4554 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
4555
4556 /* reg_pptb_prio_to_buff
4557 * Mapping of switch priority <i> to one of the allocated receive port
4558 * buffers.
4559 * Access: RW
4560 */
4561 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
4562
4563 /* reg_pptb_pm_msb
4564 * Enables the update of the prio_to_buff field.
4565 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
4566 * Access: RW
4567 */
4568 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
4569
4570 /* reg_pptb_untagged_buff
4571 * Mapping of untagged frames to one of the allocated receive port buffers.
4572 * Access: RW
4573 *
4574 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
4575 * Spectrum, as it maps untagged packets based on the default switch priority.
4576 */
4577 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
4578
4579 /* reg_pptb_prio_to_buff_msb
4580 * Mapping of switch priority <i+8> to one of the allocated receive port
4581 * buffers.
4582 * Access: RW
4583 */
4584 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
4585
4586 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
4587
mlxsw_reg_pptb_pack(char * payload,u8 local_port)4588 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
4589 {
4590 MLXSW_REG_ZERO(pptb, payload);
4591 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
4592 mlxsw_reg_pptb_local_port_set(payload, local_port);
4593 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
4594 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
4595 }
4596
mlxsw_reg_pptb_prio_to_buff_pack(char * payload,u8 prio,u8 buff)4597 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
4598 u8 buff)
4599 {
4600 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
4601 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
4602 }
4603
4604 /* PBMC - Port Buffer Management Control Register
4605 * ----------------------------------------------
4606 * The PBMC register configures and retrieves the port packet buffer
4607 * allocation for different Prios, and the Pause threshold management.
4608 */
4609 #define MLXSW_REG_PBMC_ID 0x500C
4610 #define MLXSW_REG_PBMC_LEN 0x6C
4611
4612 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
4613
4614 /* reg_pbmc_local_port
4615 * Local port number.
4616 * Access: Index
4617 */
4618 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
4619
4620 /* reg_pbmc_xoff_timer_value
4621 * When device generates a pause frame, it uses this value as the pause
4622 * timer (time for the peer port to pause in quota-512 bit time).
4623 * Access: RW
4624 */
4625 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
4626
4627 /* reg_pbmc_xoff_refresh
4628 * The time before a new pause frame should be sent to refresh the pause RW
4629 * state. Using the same units as xoff_timer_value above (in quota-512 bit
4630 * time).
4631 * Access: RW
4632 */
4633 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
4634
4635 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
4636
4637 /* reg_pbmc_buf_lossy
4638 * The field indicates if the buffer is lossy.
4639 * 0 - Lossless
4640 * 1 - Lossy
4641 * Access: RW
4642 */
4643 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
4644
4645 /* reg_pbmc_buf_epsb
4646 * Eligible for Port Shared buffer.
4647 * If epsb is set, packets assigned to buffer are allowed to insert the port
4648 * shared buffer.
4649 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
4650 * Access: RW
4651 */
4652 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
4653
4654 /* reg_pbmc_buf_size
4655 * The part of the packet buffer array is allocated for the specific buffer.
4656 * Units are represented in cells.
4657 * Access: RW
4658 */
4659 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
4660
4661 /* reg_pbmc_buf_xoff_threshold
4662 * Once the amount of data in the buffer goes above this value, device
4663 * starts sending PFC frames for all priorities associated with the
4664 * buffer. Units are represented in cells. Reserved in case of lossy
4665 * buffer.
4666 * Access: RW
4667 *
4668 * Note: In Spectrum, reserved for buffer[9].
4669 */
4670 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
4671 0x08, 0x04, false);
4672
4673 /* reg_pbmc_buf_xon_threshold
4674 * When the amount of data in the buffer goes below this value, device
4675 * stops sending PFC frames for the priorities associated with the
4676 * buffer. Units are represented in cells. Reserved in case of lossy
4677 * buffer.
4678 * Access: RW
4679 *
4680 * Note: In Spectrum, reserved for buffer[9].
4681 */
4682 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
4683 0x08, 0x04, false);
4684
mlxsw_reg_pbmc_pack(char * payload,u8 local_port,u16 xoff_timer_value,u16 xoff_refresh)4685 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
4686 u16 xoff_timer_value, u16 xoff_refresh)
4687 {
4688 MLXSW_REG_ZERO(pbmc, payload);
4689 mlxsw_reg_pbmc_local_port_set(payload, local_port);
4690 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
4691 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
4692 }
4693
mlxsw_reg_pbmc_lossy_buffer_pack(char * payload,int buf_index,u16 size)4694 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
4695 int buf_index,
4696 u16 size)
4697 {
4698 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
4699 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
4700 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
4701 }
4702
mlxsw_reg_pbmc_lossless_buffer_pack(char * payload,int buf_index,u16 size,u16 threshold)4703 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
4704 int buf_index, u16 size,
4705 u16 threshold)
4706 {
4707 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
4708 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
4709 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
4710 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
4711 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
4712 }
4713
4714 /* PSPA - Port Switch Partition Allocation
4715 * ---------------------------------------
4716 * Controls the association of a port with a switch partition and enables
4717 * configuring ports as stacking ports.
4718 */
4719 #define MLXSW_REG_PSPA_ID 0x500D
4720 #define MLXSW_REG_PSPA_LEN 0x8
4721
4722 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
4723
4724 /* reg_pspa_swid
4725 * Switch partition ID.
4726 * Access: RW
4727 */
4728 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
4729
4730 /* reg_pspa_local_port
4731 * Local port number.
4732 * Access: Index
4733 */
4734 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
4735
4736 /* reg_pspa_sub_port
4737 * Virtual port within the local port. Set to 0 when virtual ports are
4738 * disabled on the local port.
4739 * Access: Index
4740 */
4741 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
4742
mlxsw_reg_pspa_pack(char * payload,u8 swid,u8 local_port)4743 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
4744 {
4745 MLXSW_REG_ZERO(pspa, payload);
4746 mlxsw_reg_pspa_swid_set(payload, swid);
4747 mlxsw_reg_pspa_local_port_set(payload, local_port);
4748 mlxsw_reg_pspa_sub_port_set(payload, 0);
4749 }
4750
4751 /* HTGT - Host Trap Group Table
4752 * ----------------------------
4753 * Configures the properties for forwarding to CPU.
4754 */
4755 #define MLXSW_REG_HTGT_ID 0x7002
4756 #define MLXSW_REG_HTGT_LEN 0x20
4757
4758 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
4759
4760 /* reg_htgt_swid
4761 * Switch partition ID.
4762 * Access: Index
4763 */
4764 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
4765
4766 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
4767
4768 /* reg_htgt_type
4769 * CPU path type.
4770 * Access: RW
4771 */
4772 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
4773
4774 enum mlxsw_reg_htgt_trap_group {
4775 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4776 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
4777 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
4778 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
4779 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
4780 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
4781 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
4782 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
4783 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
4784 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
4785 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
4786 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
4787 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
4788 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
4789 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
4790 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
4791 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
4792 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
4793 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
4794 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
4795 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
4796 };
4797
4798 /* reg_htgt_trap_group
4799 * Trap group number. User defined number specifying which trap groups
4800 * should be forwarded to the CPU. The mapping between trap IDs and trap
4801 * groups is configured using HPKT register.
4802 * Access: Index
4803 */
4804 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
4805
4806 enum {
4807 MLXSW_REG_HTGT_POLICER_DISABLE,
4808 MLXSW_REG_HTGT_POLICER_ENABLE,
4809 };
4810
4811 /* reg_htgt_pide
4812 * Enable policer ID specified using 'pid' field.
4813 * Access: RW
4814 */
4815 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
4816
4817 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
4818
4819 /* reg_htgt_pid
4820 * Policer ID for the trap group.
4821 * Access: RW
4822 */
4823 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
4824
4825 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
4826
4827 /* reg_htgt_mirror_action
4828 * Mirror action to use.
4829 * 0 - Trap to CPU.
4830 * 1 - Trap to CPU and mirror to a mirroring agent.
4831 * 2 - Mirror to a mirroring agent and do not trap to CPU.
4832 * Access: RW
4833 *
4834 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
4835 */
4836 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
4837
4838 /* reg_htgt_mirroring_agent
4839 * Mirroring agent.
4840 * Access: RW
4841 */
4842 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
4843
4844 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
4845
4846 /* reg_htgt_priority
4847 * Trap group priority.
4848 * In case a packet matches multiple classification rules, the packet will
4849 * only be trapped once, based on the trap ID associated with the group (via
4850 * register HPKT) with the highest priority.
4851 * Supported values are 0-7, with 7 represnting the highest priority.
4852 * Access: RW
4853 *
4854 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
4855 * by the 'trap_group' field.
4856 */
4857 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
4858
4859 #define MLXSW_REG_HTGT_DEFAULT_TC 7
4860
4861 /* reg_htgt_local_path_cpu_tclass
4862 * CPU ingress traffic class for the trap group.
4863 * Access: RW
4864 */
4865 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
4866
4867 enum mlxsw_reg_htgt_local_path_rdq {
4868 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
4869 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
4870 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
4871 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
4872 };
4873 /* reg_htgt_local_path_rdq
4874 * Receive descriptor queue (RDQ) to use for the trap group.
4875 * Access: RW
4876 */
4877 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
4878
mlxsw_reg_htgt_pack(char * payload,u8 group,u8 policer_id,u8 priority,u8 tc)4879 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
4880 u8 priority, u8 tc)
4881 {
4882 MLXSW_REG_ZERO(htgt, payload);
4883
4884 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
4885 mlxsw_reg_htgt_pide_set(payload,
4886 MLXSW_REG_HTGT_POLICER_DISABLE);
4887 } else {
4888 mlxsw_reg_htgt_pide_set(payload,
4889 MLXSW_REG_HTGT_POLICER_ENABLE);
4890 mlxsw_reg_htgt_pid_set(payload, policer_id);
4891 }
4892
4893 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
4894 mlxsw_reg_htgt_trap_group_set(payload, group);
4895 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
4896 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
4897 mlxsw_reg_htgt_priority_set(payload, priority);
4898 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
4899 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
4900 }
4901
4902 /* HPKT - Host Packet Trap
4903 * -----------------------
4904 * Configures trap IDs inside trap groups.
4905 */
4906 #define MLXSW_REG_HPKT_ID 0x7003
4907 #define MLXSW_REG_HPKT_LEN 0x10
4908
4909 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
4910
4911 enum {
4912 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
4913 MLXSW_REG_HPKT_ACK_REQUIRED,
4914 };
4915
4916 /* reg_hpkt_ack
4917 * Require acknowledgements from the host for events.
4918 * If set, then the device will wait for the event it sent to be acknowledged
4919 * by the host. This option is only relevant for event trap IDs.
4920 * Access: RW
4921 *
4922 * Note: Currently not supported by firmware.
4923 */
4924 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
4925
4926 enum mlxsw_reg_hpkt_action {
4927 MLXSW_REG_HPKT_ACTION_FORWARD,
4928 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
4929 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
4930 MLXSW_REG_HPKT_ACTION_DISCARD,
4931 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
4932 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
4933 };
4934
4935 /* reg_hpkt_action
4936 * Action to perform on packet when trapped.
4937 * 0 - No action. Forward to CPU based on switching rules.
4938 * 1 - Trap to CPU (CPU receives sole copy).
4939 * 2 - Mirror to CPU (CPU receives a replica of the packet).
4940 * 3 - Discard.
4941 * 4 - Soft discard (allow other traps to act on the packet).
4942 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
4943 * Access: RW
4944 *
4945 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
4946 * addressed to the CPU.
4947 */
4948 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
4949
4950 /* reg_hpkt_trap_group
4951 * Trap group to associate the trap with.
4952 * Access: RW
4953 */
4954 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
4955
4956 /* reg_hpkt_trap_id
4957 * Trap ID.
4958 * Access: Index
4959 *
4960 * Note: A trap ID can only be associated with a single trap group. The device
4961 * will associate the trap ID with the last trap group configured.
4962 */
4963 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
4964
4965 enum {
4966 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
4967 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
4968 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
4969 };
4970
4971 /* reg_hpkt_ctrl
4972 * Configure dedicated buffer resources for control packets.
4973 * Ignored by SwitchX-2.
4974 * 0 - Keep factory defaults.
4975 * 1 - Do not use control buffer for this trap ID.
4976 * 2 - Use control buffer for this trap ID.
4977 * Access: RW
4978 */
4979 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
4980
mlxsw_reg_hpkt_pack(char * payload,u8 action,u16 trap_id,enum mlxsw_reg_htgt_trap_group trap_group,bool is_ctrl)4981 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
4982 enum mlxsw_reg_htgt_trap_group trap_group,
4983 bool is_ctrl)
4984 {
4985 MLXSW_REG_ZERO(hpkt, payload);
4986 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
4987 mlxsw_reg_hpkt_action_set(payload, action);
4988 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
4989 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
4990 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
4991 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
4992 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
4993 }
4994
4995 /* RGCR - Router General Configuration Register
4996 * --------------------------------------------
4997 * The register is used for setting up the router configuration.
4998 */
4999 #define MLXSW_REG_RGCR_ID 0x8001
5000 #define MLXSW_REG_RGCR_LEN 0x28
5001
5002 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5003
5004 /* reg_rgcr_ipv4_en
5005 * IPv4 router enable.
5006 * Access: RW
5007 */
5008 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5009
5010 /* reg_rgcr_ipv6_en
5011 * IPv6 router enable.
5012 * Access: RW
5013 */
5014 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5015
5016 /* reg_rgcr_max_router_interfaces
5017 * Defines the maximum number of active router interfaces for all virtual
5018 * routers.
5019 * Access: RW
5020 */
5021 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5022
5023 /* reg_rgcr_usp
5024 * Update switch priority and packet color.
5025 * 0 - Preserve the value of Switch Priority and packet color.
5026 * 1 - Recalculate the value of Switch Priority and packet color.
5027 * Access: RW
5028 *
5029 * Note: Not supported by SwitchX and SwitchX-2.
5030 */
5031 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5032
5033 /* reg_rgcr_pcp_rw
5034 * Indicates how to handle the pcp_rewrite_en value:
5035 * 0 - Preserve the value of pcp_rewrite_en.
5036 * 2 - Disable PCP rewrite.
5037 * 3 - Enable PCP rewrite.
5038 * Access: RW
5039 *
5040 * Note: Not supported by SwitchX and SwitchX-2.
5041 */
5042 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5043
5044 /* reg_rgcr_activity_dis
5045 * Activity disable:
5046 * 0 - Activity will be set when an entry is hit (default).
5047 * 1 - Activity will not be set when an entry is hit.
5048 *
5049 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
5050 * (RALUE).
5051 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
5052 * Entry (RAUHT).
5053 * Bits 2:7 are reserved.
5054 * Access: RW
5055 *
5056 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
5057 */
5058 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5059
mlxsw_reg_rgcr_pack(char * payload,bool ipv4_en,bool ipv6_en)5060 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5061 bool ipv6_en)
5062 {
5063 MLXSW_REG_ZERO(rgcr, payload);
5064 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5065 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5066 }
5067
5068 /* RITR - Router Interface Table Register
5069 * --------------------------------------
5070 * The register is used to configure the router interface table.
5071 */
5072 #define MLXSW_REG_RITR_ID 0x8002
5073 #define MLXSW_REG_RITR_LEN 0x40
5074
5075 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5076
5077 /* reg_ritr_enable
5078 * Enables routing on the router interface.
5079 * Access: RW
5080 */
5081 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5082
5083 /* reg_ritr_ipv4
5084 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
5085 * interface.
5086 * Access: RW
5087 */
5088 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5089
5090 /* reg_ritr_ipv6
5091 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
5092 * interface.
5093 * Access: RW
5094 */
5095 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5096
5097 /* reg_ritr_ipv4_mc
5098 * IPv4 multicast routing enable.
5099 * Access: RW
5100 */
5101 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5102
5103 /* reg_ritr_ipv6_mc
5104 * IPv6 multicast routing enable.
5105 * Access: RW
5106 */
5107 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5108
5109 enum mlxsw_reg_ritr_if_type {
5110 /* VLAN interface. */
5111 MLXSW_REG_RITR_VLAN_IF,
5112 /* FID interface. */
5113 MLXSW_REG_RITR_FID_IF,
5114 /* Sub-port interface. */
5115 MLXSW_REG_RITR_SP_IF,
5116 /* Loopback Interface. */
5117 MLXSW_REG_RITR_LOOPBACK_IF,
5118 };
5119
5120 /* reg_ritr_type
5121 * Router interface type as per enum mlxsw_reg_ritr_if_type.
5122 * Access: RW
5123 */
5124 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5125
5126 enum {
5127 MLXSW_REG_RITR_RIF_CREATE,
5128 MLXSW_REG_RITR_RIF_DEL,
5129 };
5130
5131 /* reg_ritr_op
5132 * Opcode:
5133 * 0 - Create or edit RIF.
5134 * 1 - Delete RIF.
5135 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
5136 * is not supported. An interface must be deleted and re-created in order
5137 * to update properties.
5138 * Access: WO
5139 */
5140 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5141
5142 /* reg_ritr_rif
5143 * Router interface index. A pointer to the Router Interface Table.
5144 * Access: Index
5145 */
5146 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5147
5148 /* reg_ritr_ipv4_fe
5149 * IPv4 Forwarding Enable.
5150 * Enables routing of IPv4 traffic on the router interface. When disabled,
5151 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5152 * Not supported in SwitchX-2.
5153 * Access: RW
5154 */
5155 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5156
5157 /* reg_ritr_ipv6_fe
5158 * IPv6 Forwarding Enable.
5159 * Enables routing of IPv6 traffic on the router interface. When disabled,
5160 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5161 * Not supported in SwitchX-2.
5162 * Access: RW
5163 */
5164 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5165
5166 /* reg_ritr_ipv4_mc_fe
5167 * IPv4 Multicast Forwarding Enable.
5168 * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5169 * will be enabled.
5170 * Access: RW
5171 */
5172 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5173
5174 /* reg_ritr_ipv6_mc_fe
5175 * IPv6 Multicast Forwarding Enable.
5176 * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5177 * will be enabled.
5178 * Access: RW
5179 */
5180 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5181
5182 /* reg_ritr_lb_en
5183 * Loop-back filter enable for unicast packets.
5184 * If the flag is set then loop-back filter for unicast packets is
5185 * implemented on the RIF. Multicast packets are always subject to
5186 * loop-back filtering.
5187 * Access: RW
5188 */
5189 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5190
5191 /* reg_ritr_virtual_router
5192 * Virtual router ID associated with the router interface.
5193 * Access: RW
5194 */
5195 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5196
5197 /* reg_ritr_mtu
5198 * Router interface MTU.
5199 * Access: RW
5200 */
5201 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5202
5203 /* reg_ritr_if_swid
5204 * Switch partition ID.
5205 * Access: RW
5206 */
5207 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5208
5209 /* reg_ritr_if_mac
5210 * Router interface MAC address.
5211 * In Spectrum, all MAC addresses must have the same 38 MSBits.
5212 * Access: RW
5213 */
5214 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5215
5216 /* reg_ritr_if_vrrp_id_ipv6
5217 * VRRP ID for IPv6
5218 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5219 * Access: RW
5220 */
5221 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5222
5223 /* reg_ritr_if_vrrp_id_ipv4
5224 * VRRP ID for IPv4
5225 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5226 * Access: RW
5227 */
5228 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5229
5230 /* VLAN Interface */
5231
5232 /* reg_ritr_vlan_if_vid
5233 * VLAN ID.
5234 * Access: RW
5235 */
5236 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5237
5238 /* FID Interface */
5239
5240 /* reg_ritr_fid_if_fid
5241 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
5242 * the vFID range are supported.
5243 * Access: RW
5244 */
5245 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5246
mlxsw_reg_ritr_fid_set(char * payload,enum mlxsw_reg_ritr_if_type rif_type,u16 fid)5247 static inline void mlxsw_reg_ritr_fid_set(char *payload,
5248 enum mlxsw_reg_ritr_if_type rif_type,
5249 u16 fid)
5250 {
5251 if (rif_type == MLXSW_REG_RITR_FID_IF)
5252 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5253 else
5254 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5255 }
5256
5257 /* Sub-port Interface */
5258
5259 /* reg_ritr_sp_if_lag
5260 * LAG indication. When this bit is set the system_port field holds the
5261 * LAG identifier.
5262 * Access: RW
5263 */
5264 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5265
5266 /* reg_ritr_sp_system_port
5267 * Port unique indentifier. When lag bit is set, this field holds the
5268 * lag_id in bits 0:9.
5269 * Access: RW
5270 */
5271 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5272
5273 /* reg_ritr_sp_if_vid
5274 * VLAN ID.
5275 * Access: RW
5276 */
5277 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5278
5279 /* Loopback Interface */
5280
5281 enum mlxsw_reg_ritr_loopback_protocol {
5282 /* IPinIP IPv4 underlay Unicast */
5283 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5284 /* IPinIP IPv6 underlay Unicast */
5285 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5286 };
5287
5288 /* reg_ritr_loopback_protocol
5289 * Access: RW
5290 */
5291 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5292
5293 enum mlxsw_reg_ritr_loopback_ipip_type {
5294 /* Tunnel is IPinIP. */
5295 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5296 /* Tunnel is GRE, no key. */
5297 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5298 /* Tunnel is GRE, with a key. */
5299 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5300 };
5301
5302 /* reg_ritr_loopback_ipip_type
5303 * Encapsulation type.
5304 * Access: RW
5305 */
5306 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5307
5308 enum mlxsw_reg_ritr_loopback_ipip_options {
5309 /* The key is defined by gre_key. */
5310 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5311 };
5312
5313 /* reg_ritr_loopback_ipip_options
5314 * Access: RW
5315 */
5316 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5317
5318 /* reg_ritr_loopback_ipip_uvr
5319 * Underlay Virtual Router ID.
5320 * Range is 0..cap_max_virtual_routers-1.
5321 * Reserved for Spectrum-2.
5322 * Access: RW
5323 */
5324 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5325
5326 /* reg_ritr_loopback_ipip_usip*
5327 * Encapsulation Underlay source IP.
5328 * Access: RW
5329 */
5330 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5331 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5332
5333 /* reg_ritr_loopback_ipip_gre_key
5334 * GRE Key.
5335 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
5336 * Access: RW
5337 */
5338 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5339
5340 /* Shared between ingress/egress */
5341 enum mlxsw_reg_ritr_counter_set_type {
5342 /* No Count. */
5343 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5344 /* Basic. Used for router interfaces, counting the following:
5345 * - Error and Discard counters.
5346 * - Unicast, Multicast and Broadcast counters. Sharing the
5347 * same set of counters for the different type of traffic
5348 * (IPv4, IPv6 and mpls).
5349 */
5350 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
5351 };
5352
5353 /* reg_ritr_ingress_counter_index
5354 * Counter Index for flow counter.
5355 * Access: RW
5356 */
5357 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
5358
5359 /* reg_ritr_ingress_counter_set_type
5360 * Igress Counter Set Type for router interface counter.
5361 * Access: RW
5362 */
5363 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
5364
5365 /* reg_ritr_egress_counter_index
5366 * Counter Index for flow counter.
5367 * Access: RW
5368 */
5369 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
5370
5371 /* reg_ritr_egress_counter_set_type
5372 * Egress Counter Set Type for router interface counter.
5373 * Access: RW
5374 */
5375 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
5376
mlxsw_reg_ritr_counter_pack(char * payload,u32 index,bool enable,bool egress)5377 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
5378 bool enable, bool egress)
5379 {
5380 enum mlxsw_reg_ritr_counter_set_type set_type;
5381
5382 if (enable)
5383 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
5384 else
5385 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
5386 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
5387
5388 if (egress)
5389 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
5390 else
5391 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
5392 }
5393
mlxsw_reg_ritr_rif_pack(char * payload,u16 rif)5394 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
5395 {
5396 MLXSW_REG_ZERO(ritr, payload);
5397 mlxsw_reg_ritr_rif_set(payload, rif);
5398 }
5399
mlxsw_reg_ritr_sp_if_pack(char * payload,bool lag,u16 system_port,u16 vid)5400 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
5401 u16 system_port, u16 vid)
5402 {
5403 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
5404 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
5405 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
5406 }
5407
mlxsw_reg_ritr_pack(char * payload,bool enable,enum mlxsw_reg_ritr_if_type type,u16 rif,u16 vr_id,u16 mtu)5408 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
5409 enum mlxsw_reg_ritr_if_type type,
5410 u16 rif, u16 vr_id, u16 mtu)
5411 {
5412 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
5413
5414 MLXSW_REG_ZERO(ritr, payload);
5415 mlxsw_reg_ritr_enable_set(payload, enable);
5416 mlxsw_reg_ritr_ipv4_set(payload, 1);
5417 mlxsw_reg_ritr_ipv6_set(payload, 1);
5418 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
5419 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
5420 mlxsw_reg_ritr_type_set(payload, type);
5421 mlxsw_reg_ritr_op_set(payload, op);
5422 mlxsw_reg_ritr_rif_set(payload, rif);
5423 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
5424 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
5425 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
5426 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
5427 mlxsw_reg_ritr_lb_en_set(payload, 1);
5428 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
5429 mlxsw_reg_ritr_mtu_set(payload, mtu);
5430 }
5431
mlxsw_reg_ritr_mac_pack(char * payload,const char * mac)5432 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
5433 {
5434 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
5435 }
5436
5437 static inline void
mlxsw_reg_ritr_loopback_ipip_common_pack(char * payload,enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,enum mlxsw_reg_ritr_loopback_ipip_options options,u16 uvr_id,u32 gre_key)5438 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
5439 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5440 enum mlxsw_reg_ritr_loopback_ipip_options options,
5441 u16 uvr_id, u32 gre_key)
5442 {
5443 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
5444 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
5445 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
5446 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
5447 }
5448
5449 static inline void
mlxsw_reg_ritr_loopback_ipip4_pack(char * payload,enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,enum mlxsw_reg_ritr_loopback_ipip_options options,u16 uvr_id,u32 usip,u32 gre_key)5450 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
5451 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5452 enum mlxsw_reg_ritr_loopback_ipip_options options,
5453 u16 uvr_id, u32 usip, u32 gre_key)
5454 {
5455 mlxsw_reg_ritr_loopback_protocol_set(payload,
5456 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
5457 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
5458 uvr_id, gre_key);
5459 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
5460 }
5461
5462 /* RTAR - Router TCAM Allocation Register
5463 * --------------------------------------
5464 * This register is used for allocation of regions in the TCAM table.
5465 */
5466 #define MLXSW_REG_RTAR_ID 0x8004
5467 #define MLXSW_REG_RTAR_LEN 0x20
5468
5469 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
5470
5471 enum mlxsw_reg_rtar_op {
5472 MLXSW_REG_RTAR_OP_ALLOCATE,
5473 MLXSW_REG_RTAR_OP_RESIZE,
5474 MLXSW_REG_RTAR_OP_DEALLOCATE,
5475 };
5476
5477 /* reg_rtar_op
5478 * Access: WO
5479 */
5480 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
5481
5482 enum mlxsw_reg_rtar_key_type {
5483 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
5484 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
5485 };
5486
5487 /* reg_rtar_key_type
5488 * TCAM key type for the region.
5489 * Access: WO
5490 */
5491 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
5492
5493 /* reg_rtar_region_size
5494 * TCAM region size. When allocating/resizing this is the requested
5495 * size, the response is the actual size.
5496 * Note: Actual size may be larger than requested.
5497 * Reserved for op = Deallocate
5498 * Access: WO
5499 */
5500 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
5501
mlxsw_reg_rtar_pack(char * payload,enum mlxsw_reg_rtar_op op,enum mlxsw_reg_rtar_key_type key_type,u16 region_size)5502 static inline void mlxsw_reg_rtar_pack(char *payload,
5503 enum mlxsw_reg_rtar_op op,
5504 enum mlxsw_reg_rtar_key_type key_type,
5505 u16 region_size)
5506 {
5507 MLXSW_REG_ZERO(rtar, payload);
5508 mlxsw_reg_rtar_op_set(payload, op);
5509 mlxsw_reg_rtar_key_type_set(payload, key_type);
5510 mlxsw_reg_rtar_region_size_set(payload, region_size);
5511 }
5512
5513 /* RATR - Router Adjacency Table Register
5514 * --------------------------------------
5515 * The RATR register is used to configure the Router Adjacency (next-hop)
5516 * Table.
5517 */
5518 #define MLXSW_REG_RATR_ID 0x8008
5519 #define MLXSW_REG_RATR_LEN 0x2C
5520
5521 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
5522
5523 enum mlxsw_reg_ratr_op {
5524 /* Read */
5525 MLXSW_REG_RATR_OP_QUERY_READ = 0,
5526 /* Read and clear activity */
5527 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
5528 /* Write Adjacency entry */
5529 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
5530 /* Write Adjacency entry only if the activity is cleared.
5531 * The write may not succeed if the activity is set. There is not
5532 * direct feedback if the write has succeeded or not, however
5533 * the get will reveal the actual entry (SW can compare the get
5534 * response to the set command).
5535 */
5536 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
5537 };
5538
5539 /* reg_ratr_op
5540 * Note that Write operation may also be used for updating
5541 * counter_set_type and counter_index. In this case all other
5542 * fields must not be updated.
5543 * Access: OP
5544 */
5545 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
5546
5547 /* reg_ratr_v
5548 * Valid bit. Indicates if the adjacency entry is valid.
5549 * Note: the device may need some time before reusing an invalidated
5550 * entry. During this time the entry can not be reused. It is
5551 * recommended to use another entry before reusing an invalidated
5552 * entry (e.g. software can put it at the end of the list for
5553 * reusing). Trying to access an invalidated entry not yet cleared
5554 * by the device results with failure indicating "Try Again" status.
5555 * When valid is '0' then egress_router_interface,trap_action,
5556 * adjacency_parameters and counters are reserved
5557 * Access: RW
5558 */
5559 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
5560
5561 /* reg_ratr_a
5562 * Activity. Set for new entries. Set if a packet lookup has hit on
5563 * the specific entry. To clear the a bit, use "clear activity".
5564 * Access: RO
5565 */
5566 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
5567
5568 enum mlxsw_reg_ratr_type {
5569 /* Ethernet */
5570 MLXSW_REG_RATR_TYPE_ETHERNET,
5571 /* IPoIB Unicast without GRH.
5572 * Reserved for Spectrum.
5573 */
5574 MLXSW_REG_RATR_TYPE_IPOIB_UC,
5575 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
5576 * adjacency).
5577 * Reserved for Spectrum.
5578 */
5579 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
5580 /* IPoIB Multicast.
5581 * Reserved for Spectrum.
5582 */
5583 MLXSW_REG_RATR_TYPE_IPOIB_MC,
5584 /* MPLS.
5585 * Reserved for SwitchX/-2.
5586 */
5587 MLXSW_REG_RATR_TYPE_MPLS,
5588 /* IPinIP Encap.
5589 * Reserved for SwitchX/-2.
5590 */
5591 MLXSW_REG_RATR_TYPE_IPIP,
5592 };
5593
5594 /* reg_ratr_type
5595 * Adjacency entry type.
5596 * Access: RW
5597 */
5598 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
5599
5600 /* reg_ratr_adjacency_index_low
5601 * Bits 15:0 of index into the adjacency table.
5602 * For SwitchX and SwitchX-2, the adjacency table is linear and
5603 * used for adjacency entries only.
5604 * For Spectrum, the index is to the KVD linear.
5605 * Access: Index
5606 */
5607 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
5608
5609 /* reg_ratr_egress_router_interface
5610 * Range is 0 .. cap_max_router_interfaces - 1
5611 * Access: RW
5612 */
5613 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
5614
5615 enum mlxsw_reg_ratr_trap_action {
5616 MLXSW_REG_RATR_TRAP_ACTION_NOP,
5617 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
5618 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
5619 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
5620 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
5621 };
5622
5623 /* reg_ratr_trap_action
5624 * see mlxsw_reg_ratr_trap_action
5625 * Access: RW
5626 */
5627 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
5628
5629 /* reg_ratr_adjacency_index_high
5630 * Bits 23:16 of the adjacency_index.
5631 * Access: Index
5632 */
5633 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
5634
5635 enum mlxsw_reg_ratr_trap_id {
5636 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
5637 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
5638 };
5639
5640 /* reg_ratr_trap_id
5641 * Trap ID to be reported to CPU.
5642 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
5643 * For trap_action of NOP, MIRROR and DISCARD_ERROR
5644 * Access: RW
5645 */
5646 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
5647
5648 /* reg_ratr_eth_destination_mac
5649 * MAC address of the destination next-hop.
5650 * Access: RW
5651 */
5652 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
5653
5654 enum mlxsw_reg_ratr_ipip_type {
5655 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
5656 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
5657 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
5658 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
5659 };
5660
5661 /* reg_ratr_ipip_type
5662 * Underlay destination ip type.
5663 * Note: the type field must match the protocol of the router interface.
5664 * Access: RW
5665 */
5666 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
5667
5668 /* reg_ratr_ipip_ipv4_udip
5669 * Underlay ipv4 dip.
5670 * Reserved when ipip_type is IPv6.
5671 * Access: RW
5672 */
5673 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
5674
5675 /* reg_ratr_ipip_ipv6_ptr
5676 * Pointer to IPv6 underlay destination ip address.
5677 * For Spectrum: Pointer to KVD linear space.
5678 * Access: RW
5679 */
5680 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
5681
5682 enum mlxsw_reg_flow_counter_set_type {
5683 /* No count */
5684 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
5685 /* Count packets and bytes */
5686 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
5687 /* Count only packets */
5688 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
5689 };
5690
5691 /* reg_ratr_counter_set_type
5692 * Counter set type for flow counters
5693 * Access: RW
5694 */
5695 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
5696
5697 /* reg_ratr_counter_index
5698 * Counter index for flow counters
5699 * Access: RW
5700 */
5701 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
5702
5703 static inline void
mlxsw_reg_ratr_pack(char * payload,enum mlxsw_reg_ratr_op op,bool valid,enum mlxsw_reg_ratr_type type,u32 adjacency_index,u16 egress_rif)5704 mlxsw_reg_ratr_pack(char *payload,
5705 enum mlxsw_reg_ratr_op op, bool valid,
5706 enum mlxsw_reg_ratr_type type,
5707 u32 adjacency_index, u16 egress_rif)
5708 {
5709 MLXSW_REG_ZERO(ratr, payload);
5710 mlxsw_reg_ratr_op_set(payload, op);
5711 mlxsw_reg_ratr_v_set(payload, valid);
5712 mlxsw_reg_ratr_type_set(payload, type);
5713 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
5714 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
5715 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
5716 }
5717
mlxsw_reg_ratr_eth_entry_pack(char * payload,const char * dest_mac)5718 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
5719 const char *dest_mac)
5720 {
5721 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
5722 }
5723
mlxsw_reg_ratr_ipip4_entry_pack(char * payload,u32 ipv4_udip)5724 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
5725 {
5726 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
5727 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
5728 }
5729
mlxsw_reg_ratr_counter_pack(char * payload,u64 counter_index,bool counter_enable)5730 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
5731 bool counter_enable)
5732 {
5733 enum mlxsw_reg_flow_counter_set_type set_type;
5734
5735 if (counter_enable)
5736 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
5737 else
5738 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
5739
5740 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
5741 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
5742 }
5743
5744 /* RDPM - Router DSCP to Priority Mapping
5745 * --------------------------------------
5746 * Controls the mapping from DSCP field to switch priority on routed packets
5747 */
5748 #define MLXSW_REG_RDPM_ID 0x8009
5749 #define MLXSW_REG_RDPM_BASE_LEN 0x00
5750 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
5751 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
5752 #define MLXSW_REG_RDPM_LEN 0x40
5753 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
5754 MLXSW_REG_RDPM_LEN - \
5755 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
5756
5757 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
5758
5759 /* reg_dscp_entry_e
5760 * Enable update of the specific entry
5761 * Access: Index
5762 */
5763 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
5764 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
5765
5766 /* reg_dscp_entry_prio
5767 * Switch Priority
5768 * Access: RW
5769 */
5770 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
5771 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
5772
mlxsw_reg_rdpm_pack(char * payload,unsigned short index,u8 prio)5773 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
5774 u8 prio)
5775 {
5776 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
5777 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
5778 }
5779
5780 /* RICNT - Router Interface Counter Register
5781 * -----------------------------------------
5782 * The RICNT register retrieves per port performance counters
5783 */
5784 #define MLXSW_REG_RICNT_ID 0x800B
5785 #define MLXSW_REG_RICNT_LEN 0x100
5786
5787 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
5788
5789 /* reg_ricnt_counter_index
5790 * Counter index
5791 * Access: RW
5792 */
5793 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
5794
5795 enum mlxsw_reg_ricnt_counter_set_type {
5796 /* No Count. */
5797 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
5798 /* Basic. Used for router interfaces, counting the following:
5799 * - Error and Discard counters.
5800 * - Unicast, Multicast and Broadcast counters. Sharing the
5801 * same set of counters for the different type of traffic
5802 * (IPv4, IPv6 and mpls).
5803 */
5804 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
5805 };
5806
5807 /* reg_ricnt_counter_set_type
5808 * Counter Set Type for router interface counter
5809 * Access: RW
5810 */
5811 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
5812
5813 enum mlxsw_reg_ricnt_opcode {
5814 /* Nop. Supported only for read access*/
5815 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
5816 /* Clear. Setting the clr bit will reset the counter value for
5817 * all counters of the specified Router Interface.
5818 */
5819 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
5820 };
5821
5822 /* reg_ricnt_opcode
5823 * Opcode
5824 * Access: RW
5825 */
5826 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
5827
5828 /* reg_ricnt_good_unicast_packets
5829 * good unicast packets.
5830 * Access: RW
5831 */
5832 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
5833
5834 /* reg_ricnt_good_multicast_packets
5835 * good multicast packets.
5836 * Access: RW
5837 */
5838 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
5839
5840 /* reg_ricnt_good_broadcast_packets
5841 * good broadcast packets
5842 * Access: RW
5843 */
5844 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
5845
5846 /* reg_ricnt_good_unicast_bytes
5847 * A count of L3 data and padding octets not including L2 headers
5848 * for good unicast frames.
5849 * Access: RW
5850 */
5851 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
5852
5853 /* reg_ricnt_good_multicast_bytes
5854 * A count of L3 data and padding octets not including L2 headers
5855 * for good multicast frames.
5856 * Access: RW
5857 */
5858 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
5859
5860 /* reg_ritr_good_broadcast_bytes
5861 * A count of L3 data and padding octets not including L2 headers
5862 * for good broadcast frames.
5863 * Access: RW
5864 */
5865 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
5866
5867 /* reg_ricnt_error_packets
5868 * A count of errored frames that do not pass the router checks.
5869 * Access: RW
5870 */
5871 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
5872
5873 /* reg_ricnt_discrad_packets
5874 * A count of non-errored frames that do not pass the router checks.
5875 * Access: RW
5876 */
5877 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
5878
5879 /* reg_ricnt_error_bytes
5880 * A count of L3 data and padding octets not including L2 headers
5881 * for errored frames.
5882 * Access: RW
5883 */
5884 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
5885
5886 /* reg_ricnt_discard_bytes
5887 * A count of L3 data and padding octets not including L2 headers
5888 * for non-errored frames that do not pass the router checks.
5889 * Access: RW
5890 */
5891 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
5892
mlxsw_reg_ricnt_pack(char * payload,u32 index,enum mlxsw_reg_ricnt_opcode op)5893 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
5894 enum mlxsw_reg_ricnt_opcode op)
5895 {
5896 MLXSW_REG_ZERO(ricnt, payload);
5897 mlxsw_reg_ricnt_op_set(payload, op);
5898 mlxsw_reg_ricnt_counter_index_set(payload, index);
5899 mlxsw_reg_ricnt_counter_set_type_set(payload,
5900 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
5901 }
5902
5903 /* RRCR - Router Rules Copy Register Layout
5904 * ----------------------------------------
5905 * This register is used for moving and copying route entry rules.
5906 */
5907 #define MLXSW_REG_RRCR_ID 0x800F
5908 #define MLXSW_REG_RRCR_LEN 0x24
5909
5910 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
5911
5912 enum mlxsw_reg_rrcr_op {
5913 /* Move rules */
5914 MLXSW_REG_RRCR_OP_MOVE,
5915 /* Copy rules */
5916 MLXSW_REG_RRCR_OP_COPY,
5917 };
5918
5919 /* reg_rrcr_op
5920 * Access: WO
5921 */
5922 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
5923
5924 /* reg_rrcr_offset
5925 * Offset within the region from which to copy/move.
5926 * Access: Index
5927 */
5928 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
5929
5930 /* reg_rrcr_size
5931 * The number of rules to copy/move.
5932 * Access: WO
5933 */
5934 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
5935
5936 /* reg_rrcr_table_id
5937 * Identifier of the table on which to perform the operation. Encoding is the
5938 * same as in RTAR.key_type
5939 * Access: Index
5940 */
5941 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
5942
5943 /* reg_rrcr_dest_offset
5944 * Offset within the region to which to copy/move
5945 * Access: Index
5946 */
5947 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
5948
mlxsw_reg_rrcr_pack(char * payload,enum mlxsw_reg_rrcr_op op,u16 offset,u16 size,enum mlxsw_reg_rtar_key_type table_id,u16 dest_offset)5949 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
5950 u16 offset, u16 size,
5951 enum mlxsw_reg_rtar_key_type table_id,
5952 u16 dest_offset)
5953 {
5954 MLXSW_REG_ZERO(rrcr, payload);
5955 mlxsw_reg_rrcr_op_set(payload, op);
5956 mlxsw_reg_rrcr_offset_set(payload, offset);
5957 mlxsw_reg_rrcr_size_set(payload, size);
5958 mlxsw_reg_rrcr_table_id_set(payload, table_id);
5959 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
5960 }
5961
5962 /* RALTA - Router Algorithmic LPM Tree Allocation Register
5963 * -------------------------------------------------------
5964 * RALTA is used to allocate the LPM trees of the SHSPM method.
5965 */
5966 #define MLXSW_REG_RALTA_ID 0x8010
5967 #define MLXSW_REG_RALTA_LEN 0x04
5968
5969 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
5970
5971 /* reg_ralta_op
5972 * opcode (valid for Write, must be 0 on Read)
5973 * 0 - allocate a tree
5974 * 1 - deallocate a tree
5975 * Access: OP
5976 */
5977 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
5978
5979 enum mlxsw_reg_ralxx_protocol {
5980 MLXSW_REG_RALXX_PROTOCOL_IPV4,
5981 MLXSW_REG_RALXX_PROTOCOL_IPV6,
5982 };
5983
5984 /* reg_ralta_protocol
5985 * Protocol.
5986 * Deallocation opcode: Reserved.
5987 * Access: RW
5988 */
5989 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
5990
5991 /* reg_ralta_tree_id
5992 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
5993 * the tree identifier (managed by software).
5994 * Note that tree_id 0 is allocated for a default-route tree.
5995 * Access: Index
5996 */
5997 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
5998
mlxsw_reg_ralta_pack(char * payload,bool alloc,enum mlxsw_reg_ralxx_protocol protocol,u8 tree_id)5999 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6000 enum mlxsw_reg_ralxx_protocol protocol,
6001 u8 tree_id)
6002 {
6003 MLXSW_REG_ZERO(ralta, payload);
6004 mlxsw_reg_ralta_op_set(payload, !alloc);
6005 mlxsw_reg_ralta_protocol_set(payload, protocol);
6006 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6007 }
6008
6009 /* RALST - Router Algorithmic LPM Structure Tree Register
6010 * ------------------------------------------------------
6011 * RALST is used to set and query the structure of an LPM tree.
6012 * The structure of the tree must be sorted as a sorted binary tree, while
6013 * each node is a bin that is tagged as the length of the prefixes the lookup
6014 * will refer to. Therefore, bin X refers to a set of entries with prefixes
6015 * of X bits to match with the destination address. The bin 0 indicates
6016 * the default action, when there is no match of any prefix.
6017 */
6018 #define MLXSW_REG_RALST_ID 0x8011
6019 #define MLXSW_REG_RALST_LEN 0x104
6020
6021 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6022
6023 /* reg_ralst_root_bin
6024 * The bin number of the root bin.
6025 * 0<root_bin=<(length of IP address)
6026 * For a default-route tree configure 0xff
6027 * Access: RW
6028 */
6029 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6030
6031 /* reg_ralst_tree_id
6032 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6033 * Access: Index
6034 */
6035 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6036
6037 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6038 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
6039 #define MLXSW_REG_RALST_BIN_COUNT 128
6040
6041 /* reg_ralst_left_child_bin
6042 * Holding the children of the bin according to the stored tree's structure.
6043 * For trees composed of less than 4 blocks, the bins in excess are reserved.
6044 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6045 * Access: RW
6046 */
6047 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6048
6049 /* reg_ralst_right_child_bin
6050 * Holding the children of the bin according to the stored tree's structure.
6051 * For trees composed of less than 4 blocks, the bins in excess are reserved.
6052 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6053 * Access: RW
6054 */
6055 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6056 false);
6057
mlxsw_reg_ralst_pack(char * payload,u8 root_bin,u8 tree_id)6058 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6059 {
6060 MLXSW_REG_ZERO(ralst, payload);
6061
6062 /* Initialize all bins to have no left or right child */
6063 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6064 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6065
6066 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6067 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6068 }
6069
mlxsw_reg_ralst_bin_pack(char * payload,u8 bin_number,u8 left_child_bin,u8 right_child_bin)6070 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6071 u8 left_child_bin,
6072 u8 right_child_bin)
6073 {
6074 int bin_index = bin_number - 1;
6075
6076 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6077 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6078 right_child_bin);
6079 }
6080
6081 /* RALTB - Router Algorithmic LPM Tree Binding Register
6082 * ----------------------------------------------------
6083 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
6084 */
6085 #define MLXSW_REG_RALTB_ID 0x8012
6086 #define MLXSW_REG_RALTB_LEN 0x04
6087
6088 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6089
6090 /* reg_raltb_virtual_router
6091 * Virtual Router ID
6092 * Range is 0..cap_max_virtual_routers-1
6093 * Access: Index
6094 */
6095 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6096
6097 /* reg_raltb_protocol
6098 * Protocol.
6099 * Access: Index
6100 */
6101 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6102
6103 /* reg_raltb_tree_id
6104 * Tree to be used for the {virtual_router, protocol}
6105 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6106 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
6107 * Access: RW
6108 */
6109 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6110
mlxsw_reg_raltb_pack(char * payload,u16 virtual_router,enum mlxsw_reg_ralxx_protocol protocol,u8 tree_id)6111 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6112 enum mlxsw_reg_ralxx_protocol protocol,
6113 u8 tree_id)
6114 {
6115 MLXSW_REG_ZERO(raltb, payload);
6116 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6117 mlxsw_reg_raltb_protocol_set(payload, protocol);
6118 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6119 }
6120
6121 /* RALUE - Router Algorithmic LPM Unicast Entry Register
6122 * -----------------------------------------------------
6123 * RALUE is used to configure and query LPM entries that serve
6124 * the Unicast protocols.
6125 */
6126 #define MLXSW_REG_RALUE_ID 0x8013
6127 #define MLXSW_REG_RALUE_LEN 0x38
6128
6129 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6130
6131 /* reg_ralue_protocol
6132 * Protocol.
6133 * Access: Index
6134 */
6135 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6136
6137 enum mlxsw_reg_ralue_op {
6138 /* Read operation. If entry doesn't exist, the operation fails. */
6139 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6140 /* Clear on read operation. Used to read entry and
6141 * clear Activity bit.
6142 */
6143 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6144 /* Write operation. Used to write a new entry to the table. All RW
6145 * fields are written for new entry. Activity bit is set
6146 * for new entries.
6147 */
6148 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6149 /* Update operation. Used to update an existing route entry and
6150 * only update the RW fields that are detailed in the field
6151 * op_u_mask. If entry doesn't exist, the operation fails.
6152 */
6153 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6154 /* Clear activity. The Activity bit (the field a) is cleared
6155 * for the entry.
6156 */
6157 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6158 /* Delete operation. Used to delete an existing entry. If entry
6159 * doesn't exist, the operation fails.
6160 */
6161 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6162 };
6163
6164 /* reg_ralue_op
6165 * Operation.
6166 * Access: OP
6167 */
6168 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6169
6170 /* reg_ralue_a
6171 * Activity. Set for new entries. Set if a packet lookup has hit on the
6172 * specific entry, only if the entry is a route. To clear the a bit, use
6173 * "clear activity" op.
6174 * Enabled by activity_dis in RGCR
6175 * Access: RO
6176 */
6177 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6178
6179 /* reg_ralue_virtual_router
6180 * Virtual Router ID
6181 * Range is 0..cap_max_virtual_routers-1
6182 * Access: Index
6183 */
6184 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6185
6186 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
6187 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
6188 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
6189
6190 /* reg_ralue_op_u_mask
6191 * opcode update mask.
6192 * On read operation, this field is reserved.
6193 * This field is valid for update opcode, otherwise - reserved.
6194 * This field is a bitmask of the fields that should be updated.
6195 * Access: WO
6196 */
6197 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6198
6199 /* reg_ralue_prefix_len
6200 * Number of bits in the prefix of the LPM route.
6201 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
6202 * two entries in the physical HW table.
6203 * Access: Index
6204 */
6205 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6206
6207 /* reg_ralue_dip*
6208 * The prefix of the route or of the marker that the object of the LPM
6209 * is compared with. The most significant bits of the dip are the prefix.
6210 * The least significant bits must be '0' if the prefix_len is smaller
6211 * than 128 for IPv6 or smaller than 32 for IPv4.
6212 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
6213 * Access: Index
6214 */
6215 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6216 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6217
6218 enum mlxsw_reg_ralue_entry_type {
6219 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6220 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6221 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6222 };
6223
6224 /* reg_ralue_entry_type
6225 * Entry type.
6226 * Note - for Marker entries, the action_type and action fields are reserved.
6227 * Access: RW
6228 */
6229 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6230
6231 /* reg_ralue_bmp_len
6232 * The best match prefix length in the case that there is no match for
6233 * longer prefixes.
6234 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
6235 * Note for any update operation with entry_type modification this
6236 * field must be set.
6237 * Access: RW
6238 */
6239 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6240
6241 enum mlxsw_reg_ralue_action_type {
6242 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6243 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6244 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6245 };
6246
6247 /* reg_ralue_action_type
6248 * Action Type
6249 * Indicates how the IP address is connected.
6250 * It can be connected to a local subnet through local_erif or can be
6251 * on a remote subnet connected through a next-hop router,
6252 * or transmitted to the CPU.
6253 * Reserved when entry_type = MARKER_ENTRY
6254 * Access: RW
6255 */
6256 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6257
6258 enum mlxsw_reg_ralue_trap_action {
6259 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6260 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6261 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6262 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6263 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6264 };
6265
6266 /* reg_ralue_trap_action
6267 * Trap action.
6268 * For IP2ME action, only NOP and MIRROR are possible.
6269 * Access: RW
6270 */
6271 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6272
6273 /* reg_ralue_trap_id
6274 * Trap ID to be reported to CPU.
6275 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
6276 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
6277 * Access: RW
6278 */
6279 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6280
6281 /* reg_ralue_adjacency_index
6282 * Points to the first entry of the group-based ECMP.
6283 * Only relevant in case of REMOTE action.
6284 * Access: RW
6285 */
6286 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6287
6288 /* reg_ralue_ecmp_size
6289 * Amount of sequential entries starting
6290 * from the adjacency_index (the number of ECMPs).
6291 * The valid range is 1-64, 512, 1024, 2048 and 4096.
6292 * Reserved when trap_action is TRAP or DISCARD_ERROR.
6293 * Only relevant in case of REMOTE action.
6294 * Access: RW
6295 */
6296 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6297
6298 /* reg_ralue_local_erif
6299 * Egress Router Interface.
6300 * Only relevant in case of LOCAL action.
6301 * Access: RW
6302 */
6303 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6304
6305 /* reg_ralue_ip2me_v
6306 * Valid bit for the tunnel_ptr field.
6307 * If valid = 0 then trap to CPU as IP2ME trap ID.
6308 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
6309 * decapsulation then tunnel decapsulation is done.
6310 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
6311 * decapsulation then trap as IP2ME trap ID.
6312 * Only relevant in case of IP2ME action.
6313 * Access: RW
6314 */
6315 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6316
6317 /* reg_ralue_ip2me_tunnel_ptr
6318 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
6319 * For Spectrum, pointer to KVD Linear.
6320 * Only relevant in case of IP2ME action.
6321 * Access: RW
6322 */
6323 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6324
mlxsw_reg_ralue_pack(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len)6325 static inline void mlxsw_reg_ralue_pack(char *payload,
6326 enum mlxsw_reg_ralxx_protocol protocol,
6327 enum mlxsw_reg_ralue_op op,
6328 u16 virtual_router, u8 prefix_len)
6329 {
6330 MLXSW_REG_ZERO(ralue, payload);
6331 mlxsw_reg_ralue_protocol_set(payload, protocol);
6332 mlxsw_reg_ralue_op_set(payload, op);
6333 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6334 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6335 mlxsw_reg_ralue_entry_type_set(payload,
6336 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6337 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6338 }
6339
mlxsw_reg_ralue_pack4(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len,u32 dip)6340 static inline void mlxsw_reg_ralue_pack4(char *payload,
6341 enum mlxsw_reg_ralxx_protocol protocol,
6342 enum mlxsw_reg_ralue_op op,
6343 u16 virtual_router, u8 prefix_len,
6344 u32 dip)
6345 {
6346 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6347 mlxsw_reg_ralue_dip4_set(payload, dip);
6348 }
6349
mlxsw_reg_ralue_pack6(char * payload,enum mlxsw_reg_ralxx_protocol protocol,enum mlxsw_reg_ralue_op op,u16 virtual_router,u8 prefix_len,const void * dip)6350 static inline void mlxsw_reg_ralue_pack6(char *payload,
6351 enum mlxsw_reg_ralxx_protocol protocol,
6352 enum mlxsw_reg_ralue_op op,
6353 u16 virtual_router, u8 prefix_len,
6354 const void *dip)
6355 {
6356 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6357 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
6358 }
6359
6360 static inline void
mlxsw_reg_ralue_act_remote_pack(char * payload,enum mlxsw_reg_ralue_trap_action trap_action,u16 trap_id,u32 adjacency_index,u16 ecmp_size)6361 mlxsw_reg_ralue_act_remote_pack(char *payload,
6362 enum mlxsw_reg_ralue_trap_action trap_action,
6363 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
6364 {
6365 mlxsw_reg_ralue_action_type_set(payload,
6366 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
6367 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6368 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6369 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
6370 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
6371 }
6372
6373 static inline void
mlxsw_reg_ralue_act_local_pack(char * payload,enum mlxsw_reg_ralue_trap_action trap_action,u16 trap_id,u16 local_erif)6374 mlxsw_reg_ralue_act_local_pack(char *payload,
6375 enum mlxsw_reg_ralue_trap_action trap_action,
6376 u16 trap_id, u16 local_erif)
6377 {
6378 mlxsw_reg_ralue_action_type_set(payload,
6379 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
6380 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
6381 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
6382 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
6383 }
6384
6385 static inline void
mlxsw_reg_ralue_act_ip2me_pack(char * payload)6386 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
6387 {
6388 mlxsw_reg_ralue_action_type_set(payload,
6389 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6390 }
6391
6392 static inline void
mlxsw_reg_ralue_act_ip2me_tun_pack(char * payload,u32 tunnel_ptr)6393 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
6394 {
6395 mlxsw_reg_ralue_action_type_set(payload,
6396 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
6397 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
6398 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
6399 }
6400
6401 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
6402 * ----------------------------------------------------------
6403 * The RAUHT register is used to configure and query the Unicast Host table in
6404 * devices that implement the Algorithmic LPM.
6405 */
6406 #define MLXSW_REG_RAUHT_ID 0x8014
6407 #define MLXSW_REG_RAUHT_LEN 0x74
6408
6409 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
6410
6411 enum mlxsw_reg_rauht_type {
6412 MLXSW_REG_RAUHT_TYPE_IPV4,
6413 MLXSW_REG_RAUHT_TYPE_IPV6,
6414 };
6415
6416 /* reg_rauht_type
6417 * Access: Index
6418 */
6419 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
6420
6421 enum mlxsw_reg_rauht_op {
6422 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
6423 /* Read operation */
6424 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
6425 /* Clear on read operation. Used to read entry and clear
6426 * activity bit.
6427 */
6428 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
6429 /* Add. Used to write a new entry to the table. All R/W fields are
6430 * relevant for new entry. Activity bit is set for new entries.
6431 */
6432 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
6433 /* Update action. Used to update an existing route entry and
6434 * only update the following fields:
6435 * trap_action, trap_id, mac, counter_set_type, counter_index
6436 */
6437 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
6438 /* Clear activity. A bit is cleared for the entry. */
6439 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
6440 /* Delete entry */
6441 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
6442 /* Delete all host entries on a RIF. In this command, dip
6443 * field is reserved.
6444 */
6445 };
6446
6447 /* reg_rauht_op
6448 * Access: OP
6449 */
6450 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
6451
6452 /* reg_rauht_a
6453 * Activity. Set for new entries. Set if a packet lookup has hit on
6454 * the specific entry.
6455 * To clear the a bit, use "clear activity" op.
6456 * Enabled by activity_dis in RGCR
6457 * Access: RO
6458 */
6459 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
6460
6461 /* reg_rauht_rif
6462 * Router Interface
6463 * Access: Index
6464 */
6465 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
6466
6467 /* reg_rauht_dip*
6468 * Destination address.
6469 * Access: Index
6470 */
6471 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
6472 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
6473
6474 enum mlxsw_reg_rauht_trap_action {
6475 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
6476 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
6477 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
6478 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
6479 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
6480 };
6481
6482 /* reg_rauht_trap_action
6483 * Access: RW
6484 */
6485 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
6486
6487 enum mlxsw_reg_rauht_trap_id {
6488 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
6489 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
6490 };
6491
6492 /* reg_rauht_trap_id
6493 * Trap ID to be reported to CPU.
6494 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
6495 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
6496 * trap_id is reserved.
6497 * Access: RW
6498 */
6499 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
6500
6501 /* reg_rauht_counter_set_type
6502 * Counter set type for flow counters
6503 * Access: RW
6504 */
6505 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
6506
6507 /* reg_rauht_counter_index
6508 * Counter index for flow counters
6509 * Access: RW
6510 */
6511 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
6512
6513 /* reg_rauht_mac
6514 * MAC address.
6515 * Access: RW
6516 */
6517 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
6518
mlxsw_reg_rauht_pack(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac)6519 static inline void mlxsw_reg_rauht_pack(char *payload,
6520 enum mlxsw_reg_rauht_op op, u16 rif,
6521 const char *mac)
6522 {
6523 MLXSW_REG_ZERO(rauht, payload);
6524 mlxsw_reg_rauht_op_set(payload, op);
6525 mlxsw_reg_rauht_rif_set(payload, rif);
6526 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
6527 }
6528
mlxsw_reg_rauht_pack4(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac,u32 dip)6529 static inline void mlxsw_reg_rauht_pack4(char *payload,
6530 enum mlxsw_reg_rauht_op op, u16 rif,
6531 const char *mac, u32 dip)
6532 {
6533 mlxsw_reg_rauht_pack(payload, op, rif, mac);
6534 mlxsw_reg_rauht_dip4_set(payload, dip);
6535 }
6536
mlxsw_reg_rauht_pack6(char * payload,enum mlxsw_reg_rauht_op op,u16 rif,const char * mac,const char * dip)6537 static inline void mlxsw_reg_rauht_pack6(char *payload,
6538 enum mlxsw_reg_rauht_op op, u16 rif,
6539 const char *mac, const char *dip)
6540 {
6541 mlxsw_reg_rauht_pack(payload, op, rif, mac);
6542 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
6543 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
6544 }
6545
mlxsw_reg_rauht_pack_counter(char * payload,u64 counter_index)6546 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
6547 u64 counter_index)
6548 {
6549 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
6550 mlxsw_reg_rauht_counter_set_type_set(payload,
6551 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
6552 }
6553
6554 /* RALEU - Router Algorithmic LPM ECMP Update Register
6555 * ---------------------------------------------------
6556 * The register enables updating the ECMP section in the action for multiple
6557 * LPM Unicast entries in a single operation. The update is executed to
6558 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
6559 */
6560 #define MLXSW_REG_RALEU_ID 0x8015
6561 #define MLXSW_REG_RALEU_LEN 0x28
6562
6563 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
6564
6565 /* reg_raleu_protocol
6566 * Protocol.
6567 * Access: Index
6568 */
6569 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
6570
6571 /* reg_raleu_virtual_router
6572 * Virtual Router ID
6573 * Range is 0..cap_max_virtual_routers-1
6574 * Access: Index
6575 */
6576 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
6577
6578 /* reg_raleu_adjacency_index
6579 * Adjacency Index used for matching on the existing entries.
6580 * Access: Index
6581 */
6582 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
6583
6584 /* reg_raleu_ecmp_size
6585 * ECMP Size used for matching on the existing entries.
6586 * Access: Index
6587 */
6588 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
6589
6590 /* reg_raleu_new_adjacency_index
6591 * New Adjacency Index.
6592 * Access: WO
6593 */
6594 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
6595
6596 /* reg_raleu_new_ecmp_size
6597 * New ECMP Size.
6598 * Access: WO
6599 */
6600 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
6601
mlxsw_reg_raleu_pack(char * payload,enum mlxsw_reg_ralxx_protocol protocol,u16 virtual_router,u32 adjacency_index,u16 ecmp_size,u32 new_adjacency_index,u16 new_ecmp_size)6602 static inline void mlxsw_reg_raleu_pack(char *payload,
6603 enum mlxsw_reg_ralxx_protocol protocol,
6604 u16 virtual_router,
6605 u32 adjacency_index, u16 ecmp_size,
6606 u32 new_adjacency_index,
6607 u16 new_ecmp_size)
6608 {
6609 MLXSW_REG_ZERO(raleu, payload);
6610 mlxsw_reg_raleu_protocol_set(payload, protocol);
6611 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
6612 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
6613 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
6614 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
6615 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
6616 }
6617
6618 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
6619 * ----------------------------------------------------------------
6620 * The RAUHTD register allows dumping entries from the Router Unicast Host
6621 * Table. For a given session an entry is dumped no more than one time. The
6622 * first RAUHTD access after reset is a new session. A session ends when the
6623 * num_rec response is smaller than num_rec request or for IPv4 when the
6624 * num_entries is smaller than 4. The clear activity affect the current session
6625 * or the last session if a new session has not started.
6626 */
6627 #define MLXSW_REG_RAUHTD_ID 0x8018
6628 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
6629 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
6630 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
6631 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
6632 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
6633 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
6634
6635 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
6636
6637 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
6638 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
6639
6640 /* reg_rauhtd_filter_fields
6641 * if a bit is '0' then the relevant field is ignored and dump is done
6642 * regardless of the field value
6643 * Bit0 - filter by activity: entry_a
6644 * Bit3 - filter by entry rip: entry_rif
6645 * Access: Index
6646 */
6647 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
6648
6649 enum mlxsw_reg_rauhtd_op {
6650 MLXSW_REG_RAUHTD_OP_DUMP,
6651 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
6652 };
6653
6654 /* reg_rauhtd_op
6655 * Access: OP
6656 */
6657 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
6658
6659 /* reg_rauhtd_num_rec
6660 * At request: number of records requested
6661 * At response: number of records dumped
6662 * For IPv4, each record has 4 entries at request and up to 4 entries
6663 * at response
6664 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
6665 * Access: Index
6666 */
6667 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
6668
6669 /* reg_rauhtd_entry_a
6670 * Dump only if activity has value of entry_a
6671 * Reserved if filter_fields bit0 is '0'
6672 * Access: Index
6673 */
6674 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
6675
6676 enum mlxsw_reg_rauhtd_type {
6677 MLXSW_REG_RAUHTD_TYPE_IPV4,
6678 MLXSW_REG_RAUHTD_TYPE_IPV6,
6679 };
6680
6681 /* reg_rauhtd_type
6682 * Dump only if record type is:
6683 * 0 - IPv4
6684 * 1 - IPv6
6685 * Access: Index
6686 */
6687 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
6688
6689 /* reg_rauhtd_entry_rif
6690 * Dump only if RIF has value of entry_rif
6691 * Reserved if filter_fields bit3 is '0'
6692 * Access: Index
6693 */
6694 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
6695
mlxsw_reg_rauhtd_pack(char * payload,enum mlxsw_reg_rauhtd_type type)6696 static inline void mlxsw_reg_rauhtd_pack(char *payload,
6697 enum mlxsw_reg_rauhtd_type type)
6698 {
6699 MLXSW_REG_ZERO(rauhtd, payload);
6700 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
6701 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
6702 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
6703 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
6704 mlxsw_reg_rauhtd_type_set(payload, type);
6705 }
6706
6707 /* reg_rauhtd_ipv4_rec_num_entries
6708 * Number of valid entries in this record:
6709 * 0 - 1 valid entry
6710 * 1 - 2 valid entries
6711 * 2 - 3 valid entries
6712 * 3 - 4 valid entries
6713 * Access: RO
6714 */
6715 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
6716 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
6717 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
6718
6719 /* reg_rauhtd_rec_type
6720 * Record type.
6721 * 0 - IPv4
6722 * 1 - IPv6
6723 * Access: RO
6724 */
6725 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
6726 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
6727
6728 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
6729
6730 /* reg_rauhtd_ipv4_ent_a
6731 * Activity. Set for new entries. Set if a packet lookup has hit on the
6732 * specific entry.
6733 * Access: RO
6734 */
6735 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
6736 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
6737
6738 /* reg_rauhtd_ipv4_ent_rif
6739 * Router interface.
6740 * Access: RO
6741 */
6742 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6743 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
6744
6745 /* reg_rauhtd_ipv4_ent_dip
6746 * Destination IPv4 address.
6747 * Access: RO
6748 */
6749 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6750 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
6751
6752 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
6753
6754 /* reg_rauhtd_ipv6_ent_a
6755 * Activity. Set for new entries. Set if a packet lookup has hit on the
6756 * specific entry.
6757 * Access: RO
6758 */
6759 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
6760 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
6761
6762 /* reg_rauhtd_ipv6_ent_rif
6763 * Router interface.
6764 * Access: RO
6765 */
6766 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
6767 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
6768
6769 /* reg_rauhtd_ipv6_ent_dip
6770 * Destination IPv6 address.
6771 * Access: RO
6772 */
6773 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
6774 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
6775
mlxsw_reg_rauhtd_ent_ipv4_unpack(char * payload,int ent_index,u16 * p_rif,u32 * p_dip)6776 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
6777 int ent_index, u16 *p_rif,
6778 u32 *p_dip)
6779 {
6780 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
6781 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
6782 }
6783
mlxsw_reg_rauhtd_ent_ipv6_unpack(char * payload,int rec_index,u16 * p_rif,char * p_dip)6784 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
6785 int rec_index, u16 *p_rif,
6786 char *p_dip)
6787 {
6788 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
6789 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
6790 }
6791
6792 /* RTDP - Routing Tunnel Decap Properties Register
6793 * -----------------------------------------------
6794 * The RTDP register is used for configuring the tunnel decap properties of NVE
6795 * and IPinIP.
6796 */
6797 #define MLXSW_REG_RTDP_ID 0x8020
6798 #define MLXSW_REG_RTDP_LEN 0x44
6799
6800 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
6801
6802 enum mlxsw_reg_rtdp_type {
6803 MLXSW_REG_RTDP_TYPE_NVE,
6804 MLXSW_REG_RTDP_TYPE_IPIP,
6805 };
6806
6807 /* reg_rtdp_type
6808 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
6809 * Access: RW
6810 */
6811 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
6812
6813 /* reg_rtdp_tunnel_index
6814 * Index to the Decap entry.
6815 * For Spectrum, Index to KVD Linear.
6816 * Access: Index
6817 */
6818 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
6819
6820 /* IPinIP */
6821
6822 /* reg_rtdp_ipip_irif
6823 * Ingress Router Interface for the overlay router
6824 * Access: RW
6825 */
6826 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
6827
6828 enum mlxsw_reg_rtdp_ipip_sip_check {
6829 /* No sip checks. */
6830 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
6831 /* Filter packet if underlay is not IPv4 or if underlay SIP does not
6832 * equal ipv4_usip.
6833 */
6834 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
6835 /* Filter packet if underlay is not IPv6 or if underlay SIP does not
6836 * equal ipv6_usip.
6837 */
6838 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
6839 };
6840
6841 /* reg_rtdp_ipip_sip_check
6842 * SIP check to perform. If decapsulation failed due to these configurations
6843 * then trap_id is IPIP_DECAP_ERROR.
6844 * Access: RW
6845 */
6846 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
6847
6848 /* If set, allow decapsulation of IPinIP (without GRE). */
6849 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
6850 /* If set, allow decapsulation of IPinGREinIP without a key. */
6851 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
6852 /* If set, allow decapsulation of IPinGREinIP with a key. */
6853 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
6854
6855 /* reg_rtdp_ipip_type_check
6856 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
6857 * these configurations then trap_id is IPIP_DECAP_ERROR.
6858 * Access: RW
6859 */
6860 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
6861
6862 /* reg_rtdp_ipip_gre_key_check
6863 * Whether GRE key should be checked. When check is enabled:
6864 * - A packet received as IPinIP (without GRE) will always pass.
6865 * - A packet received as IPinGREinIP without a key will not pass the check.
6866 * - A packet received as IPinGREinIP with a key will pass the check only if the
6867 * key in the packet is equal to expected_gre_key.
6868 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
6869 * Access: RW
6870 */
6871 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
6872
6873 /* reg_rtdp_ipip_ipv4_usip
6874 * Underlay IPv4 address for ipv4 source address check.
6875 * Reserved when sip_check is not '1'.
6876 * Access: RW
6877 */
6878 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
6879
6880 /* reg_rtdp_ipip_ipv6_usip_ptr
6881 * This field is valid when sip_check is "sipv6 check explicitly". This is a
6882 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
6883 * is to the KVD linear.
6884 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
6885 * Access: RW
6886 */
6887 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
6888
6889 /* reg_rtdp_ipip_expected_gre_key
6890 * GRE key for checking.
6891 * Reserved when gre_key_check is '0'.
6892 * Access: RW
6893 */
6894 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
6895
mlxsw_reg_rtdp_pack(char * payload,enum mlxsw_reg_rtdp_type type,u32 tunnel_index)6896 static inline void mlxsw_reg_rtdp_pack(char *payload,
6897 enum mlxsw_reg_rtdp_type type,
6898 u32 tunnel_index)
6899 {
6900 MLXSW_REG_ZERO(rtdp, payload);
6901 mlxsw_reg_rtdp_type_set(payload, type);
6902 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
6903 }
6904
6905 static inline void
mlxsw_reg_rtdp_ipip4_pack(char * payload,u16 irif,enum mlxsw_reg_rtdp_ipip_sip_check sip_check,unsigned int type_check,bool gre_key_check,u32 ipv4_usip,u32 expected_gre_key)6906 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
6907 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
6908 unsigned int type_check, bool gre_key_check,
6909 u32 ipv4_usip, u32 expected_gre_key)
6910 {
6911 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
6912 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
6913 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
6914 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
6915 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
6916 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
6917 }
6918
6919 /* RIGR-V2 - Router Interface Group Register Version 2
6920 * ---------------------------------------------------
6921 * The RIGR_V2 register is used to add, remove and query egress interface list
6922 * of a multicast forwarding entry.
6923 */
6924 #define MLXSW_REG_RIGR2_ID 0x8023
6925 #define MLXSW_REG_RIGR2_LEN 0xB0
6926
6927 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
6928
6929 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
6930
6931 /* reg_rigr2_rigr_index
6932 * KVD Linear index.
6933 * Access: Index
6934 */
6935 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
6936
6937 /* reg_rigr2_vnext
6938 * Next RIGR Index is valid.
6939 * Access: RW
6940 */
6941 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
6942
6943 /* reg_rigr2_next_rigr_index
6944 * Next RIGR Index. The index is to the KVD linear.
6945 * Reserved when vnxet = '0'.
6946 * Access: RW
6947 */
6948 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
6949
6950 /* reg_rigr2_vrmid
6951 * RMID Index is valid.
6952 * Access: RW
6953 */
6954 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
6955
6956 /* reg_rigr2_rmid_index
6957 * RMID Index.
6958 * Range 0 .. max_mid - 1
6959 * Reserved when vrmid = '0'.
6960 * The index is to the Port Group Table (PGT)
6961 * Access: RW
6962 */
6963 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
6964
6965 /* reg_rigr2_erif_entry_v
6966 * Egress Router Interface is valid.
6967 * Note that low-entries must be set if high-entries are set. For
6968 * example: if erif_entry[2].v is set then erif_entry[1].v and
6969 * erif_entry[0].v must be set.
6970 * Index can be from 0 to cap_mc_erif_list_entries-1
6971 * Access: RW
6972 */
6973 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
6974
6975 /* reg_rigr2_erif_entry_erif
6976 * Egress Router Interface.
6977 * Valid range is from 0 to cap_max_router_interfaces - 1
6978 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
6979 * Access: RW
6980 */
6981 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
6982
mlxsw_reg_rigr2_pack(char * payload,u32 rigr_index,bool vnext,u32 next_rigr_index)6983 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
6984 bool vnext, u32 next_rigr_index)
6985 {
6986 MLXSW_REG_ZERO(rigr2, payload);
6987 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
6988 mlxsw_reg_rigr2_vnext_set(payload, vnext);
6989 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
6990 mlxsw_reg_rigr2_vrmid_set(payload, 0);
6991 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
6992 }
6993
mlxsw_reg_rigr2_erif_entry_pack(char * payload,int index,bool v,u16 erif)6994 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
6995 bool v, u16 erif)
6996 {
6997 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
6998 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
6999 }
7000
7001 /* RECR-V2 - Router ECMP Configuration Version 2 Register
7002 * ------------------------------------------------------
7003 */
7004 #define MLXSW_REG_RECR2_ID 0x8025
7005 #define MLXSW_REG_RECR2_LEN 0x38
7006
7007 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7008
7009 /* reg_recr2_pp
7010 * Per-port configuration
7011 * Access: Index
7012 */
7013 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7014
7015 /* reg_recr2_sh
7016 * Symmetric hash
7017 * Access: RW
7018 */
7019 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7020
7021 /* reg_recr2_seed
7022 * Seed
7023 * Access: RW
7024 */
7025 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7026
7027 enum {
7028 /* Enable IPv4 fields if packet is not TCP and not UDP */
7029 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
7030 /* Enable IPv4 fields if packet is TCP or UDP */
7031 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
7032 /* Enable IPv6 fields if packet is not TCP and not UDP */
7033 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
7034 /* Enable IPv6 fields if packet is TCP or UDP */
7035 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
7036 /* Enable TCP/UDP header fields if packet is IPv4 */
7037 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
7038 /* Enable TCP/UDP header fields if packet is IPv6 */
7039 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
7040 };
7041
7042 /* reg_recr2_outer_header_enables
7043 * Bit mask where each bit enables a specific layer to be included in
7044 * the hash calculation.
7045 * Access: RW
7046 */
7047 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7048
7049 enum {
7050 /* IPv4 Source IP */
7051 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
7052 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
7053 /* IPv4 Destination IP */
7054 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
7055 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
7056 /* IP Protocol */
7057 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
7058 /* IPv6 Source IP */
7059 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
7060 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
7061 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
7062 /* IPv6 Destination IP */
7063 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
7064 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
7065 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
7066 /* IPv6 Next Header */
7067 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
7068 /* IPv6 Flow Label */
7069 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
7070 /* TCP/UDP Source Port */
7071 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
7072 /* TCP/UDP Destination Port */
7073 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
7074 };
7075
7076 /* reg_recr2_outer_header_fields_enable
7077 * Packet fields to enable for ECMP hash subject to outer_header_enable.
7078 * Access: RW
7079 */
7080 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7081
mlxsw_reg_recr2_ipv4_sip_enable(char * payload)7082 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7083 {
7084 int i;
7085
7086 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7087 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7088 true);
7089 }
7090
mlxsw_reg_recr2_ipv4_dip_enable(char * payload)7091 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7092 {
7093 int i;
7094
7095 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7096 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7097 true);
7098 }
7099
mlxsw_reg_recr2_ipv6_sip_enable(char * payload)7100 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7101 {
7102 int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7103
7104 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7105
7106 i = MLXSW_REG_RECR2_IPV6_SIP8;
7107 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7108 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7109 true);
7110 }
7111
mlxsw_reg_recr2_ipv6_dip_enable(char * payload)7112 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7113 {
7114 int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7115
7116 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7117
7118 i = MLXSW_REG_RECR2_IPV6_DIP8;
7119 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7120 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7121 true);
7122 }
7123
mlxsw_reg_recr2_pack(char * payload,u32 seed)7124 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7125 {
7126 MLXSW_REG_ZERO(recr2, payload);
7127 mlxsw_reg_recr2_pp_set(payload, false);
7128 mlxsw_reg_recr2_sh_set(payload, true);
7129 mlxsw_reg_recr2_seed_set(payload, seed);
7130 }
7131
7132 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
7133 * --------------------------------------------------------------
7134 * The RMFT_V2 register is used to configure and query the multicast table.
7135 */
7136 #define MLXSW_REG_RMFT2_ID 0x8027
7137 #define MLXSW_REG_RMFT2_LEN 0x174
7138
7139 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7140
7141 /* reg_rmft2_v
7142 * Valid
7143 * Access: RW
7144 */
7145 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7146
7147 enum mlxsw_reg_rmft2_type {
7148 MLXSW_REG_RMFT2_TYPE_IPV4,
7149 MLXSW_REG_RMFT2_TYPE_IPV6
7150 };
7151
7152 /* reg_rmft2_type
7153 * Access: Index
7154 */
7155 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7156
7157 enum mlxsw_sp_reg_rmft2_op {
7158 /* For Write:
7159 * Write operation. Used to write a new entry to the table. All RW
7160 * fields are relevant for new entry. Activity bit is set for new
7161 * entries - Note write with v (Valid) 0 will delete the entry.
7162 * For Query:
7163 * Read operation
7164 */
7165 MLXSW_REG_RMFT2_OP_READ_WRITE,
7166 };
7167
7168 /* reg_rmft2_op
7169 * Operation.
7170 * Access: OP
7171 */
7172 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7173
7174 /* reg_rmft2_a
7175 * Activity. Set for new entries. Set if a packet lookup has hit on the specific
7176 * entry.
7177 * Access: RO
7178 */
7179 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7180
7181 /* reg_rmft2_offset
7182 * Offset within the multicast forwarding table to write to.
7183 * Access: Index
7184 */
7185 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7186
7187 /* reg_rmft2_virtual_router
7188 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
7189 * Access: RW
7190 */
7191 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7192
7193 enum mlxsw_reg_rmft2_irif_mask {
7194 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7195 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7196 };
7197
7198 /* reg_rmft2_irif_mask
7199 * Ingress RIF mask.
7200 * Access: RW
7201 */
7202 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7203
7204 /* reg_rmft2_irif
7205 * Ingress RIF index.
7206 * Access: RW
7207 */
7208 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7209
7210 /* reg_rmft2_dip{4,6}
7211 * Destination IPv4/6 address
7212 * Access: RW
7213 */
7214 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7215 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7216
7217 /* reg_rmft2_dip{4,6}_mask
7218 * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7219 * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7220 * Access: RW
7221 */
7222 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7223 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7224
7225 /* reg_rmft2_sip{4,6}
7226 * Source IPv4/6 address
7227 * Access: RW
7228 */
7229 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7230 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7231
7232 /* reg_rmft2_sip{4,6}_mask
7233 * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7234 * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7235 * Access: RW
7236 */
7237 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7238 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7239
7240 /* reg_rmft2_flexible_action_set
7241 * ACL action set. The only supported action types in this field and in any
7242 * action-set pointed from here are as follows:
7243 * 00h: ACTION_NULL
7244 * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
7245 * 03h: ACTION_TRAP
7246 * 06h: ACTION_QOS
7247 * 08h: ACTION_POLICING_MONITORING
7248 * 10h: ACTION_ROUTER_MC
7249 * Access: RW
7250 */
7251 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7252 MLXSW_REG_FLEX_ACTION_SET_LEN);
7253
7254 static inline void
mlxsw_reg_rmft2_common_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,const char * flex_action_set)7255 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7256 u16 virtual_router,
7257 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7258 const char *flex_action_set)
7259 {
7260 MLXSW_REG_ZERO(rmft2, payload);
7261 mlxsw_reg_rmft2_v_set(payload, v);
7262 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7263 mlxsw_reg_rmft2_offset_set(payload, offset);
7264 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7265 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7266 mlxsw_reg_rmft2_irif_set(payload, irif);
7267 if (flex_action_set)
7268 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7269 flex_action_set);
7270 }
7271
7272 static inline void
mlxsw_reg_rmft2_ipv4_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,u32 dip4,u32 dip4_mask,u32 sip4,u32 sip4_mask,const char * flexible_action_set)7273 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7274 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7275 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7276 const char *flexible_action_set)
7277 {
7278 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7279 irif_mask, irif, flexible_action_set);
7280 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7281 mlxsw_reg_rmft2_dip4_set(payload, dip4);
7282 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7283 mlxsw_reg_rmft2_sip4_set(payload, sip4);
7284 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7285 }
7286
7287 static inline void
mlxsw_reg_rmft2_ipv6_pack(char * payload,bool v,u16 offset,u16 virtual_router,enum mlxsw_reg_rmft2_irif_mask irif_mask,u16 irif,struct in6_addr dip6,struct in6_addr dip6_mask,struct in6_addr sip6,struct in6_addr sip6_mask,const char * flexible_action_set)7288 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7289 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7290 struct in6_addr dip6, struct in6_addr dip6_mask,
7291 struct in6_addr sip6, struct in6_addr sip6_mask,
7292 const char *flexible_action_set)
7293 {
7294 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7295 irif_mask, irif, flexible_action_set);
7296 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7297 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7298 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7299 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7300 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7301 }
7302
7303 /* MFCR - Management Fan Control Register
7304 * --------------------------------------
7305 * This register controls the settings of the Fan Speed PWM mechanism.
7306 */
7307 #define MLXSW_REG_MFCR_ID 0x9001
7308 #define MLXSW_REG_MFCR_LEN 0x08
7309
7310 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7311
7312 enum mlxsw_reg_mfcr_pwm_frequency {
7313 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7314 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7315 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7316 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7317 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7318 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7319 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7320 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7321 };
7322
7323 /* reg_mfcr_pwm_frequency
7324 * Controls the frequency of the PWM signal.
7325 * Access: RW
7326 */
7327 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7328
7329 #define MLXSW_MFCR_TACHOS_MAX 10
7330
7331 /* reg_mfcr_tacho_active
7332 * Indicates which of the tachometer is active (bit per tachometer).
7333 * Access: RO
7334 */
7335 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7336
7337 #define MLXSW_MFCR_PWMS_MAX 5
7338
7339 /* reg_mfcr_pwm_active
7340 * Indicates which of the PWM control is active (bit per PWM).
7341 * Access: RO
7342 */
7343 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
7344
7345 static inline void
mlxsw_reg_mfcr_pack(char * payload,enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)7346 mlxsw_reg_mfcr_pack(char *payload,
7347 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
7348 {
7349 MLXSW_REG_ZERO(mfcr, payload);
7350 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
7351 }
7352
7353 static inline void
mlxsw_reg_mfcr_unpack(char * payload,enum mlxsw_reg_mfcr_pwm_frequency * p_pwm_frequency,u16 * p_tacho_active,u8 * p_pwm_active)7354 mlxsw_reg_mfcr_unpack(char *payload,
7355 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
7356 u16 *p_tacho_active, u8 *p_pwm_active)
7357 {
7358 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
7359 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
7360 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
7361 }
7362
7363 /* MFSC - Management Fan Speed Control Register
7364 * --------------------------------------------
7365 * This register controls the settings of the Fan Speed PWM mechanism.
7366 */
7367 #define MLXSW_REG_MFSC_ID 0x9002
7368 #define MLXSW_REG_MFSC_LEN 0x08
7369
7370 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
7371
7372 /* reg_mfsc_pwm
7373 * Fan pwm to control / monitor.
7374 * Access: Index
7375 */
7376 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
7377
7378 /* reg_mfsc_pwm_duty_cycle
7379 * Controls the duty cycle of the PWM. Value range from 0..255 to
7380 * represent duty cycle of 0%...100%.
7381 * Access: RW
7382 */
7383 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
7384
mlxsw_reg_mfsc_pack(char * payload,u8 pwm,u8 pwm_duty_cycle)7385 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
7386 u8 pwm_duty_cycle)
7387 {
7388 MLXSW_REG_ZERO(mfsc, payload);
7389 mlxsw_reg_mfsc_pwm_set(payload, pwm);
7390 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
7391 }
7392
7393 /* MFSM - Management Fan Speed Measurement
7394 * ---------------------------------------
7395 * This register controls the settings of the Tacho measurements and
7396 * enables reading the Tachometer measurements.
7397 */
7398 #define MLXSW_REG_MFSM_ID 0x9003
7399 #define MLXSW_REG_MFSM_LEN 0x08
7400
7401 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
7402
7403 /* reg_mfsm_tacho
7404 * Fan tachometer index.
7405 * Access: Index
7406 */
7407 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
7408
7409 /* reg_mfsm_rpm
7410 * Fan speed (round per minute).
7411 * Access: RO
7412 */
7413 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
7414
mlxsw_reg_mfsm_pack(char * payload,u8 tacho)7415 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
7416 {
7417 MLXSW_REG_ZERO(mfsm, payload);
7418 mlxsw_reg_mfsm_tacho_set(payload, tacho);
7419 }
7420
7421 /* MFSL - Management Fan Speed Limit Register
7422 * ------------------------------------------
7423 * The Fan Speed Limit register is used to configure the fan speed
7424 * event / interrupt notification mechanism. Fan speed threshold are
7425 * defined for both under-speed and over-speed.
7426 */
7427 #define MLXSW_REG_MFSL_ID 0x9004
7428 #define MLXSW_REG_MFSL_LEN 0x0C
7429
7430 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
7431
7432 /* reg_mfsl_tacho
7433 * Fan tachometer index.
7434 * Access: Index
7435 */
7436 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
7437
7438 /* reg_mfsl_tach_min
7439 * Tachometer minimum value (minimum RPM).
7440 * Access: RW
7441 */
7442 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
7443
7444 /* reg_mfsl_tach_max
7445 * Tachometer maximum value (maximum RPM).
7446 * Access: RW
7447 */
7448 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
7449
mlxsw_reg_mfsl_pack(char * payload,u8 tacho,u16 tach_min,u16 tach_max)7450 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
7451 u16 tach_min, u16 tach_max)
7452 {
7453 MLXSW_REG_ZERO(mfsl, payload);
7454 mlxsw_reg_mfsl_tacho_set(payload, tacho);
7455 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
7456 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
7457 }
7458
mlxsw_reg_mfsl_unpack(char * payload,u8 tacho,u16 * p_tach_min,u16 * p_tach_max)7459 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
7460 u16 *p_tach_min, u16 *p_tach_max)
7461 {
7462 if (p_tach_min)
7463 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
7464
7465 if (p_tach_max)
7466 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
7467 }
7468
7469 /* MTCAP - Management Temperature Capabilities
7470 * -------------------------------------------
7471 * This register exposes the capabilities of the device and
7472 * system temperature sensing.
7473 */
7474 #define MLXSW_REG_MTCAP_ID 0x9009
7475 #define MLXSW_REG_MTCAP_LEN 0x08
7476
7477 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
7478
7479 /* reg_mtcap_sensor_count
7480 * Number of sensors supported by the device.
7481 * This includes the QSFP module sensors (if exists in the QSFP module).
7482 * Access: RO
7483 */
7484 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
7485
7486 /* MTMP - Management Temperature
7487 * -----------------------------
7488 * This register controls the settings of the temperature measurements
7489 * and enables reading the temperature measurements. Note that temperature
7490 * is in 0.125 degrees Celsius.
7491 */
7492 #define MLXSW_REG_MTMP_ID 0x900A
7493 #define MLXSW_REG_MTMP_LEN 0x20
7494
7495 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
7496
7497 /* reg_mtmp_sensor_index
7498 * Sensors index to access.
7499 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
7500 * (module 0 is mapped to sensor_index 64).
7501 * Access: Index
7502 */
7503 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
7504
7505 /* Convert to milli degrees Celsius */
7506 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
7507
7508 /* reg_mtmp_temperature
7509 * Temperature reading from the sensor. Reading is in 0.125 Celsius
7510 * degrees units.
7511 * Access: RO
7512 */
7513 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
7514
7515 /* reg_mtmp_mte
7516 * Max Temperature Enable - enables measuring the max temperature on a sensor.
7517 * Access: RW
7518 */
7519 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
7520
7521 /* reg_mtmp_mtr
7522 * Max Temperature Reset - clears the value of the max temperature register.
7523 * Access: WO
7524 */
7525 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
7526
7527 /* reg_mtmp_max_temperature
7528 * The highest measured temperature from the sensor.
7529 * When the bit mte is cleared, the field max_temperature is reserved.
7530 * Access: RO
7531 */
7532 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
7533
7534 /* reg_mtmp_tee
7535 * Temperature Event Enable.
7536 * 0 - Do not generate event
7537 * 1 - Generate event
7538 * 2 - Generate single event
7539 * Access: RW
7540 */
7541 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
7542
7543 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */
7544
7545 /* reg_mtmp_temperature_threshold_hi
7546 * High threshold for Temperature Warning Event. In 0.125 Celsius.
7547 * Access: RW
7548 */
7549 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
7550
7551 /* reg_mtmp_temperature_threshold_lo
7552 * Low threshold for Temperature Warning Event. In 0.125 Celsius.
7553 * Access: RW
7554 */
7555 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
7556
7557 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
7558
7559 /* reg_mtmp_sensor_name
7560 * Sensor Name
7561 * Access: RO
7562 */
7563 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
7564
mlxsw_reg_mtmp_pack(char * payload,u8 sensor_index,bool max_temp_enable,bool max_temp_reset)7565 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
7566 bool max_temp_enable,
7567 bool max_temp_reset)
7568 {
7569 MLXSW_REG_ZERO(mtmp, payload);
7570 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
7571 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
7572 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
7573 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
7574 MLXSW_REG_MTMP_THRESH_HI);
7575 }
7576
mlxsw_reg_mtmp_unpack(char * payload,unsigned int * p_temp,unsigned int * p_max_temp,char * sensor_name)7577 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
7578 unsigned int *p_max_temp,
7579 char *sensor_name)
7580 {
7581 u16 temp;
7582
7583 if (p_temp) {
7584 temp = mlxsw_reg_mtmp_temperature_get(payload);
7585 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
7586 }
7587 if (p_max_temp) {
7588 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
7589 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
7590 }
7591 if (sensor_name)
7592 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
7593 }
7594
7595 /* MCIA - Management Cable Info Access
7596 * -----------------------------------
7597 * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
7598 */
7599
7600 #define MLXSW_REG_MCIA_ID 0x9014
7601 #define MLXSW_REG_MCIA_LEN 0x40
7602
7603 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
7604
7605 /* reg_mcia_l
7606 * Lock bit. Setting this bit will lock the access to the specific
7607 * cable. Used for updating a full page in a cable EPROM. Any access
7608 * other then subsequence writes will fail while the port is locked.
7609 * Access: RW
7610 */
7611 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
7612
7613 /* reg_mcia_module
7614 * Module number.
7615 * Access: Index
7616 */
7617 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
7618
7619 /* reg_mcia_status
7620 * Module status.
7621 * Access: RO
7622 */
7623 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
7624
7625 /* reg_mcia_i2c_device_address
7626 * I2C device address.
7627 * Access: RW
7628 */
7629 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
7630
7631 /* reg_mcia_page_number
7632 * Page number.
7633 * Access: RW
7634 */
7635 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
7636
7637 /* reg_mcia_device_address
7638 * Device address.
7639 * Access: RW
7640 */
7641 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
7642
7643 /* reg_mcia_size
7644 * Number of bytes to read/write (up to 48 bytes).
7645 * Access: RW
7646 */
7647 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
7648
7649 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48
7650
7651 /* reg_mcia_eeprom
7652 * Bytes to read/write.
7653 * Access: RW
7654 */
7655 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
7656
mlxsw_reg_mcia_pack(char * payload,u8 module,u8 lock,u8 page_number,u16 device_addr,u8 size,u8 i2c_device_addr)7657 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
7658 u8 page_number, u16 device_addr,
7659 u8 size, u8 i2c_device_addr)
7660 {
7661 MLXSW_REG_ZERO(mcia, payload);
7662 mlxsw_reg_mcia_module_set(payload, module);
7663 mlxsw_reg_mcia_l_set(payload, lock);
7664 mlxsw_reg_mcia_page_number_set(payload, page_number);
7665 mlxsw_reg_mcia_device_address_set(payload, device_addr);
7666 mlxsw_reg_mcia_size_set(payload, size);
7667 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
7668 }
7669
7670 /* MPAT - Monitoring Port Analyzer Table
7671 * -------------------------------------
7672 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
7673 * For an enabled analyzer, all fields except e (enable) cannot be modified.
7674 */
7675 #define MLXSW_REG_MPAT_ID 0x901A
7676 #define MLXSW_REG_MPAT_LEN 0x78
7677
7678 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
7679
7680 /* reg_mpat_pa_id
7681 * Port Analyzer ID.
7682 * Access: Index
7683 */
7684 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
7685
7686 /* reg_mpat_system_port
7687 * A unique port identifier for the final destination of the packet.
7688 * Access: RW
7689 */
7690 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
7691
7692 /* reg_mpat_e
7693 * Enable. Indicating the Port Analyzer is enabled.
7694 * Access: RW
7695 */
7696 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
7697
7698 /* reg_mpat_qos
7699 * Quality Of Service Mode.
7700 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
7701 * PCP, DEI, DSCP or VL) are configured.
7702 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
7703 * same as in the original packet that has triggered the mirroring. For
7704 * SPAN also the pcp,dei are maintained.
7705 * Access: RW
7706 */
7707 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
7708
7709 /* reg_mpat_be
7710 * Best effort mode. Indicates mirroring traffic should not cause packet
7711 * drop or back pressure, but will discard the mirrored packets. Mirrored
7712 * packets will be forwarded on a best effort manner.
7713 * 0: Do not discard mirrored packets
7714 * 1: Discard mirrored packets if causing congestion
7715 * Access: RW
7716 */
7717 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
7718
7719 enum mlxsw_reg_mpat_span_type {
7720 /* Local SPAN Ethernet.
7721 * The original packet is not encapsulated.
7722 */
7723 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
7724
7725 /* Remote SPAN Ethernet VLAN.
7726 * The packet is forwarded to the monitoring port on the monitoring
7727 * VLAN.
7728 */
7729 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
7730
7731 /* Encapsulated Remote SPAN Ethernet L3 GRE.
7732 * The packet is encapsulated with GRE header.
7733 */
7734 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
7735 };
7736
7737 /* reg_mpat_span_type
7738 * SPAN type.
7739 * Access: RW
7740 */
7741 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
7742
7743 /* Remote SPAN - Ethernet VLAN
7744 * - - - - - - - - - - - - - -
7745 */
7746
7747 /* reg_mpat_eth_rspan_vid
7748 * Encapsulation header VLAN ID.
7749 * Access: RW
7750 */
7751 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
7752
7753 /* Encapsulated Remote SPAN - Ethernet L2
7754 * - - - - - - - - - - - - - - - - - - -
7755 */
7756
7757 enum mlxsw_reg_mpat_eth_rspan_version {
7758 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
7759 };
7760
7761 /* reg_mpat_eth_rspan_version
7762 * RSPAN mirror header version.
7763 * Access: RW
7764 */
7765 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
7766
7767 /* reg_mpat_eth_rspan_mac
7768 * Destination MAC address.
7769 * Access: RW
7770 */
7771 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
7772
7773 /* reg_mpat_eth_rspan_tp
7774 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
7775 * Access: RW
7776 */
7777 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
7778
7779 /* Encapsulated Remote SPAN - Ethernet L3
7780 * - - - - - - - - - - - - - - - - - - -
7781 */
7782
7783 enum mlxsw_reg_mpat_eth_rspan_protocol {
7784 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
7785 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
7786 };
7787
7788 /* reg_mpat_eth_rspan_protocol
7789 * SPAN encapsulation protocol.
7790 * Access: RW
7791 */
7792 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
7793
7794 /* reg_mpat_eth_rspan_ttl
7795 * Encapsulation header Time-to-Live/HopLimit.
7796 * Access: RW
7797 */
7798 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
7799
7800 /* reg_mpat_eth_rspan_smac
7801 * Source MAC address
7802 * Access: RW
7803 */
7804 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
7805
7806 /* reg_mpat_eth_rspan_dip*
7807 * Destination IP address. The IP version is configured by protocol.
7808 * Access: RW
7809 */
7810 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
7811 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
7812
7813 /* reg_mpat_eth_rspan_sip*
7814 * Source IP address. The IP version is configured by protocol.
7815 * Access: RW
7816 */
7817 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
7818 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
7819
mlxsw_reg_mpat_pack(char * payload,u8 pa_id,u16 system_port,bool e,enum mlxsw_reg_mpat_span_type span_type)7820 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
7821 u16 system_port, bool e,
7822 enum mlxsw_reg_mpat_span_type span_type)
7823 {
7824 MLXSW_REG_ZERO(mpat, payload);
7825 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
7826 mlxsw_reg_mpat_system_port_set(payload, system_port);
7827 mlxsw_reg_mpat_e_set(payload, e);
7828 mlxsw_reg_mpat_qos_set(payload, 1);
7829 mlxsw_reg_mpat_be_set(payload, 1);
7830 mlxsw_reg_mpat_span_type_set(payload, span_type);
7831 }
7832
mlxsw_reg_mpat_eth_rspan_pack(char * payload,u16 vid)7833 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
7834 {
7835 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
7836 }
7837
7838 static inline void
mlxsw_reg_mpat_eth_rspan_l2_pack(char * payload,enum mlxsw_reg_mpat_eth_rspan_version version,const char * mac,bool tp)7839 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
7840 enum mlxsw_reg_mpat_eth_rspan_version version,
7841 const char *mac,
7842 bool tp)
7843 {
7844 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
7845 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
7846 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
7847 }
7848
7849 static inline void
mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char * payload,u8 ttl,const char * smac,u32 sip,u32 dip)7850 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
7851 const char *smac,
7852 u32 sip, u32 dip)
7853 {
7854 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
7855 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
7856 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
7857 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
7858 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
7859 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
7860 }
7861
7862 static inline void
mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char * payload,u8 ttl,const char * smac,struct in6_addr sip,struct in6_addr dip)7863 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
7864 const char *smac,
7865 struct in6_addr sip, struct in6_addr dip)
7866 {
7867 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
7868 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
7869 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
7870 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
7871 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
7872 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
7873 }
7874
7875 /* MPAR - Monitoring Port Analyzer Register
7876 * ----------------------------------------
7877 * MPAR register is used to query and configure the port analyzer port mirroring
7878 * properties.
7879 */
7880 #define MLXSW_REG_MPAR_ID 0x901B
7881 #define MLXSW_REG_MPAR_LEN 0x08
7882
7883 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
7884
7885 /* reg_mpar_local_port
7886 * The local port to mirror the packets from.
7887 * Access: Index
7888 */
7889 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
7890
7891 enum mlxsw_reg_mpar_i_e {
7892 MLXSW_REG_MPAR_TYPE_EGRESS,
7893 MLXSW_REG_MPAR_TYPE_INGRESS,
7894 };
7895
7896 /* reg_mpar_i_e
7897 * Ingress/Egress
7898 * Access: Index
7899 */
7900 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
7901
7902 /* reg_mpar_enable
7903 * Enable mirroring
7904 * By default, port mirroring is disabled for all ports.
7905 * Access: RW
7906 */
7907 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
7908
7909 /* reg_mpar_pa_id
7910 * Port Analyzer ID.
7911 * Access: RW
7912 */
7913 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
7914
mlxsw_reg_mpar_pack(char * payload,u8 local_port,enum mlxsw_reg_mpar_i_e i_e,bool enable,u8 pa_id)7915 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
7916 enum mlxsw_reg_mpar_i_e i_e,
7917 bool enable, u8 pa_id)
7918 {
7919 MLXSW_REG_ZERO(mpar, payload);
7920 mlxsw_reg_mpar_local_port_set(payload, local_port);
7921 mlxsw_reg_mpar_enable_set(payload, enable);
7922 mlxsw_reg_mpar_i_e_set(payload, i_e);
7923 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
7924 }
7925
7926 /* MRSR - Management Reset and Shutdown Register
7927 * ---------------------------------------------
7928 * MRSR register is used to reset or shutdown the switch or
7929 * the entire system (when applicable).
7930 */
7931 #define MLXSW_REG_MRSR_ID 0x9023
7932 #define MLXSW_REG_MRSR_LEN 0x08
7933
7934 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
7935
7936 /* reg_mrsr_command
7937 * Reset/shutdown command
7938 * 0 - do nothing
7939 * 1 - software reset
7940 * Access: WO
7941 */
7942 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
7943
mlxsw_reg_mrsr_pack(char * payload)7944 static inline void mlxsw_reg_mrsr_pack(char *payload)
7945 {
7946 MLXSW_REG_ZERO(mrsr, payload);
7947 mlxsw_reg_mrsr_command_set(payload, 1);
7948 }
7949
7950 /* MLCR - Management LED Control Register
7951 * --------------------------------------
7952 * Controls the system LEDs.
7953 */
7954 #define MLXSW_REG_MLCR_ID 0x902B
7955 #define MLXSW_REG_MLCR_LEN 0x0C
7956
7957 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
7958
7959 /* reg_mlcr_local_port
7960 * Local port number.
7961 * Access: RW
7962 */
7963 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
7964
7965 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
7966
7967 /* reg_mlcr_beacon_duration
7968 * Duration of the beacon to be active, in seconds.
7969 * 0x0 - Will turn off the beacon.
7970 * 0xFFFF - Will turn on the beacon until explicitly turned off.
7971 * Access: RW
7972 */
7973 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
7974
7975 /* reg_mlcr_beacon_remain
7976 * Remaining duration of the beacon, in seconds.
7977 * 0xFFFF indicates an infinite amount of time.
7978 * Access: RO
7979 */
7980 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
7981
mlxsw_reg_mlcr_pack(char * payload,u8 local_port,bool active)7982 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
7983 bool active)
7984 {
7985 MLXSW_REG_ZERO(mlcr, payload);
7986 mlxsw_reg_mlcr_local_port_set(payload, local_port);
7987 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
7988 MLXSW_REG_MLCR_DURATION_MAX : 0);
7989 }
7990
7991 /* MCQI - Management Component Query Information
7992 * ---------------------------------------------
7993 * This register allows querying information about firmware components.
7994 */
7995 #define MLXSW_REG_MCQI_ID 0x9061
7996 #define MLXSW_REG_MCQI_BASE_LEN 0x18
7997 #define MLXSW_REG_MCQI_CAP_LEN 0x14
7998 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
7999
8000 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8001
8002 /* reg_mcqi_component_index
8003 * Index of the accessed component.
8004 * Access: Index
8005 */
8006 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8007
8008 enum mlxfw_reg_mcqi_info_type {
8009 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8010 };
8011
8012 /* reg_mcqi_info_type
8013 * Component properties set.
8014 * Access: RW
8015 */
8016 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8017
8018 /* reg_mcqi_offset
8019 * The requested/returned data offset from the section start, given in bytes.
8020 * Must be DWORD aligned.
8021 * Access: RW
8022 */
8023 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8024
8025 /* reg_mcqi_data_size
8026 * The requested/returned data size, given in bytes. If data_size is not DWORD
8027 * aligned, the last bytes are zero padded.
8028 * Access: RW
8029 */
8030 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8031
8032 /* reg_mcqi_cap_max_component_size
8033 * Maximum size for this component, given in bytes.
8034 * Access: RO
8035 */
8036 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8037
8038 /* reg_mcqi_cap_log_mcda_word_size
8039 * Log 2 of the access word size in bytes. Read and write access must be aligned
8040 * to the word size. Write access must be done for an integer number of words.
8041 * Access: RO
8042 */
8043 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8044
8045 /* reg_mcqi_cap_mcda_max_write_size
8046 * Maximal write size for MCDA register
8047 * Access: RO
8048 */
8049 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8050
mlxsw_reg_mcqi_pack(char * payload,u16 component_index)8051 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
8052 {
8053 MLXSW_REG_ZERO(mcqi, payload);
8054 mlxsw_reg_mcqi_component_index_set(payload, component_index);
8055 mlxsw_reg_mcqi_info_type_set(payload,
8056 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
8057 mlxsw_reg_mcqi_offset_set(payload, 0);
8058 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
8059 }
8060
mlxsw_reg_mcqi_unpack(char * payload,u32 * p_cap_max_component_size,u8 * p_cap_log_mcda_word_size,u16 * p_cap_mcda_max_write_size)8061 static inline void mlxsw_reg_mcqi_unpack(char *payload,
8062 u32 *p_cap_max_component_size,
8063 u8 *p_cap_log_mcda_word_size,
8064 u16 *p_cap_mcda_max_write_size)
8065 {
8066 *p_cap_max_component_size =
8067 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
8068 *p_cap_log_mcda_word_size =
8069 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
8070 *p_cap_mcda_max_write_size =
8071 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
8072 }
8073
8074 /* MCC - Management Component Control
8075 * ----------------------------------
8076 * Controls the firmware component and updates the FSM.
8077 */
8078 #define MLXSW_REG_MCC_ID 0x9062
8079 #define MLXSW_REG_MCC_LEN 0x1C
8080
8081 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
8082
8083 enum mlxsw_reg_mcc_instruction {
8084 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
8085 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
8086 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
8087 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
8088 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
8089 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
8090 };
8091
8092 /* reg_mcc_instruction
8093 * Command to be executed by the FSM.
8094 * Applicable for write operation only.
8095 * Access: RW
8096 */
8097 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
8098
8099 /* reg_mcc_component_index
8100 * Index of the accessed component. Applicable only for commands that
8101 * refer to components. Otherwise, this field is reserved.
8102 * Access: Index
8103 */
8104 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
8105
8106 /* reg_mcc_update_handle
8107 * Token representing the current flow executed by the FSM.
8108 * Access: WO
8109 */
8110 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
8111
8112 /* reg_mcc_error_code
8113 * Indicates the successful completion of the instruction, or the reason it
8114 * failed
8115 * Access: RO
8116 */
8117 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
8118
8119 /* reg_mcc_control_state
8120 * Current FSM state
8121 * Access: RO
8122 */
8123 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
8124
8125 /* reg_mcc_component_size
8126 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
8127 * the size may shorten the update time. Value 0x0 means that size is
8128 * unspecified.
8129 * Access: WO
8130 */
8131 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
8132
mlxsw_reg_mcc_pack(char * payload,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)8133 static inline void mlxsw_reg_mcc_pack(char *payload,
8134 enum mlxsw_reg_mcc_instruction instr,
8135 u16 component_index, u32 update_handle,
8136 u32 component_size)
8137 {
8138 MLXSW_REG_ZERO(mcc, payload);
8139 mlxsw_reg_mcc_instruction_set(payload, instr);
8140 mlxsw_reg_mcc_component_index_set(payload, component_index);
8141 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
8142 mlxsw_reg_mcc_component_size_set(payload, component_size);
8143 }
8144
mlxsw_reg_mcc_unpack(char * payload,u32 * p_update_handle,u8 * p_error_code,u8 * p_control_state)8145 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
8146 u8 *p_error_code, u8 *p_control_state)
8147 {
8148 if (p_update_handle)
8149 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
8150 if (p_error_code)
8151 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
8152 if (p_control_state)
8153 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
8154 }
8155
8156 /* MCDA - Management Component Data Access
8157 * ---------------------------------------
8158 * This register allows reading and writing a firmware component.
8159 */
8160 #define MLXSW_REG_MCDA_ID 0x9063
8161 #define MLXSW_REG_MCDA_BASE_LEN 0x10
8162 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
8163 #define MLXSW_REG_MCDA_LEN \
8164 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
8165
8166 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
8167
8168 /* reg_mcda_update_handle
8169 * Token representing the current flow executed by the FSM.
8170 * Access: RW
8171 */
8172 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
8173
8174 /* reg_mcda_offset
8175 * Offset of accessed address relative to component start. Accesses must be in
8176 * accordance to log_mcda_word_size in MCQI reg.
8177 * Access: RW
8178 */
8179 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
8180
8181 /* reg_mcda_size
8182 * Size of the data accessed, given in bytes.
8183 * Access: RW
8184 */
8185 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
8186
8187 /* reg_mcda_data
8188 * Data block accessed.
8189 * Access: RW
8190 */
8191 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
8192
mlxsw_reg_mcda_pack(char * payload,u32 update_handle,u32 offset,u16 size,u8 * data)8193 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
8194 u32 offset, u16 size, u8 *data)
8195 {
8196 int i;
8197
8198 MLXSW_REG_ZERO(mcda, payload);
8199 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
8200 mlxsw_reg_mcda_offset_set(payload, offset);
8201 mlxsw_reg_mcda_size_set(payload, size);
8202
8203 for (i = 0; i < size / 4; i++)
8204 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
8205 }
8206
8207 /* MPSC - Monitoring Packet Sampling Configuration Register
8208 * --------------------------------------------------------
8209 * MPSC Register is used to configure the Packet Sampling mechanism.
8210 */
8211 #define MLXSW_REG_MPSC_ID 0x9080
8212 #define MLXSW_REG_MPSC_LEN 0x1C
8213
8214 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
8215
8216 /* reg_mpsc_local_port
8217 * Local port number
8218 * Not supported for CPU port
8219 * Access: Index
8220 */
8221 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
8222
8223 /* reg_mpsc_e
8224 * Enable sampling on port local_port
8225 * Access: RW
8226 */
8227 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
8228
8229 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
8230
8231 /* reg_mpsc_rate
8232 * Sampling rate = 1 out of rate packets (with randomization around
8233 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
8234 * Access: RW
8235 */
8236 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
8237
mlxsw_reg_mpsc_pack(char * payload,u8 local_port,bool e,u32 rate)8238 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
8239 u32 rate)
8240 {
8241 MLXSW_REG_ZERO(mpsc, payload);
8242 mlxsw_reg_mpsc_local_port_set(payload, local_port);
8243 mlxsw_reg_mpsc_e_set(payload, e);
8244 mlxsw_reg_mpsc_rate_set(payload, rate);
8245 }
8246
8247 /* MGPC - Monitoring General Purpose Counter Set Register
8248 * The MGPC register retrieves and sets the General Purpose Counter Set.
8249 */
8250 #define MLXSW_REG_MGPC_ID 0x9081
8251 #define MLXSW_REG_MGPC_LEN 0x18
8252
8253 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
8254
8255 /* reg_mgpc_counter_set_type
8256 * Counter set type.
8257 * Access: OP
8258 */
8259 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
8260
8261 /* reg_mgpc_counter_index
8262 * Counter index.
8263 * Access: Index
8264 */
8265 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
8266
8267 enum mlxsw_reg_mgpc_opcode {
8268 /* Nop */
8269 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
8270 /* Clear counters */
8271 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
8272 };
8273
8274 /* reg_mgpc_opcode
8275 * Opcode.
8276 * Access: OP
8277 */
8278 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
8279
8280 /* reg_mgpc_byte_counter
8281 * Byte counter value.
8282 * Access: RW
8283 */
8284 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
8285
8286 /* reg_mgpc_packet_counter
8287 * Packet counter value.
8288 * Access: RW
8289 */
8290 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
8291
mlxsw_reg_mgpc_pack(char * payload,u32 counter_index,enum mlxsw_reg_mgpc_opcode opcode,enum mlxsw_reg_flow_counter_set_type set_type)8292 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
8293 enum mlxsw_reg_mgpc_opcode opcode,
8294 enum mlxsw_reg_flow_counter_set_type set_type)
8295 {
8296 MLXSW_REG_ZERO(mgpc, payload);
8297 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
8298 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
8299 mlxsw_reg_mgpc_opcode_set(payload, opcode);
8300 }
8301
8302 /* TIGCR - Tunneling IPinIP General Configuration Register
8303 * -------------------------------------------------------
8304 * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
8305 */
8306 #define MLXSW_REG_TIGCR_ID 0xA801
8307 #define MLXSW_REG_TIGCR_LEN 0x10
8308
8309 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
8310
8311 /* reg_tigcr_ipip_ttlc
8312 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
8313 * header.
8314 * Access: RW
8315 */
8316 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
8317
8318 /* reg_tigcr_ipip_ttl_uc
8319 * The TTL for IPinIP Tunnel encapsulation of unicast packets if
8320 * reg_tigcr_ipip_ttlc is unset.
8321 * Access: RW
8322 */
8323 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
8324
mlxsw_reg_tigcr_pack(char * payload,bool ttlc,u8 ttl_uc)8325 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
8326 {
8327 MLXSW_REG_ZERO(tigcr, payload);
8328 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
8329 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
8330 }
8331
8332 /* SBPR - Shared Buffer Pools Register
8333 * -----------------------------------
8334 * The SBPR configures and retrieves the shared buffer pools and configuration.
8335 */
8336 #define MLXSW_REG_SBPR_ID 0xB001
8337 #define MLXSW_REG_SBPR_LEN 0x14
8338
8339 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
8340
8341 /* shared direstion enum for SBPR, SBCM, SBPM */
8342 enum mlxsw_reg_sbxx_dir {
8343 MLXSW_REG_SBXX_DIR_INGRESS,
8344 MLXSW_REG_SBXX_DIR_EGRESS,
8345 };
8346
8347 /* reg_sbpr_dir
8348 * Direction.
8349 * Access: Index
8350 */
8351 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
8352
8353 /* reg_sbpr_pool
8354 * Pool index.
8355 * Access: Index
8356 */
8357 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
8358
8359 /* reg_sbpr_size
8360 * Pool size in buffer cells.
8361 * Access: RW
8362 */
8363 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
8364
8365 enum mlxsw_reg_sbpr_mode {
8366 MLXSW_REG_SBPR_MODE_STATIC,
8367 MLXSW_REG_SBPR_MODE_DYNAMIC,
8368 };
8369
8370 /* reg_sbpr_mode
8371 * Pool quota calculation mode.
8372 * Access: RW
8373 */
8374 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
8375
mlxsw_reg_sbpr_pack(char * payload,u8 pool,enum mlxsw_reg_sbxx_dir dir,enum mlxsw_reg_sbpr_mode mode,u32 size)8376 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
8377 enum mlxsw_reg_sbxx_dir dir,
8378 enum mlxsw_reg_sbpr_mode mode, u32 size)
8379 {
8380 MLXSW_REG_ZERO(sbpr, payload);
8381 mlxsw_reg_sbpr_pool_set(payload, pool);
8382 mlxsw_reg_sbpr_dir_set(payload, dir);
8383 mlxsw_reg_sbpr_mode_set(payload, mode);
8384 mlxsw_reg_sbpr_size_set(payload, size);
8385 }
8386
8387 /* SBCM - Shared Buffer Class Management Register
8388 * ----------------------------------------------
8389 * The SBCM register configures and retrieves the shared buffer allocation
8390 * and configuration according to Port-PG, including the binding to pool
8391 * and definition of the associated quota.
8392 */
8393 #define MLXSW_REG_SBCM_ID 0xB002
8394 #define MLXSW_REG_SBCM_LEN 0x28
8395
8396 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
8397
8398 /* reg_sbcm_local_port
8399 * Local port number.
8400 * For Ingress: excludes CPU port and Router port
8401 * For Egress: excludes IP Router
8402 * Access: Index
8403 */
8404 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
8405
8406 /* reg_sbcm_pg_buff
8407 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
8408 * For PG buffer: range is 0..cap_max_pg_buffers - 1
8409 * For traffic class: range is 0..cap_max_tclass - 1
8410 * Note that when traffic class is in MC aware mode then the traffic
8411 * classes which are MC aware cannot be configured.
8412 * Access: Index
8413 */
8414 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
8415
8416 /* reg_sbcm_dir
8417 * Direction.
8418 * Access: Index
8419 */
8420 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
8421
8422 /* reg_sbcm_min_buff
8423 * Minimum buffer size for the limiter, in cells.
8424 * Access: RW
8425 */
8426 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
8427
8428 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
8429 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
8430 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
8431
8432 /* reg_sbcm_max_buff
8433 * When the pool associated to the port-pg/tclass is configured to
8434 * static, Maximum buffer size for the limiter configured in cells.
8435 * When the pool associated to the port-pg/tclass is configured to
8436 * dynamic, the max_buff holds the "alpha" parameter, supporting
8437 * the following values:
8438 * 0: 0
8439 * i: (1/128)*2^(i-1), for i=1..14
8440 * 0xFF: Infinity
8441 * Access: RW
8442 */
8443 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
8444
8445 /* reg_sbcm_pool
8446 * Association of the port-priority to a pool.
8447 * Access: RW
8448 */
8449 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
8450
mlxsw_reg_sbcm_pack(char * payload,u8 local_port,u8 pg_buff,enum mlxsw_reg_sbxx_dir dir,u32 min_buff,u32 max_buff,u8 pool)8451 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
8452 enum mlxsw_reg_sbxx_dir dir,
8453 u32 min_buff, u32 max_buff, u8 pool)
8454 {
8455 MLXSW_REG_ZERO(sbcm, payload);
8456 mlxsw_reg_sbcm_local_port_set(payload, local_port);
8457 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
8458 mlxsw_reg_sbcm_dir_set(payload, dir);
8459 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
8460 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
8461 mlxsw_reg_sbcm_pool_set(payload, pool);
8462 }
8463
8464 /* SBPM - Shared Buffer Port Management Register
8465 * ---------------------------------------------
8466 * The SBPM register configures and retrieves the shared buffer allocation
8467 * and configuration according to Port-Pool, including the definition
8468 * of the associated quota.
8469 */
8470 #define MLXSW_REG_SBPM_ID 0xB003
8471 #define MLXSW_REG_SBPM_LEN 0x28
8472
8473 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
8474
8475 /* reg_sbpm_local_port
8476 * Local port number.
8477 * For Ingress: excludes CPU port and Router port
8478 * For Egress: excludes IP Router
8479 * Access: Index
8480 */
8481 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
8482
8483 /* reg_sbpm_pool
8484 * The pool associated to quota counting on the local_port.
8485 * Access: Index
8486 */
8487 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
8488
8489 /* reg_sbpm_dir
8490 * Direction.
8491 * Access: Index
8492 */
8493 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
8494
8495 /* reg_sbpm_buff_occupancy
8496 * Current buffer occupancy in cells.
8497 * Access: RO
8498 */
8499 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
8500
8501 /* reg_sbpm_clr
8502 * Clear Max Buffer Occupancy
8503 * When this bit is set, max_buff_occupancy field is cleared (and a
8504 * new max value is tracked from the time the clear was performed).
8505 * Access: OP
8506 */
8507 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
8508
8509 /* reg_sbpm_max_buff_occupancy
8510 * Maximum value of buffer occupancy in cells monitored. Cleared by
8511 * writing to the clr field.
8512 * Access: RO
8513 */
8514 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
8515
8516 /* reg_sbpm_min_buff
8517 * Minimum buffer size for the limiter, in cells.
8518 * Access: RW
8519 */
8520 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
8521
8522 /* reg_sbpm_max_buff
8523 * When the pool associated to the port-pg/tclass is configured to
8524 * static, Maximum buffer size for the limiter configured in cells.
8525 * When the pool associated to the port-pg/tclass is configured to
8526 * dynamic, the max_buff holds the "alpha" parameter, supporting
8527 * the following values:
8528 * 0: 0
8529 * i: (1/128)*2^(i-1), for i=1..14
8530 * 0xFF: Infinity
8531 * Access: RW
8532 */
8533 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
8534
mlxsw_reg_sbpm_pack(char * payload,u8 local_port,u8 pool,enum mlxsw_reg_sbxx_dir dir,bool clr,u32 min_buff,u32 max_buff)8535 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
8536 enum mlxsw_reg_sbxx_dir dir, bool clr,
8537 u32 min_buff, u32 max_buff)
8538 {
8539 MLXSW_REG_ZERO(sbpm, payload);
8540 mlxsw_reg_sbpm_local_port_set(payload, local_port);
8541 mlxsw_reg_sbpm_pool_set(payload, pool);
8542 mlxsw_reg_sbpm_dir_set(payload, dir);
8543 mlxsw_reg_sbpm_clr_set(payload, clr);
8544 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
8545 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
8546 }
8547
mlxsw_reg_sbpm_unpack(char * payload,u32 * p_buff_occupancy,u32 * p_max_buff_occupancy)8548 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
8549 u32 *p_max_buff_occupancy)
8550 {
8551 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
8552 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
8553 }
8554
8555 /* SBMM - Shared Buffer Multicast Management Register
8556 * --------------------------------------------------
8557 * The SBMM register configures and retrieves the shared buffer allocation
8558 * and configuration for MC packets according to Switch-Priority, including
8559 * the binding to pool and definition of the associated quota.
8560 */
8561 #define MLXSW_REG_SBMM_ID 0xB004
8562 #define MLXSW_REG_SBMM_LEN 0x28
8563
8564 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
8565
8566 /* reg_sbmm_prio
8567 * Switch Priority.
8568 * Access: Index
8569 */
8570 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
8571
8572 /* reg_sbmm_min_buff
8573 * Minimum buffer size for the limiter, in cells.
8574 * Access: RW
8575 */
8576 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
8577
8578 /* reg_sbmm_max_buff
8579 * When the pool associated to the port-pg/tclass is configured to
8580 * static, Maximum buffer size for the limiter configured in cells.
8581 * When the pool associated to the port-pg/tclass is configured to
8582 * dynamic, the max_buff holds the "alpha" parameter, supporting
8583 * the following values:
8584 * 0: 0
8585 * i: (1/128)*2^(i-1), for i=1..14
8586 * 0xFF: Infinity
8587 * Access: RW
8588 */
8589 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
8590
8591 /* reg_sbmm_pool
8592 * Association of the port-priority to a pool.
8593 * Access: RW
8594 */
8595 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
8596
mlxsw_reg_sbmm_pack(char * payload,u8 prio,u32 min_buff,u32 max_buff,u8 pool)8597 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
8598 u32 max_buff, u8 pool)
8599 {
8600 MLXSW_REG_ZERO(sbmm, payload);
8601 mlxsw_reg_sbmm_prio_set(payload, prio);
8602 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
8603 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
8604 mlxsw_reg_sbmm_pool_set(payload, pool);
8605 }
8606
8607 /* SBSR - Shared Buffer Status Register
8608 * ------------------------------------
8609 * The SBSR register retrieves the shared buffer occupancy according to
8610 * Port-Pool. Note that this register enables reading a large amount of data.
8611 * It is the user's responsibility to limit the amount of data to ensure the
8612 * response can match the maximum transfer unit. In case the response exceeds
8613 * the maximum transport unit, it will be truncated with no special notice.
8614 */
8615 #define MLXSW_REG_SBSR_ID 0xB005
8616 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
8617 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
8618 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
8619 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
8620 MLXSW_REG_SBSR_REC_LEN * \
8621 MLXSW_REG_SBSR_REC_MAX_COUNT)
8622
8623 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
8624
8625 /* reg_sbsr_clr
8626 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
8627 * field is cleared (and a new max value is tracked from the time the clear
8628 * was performed).
8629 * Access: OP
8630 */
8631 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
8632
8633 /* reg_sbsr_ingress_port_mask
8634 * Bit vector for all ingress network ports.
8635 * Indicates which of the ports (for which the relevant bit is set)
8636 * are affected by the set operation. Configuration of any other port
8637 * does not change.
8638 * Access: Index
8639 */
8640 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
8641
8642 /* reg_sbsr_pg_buff_mask
8643 * Bit vector for all switch priority groups.
8644 * Indicates which of the priorities (for which the relevant bit is set)
8645 * are affected by the set operation. Configuration of any other priority
8646 * does not change.
8647 * Range is 0..cap_max_pg_buffers - 1
8648 * Access: Index
8649 */
8650 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
8651
8652 /* reg_sbsr_egress_port_mask
8653 * Bit vector for all egress network ports.
8654 * Indicates which of the ports (for which the relevant bit is set)
8655 * are affected by the set operation. Configuration of any other port
8656 * does not change.
8657 * Access: Index
8658 */
8659 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
8660
8661 /* reg_sbsr_tclass_mask
8662 * Bit vector for all traffic classes.
8663 * Indicates which of the traffic classes (for which the relevant bit is
8664 * set) are affected by the set operation. Configuration of any other
8665 * traffic class does not change.
8666 * Range is 0..cap_max_tclass - 1
8667 * Access: Index
8668 */
8669 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
8670
mlxsw_reg_sbsr_pack(char * payload,bool clr)8671 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
8672 {
8673 MLXSW_REG_ZERO(sbsr, payload);
8674 mlxsw_reg_sbsr_clr_set(payload, clr);
8675 }
8676
8677 /* reg_sbsr_rec_buff_occupancy
8678 * Current buffer occupancy in cells.
8679 * Access: RO
8680 */
8681 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
8682 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
8683
8684 /* reg_sbsr_rec_max_buff_occupancy
8685 * Maximum value of buffer occupancy in cells monitored. Cleared by
8686 * writing to the clr field.
8687 * Access: RO
8688 */
8689 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
8690 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
8691
mlxsw_reg_sbsr_rec_unpack(char * payload,int rec_index,u32 * p_buff_occupancy,u32 * p_max_buff_occupancy)8692 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
8693 u32 *p_buff_occupancy,
8694 u32 *p_max_buff_occupancy)
8695 {
8696 *p_buff_occupancy =
8697 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
8698 *p_max_buff_occupancy =
8699 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
8700 }
8701
8702 /* SBIB - Shared Buffer Internal Buffer Register
8703 * ---------------------------------------------
8704 * The SBIB register configures per port buffers for internal use. The internal
8705 * buffers consume memory on the port buffers (note that the port buffers are
8706 * used also by PBMC).
8707 *
8708 * For Spectrum this is used for egress mirroring.
8709 */
8710 #define MLXSW_REG_SBIB_ID 0xB006
8711 #define MLXSW_REG_SBIB_LEN 0x10
8712
8713 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
8714
8715 /* reg_sbib_local_port
8716 * Local port number
8717 * Not supported for CPU port and router port
8718 * Access: Index
8719 */
8720 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
8721
8722 /* reg_sbib_buff_size
8723 * Units represented in cells
8724 * Allowed range is 0 to (cap_max_headroom_size - 1)
8725 * Default is 0
8726 * Access: RW
8727 */
8728 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
8729
mlxsw_reg_sbib_pack(char * payload,u8 local_port,u32 buff_size)8730 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
8731 u32 buff_size)
8732 {
8733 MLXSW_REG_ZERO(sbib, payload);
8734 mlxsw_reg_sbib_local_port_set(payload, local_port);
8735 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
8736 }
8737
8738 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
8739 MLXSW_REG(sgcr),
8740 MLXSW_REG(spad),
8741 MLXSW_REG(smid),
8742 MLXSW_REG(sspr),
8743 MLXSW_REG(sfdat),
8744 MLXSW_REG(sfd),
8745 MLXSW_REG(sfn),
8746 MLXSW_REG(spms),
8747 MLXSW_REG(spvid),
8748 MLXSW_REG(spvm),
8749 MLXSW_REG(spaft),
8750 MLXSW_REG(sfgc),
8751 MLXSW_REG(sftr),
8752 MLXSW_REG(sfdf),
8753 MLXSW_REG(sldr),
8754 MLXSW_REG(slcr),
8755 MLXSW_REG(slcor),
8756 MLXSW_REG(spmlr),
8757 MLXSW_REG(svfa),
8758 MLXSW_REG(svpe),
8759 MLXSW_REG(sfmr),
8760 MLXSW_REG(spvmlr),
8761 MLXSW_REG(cwtp),
8762 MLXSW_REG(cwtpm),
8763 MLXSW_REG(pgcr),
8764 MLXSW_REG(ppbt),
8765 MLXSW_REG(pacl),
8766 MLXSW_REG(pagt),
8767 MLXSW_REG(ptar),
8768 MLXSW_REG(ppbs),
8769 MLXSW_REG(prcr),
8770 MLXSW_REG(pefa),
8771 MLXSW_REG(ptce2),
8772 MLXSW_REG(perpt),
8773 MLXSW_REG(perar),
8774 MLXSW_REG(ptce3),
8775 MLXSW_REG(percr),
8776 MLXSW_REG(pererp),
8777 MLXSW_REG(iedr),
8778 MLXSW_REG(qpts),
8779 MLXSW_REG(qpcr),
8780 MLXSW_REG(qtct),
8781 MLXSW_REG(qeec),
8782 MLXSW_REG(qrwe),
8783 MLXSW_REG(qpdsm),
8784 MLXSW_REG(qpdpm),
8785 MLXSW_REG(qtctm),
8786 MLXSW_REG(pmlp),
8787 MLXSW_REG(pmtu),
8788 MLXSW_REG(ptys),
8789 MLXSW_REG(ppad),
8790 MLXSW_REG(paos),
8791 MLXSW_REG(pfcc),
8792 MLXSW_REG(ppcnt),
8793 MLXSW_REG(plib),
8794 MLXSW_REG(pptb),
8795 MLXSW_REG(pbmc),
8796 MLXSW_REG(pspa),
8797 MLXSW_REG(htgt),
8798 MLXSW_REG(hpkt),
8799 MLXSW_REG(rgcr),
8800 MLXSW_REG(ritr),
8801 MLXSW_REG(rtar),
8802 MLXSW_REG(ratr),
8803 MLXSW_REG(rtdp),
8804 MLXSW_REG(rdpm),
8805 MLXSW_REG(ricnt),
8806 MLXSW_REG(rrcr),
8807 MLXSW_REG(ralta),
8808 MLXSW_REG(ralst),
8809 MLXSW_REG(raltb),
8810 MLXSW_REG(ralue),
8811 MLXSW_REG(rauht),
8812 MLXSW_REG(raleu),
8813 MLXSW_REG(rauhtd),
8814 MLXSW_REG(rigr2),
8815 MLXSW_REG(recr2),
8816 MLXSW_REG(rmft2),
8817 MLXSW_REG(mfcr),
8818 MLXSW_REG(mfsc),
8819 MLXSW_REG(mfsm),
8820 MLXSW_REG(mfsl),
8821 MLXSW_REG(mtcap),
8822 MLXSW_REG(mtmp),
8823 MLXSW_REG(mcia),
8824 MLXSW_REG(mpat),
8825 MLXSW_REG(mpar),
8826 MLXSW_REG(mrsr),
8827 MLXSW_REG(mlcr),
8828 MLXSW_REG(mpsc),
8829 MLXSW_REG(mcqi),
8830 MLXSW_REG(mcc),
8831 MLXSW_REG(mcda),
8832 MLXSW_REG(mgpc),
8833 MLXSW_REG(tigcr),
8834 MLXSW_REG(sbpr),
8835 MLXSW_REG(sbcm),
8836 MLXSW_REG(sbpm),
8837 MLXSW_REG(sbmm),
8838 MLXSW_REG(sbsr),
8839 MLXSW_REG(sbib),
8840 };
8841
mlxsw_reg_id_str(u16 reg_id)8842 static inline const char *mlxsw_reg_id_str(u16 reg_id)
8843 {
8844 const struct mlxsw_reg_info *reg_info;
8845 int i;
8846
8847 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
8848 reg_info = mlxsw_reg_infos[i];
8849 if (reg_info->id == reg_id)
8850 return reg_info->name;
8851 }
8852 return "*UNKNOWN*";
8853 }
8854
8855 /* PUDE - Port Up / Down Event
8856 * ---------------------------
8857 * Reports the operational state change of a port.
8858 */
8859 #define MLXSW_REG_PUDE_LEN 0x10
8860
8861 /* reg_pude_swid
8862 * Switch partition ID with which to associate the port.
8863 * Access: Index
8864 */
8865 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
8866
8867 /* reg_pude_local_port
8868 * Local port number.
8869 * Access: Index
8870 */
8871 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
8872
8873 /* reg_pude_admin_status
8874 * Port administrative state (the desired state).
8875 * 1 - Up.
8876 * 2 - Down.
8877 * 3 - Up once. This means that in case of link failure, the port won't go
8878 * into polling mode, but will wait to be re-enabled by software.
8879 * 4 - Disabled by system. Can only be set by hardware.
8880 * Access: RO
8881 */
8882 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
8883
8884 /* reg_pude_oper_status
8885 * Port operatioanl state.
8886 * 1 - Up.
8887 * 2 - Down.
8888 * 3 - Down by port failure. This means that the device will not let the
8889 * port up again until explicitly specified by software.
8890 * Access: RO
8891 */
8892 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
8893
8894 #endif
8895