1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 * Description: ufs header 18 */ 19 20 #ifndef __UFS_HISI_H__ 21 #define __UFS_HISI_H__ 22 23 #define COMBO_PHY_V120 24 #define UFS_USE_HISI_MPHY_TC 25 #define CLOSE_CLK_GATING 26 27 #define REG_BASE_UFSHCI_ADDRESS 0x10010000 28 /* SYNOPSYS UniPro register */ 29 #define UNIPRO_DME_RESET 0xD010 30 #define UNIPRO_DME_LAYBER_ENABLE 0xD000 31 32 /* MPHY registers addr */ 33 #define AD_DIF_P_LS_TIMEOUT_VAL 0x0003 34 #define PWM_PREPARE_TO 0x00000080 35 #define SKP_DET_SEL 0x0009 36 #define SKP_DET_SEL_EN 0x00000001 37 38 #define MRX_EN 0x00F0 39 #define MRX_ENABLE (0x01 << 0) 40 #define RX_SQ_VREF 0x00F1 41 #define RX_SQ_VREF_175 0x00000002 42 #define VCO_AUTO_CHG 0x00DF 43 #define VCO_AUTO_CHG_EN (0x01 << 0) 44 #define VCO_FORCE_ON_EN (0x01 << 1) 45 46 #define RG_PLL_PRE_DIV 0x00C2 47 #define RG_PLL_FBK_P 0x00C3 48 #define RG_PLL_FBK_S 0x00C4 49 #define RG_PLL_SWC_EN 0x00C9 50 #define RG_PLL_RXHSGR 0x00CD 51 #define RG_PLL_RXLSGR 0x00CE 52 #define RG_PLL_TXHSGR 0x00CF 53 #define HS_R_A_FBK_P 0x41 54 #define HS_R_B_FBK_P 0x4C 55 #define RG_PLL_TXLSGR 0x00D0 56 57 #define RG_PLL_TXHS_EN 0x00C7 58 #define RG_PLL_TXHS_ENANBLE (0x01 << 0) 59 #define RG_PLL_TXHS_EN_CONTROL (0x01 << 1) 60 #define RG_PLL_TXLS_EN 0x00C8 61 #define RG_PLL_TXLS_ENABLE (0x01 << 0) 62 #define RG_PLL_TXLS_EN_CONTROL (0x01 << 1) 63 64 #define CGE BIT(12) 65 #define LP_AH8_PGE BIT(17) 66 dwc_ufs_write_reg(uint32_t reg_offset,uint32_t value)67static inline void dwc_ufs_write_reg(uint32_t reg_offset, uint32_t value) 68 { 69 writel(value, (uintptr_t)(REG_BASE_UFSHCI_ADDRESS + reg_offset)); 70 } 71 dwc_ufs_read_reg(uint32_t reg_offset)72static inline uint32_t dwc_ufs_read_reg(uint32_t reg_offset) 73 { 74 return readl((uintptr_t)(REG_BASE_UFSHCI_ADDRESS + reg_offset)); 75 } 76 77 #endif