1 /*
2 * Copyright (c) 2020-2021 Huawei Device Co., Ltd.
3 *
4 * HDF is dual licensed: you can use it either under the terms of
5 * the GPL, or the BSD license, at your option.
6 * See the LICENSE file in the root of this repository for complete details.
7 */
8
9 #include "mmc_emmc.h"
10 #include "mmc_sd.h"
11 #include "mmc_sdio.h"
12 #include "securec.h"
13
14 #define HDF_LOG_TAG mmc_protocol_c
15
16 #define INIT_CMD_RETRY_TIMES 100
17 #define MMC_CMD_DEFAULT_RETRY_TIMES 3
18 #define SEND_STATUS_CMD_RETRY_TIMES 100
19 #define STOP_TRANSMISSION_CMD_RETRY_TIMES 5
20 #define BITS_NUMBER_OF_4_BYTES 32
21
22 /* TRAN_SPEED: Frequency unit 0 = 100KHz, 1 = 1MHz, 2 = 10MHz, 3 = 100MHz, 4...7 = reserved */
23 uint32_t g_tranSpeedUnit[] = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 };
24
25 /* TAAC: Time unit 0 = 1ns, 1 = 10ns, 2 = 100ns, 3 = 1us, 4 = 10us, 5 = 100us, 6 = 1ms, 7 = 10ms */
26 uint32_t g_taccUnit[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 };
27
28 /*
29 * TRAN_SPEED/TAAC: Multiplier factor 0 = reserved, 1 = 1.0, 2 = 1.2, 3 = 1.3, 4 = 1.5, 5 = 2.0, 6 = 2.5,
30 * 7 = 3.0, 8 = 3.5, 9 = 4.0, A = 4.5, B = 5.0, C = 5.5, D = 6.0, E = 7.0, F = 8.0
31 */
32 uint32_t g_commFactor[] = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
33
34 /* Little-endian and Big-endian interconversion. */
MmcEndianConversion(uint32_t x)35 static uint32_t MmcEndianConversion(uint32_t x)
36 {
37 uint32_t val = x;
38
39 return (uint32_t)(
40 (((uint32_t)(val) & (uint32_t)0x000000ffUL) << 24) |
41 (((uint32_t)(val) & (uint32_t)0x0000ff00UL) << 8) |
42 (((uint32_t)(val) & (uint32_t)0x00ff0000UL) >> 8) |
43 (((uint32_t)(val) & (uint32_t)0xff000000UL) >> 24));
44 }
45
46 /* Decoding algorithm */
MmcParseBits(uint32_t * data,uint32_t bitsLen,uint32_t start,uint32_t size)47 static uint32_t MmcParseBits(uint32_t *data, uint32_t bitsLen, uint32_t start, uint32_t size)
48 {
49 uint32_t index;
50 uint32_t shift;
51 uint32_t ret;
52
53 if (start >= bitsLen || size == 0) {
54 HDF_LOGE("MmcParseBits: input invalid!");
55 return 0;
56 }
57 if (size > BITS_NUMBER_OF_4_BYTES) {
58 HDF_LOGE("MmcParseBits: not support!");
59 return 0;
60 }
61
62 index = (bitsLen / BITS_NUMBER_OF_4_BYTES) - (start / BITS_NUMBER_OF_4_BYTES) - 1;
63 shift = start & (BITS_NUMBER_OF_4_BYTES - 1);
64 ret = data[index] >> shift;
65 if (size + shift > BITS_NUMBER_OF_4_BYTES) {
66 ret |= data[index - 1] << (BITS_NUMBER_OF_4_BYTES - shift);
67 }
68
69 if (size < BITS_NUMBER_OF_4_BYTES) {
70 return (ret & ((1u << size) - 1));
71 }
72 return (ret & 0xFFFFFFFF);
73 }
74
MmcSendCmd(struct MmcCntlr * cntlr,struct MmcCmd * cmd,struct MmcData * data,uint32_t retryTimes)75 static int32_t MmcSendCmd(struct MmcCntlr *cntlr, struct MmcCmd *cmd, struct MmcData *data, uint32_t retryTimes)
76 {
77 uint32_t i;
78 int32_t ret;
79
80 if (cntlr == NULL || cmd == NULL || retryTimes == 0) {
81 return HDF_ERR_INVALID_PARAM;
82 }
83 if (cntlr->ops == NULL || cntlr->ops->request == NULL) {
84 return HDF_ERR_NOT_SUPPORT;
85 }
86
87 cmd->data = data;
88 for (i = 0; i < retryTimes; i++) {
89 ret = MmcCntlrDoRequest(cntlr, cmd);
90 if (ret != HDF_SUCCESS) {
91 continue;
92 }
93 if (cmd->returnError != HDF_SUCCESS) {
94 continue;
95 }
96 if (data != NULL && data->returnError != HDF_SUCCESS) {
97 continue;
98 }
99 break;
100 }
101 if (data == NULL) {
102 return cmd->returnError;
103 }
104 if (cmd->returnError != HDF_SUCCESS) {
105 return cmd->returnError;
106 }
107 if (data->returnError != HDF_SUCCESS) {
108 return data->returnError;
109 }
110 return HDF_SUCCESS;
111 }
112
MmcGoIdleState(struct MmcCntlr * cntlr)113 static void MmcGoIdleState(struct MmcCntlr *cntlr)
114 {
115 struct MmcCmd cmd = {0};
116
117 /* Command GO_IDLE_STATE (CMD0) is the software reset command and sets all cards into Idle State. */
118 cmd.cmdCode = GO_IDLE_STATE;
119 /* [31:0] stuff bits. */
120 cmd.argument = 0;
121 /* Broadcast Commands (bc), no response. */
122 cmd.respType = MMC_RESP_SPI_R1 | MMC_RESP_NONE | MMC_CMD_TYPE_BC;
123 (void)MmcSendCmd(cntlr, &cmd, NULL, 1);
124 OsalMDelay(1);
125 }
126
MmcSendOpCond(struct MmcCntlr * cntlr,uint32_t arg,uint32_t * ocr)127 static int32_t MmcSendOpCond(struct MmcCntlr *cntlr, uint32_t arg, uint32_t *ocr)
128 {
129 struct MmcCmd cmd = {0};
130 int32_t err;
131 uint32_t i;
132
133 /*
134 * The SEND_OP_COND (CMD1) command is designed to provide MultiMediaCard hosts with a mechanism
135 * to identify and reject cards which do not match the VDD range desired by the host.
136 */
137 cmd.cmdCode = SEND_OP_COND;
138 /* [31:0] OCR. */
139 cmd.argument = arg;
140 cmd.respType = MMC_RESP_SPI_R1 | MMC_RESP_R3 | MMC_CMD_TYPE_BCR;
141 /*
142 * The host must poll the card (by repeatedly sending CMD1 or ACMD41) until the 'in-idle-state' bit in
143 * the card response indicates (by being set to 0) that the card completed its initialization processes
144 * and is ready for the next command.
145 */
146 for (i = 0; i < INIT_CMD_RETRY_TIMES; i++) {
147 err = MmcSendCmd(cntlr, &cmd, NULL, 1);
148 if (err != HDF_SUCCESS) {
149 break;
150 }
151 if (arg == 0 || (cmd.resp[0] & MMC_CARD_BUSY_STATUS) > 0) {
152 break;
153 }
154
155 err = HDF_ERR_TIMEOUT;
156 OsalMDelay(10);
157 }
158
159 if (ocr != NULL) {
160 *ocr = cmd.resp[0];
161 }
162 return err;
163 }
164
MmcAllSendCid(struct MmcCntlr * cntlr)165 static int32_t MmcAllSendCid(struct MmcCntlr *cntlr)
166 {
167 struct MmcCmd cmd = {0};
168 uint32_t *cid = NULL;
169 int32_t err;
170
171 if (cntlr == NULL || cntlr->curDev == NULL) {
172 return HDF_ERR_INVALID_OBJECT;
173 }
174
175 cmd.cmdCode = ALL_SEND_CID;
176 /* [31:0] stuff bits. */
177 cmd.argument = 0;
178 /* Broadcast Commands with Response(bcr). */
179 cmd.respType = MMC_RESP_R2 | MMC_CMD_TYPE_BCR;
180 err = MmcSendCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
181 if (err != HDF_SUCCESS) {
182 return err;
183 }
184 cid = cntlr->curDev->reg.rawCid;
185 if (memcpy_s(cid, sizeof(cntlr->curDev->reg.rawCid), cmd.resp, sizeof(cmd.resp)) != EOK) {
186 HDF_LOGE("MmcAllSendCid: memcpy_s fail!");
187 return HDF_FAILURE;
188 }
189 return err;
190 }
191
MmcSetRelativeAddr(struct MmcCntlr * cntlr)192 static int32_t MmcSetRelativeAddr(struct MmcCntlr *cntlr)
193 {
194 struct MmcCmd cmd = {0};
195
196 if (cntlr == NULL || cntlr->curDev == NULL) {
197 return HDF_ERR_INVALID_OBJECT;
198 }
199
200 cmd.cmdCode = SET_RELATIVE_ADDR;
201 /* [31:16] RCA, [15:0] stuff bits. */
202 cmd.argument = (cntlr->curDev->reg.rca << 16);
203 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
204 return MmcSendCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
205 }
206
MmcSelectCard(struct MmcCntlr * cntlr)207 static int32_t MmcSelectCard(struct MmcCntlr *cntlr)
208 {
209 struct MmcCmd cmd = {0};
210
211 if (cntlr == NULL || cntlr->curDev == NULL) {
212 return HDF_ERR_INVALID_OBJECT;
213 }
214
215 cmd.cmdCode = SELECT_CARD;
216 /* [31:16] RCA, [15:0] stuff bits. */
217 cmd.argument = (cntlr->curDev->reg.rca << 16);
218 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
219 return MmcSendCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
220 }
221
MmcSendExtCsd(struct MmcCntlr * cntlr,uint8_t * extCsd,uint32_t len)222 static int32_t MmcSendExtCsd(struct MmcCntlr *cntlr, uint8_t *extCsd, uint32_t len)
223 {
224 struct MmcCmd cmd = {0};
225 struct MmcData data = {0};
226
227 cmd.cmdCode = SEND_EXT_CSD;
228 cmd.argument = 0;
229 cmd.respType = MMC_RESP_SPI_R1 | MMC_RESP_R1 | MMC_CMD_TYPE_ADTC;
230
231 /* The card sends the EXT_CSD register as a block of data, 512 bytes long. */
232 data.blockSize = len;
233 data.blockNum = 1;
234 data.dataFlags = DATA_READ;
235 data.dataBuffer = extCsd;
236
237 return MmcSendCmd(cntlr, &cmd, &data, 1);
238 }
239
MmcSendCsd(struct MmcCntlr * cntlr)240 static int32_t MmcSendCsd(struct MmcCntlr *cntlr)
241 {
242 struct MmcCmd cmd = {0};
243 uint32_t *csd = NULL;
244 int32_t err;
245
246 if (cntlr == NULL || cntlr->curDev == NULL) {
247 return HDF_ERR_INVALID_OBJECT;
248 }
249
250 cmd.cmdCode = SEND_CSD;
251 cmd.argument = (cntlr->curDev->reg.rca << 16);
252 cmd.respType = MMC_RESP_R2 | MMC_CMD_TYPE_AC;
253 err = MmcSendCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
254 if (err != HDF_SUCCESS) {
255 return err;
256 }
257 csd = cntlr->curDev->reg.rawCsd;
258 if (memcpy_s(csd, sizeof(cntlr->curDev->reg.rawCsd), cmd.resp, sizeof(cmd.resp)) != EOK) {
259 HDF_LOGE("memcpy_s fail!");
260 return HDF_FAILURE;
261 }
262 return err;
263 }
264
MmcSendStatus(struct MmcCntlr * cntlr,uint32_t * status)265 int32_t MmcSendStatus(struct MmcCntlr *cntlr, uint32_t *status)
266 {
267 struct MmcCmd cmd = {0};
268 int32_t error;
269
270 if (cntlr == NULL || cntlr->curDev == NULL) {
271 return HDF_ERR_INVALID_OBJECT;
272 }
273
274 cmd.cmdCode = SEND_STATUS;
275 /* [31:16] RCA, [15:0] stuff bits. */
276 cmd.argument = (cntlr->curDev->reg.rca << 16);
277 cmd.respType = MMC_RESP_SPI_R2 | MMC_RESP_R1 | MMC_CMD_TYPE_AC;
278 error = MmcSendCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
279 if (error != HDF_SUCCESS) {
280 return error;
281 }
282 if (status != NULL) {
283 *status = cmd.resp[0];
284 }
285 return error;
286 }
287
MmcSwitch(struct MmcCntlr * cntlr,uint8_t set,uint8_t index,uint8_t value)288 static int32_t MmcSwitch(struct MmcCntlr *cntlr, uint8_t set, uint8_t index, uint8_t value)
289 {
290 int32_t error;
291 struct MmcCmd cmd = {0};
292 uint32_t status;
293
294 cmd.cmdCode = SWITCH;
295 /*
296 * [31:26] Set to 0; [25:24] Access; [23:16] Index;
297 * [15:8] Value; [7:3] Set to 0; [2:0] Cmd Set.
298 */
299 cmd.argument = (EMMC_EXT_CSD_WRITE_BYTE << 24)
300 | (index << 16)
301 | (value << 8)
302 | set;
303 cmd.respType = MMC_RESP_SPI_R1B | MMC_RESP_R1B | MMC_CMD_TYPE_AC;
304 error = MmcSendCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
305 if (error != HDF_SUCCESS) {
306 HDF_LOGE("MmcSwitch: send cmd fail!");
307 return error;
308 }
309
310 /*
311 * The SWITCH command response is of type R1b, therefore, the host should read the card status, using
312 * SEND_STATUS command, after the busy signal is de-asserted, to check the result of the SWITCH operation.
313 */
314 do {
315 error = MmcSendStatus(cntlr, &status);
316 if (error != HDF_SUCCESS) {
317 HDF_LOGE("MmcSwitch: send status cmd fail!");
318 return error;
319 }
320 } while ((!(status & READY_FOR_DATA)) || MmcCntlrDevBusy(cntlr) == true);
321
322 /*
323 * When the host tries to access a partition which has not been created before, the devices sets the
324 * SWITCH_ERROR bit in the status register and will not change the PARTITION_ACCESS bits.
325 */
326 if ((status & SWITCH_ERROR) > 0) {
327 return HDF_MMC_ERR_SWITCH_FAIL;
328 }
329 return error;
330 }
331
MmcAppCmd(struct MmcCntlr * cntlr,uint32_t acmd)332 static int32_t MmcAppCmd(struct MmcCntlr *cntlr, uint32_t acmd)
333 {
334 int32_t err;
335 struct MmcCmd cmd = {0};
336
337 if (cntlr == NULL || cntlr->curDev == NULL) {
338 return HDF_ERR_INVALID_OBJECT;
339 }
340
341 /*
342 * After the bus is activated the host will request the cards to send their valid operation conditions
343 * (ACMD41 preceding with APP_CMD - CMD55 with RCA = 0x0000).
344 */
345 cmd.cmdCode = APP_CMD;
346 if (acmd != SD_ACMD_OP_COND) {
347 /* [31:16] RCA, [15:0] stuff bits */
348 cmd.argument = (cntlr->curDev->reg.rca << 16);
349 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
350 } else {
351 cmd.argument = 0;
352 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_BCR;
353 }
354 err = MmcSendCmd(cntlr, &cmd, NULL, 1);
355 if (err != HDF_SUCCESS) {
356 return err;
357 }
358 if (!(cmd.resp[0] & IS_APP_CMD)) {
359 return HDF_FAILURE;
360 }
361 return err;
362 }
363
MmcWaitCardReady(struct MmcCntlr * cntlr)364 static int32_t MmcWaitCardReady(struct MmcCntlr *cntlr)
365 {
366 int error;
367 uint32_t status;
368 int32_t retryTimes = SEND_STATUS_CMD_RETRY_TIMES;
369
370 do {
371 error = MmcSendStatus(cntlr, &status);
372 if (error != HDF_SUCCESS) {
373 return error;
374 }
375
376 if (retryTimes >= 0) {
377 retryTimes--;
378 OsalMSleep(10);
379 } else {
380 return HDF_ERR_TIMEOUT;
381 }
382 } while (!(status & READY_FOR_DATA) || (MMC_CARD_CURRENT_STATE(status) == STATE_PRG));
383 return error;
384 }
385
MmcStopTransmission(struct MmcCntlr * cntlr,bool writeFlag,uint32_t * stopStatus)386 int32_t MmcStopTransmission(struct MmcCntlr *cntlr, bool writeFlag, uint32_t *stopStatus)
387 {
388 int32_t err;
389 struct MmcCmd cmd = {0};
390
391 cmd.cmdCode = STOP_TRANSMISSION;
392 /* R1 for read cases and R1b for write cases. */
393 if (writeFlag == true) {
394 cmd.respType = MMC_RESP_R1B | MMC_CMD_TYPE_AC;
395 } else {
396 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
397 }
398 err = MmcSendCmd(cntlr, &cmd, NULL, STOP_TRANSMISSION_CMD_RETRY_TIMES);
399 if (err != HDF_SUCCESS) {
400 return err;
401 }
402
403 *stopStatus = cmd.resp[0];
404 /* No need to check card status in case of read. */
405 if (writeFlag == false) {
406 return err;
407 }
408 return MmcWaitCardReady(cntlr);
409 }
410
MmcSendTuning(struct MmcCntlr * cntlr,uint32_t cmdCode,bool sendStop)411 int32_t MmcSendTuning(struct MmcCntlr *cntlr, uint32_t cmdCode, bool sendStop)
412 {
413 struct MmcCmd cmd = {0};
414 struct MmcData data = {0};
415 /* Tuning Block Pattern UHS-I. */
416 uint8_t tuningBlk4bit[] = {
417 0xFF, 0x0F, 0xFF, 0x00, 0xFF, 0xCC, 0xC3, 0xCC, 0xC3, 0x3C, 0xCC, 0xFF,
418 0xFE, 0xFF, 0xFE, 0xEF, 0xFF, 0xDF, 0xFF, 0xDD, 0xFF, 0xFB, 0xFF, 0xFB,
419 0xBF, 0xFF, 0x7F, 0xFF, 0x77, 0xF7, 0xBD, 0xEF, 0xFF, 0xF0, 0xFF, 0xF0,
420 0x0F, 0xFC, 0xCC, 0x3C, 0xCC, 0x33, 0xCC, 0xCF, 0xFF, 0xEF, 0xFF, 0xEE,
421 0xFF, 0xFD, 0xFF, 0xFD, 0xDF, 0xFF, 0xBF, 0xFF, 0xBB, 0xFF, 0xF7, 0xFF,
422 0xF7, 0x7f, 0x7B, 0xDE,
423 };
424 /* Tuning block pattern for 8 bit mode for HS200. */
425 uint8_t tuningBlk8bit[] = {
426 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0xCC, 0xCC,
427 0xCC, 0x33, 0xCC, 0xCC, 0xCC, 0x33, 0x33, 0xCC, 0xCC, 0xCC, 0xFF, 0xFF,
428 0xFF, 0xEE, 0xFF, 0xFF, 0xFF, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xDD, 0xFF,
429 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xBB, 0xFF, 0xFF, 0xFF, 0xBB,
430 0xBB, 0xFF, 0xFF, 0xFF, 0x77, 0xFF, 0xFF, 0xFF, 0x77, 0x77, 0xFF, 0x77,
431 0xBB, 0xDD, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00,
432 0x00, 0xFF, 0xFF, 0xCC, 0xCC, 0xCC, 0x33, 0xCC, 0xCC, 0xCC, 0x33, 0x33,
433 0xCC, 0xCC, 0xCC, 0xFF, 0xFF, 0xFF, 0xEE, 0xFF, 0xFF, 0xFF, 0xEE, 0xEE,
434 0xFF, 0xFF, 0xFF, 0xDD, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
435 0xBB, 0xFF, 0xFF, 0xFF, 0xBB, 0xBB, 0xFF, 0xFF, 0xFF, 0x77, 0xFF, 0xFF,
436 0xFF, 0x77, 0x77, 0xFF, 0x77, 0xBB, 0xDD, 0xEE,
437 };
438
439 if (cntlr == NULL || cntlr->curDev == NULL) {
440 return HDF_ERR_INVALID_OBJECT;
441 }
442
443 cmd.cmdCode = cmdCode;
444 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_ADTC;
445
446 if (cntlr->curDev->workPara.width == BUS_WIDTH4) {
447 data.blockSize = sizeof(tuningBlk4bit);
448 data.dataBuffer = tuningBlk4bit;
449 } else if (cntlr->curDev->workPara.width == BUS_WIDTH8) {
450 data.blockSize = sizeof(tuningBlk8bit);
451 data.dataBuffer = tuningBlk8bit;
452 } else {
453 HDF_LOGE("MmcSendTuning: work width is 1, can not tune!");
454 return HDF_FAILURE;
455 }
456 data.blockNum = 1;
457 data.dataFlags = DATA_READ;
458 if (sendStop == true) {
459 data.sendStopCmd = true;
460 data.stopCmd.cmdCode = STOP_TRANSMISSION;
461 data.stopCmd.respType = MMC_RESP_R1B | MMC_CMD_TYPE_AC;
462 }
463
464 return MmcSendCmd(cntlr, &cmd, &data, 1);
465 }
466
MmcSendEraseStartCmd(struct MmcCntlr * cntlr,uint32_t arg)467 static int32_t MmcSendEraseStartCmd(struct MmcCntlr *cntlr, uint32_t arg)
468 {
469 struct MmcCmd cmd = {0};
470 struct MmcDevice *dev = cntlr->curDev;
471
472 if (dev == NULL) {
473 return HDF_ERR_INVALID_OBJECT;
474 }
475
476 /* SD: CMD32; EMMC: CMD35 */
477 if (dev->type == MMC_DEV_SD) {
478 cmd.cmdCode = SD_CMD_ERASE_WR_BLK_START;
479 } else {
480 cmd.cmdCode = ERASE_GROUP_START;
481 }
482 /* [31:0]data address. */
483 cmd.argument = arg;
484 /*
485 * Data address for media =<2GB is a 32bit byte address and data address for media > 2GB is
486 * a 32bit sector (512B) address.
487 */
488 if (dev->state.bits.blockAddr == 0) {
489 cmd.argument <<= MMC_MAX_BLOCKSIZE_SHIFT;
490 }
491 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
492 return MmcSendCmd(cntlr, &cmd, NULL, 1);
493 }
494
MmcSendEraseEndCmd(struct MmcCntlr * cntlr,uint32_t arg)495 static int32_t MmcSendEraseEndCmd(struct MmcCntlr *cntlr, uint32_t arg)
496 {
497 struct MmcCmd cmd = {0};
498 struct MmcDevice *dev = cntlr->curDev;
499
500 if (dev == NULL) {
501 return HDF_ERR_INVALID_OBJECT;
502 }
503
504 /* SD: CMD33; EMMC: CMD36 */
505 if (dev->type == MMC_DEV_SD) {
506 cmd.cmdCode = SD_CMD_ERASE_WR_BLK_END;
507 } else {
508 cmd.cmdCode = ERASE_GROUP_END;
509 }
510 /* [31:0]data address. */
511 cmd.argument = arg;
512 /*
513 * Data address for media =<2GB is a 32bit byte address and data address for media > 2GB is
514 * a 32bit sector (512B) address.
515 */
516 if (dev->state.bits.blockAddr == 0) {
517 cmd.argument <<= MMC_MAX_BLOCKSIZE_SHIFT;
518 }
519 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
520 return MmcSendCmd(cntlr, &cmd, NULL, 1);
521 }
522
MmcSendEraseCmd(struct MmcCntlr * cntlr,uint32_t arg)523 static int32_t MmcSendEraseCmd(struct MmcCntlr *cntlr, uint32_t arg)
524 {
525 struct MmcCmd cmd = {0};
526 struct MmcDevice *dev = cntlr->curDev;
527
528 if (dev == NULL) {
529 return HDF_ERR_INVALID_OBJECT;
530 }
531
532 /* ERASE cmd38 */
533 cmd.cmdCode = MMC_ERASE;
534 cmd.argument = arg;
535 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
536 return MmcSendCmd(cntlr, &cmd, NULL, 1);
537 }
538
MmcAlignEraseSize(struct MmcCntlr * cntlr,uint32_t * start,uint32_t * end,uint32_t size)539 static int32_t MmcAlignEraseSize(struct MmcCntlr *cntlr, uint32_t *start, uint32_t *end, uint32_t size)
540 {
541 uint32_t curSize = size;
542 uint32_t tmp;
543
544 if (cntlr->curDev->eraseSize == 0) {
545 return HDF_ERR_NOT_SUPPORT;
546 }
547
548 /* align start. */
549 tmp = (*start) % cntlr->curDev->eraseSize;
550 if (tmp > 0) {
551 tmp = cntlr->curDev->eraseSize - tmp;
552 (*start) += tmp;
553 if (curSize > tmp) {
554 curSize -= tmp;
555 } else {
556 return HDF_ERR_NOT_SUPPORT;
557 }
558 }
559
560 /* align size. */
561 tmp = curSize % cntlr->curDev->eraseSize;
562 if (tmp > 0) {
563 curSize -= tmp;
564 }
565 if (curSize == 0) {
566 return HDF_ERR_NOT_SUPPORT;
567 }
568
569 (*end) = (*start) + curSize;
570 return HDF_SUCCESS;
571 }
572
MmcSendErase(struct MmcCntlr * cntlr,uint32_t startSec,uint32_t nSec)573 int32_t MmcSendErase(struct MmcCntlr *cntlr, uint32_t startSec, uint32_t nSec)
574 {
575 int32_t ret;
576 uint32_t start = startSec;
577 uint32_t end = start + nSec;
578
579 if (cntlr == NULL || cntlr->curDev == NULL) {
580 return HDF_ERR_INVALID_OBJECT;
581 }
582
583 if (cntlr->curDev->eraseSize == 0 ||
584 (cntlr->curDev->reg.csd.ccc & MMC_CSD_CCC_ERASE) == 0) {
585 return HDF_ERR_NOT_SUPPORT;
586 }
587
588 ret = MmcAlignEraseSize(cntlr, &start, &end, nSec);
589 if (ret != HDF_SUCCESS) {
590 /* after align, no need to erase. */
591 return HDF_SUCCESS;
592 }
593
594 /*
595 * emmc:
596 * Starting the erase process is a three steps sequence.
597 * First the host defines the start address of the range using the ERASE_GROUP_START (CMD35) command,
598 * next it defines the last address of the range using the ERASE_GROUP_END (CMD36) command and
599 * finally it starts the erase process by issuing the ERASE (CMD38) command with argument bits set to zero.
600 * sd:
601 * The host should adhere to the following command sequence: ERASE_WR_BLK_START(cmd32), ERASE_WR_BLK_END(cmd33)
602 * and ERASE(CMD38).
603 */
604 ret = MmcSendEraseStartCmd(cntlr, start);
605 if (ret != HDF_SUCCESS) {
606 HDF_LOGE("send erase start cmd fail, err = %d!", ret);
607 return ret;
608 }
609
610 ret = MmcSendEraseEndCmd(cntlr, end);
611 if (ret != HDF_SUCCESS) {
612 HDF_LOGE("send erase end cmd fail, err = %d!", ret);
613 return ret;
614 }
615
616 ret = MmcSendEraseCmd(cntlr, 0);
617 if (ret != HDF_SUCCESS) {
618 HDF_LOGE("send erase cmd fail, err = %d!", ret);
619 return ret;
620 }
621
622 return MmcWaitCardReady(cntlr);
623 }
624
MmcSetupReadWriteBlocksCmd(struct MmcDevice * mmc,struct MmcCmd * cmd,struct MmcRwData * info)625 void MmcSetupReadWriteBlocksCmd(struct MmcDevice *mmc, struct MmcCmd *cmd, struct MmcRwData *info)
626 {
627 cmd->data->blockSize = BYTES_PER_BLOCK;
628 cmd->data->blockNum = info->sectors;
629 cmd->data->dataBuffer = info->buf;
630
631 cmd->respType = MMC_RESP_R1 | MMC_CMD_TYPE_ADTC;
632 /* [31:0]data address. */
633 cmd->argument = info->startSector;
634 if (mmc->state.bits.blockAddr == 0) {
635 /* SDSC Card uses byte unit address and SDHC and SDXC Cards use block unit address(512 Bytes unit). */
636 cmd->argument <<= MMC_MAX_BLOCKSIZE_SHIFT;
637 }
638 if (info->writeFlag == true) {
639 cmd->data->dataFlags = DATA_WRITE;
640 cmd->cmdCode = WRITE_BLOCK;
641 if (info->sectors > 1) {
642 cmd->cmdCode = WRITE_MULTIPLE_BLOCK;
643 }
644 } else {
645 cmd->data->dataFlags = DATA_READ;
646 cmd->cmdCode = READ_SINGLE_BLOCK;
647 if (info->sectors > 1) {
648 cmd->cmdCode = READ_MULTIPLE_BLOCK;
649 }
650 }
651 if ((info->sectors > 1) && (mmc->cntlr->caps.bits.cmdStop > 0)) {
652 cmd->data->stopCmd.cmdCode = STOP_TRANSMISSION;
653 cmd->data->sendStopCmd = true;
654 }
655 }
656
MmcSendReadWriteBlocks(struct MmcCntlr * cntlr,struct MmcRwData * info)657 int32_t MmcSendReadWriteBlocks(struct MmcCntlr *cntlr, struct MmcRwData *info)
658 {
659 struct MmcCmd cmd = {0};
660 struct MmcData data = {0};
661
662 if (cntlr == NULL || cntlr->curDev == NULL) {
663 return HDF_ERR_INVALID_OBJECT;
664 }
665
666 cmd.data = &data;
667 MmcSetupReadWriteBlocksCmd(cntlr->curDev, &cmd, info);
668 return MmcSendCmd(cntlr, &cmd, &data, 1);
669 }
670
EmmcDecodeCsd(struct MmcCntlr * cntlr)671 static int32_t EmmcDecodeCsd(struct MmcCntlr *cntlr)
672 {
673 struct MmcCsd *csd = NULL;
674 uint32_t unit, factor;
675 uint32_t *rawCsd = NULL;
676
677 if (cntlr == NULL || cntlr->curDev == NULL) {
678 return HDF_ERR_INVALID_PARAM;
679 }
680
681 rawCsd = cntlr->curDev->reg.rawCsd;
682 csd = &(cntlr->curDev->reg.csd);
683
684 /* CSD_STRUCTURE: [127:126]. */
685 csd->structure = MmcParseBits(rawCsd, CSD_BITS, 126, 2);
686 if (csd->structure == 0) {
687 HDF_LOGE("EmmcDecodeCsd: structure is invalid!");
688 return HDF_ERR_INVALID_PARAM;
689 }
690
691 /* SPEC_VERS: [125:122]. */
692 csd->specVers = MmcParseBits(rawCsd, CSD_BITS, 122, 4);
693 /* TAAC: [119:112]; TAAC bit position-->Time unit: [2:0], Multiplier factor: [6:3]. */
694 factor = MmcParseBits(rawCsd, CSD_BITS, 115, 4);
695 unit = MmcParseBits(rawCsd, CSD_BITS, 112, 3);
696 csd->taccNs = (g_taccUnit[unit] * g_commFactor[factor] + 9) / 10;
697 /* NSAC: [111:104] */
698 csd->taccClks = MmcParseBits(rawCsd, CSD_BITS, 104, 8) * 100;
699
700 /* TRAN_SPEED: [103:96]; TRAN_SPEED bit-->Frequency unit: [2:0], Multiplier factor: [6:3]. */
701 factor = MmcParseBits(rawCsd, CSD_BITS, 99, 4);
702 unit = MmcParseBits(rawCsd, CSD_BITS, 96, 3);
703 csd->maxDtr = g_tranSpeedUnit[unit] * g_commFactor[factor];
704 csd->ccc = MmcParseBits(rawCsd, CSD_BITS, 84, 12);
705
706 /* C_SIZE: [73:62] */
707 factor = MmcParseBits(rawCsd, CSD_BITS, 62, 12);
708 /* C_SIZE_MULT: [49:47] */
709 unit = MmcParseBits(rawCsd, CSD_BITS, 47, 3);
710 csd->capacity = (1 + factor) << (unit + 2);
711 /* READ_BL_LEN: [83:80]. */
712 csd->readBlkLen = MmcParseBits(rawCsd, CSD_BITS, 80, 4);
713 /* READ_BL_PARTIAL: [79:79] */
714 csd->rdPartial = MmcParseBits(rawCsd, CSD_BITS, 79, 1);
715 /* WRITE_BLK_MISALIGN: [78:78] */
716 csd->wrMisalign = MmcParseBits(rawCsd, CSD_BITS, 78, 1);
717 /* READ_BLK_MISALIGN: [77:77] */
718 csd->rdMisalign = MmcParseBits(rawCsd, CSD_BITS, 77, 1);
719 /* Write speed factor(R2W_FACTOR) :[28:26] */
720 csd->r2wFactor = MmcParseBits(rawCsd, CSD_BITS, 26, 3);
721 /* WRITE_BL_LEN: [25:22] */
722 csd->writeBlkLen = MmcParseBits(rawCsd, CSD_BITS, 22, 4);
723 /* WRITE_BL_PARTIAL: [21:21] */
724 csd->wrPartial = MmcParseBits(rawCsd, CSD_BITS, 21, 1);
725
726 /*
727 * Note that the support for 512B read access is mandatory for all cards.
728 * And that the cards has to be in 512B block length mode by default after power-on, or software reset.
729 */
730 if (csd->writeBlkLen >= MMC_MAX_BLOCKSIZE_SHIFT) {
731 /* ERASE_GRP_SIZE: [46:42] */
732 unit = MmcParseBits(rawCsd, CSD_BITS, 42, 5);
733 /* ERASE_GRP_MULT: [41:37] */
734 factor = MmcParseBits(rawCsd, CSD_BITS, 37, 5);
735 /* size of erasable unit = (ERASE_GRP_SIZE + 1) * (ERASE_GRP_MULT + 1) */
736 csd->eraseSize = (unit + 1) * (factor + 1);
737 csd->eraseSize <<= (csd->writeBlkLen - MMC_MAX_BLOCKSIZE_SHIFT);
738 }
739 return HDF_SUCCESS;
740 }
741
EmmcDecodeCid(struct MmcCntlr * cntlr)742 static int32_t EmmcDecodeCid(struct MmcCntlr *cntlr)
743 {
744 uint32_t i;
745 struct MmcCid *cid = NULL;
746 uint32_t *rawCid = NULL;
747 uint8_t specVers, cbx;
748
749 if (cntlr == NULL || cntlr->curDev == NULL) {
750 return HDF_ERR_INVALID_PARAM;
751 }
752
753 rawCid = cntlr->curDev->reg.rawCid;
754 cid = &(cntlr->curDev->reg.cid);
755 specVers = cntlr->curDev->reg.csd.specVers;
756 if (specVers > MMC_CSD_SPEC_VER_4) {
757 HDF_LOGE("EmmcDecodeCid: specVers is invalid!");
758 return HDF_ERR_NOT_SUPPORT;
759 }
760
761 /*
762 * The manufacturing date is composed of two hexadecimal digits, four bits each,
763 * representing a two digits date code m/y;
764 */
765 cid->month = MmcParseBits(rawCid, CID_BITS, 12, 4);
766 /* The "y" field, least significant nibble, is the year code. 0 is 1997. */
767 cid->year = MmcParseBits(rawCid, CID_BITS, 8, 4) + 1997;
768
769 if (specVers == MMC_CSD_SPEC_VER_0 || specVers == MMC_CSD_SPEC_VER_1) {
770 cid->mid = MmcParseBits(rawCid, CID_BITS, 104, 24);
771 for (i = 0; i < 7; i++) {
772 cid->pnm[i] = (char)MmcParseBits(rawCid, CID_BITS, CID_PNM_START_BIT - (i * BITS_PER_BYTE), BITS_PER_BYTE);
773 }
774 cid->pnm[7] = '\0';
775 cid->hwPrv = MmcParseBits(rawCid, CID_BITS, 44, 4);
776 cid->fwPrv = MmcParseBits(rawCid, CID_BITS, 40, 4);
777 cid->psn = MmcParseBits(rawCid, CID_BITS, 16, 24);
778 } else {
779 /* Manufacturer ID(MID): [127:120] */
780 cid->mid = MmcParseBits(rawCid, CID_BITS, 120, 8);
781 /* OEM/Application ID(OID): [119:104] */
782 cid->oid = MmcParseBits(rawCid, CID_BITS, 104, 16);
783 /* Product name(PNM): [103:56] */
784 for (i = 0; i < 6; i++) {
785 cid->pnm[i] = (char)MmcParseBits(rawCid, CID_BITS, CID_PNM_START_BIT - (i * BITS_PER_BYTE), BITS_PER_BYTE);
786 }
787 cid->pnm[6] = '\0';
788 /* Product serial number(PSN): [47:16] */
789 cid->psn = MmcParseBits(rawCid, CID_BITS, 16, 32);
790 /*
791 * Card or BGA(CBX): [113:112]
792 * 00: Card (removable); 01: BGA (Discrete embedded); 10: POP; 11: Reserved.
793 */
794 cbx = MmcParseBits(rawCid, CID_BITS, 112, 2);
795 if (cbx == 0) {
796 cntlr->curDev->state.bits.removeable = 1;
797 HDF_LOGD("Emmc is removeable!");
798 }
799 }
800 return HDF_SUCCESS;
801 }
802
EmmcDecodeExtCsdSector(struct EmmcDevice * emmcDev,struct EmmcExtCsd * extCsd)803 static void EmmcDecodeExtCsdSector(struct EmmcDevice *emmcDev, struct EmmcExtCsd *extCsd)
804 {
805 uint32_t i;
806 uint32_t shift = 0;
807
808 extCsd->sectors = 0;
809 for (i = 0; i < EMMC_EXT_CSD_SEC_CNT_BYTES; i++) {
810 extCsd->sectors |= (uint32_t)(extCsd->rawSectors[i] << shift);
811 shift += BITS_PER_BYTE;
812 }
813 /* Device density > 2GiB are sector addressed. */
814 if (extCsd->sectors > (2u * 1024 * 1024 * 1024) / 512) {
815 emmcDev->mmc.state.bits.blockAddr = 1;
816 }
817 }
818
EmmcDecodeExtCsdCardType(struct EmmcExtCsd * extCsd)819 static void EmmcDecodeExtCsdCardType(struct EmmcExtCsd *extCsd)
820 {
821 uint8_t cardType = extCsd->rawCardType & EMMC_EXT_CSD_CARD_TYPE_MASK;
822
823 switch (cardType) {
824 case EMMC_EXT_CSD_CARD_TYPE_SDR_ALL:
825 case EMMC_EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_8V:
826 case EMMC_EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_2V:
827 case EMMC_EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52:
828 extCsd->hsMaxDtr = EMMC_EXT_CSD_HIGH_SPEED_200;
829 extCsd->cardType = EMMC_EXT_CSD_CARD_TYPE_SDR_200;
830 break;
831 case EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V_ALL:
832 case EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V_ALL_DDR_1_8V:
833 case EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V_ALL_DDR_1_2V:
834 case EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V_ALL_DDR_52:
835 extCsd->hsMaxDtr = EMMC_EXT_CSD_HIGH_SPEED_200;
836 extCsd->cardType = EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V;
837 break;
838 case EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V_ALL:
839 case EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V_ALL_DDR_1_8V:
840 case EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V_ALL_DDR_1_2V:
841 case EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V_ALL_DDR_52:
842 extCsd->hsMaxDtr = EMMC_EXT_CSD_HIGH_SPEED_200;
843 extCsd->cardType = EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V;
844 break;
845 case (EMMC_EXT_CSD_CARD_TYPE_DDR_52 | EMMC_EXT_CSD_CARD_TYPE_52 | EMMC_EXT_CSD_CARD_TYPE_26):
846 extCsd->hsMaxDtr = EMMC_EXT_CSD_HIGH_SPEED_52;
847 extCsd->cardType = EMMC_EXT_CSD_CARD_TYPE_DDR_52;
848 break;
849 case (EMMC_EXT_CSD_CARD_TYPE_DDR_1_2V | EMMC_EXT_CSD_CARD_TYPE_52 | EMMC_EXT_CSD_CARD_TYPE_26):
850 extCsd->hsMaxDtr = EMMC_EXT_CSD_HIGH_SPEED_52;
851 extCsd->cardType = EMMC_EXT_CSD_CARD_TYPE_DDR_1_2V;
852 break;
853 case (EMMC_EXT_CSD_CARD_TYPE_DDR_1_8V | EMMC_EXT_CSD_CARD_TYPE_52 | EMMC_EXT_CSD_CARD_TYPE_26):
854 extCsd->hsMaxDtr = EMMC_EXT_CSD_HIGH_SPEED_52;
855 extCsd->cardType = EMMC_EXT_CSD_CARD_TYPE_DDR_1_8V;
856 break;
857 case (EMMC_EXT_CSD_CARD_TYPE_52 | EMMC_EXT_CSD_CARD_TYPE_26):
858 extCsd->hsMaxDtr = EMMC_EXT_CSD_HIGH_SPEED_52;
859 break;
860 case EMMC_EXT_CSD_CARD_TYPE_26:
861 extCsd->hsMaxDtr = EMMC_EXT_CSD_HIGH_SPEED_26;
862 break;
863 default:
864 HDF_LOGD("EmmcDecodeExtCsdCardType: not support high-speed!");
865 break;
866 }
867 }
868
EmmcDecodeExtCsdRev13Field(struct EmmcExtCsd * extCsd,uint8_t * rawExtCsd)869 static void EmmcDecodeExtCsdRev13Field(struct EmmcExtCsd *extCsd, uint8_t *rawExtCsd)
870 {
871 uint8_t shift = rawExtCsd[EMMC_EXT_CSD_S_A_TIMEOUT];
872
873 extCsd->eraseGroupDef = rawExtCsd[EMMC_EXT_CSD_ERASE_GROUP_DEF];
874 extCsd->partConfig = rawExtCsd[EMMC_EXT_CSD_PARTITION_CONFIG];
875 extCsd->partSwitchTime = 10 * rawExtCsd[EMMC_EXT_CSD_PARTITION_SWITCH_TIME];
876
877 if (shift > 0 && shift <= MAX_S_A_TIMEOUT_VALUE) {
878 extCsd->saTimeout = 1 << shift;
879 }
880 extCsd->relWrSecorCount = rawExtCsd[EMMC_EXT_CSD_REL_WR_SEC_C];
881 extCsd->hcEraseTimeout = 300 * rawExtCsd[EMMC_EXT_CSD_ERASE_TIMEOUT_MULT];
882 extCsd->hcEraseSize = (extCsd->rawHcEraseGrpSize) << 10;
883 extCsd->bootSize = rawExtCsd[EMMC_EXT_CSD_BOOT_MULTI] << 17;
884 }
885
EmmcDecodeExtCsdEnhanceArea(struct EmmcDevice * emmcDev,struct EmmcExtCsd * extCsd,uint8_t * rawExtCsd)886 static void EmmcDecodeExtCsdEnhanceArea(struct EmmcDevice *emmcDev,
887 struct EmmcExtCsd *extCsd, uint8_t *rawExtCsd)
888 {
889 uint32_t i;
890 uint32_t shift = 0;
891
892 extCsd->enhAreaEnable = true;
893 extCsd->enhAreaOffset = 0;
894 for (i = 0; i < EMMC_EXT_CSD_ENH_START_ADDR_BYTES; i++) {
895 extCsd->enhAreaOffset |= ((uint64_t)rawExtCsd[EMMC_EXT_CSD_ENH_START_ADDR + i] << shift);
896 shift += BITS_PER_BYTE;
897 }
898 /*
899 * Start address of the Enhanced User Data Area segment in the User Data Area
900 * (expressedin bytes or in sectors in case of high capacity devices).
901 */
902 if (emmcDev->mmc.state.bits.blockAddr == 1) {
903 extCsd->enhAreaOffset <<= MMC_MAX_BLOCKSIZE_SHIFT;
904 }
905
906 shift = 0;
907 extCsd->enhAreaSize = 0;
908 for (i = 0; i < EMMC_EXT_CSD_ENH_SIZE_MULT_BYTES; i++) {
909 extCsd->enhAreaSize |= (uint32_t)(rawExtCsd[EMMC_EXT_CSD_ENH_SIZE_MULT + i] << shift);
910 shift += BITS_PER_BYTE;
911 }
912 /* Max Enhanced Area = MAX_ENH_SIZE_MULT * HC_WP_GRP_SIZE * HC_ERASE_GPR_SIZE * 512kBytes */
913 extCsd->enhAreaSize *= (uint32_t)(extCsd->rawHcEraseGrpSize * rawExtCsd[EMMC_EXT_CSD_HC_WP_GRP_SIZE]);
914 extCsd->enhAreaSize <<= MMC_MAX_BLOCKSIZE_SHIFT;
915 }
916
EmmcDecodeExtCsdPowerClassValue(struct EmmcExtCsd * extCsd,uint8_t * rawExtCsd)917 static void EmmcDecodeExtCsdPowerClassValue(struct EmmcExtCsd *extCsd, uint8_t *rawExtCsd)
918 {
919 extCsd->pwrClF52V195 = rawExtCsd[EMMC_EXT_CSD_PWR_CL_52_195];
920 extCsd->pwrClF26V195 = rawExtCsd[EMMC_EXT_CSD_PWR_CL_26_195];
921 extCsd->pwrClF52V360 = rawExtCsd[EMMC_EXT_CSD_PWR_CL_52_360];
922 extCsd->pwrClF26V360 = rawExtCsd[EMMC_EXT_CSD_PWR_CL_26_360];
923 extCsd->pwrClF200V195 = rawExtCsd[EMMC_EXT_CSD_PWR_CL_200_195];
924 extCsd->pwrClF200V360 = rawExtCsd[EMMC_EXT_CSD_PWR_CL_200_360];
925 extCsd->pwrClDdrF52V195 = rawExtCsd[EMMC_EXT_CSD_PWR_CL_DDR_52_195];
926 extCsd->pwrClDdrF52V360 = rawExtCsd[EMMC_EXT_CSD_PWR_CL_DDR_52_360];
927 }
928
EmmcDecodeExtCsdRev14Field(struct EmmcDevice * emmcDev,struct EmmcExtCsd * extCsd,uint8_t * rawExtCsd)929 static void EmmcDecodeExtCsdRev14Field(struct EmmcDevice *emmcDev,
930 struct EmmcExtCsd *extCsd, uint8_t *rawExtCsd)
931 {
932 if ((rawExtCsd[EMMC_EXT_CSD_PARTITIONING_SUPPORT] & PARTITIONING_SUPPORT_ENH_ATTRIBUTE_EN) > 0 &&
933 (rawExtCsd[EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE] & PARTITIONS_ATTRIBUTE_ENH_USR) > 0) {
934 EmmcDecodeExtCsdEnhanceArea(emmcDev, extCsd, rawExtCsd);
935 }
936 extCsd->secTrimMult = extCsd->rawSecTrimMult;
937 extCsd->secEraseMult = extCsd->rawSecEraseMult;
938 /* TRIM Timeout = 300ms x TRIM_MULT. */
939 extCsd->trimTimeout = 300 * extCsd->rawTrimMult;
940 EmmcDecodeExtCsdPowerClassValue(extCsd, rawExtCsd);
941 }
942
EmmcDecodeExtCsdRev15Field(struct EmmcExtCsd * extCsd,uint8_t * rawExtCsd)943 static void EmmcDecodeExtCsdRev15Field(struct EmmcExtCsd *extCsd, uint8_t *rawExtCsd)
944 {
945 /* whether the eMMC card supports HPI. */
946 if ((rawExtCsd[EMMC_EXT_CSD_HPI_FEATURES] & EMMC_EXT_CSD_HPI_SUPPORT) > 0) {
947 extCsd->hpi = true;
948 if ((rawExtCsd[EMMC_EXT_CSD_HPI_FEATURES] & EMMC_EXT_CSD_HPI_IMPLEMENTATION) > 0) {
949 extCsd->hpiCmd = STOP_TRANSMISSION;
950 } else {
951 extCsd->hpiCmd = SEND_STATUS;
952 }
953 /*
954 * This field indicates the maximum timeout to close a command interrupted by HPI –time between the end
955 * bit of CMD12/13 to the DAT0 release by the device.
956 * Time is expressed in units of 10-milliseconds.
957 */
958 extCsd->outOfInterruptTime = rawExtCsd[EMMC_EXT_CSD_OUT_OF_INTERRUPT_TIME] * 10;
959 }
960 extCsd->wrRelParam = rawExtCsd[EMMC_EXT_CSD_WR_REL_PARAM];
961 }
962
EmmcDecodeExtCsd(struct MmcCntlr * cntlr,uint8_t * rawExtCsd,uint32_t len)963 static int32_t EmmcDecodeExtCsd(struct MmcCntlr *cntlr, uint8_t *rawExtCsd, uint32_t len)
964 {
965 struct EmmcDevice *emmcDev = (struct EmmcDevice *)cntlr->curDev;
966 struct EmmcExtCsd *extCsd = &(emmcDev->emmcReg.extCsd);
967 uint32_t i;
968
969 extCsd->rawCsdStructure = rawExtCsd[EMMC_EXT_CSD_STRUCTURE];
970 if (emmcDev->mmc.reg.csd.structure == MMC_CSD_STRUCTURE_VER_OTHER) {
971 if (extCsd->rawCsdStructure > EMMC_EXT_CSD_STRUCTURE_VER_1_2) {
972 HDF_LOGE("EmmcDecodeExtCsd: rawCsdStructure is invalid!");
973 return HDF_ERR_INVALID_PARAM;
974 }
975 }
976 extCsd->rev = rawExtCsd[EMMC_EXT_CSD_REV];
977 for (i = 0; i < EMMC_EXT_CSD_SEC_CNT_BYTES; i++) {
978 extCsd->rawSectors[i] = rawExtCsd[EMMC_EXT_CSD_SEC_CNT + i];
979 }
980 if (extCsd->rev >= EMMC_EXT_CSD_REV_1_2) {
981 EmmcDecodeExtCsdSector(emmcDev, extCsd);
982 }
983
984 extCsd->strobeSupport = rawExtCsd[EMMC_EXT_CSD_STROBE_SUPPORT];
985 extCsd->rawCardType = rawExtCsd[EMMC_EXT_CSD_CARD_TYPE];
986 EmmcDecodeExtCsdCardType(extCsd);
987
988 extCsd->rawSaTimeout = rawExtCsd[EMMC_EXT_CSD_S_A_TIMEOUT];
989 extCsd->rawEraseTimeoutMult = rawExtCsd[EMMC_EXT_CSD_ERASE_TIMEOUT_MULT];
990 extCsd->rawHcEraseGrpSize = rawExtCsd[EMMC_EXT_CSD_HC_ERASE_GRP_SIZE];
991 if (extCsd->rev >= EMMC_EXT_CSD_REV_1_3) {
992 EmmcDecodeExtCsdRev13Field(extCsd, rawExtCsd);
993 }
994
995 extCsd->rawSecTrimMult = rawExtCsd[EMMC_EXT_CSD_SEC_TRIM_MULT];
996 extCsd->rawSecEraseMult = rawExtCsd[EMMC_EXT_CSD_SEC_ERASE_MULT];
997 extCsd->rawSecFeatureSupport = rawExtCsd[EMMC_EXT_CSD_SEC_FEATURE_SUPPORT];
998 extCsd->rawTrimMult = rawExtCsd[EMMC_EXT_CSD_TRIM_MULT];
999 if (extCsd->rev >= EMMC_EXT_CSD_REV_1_4) {
1000 EmmcDecodeExtCsdRev14Field(emmcDev, extCsd, rawExtCsd);
1001 }
1002
1003 if (extCsd->rev >= EMMC_EXT_CSD_REV_1_5) {
1004 EmmcDecodeExtCsdRev15Field(extCsd, rawExtCsd);
1005 }
1006 return HDF_SUCCESS;
1007 }
1008
EmmcSetBlockCapacity(struct MmcCntlr * cntlr)1009 static void EmmcSetBlockCapacity(struct MmcCntlr *cntlr)
1010 {
1011 struct EmmcDevice *emmcDev = (struct EmmcDevice *)cntlr->curDev;
1012 uint32_t gibVal, mibVal;
1013
1014 /*
1015 * ERASE_GROUP_DEF Bit0: ENABLE:
1016 * 0x0 : Use old erase group size and write protect group size definition (default)
1017 * 0x1 : Use high-capacity erase unit size, high capacity erase timeout, and high-capacity write protect
1018 * group size definition.
1019 */
1020 if (emmcDev->emmcReg.extCsd.eraseGroupDef == 1) {
1021 emmcDev->mmc.eraseSize = emmcDev->emmcReg.extCsd.hcEraseSize;
1022 } else {
1023 emmcDev->mmc.eraseSize = emmcDev->mmc.reg.csd.eraseSize;
1024 }
1025
1026 if (emmcDev->mmc.state.bits.blockAddr > 0) {
1027 emmcDev->mmc.capacity = emmcDev->emmcReg.extCsd.sectors;
1028 } else {
1029 emmcDev->mmc.capacity = (size_t)emmcDev->mmc.reg.csd.capacity <<
1030 (emmcDev->mmc.reg.csd.readBlkLen - MMC_MAX_BLOCKSIZE_SHIFT);
1031 }
1032
1033 gibVal = emmcDev->mmc.capacity >> 21;
1034 mibVal = (emmcDev->mmc.capacity & ~(gibVal << 21)) >> 11;
1035 HDF_LOGD("Emmc dev capacity %d.%d Gib", gibVal, mibVal);
1036 }
1037
EmmcCheckExtCsd(struct MmcCntlr * cntlr,enum MmcBusWidth width)1038 static int32_t EmmcCheckExtCsd(struct MmcCntlr *cntlr, enum MmcBusWidth width)
1039 {
1040 uint8_t extCsd[EXT_CSD_BYTES_LEN] = {0};
1041
1042 if (width == BUS_WIDTH1) {
1043 return 0;
1044 }
1045
1046 return MmcSendExtCsd(cntlr, extCsd, EXT_CSD_BYTES_LEN);
1047 }
1048
EmmcSwitchVoltage(struct MmcCntlr * cntlr,struct EmmcDevice * emmcDev)1049 static int32_t EmmcSwitchVoltage(struct MmcCntlr *cntlr, struct EmmcDevice *emmcDev)
1050 {
1051 uint32_t cardType = emmcDev->emmcReg.extCsd.cardType;
1052
1053 /* Host Voltage Switch. */
1054 if (cntlr->caps2.bits.hs200Sdr1v2 == 1 && (cardType & EMMC_EXT_CSD_CARD_TYPE_SDR_1_2V) > 0) {
1055 (void)MmcCntlrSwitchVoltage(cntlr, VOLT_1V2);
1056 }
1057 if (cntlr->caps2.bits.hs200Sdr1v8 && (cardType & EMMC_EXT_CSD_CARD_TYPE_SDR_1_8V) > 0) {
1058 (void)MmcCntlrSwitchVoltage(cntlr, VOLT_1V8);
1059 }
1060 return HDF_SUCCESS;
1061 }
1062
EmmcSelectHighSpeedBusWidth(struct MmcCntlr * cntlr)1063 static int32_t EmmcSelectHighSpeedBusWidth(struct MmcCntlr *cntlr)
1064 {
1065 int err = HDF_FAILURE;
1066 enum MmcBusWidth width = BUS_WIDTH1;
1067
1068 if (cntlr->caps.bits.cap8Bit > 0) {
1069 err = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_BUS_WIDTH, EMMC_EXT_CSD_BUS_WIDTH_8);
1070 if (err != HDF_SUCCESS) {
1071 HDF_LOGD("EmmcSelectHighSpeedBusWidth: switch 8 bit bus width fail!");
1072 } else {
1073 MmcCntlrSetBusWidth(cntlr, BUS_WIDTH8);
1074 width = BUS_WIDTH8;
1075 }
1076 }
1077 if (err != HDF_SUCCESS) {
1078 err = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_BUS_WIDTH, EMMC_EXT_CSD_BUS_WIDTH_4);
1079 if (err != HDF_SUCCESS) {
1080 HDF_LOGD("EmmcSelectHighSpeedBusWidth: switch 4 bit bus width fail!");
1081 } else {
1082 MmcCntlrSetBusWidth(cntlr, BUS_WIDTH4);
1083 width = BUS_WIDTH4;
1084 }
1085 }
1086 if (err != HDF_SUCCESS) {
1087 return err;
1088 }
1089
1090 return EmmcCheckExtCsd(cntlr, width);
1091 }
1092
EmmcCheckSwitchStatus(struct MmcCntlr * cntlr)1093 static int32_t EmmcCheckSwitchStatus(struct MmcCntlr *cntlr)
1094 {
1095 int err;
1096 uint32_t status;
1097
1098 err = MmcSendStatus(cntlr, &status);
1099 if (err != HDF_SUCCESS) {
1100 HDF_LOGE("EmmcCheckSwitchStatus: send status cmd fail!");
1101 return err;
1102 }
1103 if ((status & SWITCH_ERROR) > 0) {
1104 return HDF_MMC_ERR_SWITCH_FAIL;
1105 }
1106 return HDF_SUCCESS;
1107 }
1108
EmmcSwitchHighSpeed(struct MmcCntlr * cntlr)1109 static int32_t EmmcSwitchHighSpeed(struct MmcCntlr *cntlr)
1110 {
1111 int err;
1112
1113 /*
1114 * Switch dev to HS mode.
1115 * HS_TIMING must be set to "0x1" before setting BUS_WIDTH for dual data rate operation (values 5 or 6).
1116 */
1117 err = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_HS_TIMING, EMMC_EXT_CSD_BUS_TIMING_HS);
1118 if (err != HDF_SUCCESS) {
1119 HDF_LOGE("EmmcSwitchHighSpeed: switch hs fail!");
1120 return err;
1121 }
1122 /* change host freq to 52M according to JEDEC Standard No.84-B51, Page49. */
1123 MmcCntlrSetClock(cntlr, EMMC_EXT_CSD_HIGH_SPEED_52);
1124 /* Set host controller to HS timing. */
1125 MmcCntlrSetBusTiming(cntlr, BUS_TIMING_MMC_HS);
1126 return HDF_SUCCESS;
1127 }
1128
EmmcSelectHs400(struct MmcCntlr * cntlr)1129 static int32_t EmmcSelectHs400(struct MmcCntlr *cntlr)
1130 {
1131 int err;
1132
1133 err = EmmcSwitchHighSpeed(cntlr);
1134 if (err != HDF_SUCCESS) {
1135 HDF_LOGE("EmmcSelectHs400: switch hs fail!");
1136 return err;
1137 }
1138
1139 /* Switch dev to DDR. */
1140 err = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_BUS_WIDTH, EMMC_EXT_CSD_DDR_BUS_WIDTH_8);
1141 if (err != HDF_SUCCESS) {
1142 HDF_LOGE("EmmcSelectHs400: switch to ddr fail!");
1143 return err;
1144 }
1145 /* Switch dev to HS400. */
1146 err = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_HS_TIMING, EMMC_EXT_CSD_BUS_TIMING_HS400);
1147 if (err != HDF_SUCCESS) {
1148 HDF_LOGE("EmmcSelectHs400: switch to hs400 fail!");
1149 return err;
1150 }
1151 MmcCntlrSetClock(cntlr, EMMC_EXT_CSD_HIGH_SPEED_200);
1152 /* Set host controller to HS400 timing and frequency. */
1153 MmcCntlrSetBusTiming(cntlr, BUS_TIMING_MMC_HS400);
1154 return EmmcCheckSwitchStatus(cntlr);
1155 }
1156
EmmcSelectHs400es(struct MmcCntlr * cntlr,struct EmmcDevice * emmcDev)1157 static int32_t EmmcSelectHs400es(struct MmcCntlr *cntlr, struct EmmcDevice *emmcDev)
1158 {
1159 int err;
1160
1161 err = EmmcSwitchVoltage(cntlr, emmcDev);
1162 if (err != HDF_SUCCESS) {
1163 return err;
1164 }
1165
1166 err = EmmcSelectHighSpeedBusWidth(cntlr);
1167 if (err != HDF_SUCCESS) {
1168 HDF_LOGE("EmmcSelectHs400es: select hs width fail!");
1169 return err;
1170 }
1171
1172 err = EmmcSwitchHighSpeed(cntlr);
1173 if (err != HDF_SUCCESS) {
1174 HDF_LOGE("EmmcSelectHs400es: switch hs fail!");
1175 return err;
1176 }
1177
1178 /* Switch dev to DDR with strobe bit. */
1179 err = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_BUS_WIDTH,
1180 EMMC_EXT_CSD_DDR_BUS_WIDTH_8 | EMMC_EXT_CSD_BUS_WIDTH_STROBE);
1181 if (err != HDF_SUCCESS) {
1182 HDF_LOGE("EmmcSelectHs400es: switch to ddr fail!");
1183 return err;
1184 }
1185 /* Switch dev to HS400. */
1186 err = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_HS_TIMING, EMMC_EXT_CSD_BUS_TIMING_HS400);
1187 if (err != HDF_SUCCESS) {
1188 HDF_LOGE("EmmcSelectHs400es: switch to hs400 fail!");
1189 return err;
1190 }
1191 MmcCntlrSetClock(cntlr, EMMC_EXT_CSD_HIGH_SPEED_200);
1192 /* Set host controller to HS400 timing and frequency. */
1193 MmcCntlrSetBusTiming(cntlr, BUS_TIMING_MMC_HS400);
1194 MmcCntlrSetEnhanceSrobe(cntlr, true);
1195 return EmmcCheckSwitchStatus(cntlr);
1196 }
1197
EmmcSelectHs200(struct MmcCntlr * cntlr,struct EmmcDevice * emmcDev)1198 static int32_t EmmcSelectHs200(struct MmcCntlr *cntlr, struct EmmcDevice *emmcDev)
1199 {
1200 int err;
1201
1202 err = EmmcSwitchVoltage(cntlr, emmcDev);
1203 if (err != HDF_SUCCESS) {
1204 return err;
1205 }
1206
1207 err = EmmcSelectHighSpeedBusWidth(cntlr);
1208 if (err != HDF_SUCCESS) {
1209 HDF_LOGE("EmmcSelectHs200: select hs width fail!");
1210 return err;
1211 }
1212
1213 /* Switch dev to HS200. */
1214 err = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_HS_TIMING, EMMC_EXT_CSD_BUS_TIMING_HS200);
1215 if (err != HDF_SUCCESS) {
1216 HDF_LOGE("EmmcSelectHs200: switch to hs200 fail!");
1217 return err;
1218 }
1219 MmcCntlrSetBusTiming(cntlr, BUS_TIMING_MMC_HS200);
1220 return EmmcCheckSwitchStatus(cntlr);
1221 }
1222
EmmcGetPowerClassValue(struct MmcCntlr * cntlr,struct EmmcExtCsd * extCsd)1223 static uint32_t EmmcGetPowerClassValue(struct MmcCntlr *cntlr, struct EmmcExtCsd *extCsd)
1224 {
1225 uint32_t val = 0;
1226 uint32_t vdd, busWidthBit, clock;
1227
1228 busWidthBit = (cntlr->curDev->workPara.width == BUS_WIDTH8) ?
1229 EMMC_EXT_CSD_BUS_WIDTH_8 : EMMC_EXT_CSD_BUS_WIDTH_4;
1230 vdd = 1 << (cntlr->vddBit);
1231 clock = cntlr->curDev->workPara.clock;
1232
1233 if (vdd == MMC_OCR_1V65_1V95) {
1234 if (clock <= EMMC_EXT_CSD_HIGH_SPEED_26) {
1235 val = extCsd->pwrClF26V195;
1236 } else if (clock <= EMMC_EXT_CSD_HIGH_SPEED_52) {
1237 val = extCsd->pwrClF52V195;
1238 } else if (clock <= EMMC_EXT_CSD_HIGH_SPEED_200) {
1239 val = extCsd->pwrClF200V195;
1240 }
1241 } else if (vdd >= MMC_OCR_2V7_2V8 && vdd <= MMC_OCR_3V5_3V6) {
1242 if (clock <= EMMC_EXT_CSD_HIGH_SPEED_26) {
1243 val = extCsd->pwrClF26V360;
1244 } else if (clock <= EMMC_EXT_CSD_HIGH_SPEED_52) {
1245 val = extCsd->pwrClF52V360;
1246 } else if (clock <= EMMC_EXT_CSD_HIGH_SPEED_200) {
1247 val = extCsd->pwrClF200V360;
1248 }
1249 } else {
1250 return 0;
1251 }
1252
1253 if (busWidthBit == EMMC_EXT_CSD_BUS_WIDTH_8) {
1254 val = (val & EMMC_EXT_CSD_PWR_CL_8BIT_MASK) >> EMMC_EXT_CSD_PWR_CL_8BIT_SHIFT;
1255 } else {
1256 val = (val & EMMC_EXT_CSD_PWR_CL_4BIT_MASK) >> EMMC_EXT_CSD_PWR_CL_4BIT_SHIFT;
1257 }
1258 return val;
1259 }
1260
EmmcSelectPowerClass(struct MmcCntlr * cntlr,struct EmmcExtCsd * extCsd)1261 static int32_t EmmcSelectPowerClass(struct MmcCntlr *cntlr, struct EmmcExtCsd *extCsd)
1262 {
1263 int32_t error = 0;
1264 uint32_t val;
1265
1266 if (cntlr->curDev->reg.csd.specVers < MMC_CSD_SPEC_VER_4) {
1267 return HDF_SUCCESS;
1268 }
1269
1270 val = EmmcGetPowerClassValue(cntlr, extCsd);
1271 if (val > 0) {
1272 error = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_POWER_CLASS, val);
1273 }
1274 return error;
1275 }
1276
EmmcSelectActivateHighSpeed(struct MmcCntlr * cntlr,struct EmmcDevice * emmcDev,struct EmmcExtCsd * extCsd)1277 static int32_t EmmcSelectActivateHighSpeed(struct MmcCntlr *cntlr,
1278 struct EmmcDevice *emmcDev, struct EmmcExtCsd *extCsd)
1279 {
1280 int32_t error;
1281
1282 if (extCsd->hsMaxDtr > 0) {
1283 error = HDF_SUCCESS;
1284 if (MmcCntlrSupportHighSpeed200(cntlr) == true &&
1285 extCsd->hsMaxDtr > EMMC_EXT_CSD_HIGH_SPEED_52) {
1286 error = EmmcSelectHs200(cntlr, emmcDev);
1287 if (error == HDF_SUCCESS) {
1288 emmcDev->mmc.state.bits.hs200 = 1;
1289 }
1290 } else if (cntlr->caps.bits.highSpeed == 1) {
1291 error = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_HS_TIMING,
1292 EMMC_EXT_CSD_BUS_TIMING_HS);
1293 if (error == HDF_SUCCESS) {
1294 emmcDev->mmc.state.bits.highSpeed = 1;
1295 MmcCntlrSetBusTiming(cntlr, BUS_TIMING_MMC_HS);
1296 }
1297 }
1298 if (error != HDF_SUCCESS && error != HDF_MMC_ERR_SWITCH_FAIL) {
1299 return error;
1300 }
1301 }
1302
1303 return HDF_SUCCESS;
1304 }
1305
EmmcSelectBusSpeedMode(struct MmcCntlr * cntlr,struct EmmcDevice * emmcDev,struct EmmcExtCsd * extCsd)1306 static int32_t EmmcSelectBusSpeedMode(struct MmcCntlr *cntlr, struct EmmcDevice *emmcDev, struct EmmcExtCsd *extCsd)
1307 {
1308 int32_t error;
1309
1310 /* HS400ES mode requires 8-bit bus width. */
1311 if (extCsd->strobeSupport > 0 && MmcCntlrSupportHighSpeed400EnhancedStrobe(cntlr) == true) {
1312 error = EmmcSelectHs400es(cntlr, emmcDev);
1313 if (error != HDF_SUCCESS) {
1314 return error;
1315 }
1316 emmcDev->mmc.state.bits.hs400es = 1;
1317 } else {
1318 /* Activate high speed if supported. */
1319 error = EmmcSelectActivateHighSpeed(cntlr, emmcDev, extCsd);
1320 if (error != HDF_SUCCESS) {
1321 return error;
1322 }
1323 /* host set clock. */
1324 if (emmcDev->mmc.state.bits.hs200 == 1 || emmcDev->mmc.state.bits.highSpeed == 1) {
1325 if (extCsd->hsMaxDtr > 0) {
1326 MmcCntlrSetClock(cntlr, extCsd->hsMaxDtr);
1327 }
1328 } else if (emmcDev->mmc.reg.csd.maxDtr > 0) {
1329 MmcCntlrSetClock(cntlr, emmcDev->mmc.reg.csd.maxDtr);
1330 }
1331 }
1332
1333 if (emmcDev->mmc.state.bits.hs400es == 1) {
1334 error = EmmcSelectPowerClass(cntlr, extCsd);
1335 if (error != HDF_SUCCESS) {
1336 HDF_LOGD("EmmcSelectBusSpeedMode: hs400es select power class fail!");
1337 }
1338 } else if (emmcDev->mmc.state.bits.hs200 == 1) {
1339 if ((cntlr->caps2.bits.hs200Sdr1v8 | cntlr->caps2.bits.hs200Sdr1v2) > 0) {
1340 error = MmcCntlrTune(cntlr, SEND_TUNING_BLOCK_HS200);
1341 if (error != HDF_SUCCESS) {
1342 return error;
1343 }
1344 }
1345
1346 if ((extCsd->rawCardType & EMMC_EXT_CSD_CARD_TYPE_HS400) > 0 &&
1347 MmcCntlrSupportHighSpeed400(cntlr) == true) {
1348 error = EmmcSelectHs400(cntlr);
1349 if (error != HDF_SUCCESS) {
1350 return error;
1351 }
1352 emmcDev->mmc.state.bits.hs400 = 1;
1353 emmcDev->mmc.state.bits.hs200 = 0;
1354 }
1355
1356 error = EmmcSelectPowerClass(cntlr, extCsd);
1357 if (error != HDF_SUCCESS) {
1358 HDF_LOGD("EmmcSelectBusSpeedMode: hs200 select power class fail!");
1359 }
1360 }
1361
1362 return HDF_SUCCESS;
1363 }
1364
EmmcGetDdrMode(struct MmcCntlr * cntlr,struct EmmcDevice * emmcDev,struct EmmcExtCsd * extCsd)1365 static uint32_t EmmcGetDdrMode(struct MmcCntlr *cntlr, struct EmmcDevice *emmcDev, struct EmmcExtCsd *extCsd)
1366 {
1367 uint32_t ddrMode = MMC_BUS_MODE_NULL;
1368
1369 /* Indicate DDR mode (if supported). */
1370 if (emmcDev->mmc.state.bits.highSpeed == 1) {
1371 if ((extCsd->cardType & EMMC_EXT_CSD_CARD_TYPE_DDR_1_8V) > 0 &&
1372 (cntlr->caps.bits.ddr1v8 > 0) &&
1373 (cntlr->caps.bits.uhsDdr50 > 0)) {
1374 ddrMode = MMC_1_8V_DDR_MODE;
1375 } else if ((extCsd->cardType & EMMC_EXT_CSD_CARD_TYPE_DDR_1_2V) > 0 && cntlr->caps.bits.ddr1v2 > 0) {
1376 ddrMode = MMC_1_2V_DDR_MODE;
1377 }
1378 }
1379 return ddrMode;
1380 }
1381
EmmcSwitchDdrMode(struct MmcCntlr * cntlr,uint32_t ddrMode,enum MmcBusWidth width,uint32_t widthBit)1382 static int32_t EmmcSwitchDdrMode(struct MmcCntlr *cntlr, uint32_t ddrMode,
1383 enum MmcBusWidth width, uint32_t widthBit)
1384 {
1385 int32_t error;
1386
1387 error = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_BUS_WIDTH, widthBit);
1388 if (error != HDF_SUCCESS) {
1389 HDF_LOGE("EmmcSwitchDdrMode: switch BUS_WIDTH fail!");
1390 return error;
1391 }
1392
1393 if (ddrMode == MMC_1_2V_DDR_MODE) {
1394 error = MmcCntlrSwitchVoltage(cntlr, VOLT_1V2);
1395 if (error != HDF_SUCCESS) {
1396 HDF_LOGE("EmmcSwitchDdrMode: switch 1.2V fail!");
1397 return error;
1398 }
1399 }
1400 cntlr->curDev->state.bits.ddrMode = 1;
1401 MmcCntlrSetBusTiming(cntlr, BUS_TIMING_UHS_DDR50);
1402 MmcCntlrSetBusWidth(cntlr, width);
1403 return HDF_SUCCESS;
1404 }
1405
EmmcSelectSwitchDdrMode(struct MmcCntlr * cntlr,struct EmmcDevice * emmcDev,struct EmmcExtCsd * extCsd)1406 static int32_t EmmcSelectSwitchDdrMode(struct MmcCntlr *cntlr, struct EmmcDevice *emmcDev,
1407 struct EmmcExtCsd *extCsd)
1408 {
1409 int32_t error;
1410 uint32_t index, ddrMode;
1411 enum MmcBusWidth width;
1412 enum MmcBusWidth busWidths[] = { BUS_WIDTH8, BUS_WIDTH4, BUS_WIDTH1 };
1413 uint32_t busWidthBit[][2] = {
1414 { EMMC_EXT_CSD_BUS_WIDTH_8, EMMC_EXT_CSD_DDR_BUS_WIDTH_8 },
1415 { EMMC_EXT_CSD_BUS_WIDTH_4, EMMC_EXT_CSD_DDR_BUS_WIDTH_4 },
1416 { EMMC_EXT_CSD_BUS_WIDTH_1, EMMC_EXT_CSD_BUS_WIDTH_1 },
1417 };
1418
1419 ddrMode = EmmcGetDdrMode(cntlr, emmcDev, extCsd);
1420 if (emmcDev->mmc.state.bits.hs400es == 0 &&
1421 emmcDev->mmc.state.bits.hs400 == 0 &&
1422 emmcDev->mmc.state.bits.hs200 == 0 &&
1423 cntlr->curDev->reg.csd.specVers >= MMC_CSD_SPEC_VER_4 &&
1424 (cntlr->caps.bits.cap4Bit | cntlr->caps.bits.cap8Bit) > 0) {
1425 index = 1;
1426 if (cntlr->caps.bits.cap8Bit > 0) {
1427 index = 0;
1428 }
1429 for (; index < sizeof(busWidthBit) / sizeof(busWidthBit[0]); index++) {
1430 width = busWidths[index];
1431 /* no DDR for 1-bit width. */
1432 if (width == BUS_WIDTH1) {
1433 ddrMode = MMC_BUS_MODE_NULL;
1434 }
1435 error = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_BUS_WIDTH, busWidthBit[index][0]);
1436 if (error != HDF_SUCCESS) {
1437 continue;
1438 }
1439 MmcCntlrSetBusWidth(cntlr, width);
1440 error = EmmcCheckExtCsd(cntlr, width);
1441 if (error == HDF_SUCCESS) {
1442 break;
1443 }
1444 }
1445 /* switch DDR mode. */
1446 if (error == HDF_SUCCESS && ddrMode > MMC_BUS_MODE_NULL) {
1447 error = EmmcSwitchDdrMode(cntlr, ddrMode, width, busWidthBit[index][1]);
1448 }
1449 if (error != HDF_SUCCESS) {
1450 HDF_LOGE("EmmcSelectSwitchDdrMode: switch ddr mode fail!");
1451 return error;
1452 }
1453 }
1454 return HDF_SUCCESS;
1455 }
1456
EmmcActivateHpiMechanism(struct MmcCntlr * cntlr,struct EmmcExtCsd * extCsd)1457 static int32_t EmmcActivateHpiMechanism(struct MmcCntlr *cntlr, struct EmmcExtCsd *extCsd)
1458 {
1459 int32_t error;
1460
1461 if (extCsd->hpi == true) {
1462 error = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_HPI_MGMT, 1);
1463 if (error == HDF_SUCCESS) {
1464 extCsd->hpiEnable = true;
1465 } else if (error != HDF_MMC_ERR_SWITCH_FAIL) {
1466 HDF_LOGE("EmmcActivateHpiMechanism: switch HPI_MGMT fail!");
1467 return error;
1468 }
1469 }
1470 return HDF_SUCCESS;
1471 }
1472
EmmcSwitchOperationMode(struct MmcCntlr * cntlr)1473 static int32_t EmmcSwitchOperationMode(struct MmcCntlr *cntlr)
1474 {
1475 struct EmmcDevice *emmcDev = (struct EmmcDevice *)cntlr->curDev;
1476 struct EmmcExtCsd *extCsd = &(emmcDev->emmcReg.extCsd);
1477 int32_t error;
1478
1479 if (extCsd->enhAreaEnable == true) {
1480 error = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_ERASE_GROUP_DEF, 1);
1481 if (error == HDF_SUCCESS) {
1482 extCsd->eraseGroupDef = 1;
1483 } else if (error != HDF_MMC_ERR_SWITCH_FAIL) {
1484 HDF_LOGE("EmmcSwitchOperationMode: switch ERASE_GROUP_DEF fail!");
1485 return error;
1486 }
1487 }
1488
1489 if ((extCsd->partConfig & EMMC_EXT_CSD_PART_CONFIG_ACCESS_MASK) > 0) {
1490 /* No access to boot partition (default). */
1491 extCsd->partConfig &= ~EMMC_EXT_CSD_PART_CONFIG_ACCESS_MASK;
1492 error = MmcSwitch(cntlr, EMMC_EXT_CSD_CMD_SET_NORMAL, EMMC_EXT_CSD_PARTITION_CONFIG, extCsd->partConfig);
1493 if (error != HDF_SUCCESS && error != HDF_MMC_ERR_SWITCH_FAIL) {
1494 HDF_LOGE("EmmcSwitchOperationMode: switch PARTITION_CONFIG fail!");
1495 return error;
1496 }
1497 }
1498
1499 error = EmmcSelectBusSpeedMode(cntlr, emmcDev, extCsd);
1500 if (error != HDF_SUCCESS) {
1501 HDF_LOGE("EmmcSwitchOperationMode: select bus speed mode fail!");
1502 return error;
1503 }
1504
1505 error = EmmcSelectSwitchDdrMode(cntlr, emmcDev, extCsd);
1506 if (error != HDF_SUCCESS) {
1507 HDF_LOGE("EmmcSwitchOperationMode: select switch ddr mode fail!");
1508 return error;
1509 }
1510 return EmmcActivateHpiMechanism(cntlr, extCsd);
1511 }
1512
EmmcReadExtCsd(struct MmcCntlr * cntlr)1513 static int32_t EmmcReadExtCsd(struct MmcCntlr *cntlr)
1514 {
1515 uint8_t extCsd[EXT_CSD_BYTES_LEN] = {0};
1516 int32_t error;
1517
1518 if (cntlr->curDev->reg.csd.specVers < MMC_CSD_SPEC_VER_4) {
1519 return HDF_SUCCESS;
1520 }
1521
1522 error = MmcSendExtCsd(cntlr, extCsd, EXT_CSD_BYTES_LEN);
1523 if (error != HDF_SUCCESS) {
1524 HDF_LOGE("EmmcReadExtCsd: send cmd8 fail, error = %d.", error);
1525 return error;
1526 }
1527 error = EmmcDecodeExtCsd(cntlr, extCsd, EXT_CSD_BYTES_LEN);
1528 if (error != HDF_SUCCESS) {
1529 HDF_LOGE("EmmcReadExtCsd: decode ext csd fail, error = %d.", error);
1530 return error;
1531 }
1532
1533 return error;
1534 }
1535
EmmcSelect(struct MmcCntlr * cntlr,union MmcOcr ocr)1536 static int32_t EmmcSelect(struct MmcCntlr *cntlr, union MmcOcr ocr)
1537 {
1538 union MmcOcr curOcr;
1539 int32_t error;
1540
1541 MmcGoIdleState(cntlr);
1542 ocr.bits.hcs = 1;
1543 /* set dev work voltage. */
1544 error = MmcSendOpCond(cntlr, ocr.ocrData, &curOcr.ocrData);
1545 if (error != HDF_SUCCESS) {
1546 HDF_LOGE("Emmc cmd1(set voltage) fail, error = %d.", error);
1547 return error;
1548 }
1549
1550 error = MmcAllSendCid(cntlr);
1551 if (error != HDF_SUCCESS) {
1552 HDF_LOGE("Emmc cmd2(get cid) fail, error = %d.", error);
1553 return error;
1554 }
1555
1556 /* card is identified. */
1557 cntlr->curDev->reg.rca = 1;
1558 error = MmcSetRelativeAddr(cntlr);
1559 if (error != HDF_SUCCESS) {
1560 HDF_LOGE("Emmc cmd3(set rca) fail, error = %d.", error);
1561 return error;
1562 }
1563
1564 error = MmcSendCsd(cntlr);
1565 if (error != HDF_SUCCESS) {
1566 HDF_LOGE("Emmc send cmd9(get csd) fail, error = %d.", error);
1567 return error;
1568 }
1569 error = EmmcDecodeCsd(cntlr);
1570 if (error != HDF_SUCCESS) {
1571 HDF_LOGE("Emmc decode csd fail, error = %d.", error);
1572 return error;
1573 }
1574 error = EmmcDecodeCid(cntlr);
1575 if (error != HDF_SUCCESS) {
1576 HDF_LOGE("Emmc decode cid fail, error = %d.", error);
1577 return error;
1578 }
1579 error = MmcSelectCard(cntlr);
1580 if (error != HDF_SUCCESS) {
1581 HDF_LOGE("Emmc send cmd7 fail, error = %d.", error);
1582 return error;
1583 }
1584 error = EmmcReadExtCsd(cntlr);
1585 if (error != HDF_SUCCESS) {
1586 HDF_LOGE("Emmc read ext csd fail, error = %d.", error);
1587 return error;
1588 }
1589
1590 return EmmcSwitchOperationMode(cntlr);
1591 }
1592
EmmcDeviceAdd(struct MmcCntlr * cntlr)1593 static int32_t EmmcDeviceAdd(struct MmcCntlr *cntlr)
1594 {
1595 EmmcSetBlockCapacity(cntlr);
1596 /* add dev. */
1597 if (MmcDeviceAdd(cntlr->curDev) != HDF_SUCCESS) {
1598 HDF_LOGE("EmmcDeviceAdd: Add device fail!");
1599 return HDF_FAILURE;
1600 }
1601 cntlr->curDev->state.bits.present = 1;
1602 return HDF_SUCCESS;
1603 }
1604
EmmcInit(struct MmcCntlr * cntlr)1605 static int32_t EmmcInit(struct MmcCntlr *cntlr)
1606 {
1607 int32_t error;
1608 union MmcOcr ocr = {0};
1609
1610 /* cmd1, detect emmc dev and get the voltage range. */
1611 error = MmcSendOpCond(cntlr, 0, &(ocr.ocrData));
1612 if (error != HDF_SUCCESS) {
1613 HDF_LOGE("cmd1(detect emmc) fail, error = %d.", error);
1614 return error;
1615 }
1616
1617 MmcCntlrSelectWorkVoltage(cntlr, &ocr);
1618 if (cntlr->curDev->reg.ocr.ocrData == 0) {
1619 HDF_LOGE("Emmc select work voltage fail!");
1620 return HDF_ERR_INVALID_PARAM;
1621 }
1622 /* work voltage is low voltage, host should switch. */
1623 if (cntlr->curDev->reg.ocr.bits.vdd1v65To1v95 > 0) {
1624 HDF_LOGD("Emmc switch to 1.8V!");
1625 MmcCntlrSwitchVoltage(cntlr, VOLT_1V8);
1626 }
1627
1628 error = EmmcSelect(cntlr, cntlr->curDev->reg.ocr);
1629 if (error != HDF_SUCCESS) {
1630 return error;
1631 }
1632
1633 return EmmcDeviceAdd(cntlr);
1634 }
1635
EmmcDetect(struct MmcCntlr * cntlr)1636 static int32_t EmmcDetect(struct MmcCntlr *cntlr)
1637 {
1638 int32_t ret;
1639
1640 HDF_LOGD("Detect emmc dev start...");
1641 MmcGoIdleState(cntlr);
1642 ret = EmmcInit(cntlr);
1643 if (ret == HDF_SUCCESS) {
1644 HDF_LOGD("Detect emmc dev success! %s dev at address 0x%x!",
1645 cntlr->curDev->state.bits.uhs ? "Ultra high speed" :
1646 (cntlr->curDev->state.bits.highSpeed ? "High speed" : ""),
1647 cntlr->curDev->reg.rca);
1648 }
1649 return ret;
1650 }
1651
SdSendAppCmd(struct MmcCntlr * cntlr,struct MmcCmd * cmd,struct MmcData * data,uint32_t retryTimes)1652 static int32_t SdSendAppCmd(struct MmcCntlr *cntlr, struct MmcCmd *cmd,
1653 struct MmcData *data, uint32_t retryTimes)
1654 {
1655 uint32_t i;
1656 int32_t err;
1657
1658 if (cntlr == NULL || cmd == NULL || retryTimes == 0) {
1659 return HDF_ERR_INVALID_PARAM;
1660 }
1661
1662 for (i = 0; i <= retryTimes; i++) {
1663 err = MmcAppCmd(cntlr, cmd->cmdCode);
1664 if (err != HDF_SUCCESS) {
1665 continue;
1666 }
1667 err = MmcSendCmd(cntlr, cmd, data, 1);
1668 if (err == HDF_SUCCESS) {
1669 break;
1670 }
1671 }
1672 return err;
1673 }
1674
SdAcmdOpCond(struct MmcCntlr * cntlr,uint32_t arg,uint32_t * ocr)1675 static int32_t SdAcmdOpCond(struct MmcCntlr *cntlr, uint32_t arg, uint32_t *ocr)
1676 {
1677 struct MmcCmd cmd = {0};
1678 int32_t err;
1679 uint32_t i;
1680
1681 cmd.cmdCode = SD_ACMD_OP_COND;
1682 /* [31]reserved bit, [30]HCS, [29]reserved for eSD, [28]XPC, [27:25]reserved bits, [24]S18R, [23:0]VDD voltage. */
1683 cmd.argument = arg;
1684 /* Broadcast Commands with Response(bcr). */
1685 cmd.respType = MMC_RESP_R3 | MMC_CMD_TYPE_BCR;
1686 /*
1687 * The host must poll the card (by repeatedly sending CMD1 or ACMD41) until the 'in-idle-state' bit in
1688 * the card response indicates (by being set to 0) that the card completed its initialization processes
1689 * and is ready for the next command.
1690 */
1691 for (i = 0; i < INIT_CMD_RETRY_TIMES; i++) {
1692 err = SdSendAppCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
1693 if (err != HDF_SUCCESS) {
1694 break;
1695 }
1696 /* if probing, just single pass */
1697 if (arg == 0) {
1698 break;
1699 }
1700 /*
1701 * wait until init complete.
1702 * 0--On Initialization; 1--Initialization Complete.
1703 */
1704 if ((cmd.resp[0] & MMC_CARD_BUSY_STATUS) > 0) {
1705 break;
1706 }
1707 err = HDF_ERR_TIMEOUT;
1708 OsalMDelay(20);
1709 }
1710 if (ocr != NULL) {
1711 *ocr = cmd.resp[0];
1712 }
1713
1714 return err;
1715 }
1716
SdAcmdSdStatus(struct MmcCntlr * cntlr,uint32_t * ssr,uint32_t len)1717 static int32_t SdAcmdSdStatus(struct MmcCntlr *cntlr, uint32_t *ssr, uint32_t len)
1718 {
1719 struct MmcCmd cmd = {0};
1720 struct MmcData data = {0};
1721 int32_t error;
1722 uint32_t i;
1723
1724 if (cntlr == NULL || ssr == NULL || len == 0) {
1725 return HDF_ERR_INVALID_PARAM;
1726 }
1727
1728 cmd.cmdCode = SD_ACMD_SD_STATUS;
1729 /* [31:0] stuff bits. */
1730 cmd.argument = 0;
1731 /* Addressed (point-to-point) Data Transfer Commands (adtc), data transfer on DAT. */
1732 cmd.respType = MMC_RESP_SPI_R2 | MMC_RESP_R1 | MMC_CMD_TYPE_ADTC;
1733 data.blockSize = SSR_BYTES_LEN;
1734 data.blockNum = 1;
1735 data.dataFlags = DATA_READ;
1736 data.dataBuffer = (uint8_t *)ssr;
1737 error = SdSendAppCmd(cntlr, &cmd, &data, 1);
1738 if (error != HDF_SUCCESS) {
1739 return error;
1740 }
1741 for (i = 0; i < len; i++) {
1742 ssr[i] = MmcEndianConversion(ssr[i]);
1743 }
1744 return error;
1745 }
1746
SdAppSendScr(struct MmcCntlr * cntlr,uint32_t * scr,uint32_t len)1747 static int32_t SdAppSendScr(struct MmcCntlr *cntlr, uint32_t *scr, uint32_t len)
1748 {
1749 struct MmcCmd cmd = {0};
1750 struct MmcData data = {0};
1751 int32_t error;
1752 uint32_t i;
1753
1754 if (cntlr == NULL || scr == NULL || len == 0) {
1755 return HDF_ERR_INVALID_PARAM;
1756 }
1757
1758 cmd.cmdCode = SD_ACMD_SEND_SCR;
1759 /* [31:0] stuff bits. */
1760 cmd.argument = 0;
1761 /* Addressed (point-to-point) Data Transfer Commands (adtc), data transfer on DAT. */
1762 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_ADTC;
1763 data.blockSize = SCR_BYTES_LEN;
1764 data.blockNum = 1;
1765 data.dataFlags = DATA_READ;
1766 data.dataBuffer = (uint8_t *)scr;
1767 error = SdSendAppCmd(cntlr, &cmd, &data, 1);
1768 if (error != HDF_SUCCESS) {
1769 return error;
1770 }
1771 for (i = 0; i < len; i++) {
1772 scr[i] = MmcEndianConversion(scr[i]);
1773 }
1774 return error;
1775 }
1776
SdAcmdSetBusWidth(struct MmcCntlr * cntlr,uint32_t width)1777 static int32_t SdAcmdSetBusWidth(struct MmcCntlr *cntlr, uint32_t width)
1778 {
1779 struct MmcCmd cmd = {0};
1780
1781 cmd.cmdCode = SD_ACMD_SET_BUS_WIDTH;
1782 /* [31:2] stuff bits; [1:0]bus width: '00' = 1bit and '10' = 4bits. */
1783 cmd.argument = width;
1784 /* Addressed (point-to-point) Commands(ac), no data transfer on DAT. */
1785 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
1786
1787 return SdSendAppCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
1788 }
1789
SdCmdSendIfCond(struct MmcCntlr * cntlr,uint32_t ocr)1790 static int32_t SdCmdSendIfCond(struct MmcCntlr *cntlr, uint32_t ocr)
1791 {
1792 struct MmcCmd cmd = {0};
1793 int32_t err;
1794 uint32_t vhs;
1795
1796 cmd.cmdCode = SD_CMD_SEND_IF_COND;
1797 /*
1798 * [31:12]reserved bits, [11:8]supply voltage(VHS), [7:0]check pattern.
1799 * VHS = 0001, 2.7-3.6V.
1800 */
1801 vhs = ((ocr & 0xFF8000U) > 0) ? 1 : 0;
1802 cmd.argument = (vhs << 8) | 0xAA;
1803 cmd.respType = MMC_RESP_SPI_R7 | MMC_RESP_R7 | MMC_CMD_TYPE_BCR;
1804
1805 err = MmcSendCmd(cntlr, &cmd, NULL, 1);
1806 if (err != HDF_SUCCESS) {
1807 return err;
1808 }
1809 /*
1810 * Check pattern is used for the host to check validity of communication between the host and the card.
1811 * In the Response, the card echoes back the check pattern set in argument.
1812 * If check pattern is not matched, CMD8 communication is not valid.
1813 */
1814 if ((cmd.resp[0] & 0xFF) != 0xAA) {
1815 return HDF_ERR_IO;
1816 }
1817 return HDF_SUCCESS;
1818 }
1819
SdCmdSendRelativeAddr(struct MmcCntlr * cntlr,uint32_t * rca)1820 static int32_t SdCmdSendRelativeAddr(struct MmcCntlr *cntlr, uint32_t *rca)
1821 {
1822 int32_t error;
1823 struct MmcCmd cmd = {0};
1824
1825 cmd.cmdCode = SD_CMD_SEND_RELATIVE_ADDR;
1826 /* [31:0] stuff bits. */
1827 cmd.argument = 0;
1828 cmd.respType = MMC_RESP_R6 | MMC_CMD_TYPE_BCR;
1829 error = MmcSendCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
1830 if (error != HDF_SUCCESS) {
1831 return error;
1832 }
1833 if (rca != NULL) {
1834 /* New published RCA [31:16] of the card. */
1835 *rca = cmd.resp[0] >> 16;
1836 }
1837 return error;
1838 }
1839
SdCmdSwitchVoltage(struct MmcCntlr * cntlr)1840 static int32_t SdCmdSwitchVoltage(struct MmcCntlr *cntlr)
1841 {
1842 int32_t error;
1843 struct MmcCmd cmd = {0};
1844
1845 /* Voltage switch command to change signaling level 3.3V to 1.8V. */
1846 cmd.cmdCode = SD_CMD_SWITCH_VOLTAGE;
1847 /* [31:0] stuff bits. */
1848 cmd.argument = 0;
1849 cmd.respType = MMC_RESP_R1 | MMC_CMD_TYPE_AC;
1850 error = MmcSendCmd(cntlr, &cmd, NULL, 1);
1851 if (error != HDF_SUCCESS) {
1852 return error;
1853 }
1854 if (cmd.resp[0] & GENERAL_ERROR) {
1855 return HDF_ERR_IO;
1856 }
1857 return HDF_SUCCESS;
1858 }
1859
SdCmdSwitchFunc(struct MmcCntlr * cntlr,struct SdSwitchFuncParam * param,uint8_t * status,uint32_t len)1860 static int32_t SdCmdSwitchFunc(struct MmcCntlr *cntlr, struct SdSwitchFuncParam *param,
1861 uint8_t *status, uint32_t len)
1862 {
1863 struct MmcCmd cmd = {0};
1864 struct MmcData data = {0};
1865
1866 cmd.cmdCode = SD_CMD_SWITCH_FUNC;
1867 /*
1868 * [31]Mode. The switch command can be used in two modes:
1869 * Mode 0 (Check function) is used to query if the card supports a specific function or functions.
1870 * Mode 1 (set function) is used to switch the functionality of the card.
1871 */
1872 cmd.argument = (param->mode << 31) | 0x00FFFFFF;
1873 /*
1874 * [30:24] reserved(All '0'); [23:20] reserved for function group 6(All '0' or 0xF);
1875 * [19:16] reserved for function group 5(All '0' or 0xF); [15:12] function group 4 for Power Limit;
1876 * [11:8] function group 3 for Drive Strength; [7:4] function group 2 for command system;
1877 * [3:0] function group 1 for access mode.
1878 */
1879 cmd.argument &= ~(0xFU << (param->group * 4));
1880 cmd.argument |= (param->value & 0xF) << (param->group * 4);
1881 cmd.respType = MMC_RESP_SPI_R1 | MMC_RESP_R1 | MMC_CMD_TYPE_ADTC;
1882 /*
1883 * As a response to the switch function command, the SD Memory Card will send R1 response on the CMD line,
1884 * and 512 bits of status on the DAT lines.
1885 */
1886 data.blockSize = len;
1887 data.blockNum = 1;
1888 data.dataFlags = DATA_READ;
1889 data.dataBuffer = status;
1890
1891 return MmcSendCmd(cntlr, &cmd, &data, 1);
1892 }
1893
SdDecodeScr(struct MmcCntlr * cntlr)1894 static int32_t SdDecodeScr(struct MmcCntlr *cntlr)
1895 {
1896 struct SdScr *scr = NULL;
1897 uint32_t *rawScr = NULL;
1898 struct SdDevice *sdDev = NULL;
1899 uint32_t scrStruct;
1900
1901 if (cntlr == NULL || cntlr->curDev == NULL) {
1902 return HDF_ERR_INVALID_PARAM;
1903 }
1904
1905 sdDev = (struct SdDevice *)cntlr->curDev;
1906 rawScr = sdDev->reg.rawScr;
1907 scr = &(sdDev->reg.scr);
1908
1909 /*
1910 * SCR_STRUCTURE: [63:60];
1911 * SCR_STRUCTURE equal 0, SCR version 1.0; SCR_STRUCTURE equal 1-15, reserved.
1912 */
1913 scrStruct = (uint8_t)MmcParseBits(rawScr, SCR_BITS, 60, 4);
1914 if (scrStruct != 0) {
1915 HDF_LOGE("SdDecodeScr: scrStruct is invalid!");
1916 return HDF_ERR_INVALID_PARAM;
1917 }
1918 /*
1919 * SD_SPEC: [59:56].
1920 * Describes the SD Memory Card Physical Layer Specification version supported by this card.
1921 * SD_SPEC = 0 , Version 1.0-1.01; SD_SPEC = 1, Version 1.1; SD_SPEC = 2, Version >= 2.0.
1922 */
1923 scr->sdSpec = (uint8_t)MmcParseBits(rawScr, SCR_BITS, 56, 4);
1924 if (scr->sdSpec == SD_SCR_SPEC_2) {
1925 /* SD_SPEC3: [47:47] */
1926 scr->sdSpec3 = (uint8_t)MmcParseBits(rawScr, SCR_BITS, 47, 1);
1927 }
1928 /*
1929 * SD_BUS_WIDTHS: [51:48].
1930 * SD_BUS_WIDTHS equal 0, 1 bit (DAT0); SD_BUS_WIDTHS equal 2, 4 bit (DAT0-3).
1931 */
1932 scr->sdBusWidths = (uint8_t)MmcParseBits(rawScr, SCR_BITS, 48, 4);
1933 /* CMD_SUPPORT: [35:32] */
1934 scr->cmdSupport = (uint8_t)MmcParseBits(rawScr, SCR_BITS, 32, 2);
1935 return HDF_SUCCESS;
1936 }
1937
SdDecodeSSr(struct MmcCntlr * cntlr,uint32_t * rawSsr,uint32_t len)1938 static int32_t SdDecodeSSr(struct MmcCntlr *cntlr, uint32_t *rawSsr, uint32_t len)
1939 {
1940 struct SdSsr *ssr = NULL;
1941 struct SdScr *scr = NULL;
1942 struct SdDevice *sdDev = NULL;
1943 uint32_t eraseSize, eraseTimeout;
1944
1945 if (cntlr == NULL || cntlr->curDev == NULL || rawSsr == NULL || len == 0) {
1946 return HDF_ERR_INVALID_PARAM;
1947 }
1948
1949 sdDev = (struct SdDevice *)cntlr->curDev;
1950 ssr = &(sdDev->reg.ssr);
1951 scr = &(sdDev->reg.scr);
1952 /* SPEED_CLASS: [447:440] */
1953 ssr->speedClass = MmcParseBits(rawSsr, SSR_BITS, 440, 8);
1954 /* AU_SIZE: [431: 428]. */
1955 ssr->auSize = MmcParseBits(rawSsr, SSR_BITS, 428, 4);
1956 if (ssr->auSize > 0) {
1957 if ((ssr->auSize <= MMC_MAX_BLOCKSIZE_SHIFT) || scr->sdSpec3 > 0) {
1958 ssr->auValue = 1 << (ssr->auSize + 4);
1959 /*
1960 * ERASE_SIZE: [423:408]. If this field is set to 0, the erase timeout caculation is not supported.
1961 * ERASE_SIZE = 1, value = 1AU; ERASE_SIZE = 2, value = 2AU...
1962 */
1963 eraseSize = MmcParseBits(rawSsr, SSR_BITS, 408, 16);
1964 /* ERASE_TIMEOUT: [407:402] */
1965 eraseTimeout = MmcParseBits(rawSsr, SSR_BITS, 402, 6);
1966 if (eraseSize > 0) {
1967 ssr->eraseTimeout = (eraseTimeout * 1000) / eraseSize;
1968 /* ERASE_OFFSET: [401:400] */
1969 ssr->eraseOffset = 1000 * MmcParseBits(rawSsr, SSR_BITS, 400, 2);
1970 }
1971 } else {
1972 HDF_LOGD("SD Status: Invalid AU.");
1973 }
1974 }
1975 /* UHS_SPEED_GRADE: [399:396] */
1976 ssr->uhsSpeedGrade = MmcParseBits(rawSsr, SSR_BITS, 396, 4);
1977 return HDF_SUCCESS;
1978 }
1979
SdDecodeCid(struct MmcCntlr * cntlr)1980 static void SdDecodeCid(struct MmcCntlr *cntlr)
1981 {
1982 struct MmcCid *cid = NULL;
1983 uint32_t *rawCid = NULL;
1984 uint32_t i;
1985
1986 if (cntlr == NULL || cntlr->curDev == NULL) {
1987 return;
1988 }
1989
1990 rawCid = cntlr->curDev->reg.rawCid;
1991 cid = &(cntlr->curDev->reg.cid);
1992 /* Manufacturer ID(MID): [127:120] */
1993 cid->mid = MmcParseBits(rawCid, CID_BITS, 120, 8);
1994 /* OEM/Application ID(OID): [119:104] */
1995 cid->oid = MmcParseBits(rawCid, CID_BITS, 104, 16);
1996 /* Product name(PNM): [103:64] */
1997 for (i = 0; i < 5; i++) {
1998 cid->pnm[i] = (char)MmcParseBits(rawCid, CID_BITS, CID_PNM_START_BIT - (i * BITS_PER_BYTE), BITS_PER_BYTE);
1999 }
2000 cid->pnm[5] = '\0';
2001 /*
2002 * Product revision(PRV): [63:56].
2003 * The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each,
2004 * representingan "n.m" revision number.
2005 */
2006 cid->hwPrv = MmcParseBits(rawCid, CID_BITS, 60, 4);
2007 cid->fwPrv = MmcParseBits(rawCid, CID_BITS, 56, 4);
2008 /* Product serial number(PSN): [55:24] */
2009 cid->psn = MmcParseBits(rawCid, CID_BITS, 24, 32);
2010 /*
2011 * Manufacturing date(MDT): [19:8].
2012 * The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y)
2013 * and the other is four bits representing the month(m).
2014 * The "m" field [11:8] is the month code. 1 = January.
2015 * The "y" field [19:12] is the year code. 0 = 2000.
2016 */
2017 cid->year = MmcParseBits(rawCid, CID_BITS, 12, 8) + 2000;
2018 cid->month = MmcParseBits(rawCid, CID_BITS, 8, 4);
2019 }
2020
SdSetBlockCapacity(struct MmcCntlr * cntlr)2021 static void SdSetBlockCapacity(struct MmcCntlr *cntlr)
2022 {
2023 struct SdDevice *sdDev = (struct SdDevice *)cntlr->curDev;
2024 uint32_t gibVal, mibVal;
2025
2026 sdDev->mmc.eraseSize = sdDev->mmc.reg.csd.eraseSize;
2027 sdDev->mmc.capacity = sdDev->mmc.reg.csd.capacity <<
2028 (sdDev->mmc.reg.csd.readBlkLen - MMC_MAX_BLOCKSIZE_SHIFT);
2029
2030 gibVal = sdDev->mmc.capacity >> 21;
2031 mibVal = (sdDev->mmc.capacity & ~(gibVal << 21)) >> 11;
2032 HDF_LOGD("SD dev capacity %d.%d Gib", gibVal, mibVal);
2033 }
2034
SdDecodeCsdRev1Field(struct MmcCntlr * cntlr,struct MmcCsd * csd,uint32_t * rawCsd)2035 static void SdDecodeCsdRev1Field(struct MmcCntlr *cntlr, struct MmcCsd *csd, uint32_t *rawCsd)
2036 {
2037 uint32_t unit, factor;
2038
2039 /* TAAC: [119:112]; TAAC bit position-->Time unit: [2:0], Multiplier factor: [6:3]. */
2040 factor = MmcParseBits(rawCsd, CSD_BITS, 115, 4);
2041 unit = MmcParseBits(rawCsd, CSD_BITS, 112, 3);
2042 csd->taccNs = (g_taccUnit[unit] * g_commFactor[factor] + 9) / 10;
2043 /* NSAC: [111:104], the unit for NSAC is 100 clock cycles */
2044 csd->taccClks = MmcParseBits(rawCsd, CSD_BITS, 104, 8) * 100;
2045
2046 /* TRAN_SPEED: [103:96]; TRAN_SPEED bit-->Frequency unit: [2:0], Multiplier factor: [6:3]. */
2047 factor = MmcParseBits(rawCsd, CSD_BITS, 99, 4);
2048 unit = MmcParseBits(rawCsd, CSD_BITS, 96, 3);
2049 csd->maxDtr = g_tranSpeedUnit[unit] * g_commFactor[factor];
2050 /* card command classes: [95:84] */
2051 csd->ccc = MmcParseBits(rawCsd, CSD_BITS, 84, 12);
2052 /* C_SIZE: [73:62] */
2053 unit = MmcParseBits(rawCsd, CSD_BITS, 62, 12);
2054 /* C_SIZE_MULT: [49:47] */
2055 factor = MmcParseBits(rawCsd, CSD_BITS, 47, 3);
2056 csd->capacity = (1 + unit) << (factor + 2);
2057 /* READ_BL_LEN: [83:80]. */
2058 csd->readBlkLen = MmcParseBits(rawCsd, CSD_BITS, 80, 4);
2059 /* READ_BL_PARTIAL: [79:79] */
2060 csd->rdPartial = MmcParseBits(rawCsd, CSD_BITS, 79, 1);
2061 /* WRITE_BLK_MISALIGN: [78:78] */
2062 csd->wrMisalign = MmcParseBits(rawCsd, CSD_BITS, 78, 1);
2063 /* READ_BLK_MISALIGN: [77:77] */
2064 csd->rdMisalign = MmcParseBits(rawCsd, CSD_BITS, 77, 1);
2065 /* Write speed factor(R2W_FACTOR) :[28:26] */
2066 csd->r2wFactor = MmcParseBits(rawCsd, CSD_BITS, 26, 3);
2067 /* WRITE_BL_LEN: [25:22] */
2068 csd->writeBlkLen = MmcParseBits(rawCsd, CSD_BITS, 22, 4);
2069 /* WRITE_BL_PARTIAL: [21:21] */
2070 csd->wrPartial = MmcParseBits(rawCsd, CSD_BITS, 21, 1);
2071 /*
2072 * erase single block enable(ERASE_BLK_EN): [46:46]
2073 * If ERASE_BLK_EN is '0' erase area is unit of SECTOR_SIZE.
2074 * if ERASE_BLK_EN is '1' erase area is unit of SECTOR_SIZE or unit of WRITE_BL_LEN.
2075 */
2076 if (MmcParseBits(rawCsd, CSD_BITS, 46, 1) == 1) {
2077 csd->eraseSize = 1;
2078 } else if (csd->writeBlkLen >= MMC_MAX_BLOCKSIZE_SHIFT) {
2079 /*
2080 * erase sector size(SECTOR_SIZE): [45:39].
2081 * The actual size is computed by increasing this number by one.
2082 * A value of zero means 1 write block, 127 means 128 write blocks.
2083 */
2084 csd->eraseSize = MmcParseBits(rawCsd, CSD_BITS, 39, 7) + 1;
2085 csd->eraseSize <<= (csd->writeBlkLen - MMC_MAX_BLOCKSIZE_SHIFT);
2086 }
2087 }
2088
SdDecodeCsdRev2Field(struct MmcCntlr * cntlr,struct MmcCsd * csd,uint32_t * rawCsd)2089 static void SdDecodeCsdRev2Field(struct MmcCntlr *cntlr, struct MmcCsd *csd, uint32_t *rawCsd)
2090 {
2091 uint32_t unit, factor;
2092
2093 cntlr->curDev->state.bits.blockAddr = 1;
2094 /* TRAN_SPEED: [103:96]; TRAN_SPEED bit-->Frequency unit: [2:0], Multiplier factor: [6:3]. */
2095 factor = MmcParseBits(rawCsd, CSD_BITS, 99, 4);
2096 unit = MmcParseBits(rawCsd, CSD_BITS, 96, 3);
2097 csd->maxDtr = g_tranSpeedUnit[unit] * g_commFactor[factor];
2098 /* card command classes: [95:84] */
2099 csd->ccc = MmcParseBits(rawCsd, CSD_BITS, 84, 12);
2100 /* device size(C_SIZE): [69:48] */
2101 csd->cSize = MmcParseBits(rawCsd, CSD_BITS, 48, 22);
2102 /* The Minimum value of C_SIZE for SDXC in CSD Version 2.0 is 00FFFFh(65535). */
2103 if (csd->cSize >= 0xFFFF) {
2104 cntlr->curDev->state.bits.sdxc = 1;
2105 }
2106 /* memory capacity = (C_SIZE + 1) * 512KByte */
2107 csd->capacity = (1 + csd->cSize) << 10;
2108
2109 csd->taccNs = 0;
2110 csd->taccClks = 0;
2111 csd->rdPartial = 0;
2112 csd->readBlkLen = MMC_MAX_BLOCKSIZE_SHIFT;
2113 csd->rdMisalign = 0;
2114 csd->wrMisalign = 0;
2115 csd->writeBlkLen = MMC_MAX_BLOCKSIZE_SHIFT;
2116 csd->wrPartial = 0;
2117 csd->r2wFactor = 2;
2118 csd->eraseSize = 1;
2119 }
2120
SdDecodeCsd(struct MmcCntlr * cntlr)2121 static int32_t SdDecodeCsd(struct MmcCntlr *cntlr)
2122 {
2123 struct MmcCsd *csd = NULL;
2124 uint32_t *rawCsd = NULL;
2125
2126 if (cntlr == NULL || cntlr->curDev == NULL) {
2127 return HDF_ERR_INVALID_PARAM;
2128 }
2129
2130 rawCsd = cntlr->curDev->reg.rawCsd;
2131 csd = &(cntlr->curDev->reg.csd);
2132
2133 /* CSD_STRUCTURE: [127:126]. */
2134 csd->structure = MmcParseBits(rawCsd, CSD_BITS, 126, 2);
2135 if (csd->structure == 0) {
2136 /* CSD Version 1.0 */
2137 SdDecodeCsdRev1Field(cntlr, csd, rawCsd);
2138 } else if (csd->structure == 1) {
2139 /* CSD Version 2.0 */
2140 SdDecodeCsdRev2Field(cntlr, csd, rawCsd);
2141 } else {
2142 HDF_LOGE("SdDecodeCsd: not support, structure = %d.", csd->structure);
2143 return HDF_ERR_NOT_SUPPORT;
2144 }
2145
2146 return HDF_SUCCESS;
2147 }
2148
SdGetMaxClock(struct MmcCntlr * cntlr)2149 static uint32_t SdGetMaxClock(struct MmcCntlr *cntlr)
2150 {
2151 uint32_t clock = 0xFFFFFFFF;
2152 struct MmcDevice *mmcDev = cntlr->curDev;
2153 struct SdDevice *sdDev = (struct SdDevice *)mmcDev;
2154
2155 if (mmcDev->state.bits.highSpeed == 1) {
2156 if (sdDev->reg.swCaps.hsMaxDtr > 0) {
2157 clock = sdDev->reg.swCaps.hsMaxDtr;
2158 }
2159 } else if (mmcDev->reg.csd.maxDtr > 0) {
2160 clock = mmcDev->reg.csd.maxDtr;
2161 }
2162
2163 if (clock > cntlr->freqMax) {
2164 clock = cntlr->freqMax;
2165 }
2166
2167 return clock;
2168 }
2169
SdSelect(struct MmcCntlr * cntlr,uint32_t * rocr)2170 static int32_t SdSelect(struct MmcCntlr *cntlr, uint32_t *rocr)
2171 {
2172 int err;
2173 bool try = false;
2174 union MmcOcr ocr = cntlr->curDev->reg.ocr;
2175
2176 do {
2177 /* dev state: ready -> idle. */
2178 MmcGoIdleState(cntlr);
2179 /* dev state: idle -> idle. */
2180 err = SdCmdSendIfCond(cntlr, cntlr->curDev->reg.ocr.ocrData);
2181 if (err == HDF_SUCCESS) {
2182 ocr.bits.hcs = 1;
2183 }
2184 if (cntlr->caps.bits.xpc330 == 1 || cntlr->caps.bits.xpc300 == 1 || cntlr->caps.bits.xpc180 == 1) {
2185 ocr.bits.sdXpc = 1;
2186 }
2187 if (MmcCntlrSupportUhs(cntlr) == true && try == false) {
2188 ocr.bits.s18r = 1;
2189 }
2190 /* dev state: idle -> ready. */
2191 err = SdAcmdOpCond(cntlr, ocr.ocrData, rocr);
2192 if (err != HDF_SUCCESS) {
2193 HDF_LOGE("SdSelect: acmd41 fail, err = %d.", err);
2194 return err;
2195 }
2196
2197 /* host not support sd procotol 3.0 */
2198 if (cntlr->caps.bits.sdSupportProtocol3 == 0) {
2199 break;
2200 }
2201 try = false;
2202 /*
2203 * Send cmd 11 to switch the volt. If host or device do not support,
2204 * we need set 3.3v again.
2205 */
2206 if (rocr != NULL && (*rocr & 0x41000000) == 0x41000000) {
2207 /* switch host and card to 1.8V
2208 * dev state: ready -> ready.
2209 */
2210 err = SdCmdSwitchVoltage(cntlr);
2211 if (err == HDF_SUCCESS) {
2212 err = MmcCntlrSwitchVoltage(cntlr, VOLT_1V8);
2213 }
2214 if (err != HDF_SUCCESS) {
2215 ocr.bits.s18r = 0;
2216 try = true;
2217 }
2218 }
2219 }while (try == true);
2220
2221 /* get cid, dev state: ready -> ident. */
2222 err = MmcAllSendCid(cntlr);
2223 if (err != HDF_SUCCESS) {
2224 HDF_LOGE("SdSelect: cmd2 fail, err = %d.", err);
2225 return err;
2226 }
2227 SdDecodeCid(cntlr);
2228 return err;
2229 }
2230
SdReadCsd(struct MmcCntlr * cntlr)2231 static int32_t SdReadCsd(struct MmcCntlr *cntlr)
2232 {
2233 int32_t error;
2234
2235 error = MmcSendCsd(cntlr);
2236 if (error != HDF_SUCCESS) {
2237 HDF_LOGE("SdReadCsd: cmd9 fail, error = %d.", error);
2238 return error;
2239 }
2240 return SdDecodeCsd(cntlr);
2241 }
2242
SdReadScr(struct MmcCntlr * cntlr)2243 static int32_t SdReadScr(struct MmcCntlr *cntlr)
2244 {
2245 int32_t error;
2246 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
2247
2248 error = SdAppSendScr(cntlr, dev->reg.rawScr, SCR_LEN);
2249 if (error != HDF_SUCCESS) {
2250 HDF_LOGE("SdReadScr: acmd51 fail, error = %d.", error);
2251 return error;
2252 }
2253 return SdDecodeScr(cntlr);
2254 }
2255
SdReadSsr(struct MmcCntlr * cntlr)2256 static int32_t SdReadSsr(struct MmcCntlr *cntlr)
2257 {
2258 int32_t err;
2259 uint32_t rawSsr[SSR_LEN] = {0};
2260
2261 /* don't support ACMD. */
2262 if ((cntlr->curDev->reg.csd.ccc & MMC_CSD_CCC_APP_SPEC) == 0) {
2263 return HDF_SUCCESS;
2264 }
2265
2266 err = SdAcmdSdStatus(cntlr, rawSsr, SSR_LEN);
2267 if (err != HDF_SUCCESS) {
2268 HDF_LOGE("SdReadSsr: acmd13 fail, err = %d.", err);
2269 return err;
2270 }
2271 return SdDecodeSSr(cntlr, rawSsr, SSR_LEN);
2272 }
2273
SdReadSwitchCapbility(struct MmcCntlr * cntlr)2274 static int32_t SdReadSwitchCapbility(struct MmcCntlr *cntlr)
2275 {
2276 int32_t err;
2277 uint8_t status[SD_SWITCH_FUNCTION_STATUS_BYTES_LEN] = {0};
2278 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
2279 struct SdSwitchFuncParam param = {0};
2280
2281 if (dev->reg.scr.sdSpec < SD_SCR_SPEC_1) {
2282 return HDF_SUCCESS;
2283 }
2284 if ((cntlr->curDev->reg.csd.ccc & MMC_CSD_CCC_SWITCH) == 0) {
2285 return HDF_SUCCESS;
2286 }
2287
2288 param.mode = SD_SWITCH_FUNC_MODE_CHECK;
2289 param.group = SD_SWITCH_FUNC_GROUP_1;
2290 param.value = 1;
2291 /* The data(status) is in reverse order relative to the protocol. */
2292 err = SdCmdSwitchFunc(cntlr, ¶m, status, SD_SWITCH_FUNCTION_STATUS_BYTES_LEN);
2293 if (err != HDF_SUCCESS) {
2294 HDF_LOGE("SdReadSwitchCapbility: swutch func group 1 fail, err = %d.", err);
2295 return err;
2296 }
2297 /* [415:400]Function Group 1 information, [407:400]-->status[13]. */
2298 if ((status[13] & SD_BUS_SPEED_MODE_HS) > 0) {
2299 dev->reg.swCaps.hsMaxDtr = SD_HIGH_SPEED_MAX_DTR;
2300 }
2301
2302 if (dev->reg.scr.sdSpec3 == 1) {
2303 dev->reg.swCaps.sdSpec3BusMode.data = status[13];
2304 param.group = SD_SWITCH_FUNC_GROUP_3;
2305 err = SdCmdSwitchFunc(cntlr, ¶m, status, SD_SWITCH_FUNCTION_STATUS_BYTES_LEN);
2306 if (err != HDF_SUCCESS) {
2307 HDF_LOGE("SdReadSwitchCapbility: swutch func group 3 fail!");
2308 return err;
2309 }
2310 /* [447:432]Function Group 3 information, [447:440]-->status[9]. */
2311 dev->reg.swCaps.sdSpec3DrvType = (enum SdDrvType)status[9];
2312 param.group = SD_SWITCH_FUNC_GROUP_4;
2313 err = SdCmdSwitchFunc(cntlr, ¶m, status, SD_SWITCH_FUNCTION_STATUS_BYTES_LEN);
2314 if (err != HDF_SUCCESS) {
2315 HDF_LOGE("SdReadSwitchCapbility: swutch func group 4 fail!");
2316 return err;
2317 }
2318 /* [463:448]Function Group 4 information, [463:456]-->status[7]. */
2319 dev->reg.swCaps.sdSpec3CurrLimit = (enum SdMaxCurrentLimitBit)status[7];
2320 }
2321 return HDF_SUCCESS;
2322 }
2323
SdFillBusSpeedMode(struct MmcCntlr * cntlr)2324 static void SdFillBusSpeedMode(struct MmcCntlr *cntlr)
2325 {
2326 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
2327
2328 if (MmcCntlrSupportUhs(cntlr) == false || dev->reg.scr.sdSpec3 == 0) {
2329 dev->busSpeedMode = SD_BUS_SPEED_MODE_DS;
2330 return;
2331 }
2332
2333 /* select max speed mode supported by host and device. */
2334 if ((cntlr->caps.bits.uhsSdr104 == 1) && (dev->reg.swCaps.sdSpec3BusMode.bits.uhsSdr104 == 1)) {
2335 dev->busSpeedMode = SD_BUS_SPEED_MODE_UHS_SDR104;
2336 } else if ((cntlr->caps.bits.uhsDdr50 == 1) && (dev->reg.swCaps.sdSpec3BusMode.bits.uhsDdr50 == 1)) {
2337 dev->busSpeedMode = SD_BUS_SPEED_MODE_UHS_DDR50;
2338 } else if ((cntlr->caps.bits.uhsSdr104 == 1 || cntlr->caps.bits.uhsSdr50 == 1) &&
2339 (dev->reg.swCaps.sdSpec3BusMode.bits.uhsSdr50 == 1)) {
2340 dev->busSpeedMode = SD_BUS_SPEED_MODE_UHS_SDR50;
2341 } else if ((cntlr->caps.bits.uhsSdr104 == 1 || cntlr->caps.bits.uhsSdr50 == 1 ||
2342 cntlr->caps.bits.uhsSdr25 == 1) && (dev->reg.swCaps.sdSpec3BusMode.bits.uhsSdr25 == 1)) {
2343 dev->busSpeedMode = SD_BUS_SPEED_MODE_UHS_SDR25;
2344 } else if ((cntlr->caps.bits.uhsSdr104 == 1 || cntlr->caps.bits.uhsSdr50 == 1 ||
2345 cntlr->caps.bits.uhsSdr25 == 1 || cntlr->caps.bits.uhsSdr12 == 1) &&
2346 (dev->reg.swCaps.sdSpec3BusMode.bits.uhsSdr12 == 1)) {
2347 dev->busSpeedMode = SD_BUS_SPEED_MODE_UHS_SDR12;
2348 }
2349 }
2350
SdReadRegisters(struct MmcCntlr * cntlr)2351 static int32_t SdReadRegisters(struct MmcCntlr *cntlr)
2352 {
2353 int32_t error;
2354
2355 /* get SCR */
2356 error = SdReadScr(cntlr);
2357 if (error != HDF_SUCCESS) {
2358 return error;
2359 }
2360
2361 /* get SSR */
2362 error = SdReadSsr(cntlr);
2363 if (error != HDF_SUCCESS) {
2364 return error;
2365 }
2366
2367 /* get sw cap */
2368 error = SdReadSwitchCapbility(cntlr);
2369 if (error != HDF_SUCCESS) {
2370 return error;
2371 }
2372
2373 if (MmcCntlrDevReadOnly(cntlr) == true) {
2374 cntlr->curDev->state.bits.readonly = 1;
2375 }
2376 SdFillBusSpeedMode(cntlr);
2377 return HDF_SUCCESS;
2378 }
2379
SdExecuteTuning(struct MmcCntlr * cntlr)2380 static int32_t SdExecuteTuning(struct MmcCntlr *cntlr)
2381 {
2382 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
2383
2384 if (dev->busSpeedMode == SD_BUS_SPEED_MODE_UHS_DDR50) {
2385 return MmcCntlrTune(cntlr, SD_CMD_SWITCH_FUNC);
2386 }
2387 if ((dev->busSpeedMode == SD_BUS_SPEED_MODE_UHS_SDR104) ||
2388 (dev->busSpeedMode == SD_BUS_SPEED_MODE_UHS_SDR50)) {
2389 return MmcCntlrTune(cntlr, SD_CMD_SEND_TUNING_BLOCK);
2390 }
2391 return HDF_SUCCESS;
2392 }
2393
SdGetDevMaxCurrentLimitValue(enum SdMaxCurrentLimitBit devCap)2394 static uint32_t SdGetDevMaxCurrentLimitValue(enum SdMaxCurrentLimitBit devCap)
2395 {
2396 uint32_t currentLimit = 0;
2397
2398 if (devCap == SD_MAX_CURRENT_LIMIT_800) {
2399 currentLimit = SD_MAX_CURRENT_LIMIT_800_VALUE;
2400 } else if (devCap == SD_MAX_CURRENT_LIMIT_600) {
2401 currentLimit = SD_MAX_CURRENT_LIMIT_600_VALUE;
2402 } else if (devCap == SD_MAX_CURRENT_LIMIT_400) {
2403 currentLimit = SD_MAX_CURRENT_LIMIT_400_VALUE;
2404 } else if (devCap == SD_MAX_CURRENT_LIMIT_200) {
2405 currentLimit = SD_MAX_CURRENT_LIMIT_200_VALUE;
2406 }
2407 return currentLimit;
2408 }
2409
SdGetMaxCurrentLimitValue(union MmcCaps * hostCap,enum SdMaxCurrentLimitBit devCap)2410 static uint32_t SdGetMaxCurrentLimitValue(union MmcCaps *hostCap, enum SdMaxCurrentLimitBit devCap)
2411 {
2412 uint32_t currentLimit;
2413
2414 /* get max support by dev. */
2415 currentLimit = SdGetDevMaxCurrentLimitValue(devCap);
2416 if (hostCap->bits.maxCurrentLimit800 == 1) {
2417 currentLimit = ((currentLimit < SD_MAX_CURRENT_LIMIT_800_VALUE) ?
2418 currentLimit : SD_MAX_CURRENT_LIMIT_800_VALUE);
2419 } else if (hostCap->bits.maxCurrentLimit600 == 1) {
2420 currentLimit = ((currentLimit < SD_MAX_CURRENT_LIMIT_600_VALUE) ?
2421 currentLimit : SD_MAX_CURRENT_LIMIT_600_VALUE);
2422 } else if (hostCap->bits.maxCurrentLimit400 == 1) {
2423 currentLimit = ((currentLimit < SD_MAX_CURRENT_LIMIT_400_VALUE) ?
2424 currentLimit : SD_MAX_CURRENT_LIMIT_400_VALUE);
2425 } else if (hostCap->bits.maxCurrentLimit200 == 1) {
2426 currentLimit = ((currentLimit < SD_MAX_CURRENT_LIMIT_200_VALUE) ?
2427 currentLimit : SD_MAX_CURRENT_LIMIT_200_VALUE);
2428 }
2429 return currentLimit;
2430 }
2431
SdSetMaxCurrentLimit(struct MmcCntlr * cntlr)2432 static int32_t SdSetMaxCurrentLimit(struct MmcCntlr *cntlr)
2433 {
2434 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
2435 uint8_t status[SD_SWITCH_FUNCTION_STATUS_BYTES_LEN] = {0};
2436 struct SdSwitchFuncParam param = {0};
2437 uint32_t currentLimit;
2438 int32_t err;
2439
2440 if ((dev->busSpeedMode == SD_BUS_SPEED_MODE_UHS_SDR104) ||
2441 (dev->busSpeedMode == SD_BUS_SPEED_MODE_UHS_DDR50) ||
2442 (dev->busSpeedMode == SD_BUS_SPEED_MODE_UHS_SDR50)) {
2443 currentLimit = SdGetMaxCurrentLimitValue(&(cntlr->caps), dev->reg.swCaps.sdSpec3CurrLimit);
2444 } else {
2445 currentLimit = SD_MAX_CURRENT_LIMIT_200_VALUE;
2446 }
2447
2448 param.mode = SD_SWITCH_FUNC_MODE_SET;
2449 param.group = SD_SWITCH_FUNC_GROUP_4;
2450 param.value = currentLimit;
2451 /* Current Limit is selected by CMD6 Function Group 4. */
2452 err = SdCmdSwitchFunc(cntlr, ¶m, status, SD_SWITCH_FUNCTION_STATUS_BYTES_LEN);
2453 if (err != HDF_SUCCESS) {
2454 HDF_LOGE("SdSetMaxCurrentLimit: swutch func group 3 fail!");
2455 return err;
2456 }
2457 if (((status[15] >> 4) & 0x0F) != currentLimit) {
2458 HDF_LOGD("SdSetMaxCurrentLimit: status not match!");
2459 }
2460
2461 return HDF_SUCCESS;
2462 }
2463
SdSetBusSpeedMode(struct MmcCntlr * cntlr)2464 static int32_t SdSetBusSpeedMode(struct MmcCntlr *cntlr)
2465 {
2466 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
2467 uint8_t status[SD_SWITCH_FUNCTION_STATUS_BYTES_LEN] = {0};
2468 struct SdSwitchFuncParam param = {0};
2469 int32_t err;
2470 enum MmcBusTiming timing;
2471
2472 switch (dev->busSpeedMode) {
2473 case SD_BUS_SPEED_MODE_UHS_SDR104:
2474 timing = BUS_TIMING_UHS_SDR104;
2475 dev->reg.swCaps.uhsMaxDtr = SD_UHS_SDR104_MAX_DTR;
2476 break;
2477 case SD_BUS_SPEED_MODE_UHS_DDR50:
2478 timing = BUS_TIMING_UHS_DDR50;
2479 dev->reg.swCaps.uhsMaxDtr = SD_UHS_DDR50_MAX_DTR;
2480 break;
2481 case SD_BUS_SPEED_MODE_UHS_SDR50:
2482 timing = BUS_TIMING_UHS_SDR50;
2483 dev->reg.swCaps.uhsMaxDtr = SD_UHS_SDR50_MAX_DTR;
2484 break;
2485 case SD_BUS_SPEED_MODE_UHS_SDR25:
2486 timing = BUS_TIMING_UHS_SDR25;
2487 dev->reg.swCaps.uhsMaxDtr = SD_UHS_SDR25_MAX_DTR;
2488 break;
2489 case SD_BUS_SPEED_MODE_UHS_SDR12:
2490 timing = BUS_TIMING_UHS_SDR12;
2491 dev->reg.swCaps.uhsMaxDtr = SD_UHS_SDR12_MAX_DTR;
2492 break;
2493 default:
2494 return HDF_SUCCESS;
2495 }
2496 /* Bus Speed Mode is selected by CMD6 Function Group 1. */
2497 param.mode = SD_SWITCH_FUNC_MODE_SET;
2498 param.group = SD_SWITCH_FUNC_GROUP_1;
2499 param.value = dev->busSpeedMode;
2500 err = SdCmdSwitchFunc(cntlr, ¶m, status, SD_SWITCH_FUNCTION_STATUS_BYTES_LEN);
2501 if (err != HDF_SUCCESS) {
2502 HDF_LOGE("SdSetBusSpeedMode: swutch func group 1 fail!");
2503 return err;
2504 }
2505 if ((status[16] & 0xF) != dev->busSpeedMode) {
2506 HDF_LOGD("SdSetBusSpeedMode: status not match!");
2507 } else {
2508 MmcCntlrSetBusTiming(cntlr, timing);
2509 MmcCntlrSetClock(cntlr, dev->reg.swCaps.uhsMaxDtr);
2510 }
2511
2512 return HDF_SUCCESS;
2513 }
2514
SdSwitch4BitBusWidth(struct MmcCntlr * cntlr,struct SdDevice * dev)2515 static int32_t SdSwitch4BitBusWidth(struct MmcCntlr *cntlr, struct SdDevice *dev)
2516 {
2517 int32_t err = HDF_SUCCESS;
2518
2519 if ((dev->reg.scr.sdBusWidths & SD_SCR_BUS_WIDTHS_4) > 0 &&
2520 (cntlr->caps.bits.cap4Bit > 0)) {
2521 err = SdAcmdSetBusWidth(cntlr, BUS_WIDTH4);
2522 if (err != HDF_SUCCESS) {
2523 HDF_LOGE("SdSwitch4BitBusWidth: set 4-bits bus width fail!");
2524 return err;
2525 }
2526 MmcCntlrSetBusWidth(cntlr, BUS_WIDTH4);
2527 }
2528 return err;
2529 }
2530
SdUltraHighSpeedDevInit(struct MmcCntlr * cntlr)2531 static int32_t SdUltraHighSpeedDevInit(struct MmcCntlr *cntlr)
2532 {
2533 int32_t err;
2534 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
2535
2536 if (dev->reg.scr.sdSpec3 == 0) {
2537 return HDF_SUCCESS;
2538 }
2539 if ((cntlr->curDev->reg.csd.ccc & MMC_CSD_CCC_SWITCH) == 0) {
2540 return HDF_SUCCESS;
2541 }
2542
2543 err = SdSwitch4BitBusWidth(cntlr, dev);
2544 if (err != HDF_SUCCESS) {
2545 return err;
2546 }
2547 err = SdSetMaxCurrentLimit(cntlr);
2548 if (err != HDF_SUCCESS) {
2549 return err;
2550 }
2551 err = SdSetBusSpeedMode(cntlr);
2552 if (err != HDF_SUCCESS) {
2553 return err;
2554 }
2555 return SdExecuteTuning(cntlr);
2556 }
2557
SdSwitchHighSpeed(struct MmcCntlr * cntlr)2558 static int32_t SdSwitchHighSpeed(struct MmcCntlr *cntlr)
2559 {
2560 int32_t err;
2561 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
2562 uint8_t status[SD_SWITCH_FUNCTION_STATUS_BYTES_LEN] = {0};
2563 struct SdSwitchFuncParam param = {0};
2564
2565 if (dev->reg.swCaps.hsMaxDtr == 0) {
2566 return HDF_ERR_NOT_SUPPORT;
2567 }
2568 if (dev->reg.scr.sdSpec < SD_SCR_SPEC_1) {
2569 return HDF_ERR_NOT_SUPPORT;
2570 }
2571 if (cntlr->caps.bits.highSpeed == 0) {
2572 return HDF_ERR_NOT_SUPPORT;
2573 }
2574 if ((cntlr->curDev->reg.csd.ccc & MMC_CSD_CCC_SWITCH) == 0) {
2575 return HDF_ERR_NOT_SUPPORT;
2576 }
2577 /* Bus Speed Mode is selected by CMD6 Function Group 1. */
2578 param.mode = SD_SWITCH_FUNC_MODE_SET;
2579 param.group = SD_SWITCH_FUNC_GROUP_1;
2580 param.value = SD_BUS_SPEED_MODE_HS;
2581 err = SdCmdSwitchFunc(cntlr, ¶m, status, SD_SWITCH_FUNCTION_STATUS_BYTES_LEN);
2582 if (err != HDF_SUCCESS) {
2583 HDF_LOGE("SdSwitchHighSpeed: switch func group 1 fail!");
2584 return err;
2585 }
2586 if ((status[16] & 0xF) != SD_BUS_SPEED_MODE_HS) {
2587 return HDF_ERR_NOT_SUPPORT;
2588 }
2589 return HDF_SUCCESS;
2590 }
2591
SdHighSpeedDevInit(struct MmcCntlr * cntlr)2592 static int32_t SdHighSpeedDevInit(struct MmcCntlr *cntlr)
2593 {
2594 int err;
2595 struct SdDevice *sdDev = (struct SdDevice *)cntlr->curDev;
2596
2597 err = SdSwitchHighSpeed(cntlr);
2598 if (err == HDF_SUCCESS) {
2599 cntlr->curDev->state.bits.highSpeed = 1;
2600 MmcCntlrSetBusTiming(cntlr, BUS_TIMING_SD_HS);
2601 } else if (err != HDF_ERR_NOT_SUPPORT) {
2602 HDF_LOGE("SdHighSpeedDevInit: switch high speed fail!");
2603 return err;
2604 }
2605 MmcCntlrSetClock(cntlr, SdGetMaxClock(cntlr));
2606 return SdSwitch4BitBusWidth(cntlr, sdDev);
2607 }
2608
SdDeviceAdd(struct MmcCntlr * cntlr)2609 static int32_t SdDeviceAdd(struct MmcCntlr *cntlr)
2610 {
2611 /* The SD dev must be removable. */
2612 cntlr->curDev->state.bits.removeable = 1;
2613 SdSetBlockCapacity(cntlr);
2614 /* add dev. */
2615 if (MmcDeviceAdd(cntlr->curDev) != HDF_SUCCESS) {
2616 HDF_LOGE("SdDeviceAdd: add device fail!");
2617 return HDF_FAILURE;
2618 }
2619 cntlr->curDev->state.bits.present = 1;
2620 return HDF_SUCCESS;
2621 }
2622
SdInit(struct MmcCntlr * cntlr)2623 static int32_t SdInit(struct MmcCntlr *cntlr)
2624 {
2625 int32_t error;
2626 union MmcOcr ocr = {0};
2627
2628 /* acmd41, detect sd dev and get the voltage range. dev state: idle -> ready. */
2629 error = SdAcmdOpCond(cntlr, 0, &(ocr.ocrData));
2630 if (error != HDF_SUCCESS) {
2631 HDF_LOGE("acmd41(detect sd) fail, err = %d!", error);
2632 return error;
2633 }
2634
2635 MmcCntlrSelectWorkVoltage(cntlr, &ocr);
2636 if (cntlr->curDev->reg.ocr.ocrData == 0) {
2637 HDF_LOGE("SD work voltage is invalid!");
2638 return HDF_ERR_INVALID_PARAM;
2639 }
2640 error = SdSelect(cntlr, &(ocr.ocrData));
2641 if (error != HDF_SUCCESS) {
2642 return error;
2643 }
2644 /* get RCA. dev state: ident -> stby. */
2645 error = SdCmdSendRelativeAddr(cntlr, &(cntlr->curDev->reg.rca));
2646 if (error != HDF_SUCCESS) {
2647 HDF_LOGE("cmd3(get RCA) fail!, error = %d.", error);
2648 return error;
2649 }
2650 /* get CSD, CMD9 should send in stby. dev state: stby -> stby. */
2651 error = SdReadCsd(cntlr);
2652 if (error != HDF_SUCCESS) {
2653 HDF_LOGE("sd read csd fail!, error = %d.", error);
2654 return error;
2655 }
2656 /* select card. dev state: stby -> tran. */
2657 error = MmcSelectCard(cntlr);
2658 if (error != HDF_SUCCESS) {
2659 HDF_LOGE("cmd7(select card) fail!, error = %d.", error);
2660 return error;
2661 }
2662 /* dev state: tran -> tran. */
2663 error = SdReadRegisters(cntlr);
2664 if (error != HDF_SUCCESS) {
2665 return error;
2666 }
2667
2668 if (ocr.bits.s18r == 1) {
2669 /* uhs dev set */
2670 error = SdUltraHighSpeedDevInit(cntlr);
2671 if (error != HDF_SUCCESS) {
2672 return error;
2673 }
2674 cntlr->curDev->state.bits.uhs = 1;
2675 } else {
2676 /* highspeed dev set */
2677 error = SdHighSpeedDevInit(cntlr);
2678 if (error != HDF_SUCCESS) {
2679 return error;
2680 }
2681 }
2682
2683 return SdDeviceAdd(cntlr);
2684 }
2685
SdDetect(struct MmcCntlr * cntlr)2686 static int32_t SdDetect(struct MmcCntlr *cntlr)
2687 {
2688 int32_t ret;
2689
2690 HDF_LOGD("Detect sd dev start...");
2691 /* dev state: idle. */
2692 MmcGoIdleState(cntlr);
2693 /* dev state: idle -> idle. */
2694 (void)SdCmdSendIfCond(cntlr, cntlr->ocrDef.ocrData);
2695 /* Initialize SD. */
2696 ret = SdInit(cntlr);
2697 if (ret == HDF_SUCCESS) {
2698 HDF_LOGD("Detect sd dev success! %s dev at address 0x%x!",
2699 cntlr->curDev->state.bits.uhs ? "Ultra high speed" :
2700 (cntlr->curDev->state.bits.highSpeed ? "High speed" : ""),
2701 cntlr->curDev->reg.rca);
2702 }
2703 return ret;
2704 }
2705
SdioSendOpCond(struct MmcCntlr * cntlr,uint32_t arg,uint32_t * ocr)2706 static int32_t SdioSendOpCond(struct MmcCntlr *cntlr, uint32_t arg, uint32_t *ocr)
2707 {
2708 struct MmcCmd cmd = {0};
2709 int32_t err;
2710 uint32_t i;
2711
2712 /*
2713 * An SDIO aware host will send CMD5 prior to the CMD55/ACMD41 pair, and thus would receive a valid OCR in
2714 * the R4 response to CMD5 and continue to initialize the card.
2715 */
2716 cmd.cmdCode = SDIO_SEND_OP_COND;
2717 /* [23:0] OCR; [24] S18R(Switching to 1.8V Request); [31:25] Stuff Bits. */
2718 cmd.argument = arg;
2719 cmd.respType = MMC_RESP_R4 | MMC_CMD_TYPE_BCR;
2720 for (i = 0; i < INIT_CMD_RETRY_TIMES; i++) {
2721 err = MmcSendCmd(cntlr, &cmd, NULL, MMC_CMD_DEFAULT_RETRY_TIMES);
2722 if (err != HDF_SUCCESS) {
2723 break;
2724 }
2725 if (arg == 0) {
2726 break;
2727 }
2728 if ((cmd.resp[0] & MMC_CARD_BUSY_STATUS) > 0) {
2729 break;
2730 }
2731
2732 err = HDF_ERR_TIMEOUT;
2733 OsalMDelay(10);
2734 }
2735 if (ocr != NULL) {
2736 /*
2737 * Response R4 in Sd mode: [23:0] OCR; [24] S18A; [26:25] Stuff Bits;
2738 * [27] Memory Present; [30: 28] Number of I/O functions.
2739 */
2740 *ocr = cmd.resp[0];
2741 }
2742
2743 return err;
2744 }
2745
SdioRespR5Check(struct MmcCmd * cmd)2746 static int32_t SdioRespR5Check(struct MmcCmd *cmd)
2747 {
2748 if (cmd->resp[0] & SDIO_R5_ERROR) {
2749 HDF_LOGE("R5: error!");
2750 return HDF_ERR_IO;
2751 }
2752 if (cmd->resp[0] & SDIO_R5_OUT_OF_RANGE) {
2753 HDF_LOGE("R5: out of range error!");
2754 return HDF_ERR_INVALID_PARAM;
2755 }
2756 if (cmd->resp[0] & SDIO_R5_FUNCTION_NUMBER) {
2757 HDF_LOGE("R5: func num error!");
2758 return HDF_ERR_INVALID_PARAM;
2759 }
2760 return HDF_SUCCESS;
2761 }
2762
SdioRwDirect(struct MmcCntlr * cntlr,struct SdioCmdParam * param,uint8_t * out)2763 int32_t SdioRwDirect(struct MmcCntlr *cntlr, struct SdioCmdParam *param, uint8_t *out)
2764 {
2765 struct MmcCmd cmd = {0};
2766 int32_t err;
2767
2768 if (cntlr == NULL || param == NULL) {
2769 return HDF_ERR_INVALID_PARAM;
2770 }
2771
2772 /*
2773 * The IO_RW_DIRECT is the simplest means to access a single register within the total 128K of register space
2774 * in any I/O function, including the common I/O area (CIA). This command reads or writes 1 byte using only 1
2775 * command/response pair. A common use is to initialize registers or monitor status values for I/O functions.
2776 */
2777 cmd.cmdCode = SDIO_RW_DIRECT;
2778 /* [31] R/W flag. */
2779 cmd.argument = ((param->writeflag == true) ? 0x80000000 : 0x00000000);
2780 /* [30:28] Function Number. */
2781 cmd.argument |= (param->funcNum << 28);
2782 /* [25:9] Register Address. */
2783 cmd.argument |= (param->regAddr << 9);
2784 /* [7:0] Write Data or Stuff Bits. */
2785 cmd.argument |= param->writeData;
2786 cmd.respType = MMC_RESP_SPI_R5 | MMC_RESP_R5 | MMC_CMD_TYPE_AC;
2787 err = MmcSendCmd(cntlr, &cmd, NULL, 1);
2788 if (err != HDF_SUCCESS) {
2789 return err;
2790 }
2791
2792 /* resp error check. */
2793 err = SdioRespR5Check(&cmd);
2794 if (err != HDF_SUCCESS) {
2795 return err;
2796 }
2797 if (out != NULL) {
2798 *out = cmd.resp[0] & 0xFF;
2799 }
2800 return HDF_SUCCESS;
2801 }
2802
SdioRwExtended(struct MmcCntlr * cntlr,struct SdioCmdParam * param,uint8_t * buf,uint32_t blockNum,uint32_t blockSize)2803 int32_t SdioRwExtended(struct MmcCntlr *cntlr, struct SdioCmdParam *param,
2804 uint8_t *buf, uint32_t blockNum, uint32_t blockSize)
2805 {
2806 struct MmcCmd cmd = {0};
2807 struct MmcData data = {0};
2808 int32_t err;
2809
2810 if (cntlr == NULL || param == NULL) {
2811 return HDF_ERR_INVALID_PARAM;
2812 }
2813 /* Register Address: Start Address of I/O register to read or write. Range is [1FFFFh:0]. */
2814 if (param->regAddr != ((param->regAddr) & 0x1FFFF)) {
2815 return HDF_ERR_INVALID_PARAM;
2816 }
2817
2818 cmd.cmdCode = SDIO_RW_EXTENDED;
2819 /* [31] R/W flag. */
2820 cmd.argument = ((param->writeflag == true) ? 0x80000000 : 0x00000000);
2821 /* [30:28] Function Number. */
2822 cmd.argument |= (param->funcNum << 28);
2823 /* [26] Op Code. */
2824 cmd.argument |= ((param->incrAddrFlag == true) ? 0x04000000 : 0x00000000);
2825 /* [25:9] Register Address. */
2826 cmd.argument |= (param->regAddr << 9);
2827 /*
2828 * [8:0] Byte/Block Count.
2829 * If the command is operating on bytes(Block Mode = 0), this field contains the number of bytes
2830 * to read or write. A value of 0 shall cause 512 bytes to be read or written.
2831 * If the command is in block mode(Block Mode = 1), the Block Count field specifies the number
2832 * of Data Blocks to be transferred following this command.
2833 */
2834 if (blockNum == 1 && blockSize <= 512) {
2835 cmd.argument |= ((blockSize == 512) ? 0 : blockSize); /* byte mode */
2836 } else {
2837 /* [27] Block Mode. */
2838 cmd.argument |= (0x08000000 | blockNum);
2839 }
2840 cmd.respType = MMC_RESP_SPI_R5 | MMC_RESP_R5 | MMC_CMD_TYPE_ADTC;
2841
2842 data.blockSize = blockSize;
2843 data.blockNum = blockNum;
2844 data.dataFlags = ((param->writeflag == true) ? DATA_WRITE : DATA_READ);
2845 if (param->scatterFlag == false) {
2846 data.dataBuffer = buf;
2847 } else {
2848 data.scatter = (void *)buf;
2849 data.scatterLen = param->scatterLen;
2850 }
2851
2852 err = MmcSendCmd(cntlr, &cmd, &data, 1);
2853 if (err != HDF_SUCCESS) {
2854 return err;
2855 }
2856
2857 /* resp error check. */
2858 return SdioRespR5Check(&cmd);
2859 }
2860
SdioIoReset(struct MmcCntlr * cntlr)2861 static void SdioIoReset(struct MmcCntlr *cntlr)
2862 {
2863 struct SdioCmdParam param = {0};
2864 uint8_t out = 0;
2865 int32_t error;
2866
2867 /*
2868 * In order to reset an I/O only card or the I/O portion of a combo card,
2869 * use CMD52 to write a 1 to the RES bit in the CCCR(bit3 of register 6),
2870 * because it can't issue CMD52 after CMD0.
2871 */
2872 param.regAddr = IO_ABORT;
2873 /* read register 6 of CCCR. */
2874 error = SdioRwDirect(cntlr, ¶m, &out);
2875 if (error < 0) {
2876 out = SDIO_CCCR_RES;
2877 } else {
2878 out |= SDIO_CCCR_RES;
2879 }
2880 /* write the RES bit to 1. */
2881 param.writeflag = true;
2882 param.writeData = out;
2883 (void)SdioRwDirect(cntlr, ¶m, NULL);
2884 }
2885
SdioReadWriteByte(struct MmcCntlr * cntlr,bool writeFlag,uint32_t funcNum,uint32_t addr,uint8_t * data)2886 int32_t SdioReadWriteByte(struct MmcCntlr *cntlr, bool writeFlag,
2887 uint32_t funcNum, uint32_t addr, uint8_t *data)
2888 {
2889 struct SdioCmdParam param = {0};
2890
2891 if (cntlr == NULL || data == NULL) {
2892 return HDF_ERR_INVALID_PARAM;
2893 }
2894
2895 param.regAddr = addr;
2896 param.funcNum = funcNum;
2897 if (writeFlag == true) {
2898 param.writeflag = true;
2899 param.writeData = *data;
2900 return SdioRwDirect(cntlr, ¶m, NULL);
2901 }
2902 return SdioRwDirect(cntlr, ¶m, data);
2903 }
2904
SdioReadWriteRemainBytes(struct MmcCntlr * cntlr,struct SdioCmdParam * param,uint8_t * data,uint32_t size,uint32_t addr)2905 static int32_t SdioReadWriteRemainBytes(struct MmcCntlr *cntlr, struct SdioCmdParam *param,
2906 uint8_t *data, uint32_t size, uint32_t addr)
2907 {
2908 uint32_t maxBlkSize, curSize;
2909 struct SdioDevice *dev = (struct SdioDevice *)cntlr->curDev;
2910 uint32_t remLen = size;
2911 uint32_t curAddr = addr;
2912 uint8_t *buffer = data;
2913 int32_t err;
2914
2915 maxBlkSize = MMC_MIN(cntlr->maxBlkSize, dev->curFunction->maxBlkSize);
2916 maxBlkSize = MMC_MIN(maxBlkSize, BYTES_PER_BLOCK);
2917 if (maxBlkSize == 0) {
2918 HDF_LOGE("max block size is invalid!");
2919 return HDF_ERR_INVALID_PARAM;
2920 }
2921
2922 while (remLen > 0) {
2923 curSize = MMC_MIN(remLen, maxBlkSize);
2924 param->regAddr = curAddr;
2925 err = SdioRwExtended(cntlr, param, buffer, 1, curSize);
2926 if (err != HDF_SUCCESS) {
2927 HDF_LOGD("SdioReadWriteBlock: bytes mode, err = %d, addr = %d, curSize = %d!", err, addr, curSize);
2928 return err;
2929 }
2930 buffer += curSize;
2931 if (param->incrAddrFlag == true) {
2932 curAddr += curSize;
2933 }
2934 remLen -= curSize;
2935 }
2936 return HDF_SUCCESS;
2937 }
2938
SdioFillRwExtendedCmdParam(struct SdioCmdParam * param,struct SdioDevice * dev,struct SdioRwBlockInfo * info)2939 static void SdioFillRwExtendedCmdParam(struct SdioCmdParam *param,
2940 struct SdioDevice *dev, struct SdioRwBlockInfo *info)
2941 {
2942 param->funcNum = dev->curFunction->funcNum;
2943 param->incrAddrFlag = info->incrAddrFlag;
2944 param->writeflag = info->writeFlag;
2945 if (info->scatterFlag == true) {
2946 param->scatterFlag = true;
2947 param->scatterLen = info->scatterLen;
2948 param->regAddr = info->addr;
2949 }
2950 }
2951
SdioReadWriteBlock(struct MmcCntlr * cntlr,struct SdioRwBlockInfo * info)2952 int32_t SdioReadWriteBlock(struct MmcCntlr *cntlr, struct SdioRwBlockInfo *info)
2953 {
2954 uint32_t maxBlkNum, maxBlkSize, curblkNum, curSize, curAddr, remLen;
2955 int32_t err;
2956 struct SdioCmdParam param = {0};
2957 struct SdioDevice *dev = NULL;
2958 uint8_t *buffer = NULL;
2959
2960 if (cntlr == NULL || info == NULL) {
2961 return HDF_ERR_INVALID_PARAM;
2962 }
2963 dev = (struct SdioDevice *)cntlr->curDev;
2964 if (dev == NULL || dev->curFunction == NULL) {
2965 return HDF_ERR_INVALID_OBJECT;
2966 }
2967
2968 maxBlkSize = MMC_MIN(cntlr->maxBlkSize, dev->curFunction->maxBlkSize);
2969 maxBlkSize = MMC_MIN(maxBlkSize, BYTES_PER_BLOCK);
2970 if (maxBlkSize == 0) {
2971 return HDF_ERR_INVALID_PARAM;
2972 }
2973 if (dev->curFunction->curBlkSize == 0 || cntlr->maxBlkNum == 0) {
2974 return HDF_ERR_INVALID_PARAM;
2975 }
2976
2977 remLen = info->size;
2978 curAddr = info->addr;
2979 buffer = info->buf;
2980 SdioFillRwExtendedCmdParam(¶m, dev, info);
2981 if (info->scatterFlag == true) {
2982 return SdioRwExtended(cntlr, ¶m, buffer, MMC_MAX(1, remLen / maxBlkSize), MMC_MIN(remLen, maxBlkSize));
2983 }
2984 /* send block. */
2985 if (dev->sdioReg.cccr.multiBlock > 0 && (remLen > maxBlkSize)) {
2986 maxBlkNum = MMC_MIN((cntlr->maxReqSize / dev->curFunction->curBlkSize), cntlr->maxBlkNum);
2987 maxBlkNum = MMC_MIN(maxBlkNum, SDIO_BLOCK_TRANSFER_MAX_BLKNUM);
2988 while (remLen > dev->curFunction->curBlkSize) {
2989 curblkNum = remLen / dev->curFunction->curBlkSize;
2990 curblkNum = MMC_MIN(curblkNum, maxBlkNum);
2991 curSize = curblkNum * dev->curFunction->curBlkSize;
2992 param.regAddr = curAddr;
2993 err = SdioRwExtended(cntlr, ¶m, buffer, curblkNum, dev->curFunction->curBlkSize);
2994 if (err != HDF_SUCCESS) {
2995 return err;
2996 }
2997 buffer += curSize;
2998 if (info->incrAddrFlag == true) {
2999 curAddr += curSize;
3000 }
3001 remLen -= curSize;
3002 }
3003 }
3004
3005 /* send remaind bytes. */
3006 return SdioReadWriteRemainBytes(cntlr, ¶m, buffer, remLen, curAddr);
3007 }
3008
SdioCdDisable(struct MmcCntlr * cntlr)3009 static int32_t SdioCdDisable(struct MmcCntlr *cntlr)
3010 {
3011 struct SdioCmdParam param = {0};
3012 int32_t error;
3013 uint8_t ctrl;
3014
3015 param.regAddr = BUS_INTERFACE_CONTROL;
3016 /* read register 7 of CCCR. */
3017 error = SdioRwDirect(cntlr, ¶m, &ctrl);
3018 if (error != HDF_SUCCESS) {
3019 HDF_LOGE("SdioCdDisable: read BIC fail!");
3020 return error;
3021 }
3022 /*
3023 * write the CD Disable bit to 1.
3024 * This bit shall be set to 1 before issuing CMD53.
3025 */
3026 ctrl |= SDIO_CCCR_CD_DISABLE;
3027 param.writeflag = true;
3028 param.writeData = ctrl;
3029 return SdioRwDirect(cntlr, ¶m, NULL);
3030 }
3031
SdioReadCccrSdioRev(struct MmcCntlr * cntlr,struct SdioCccr * cccr,uint8_t * cccrRev)3032 static int32_t SdioReadCccrSdioRev(struct MmcCntlr *cntlr, struct SdioCccr *cccr, uint8_t *cccrRev)
3033 {
3034 struct SdioCmdParam param = {0};
3035 int32_t err;
3036 uint8_t data;
3037
3038 /* read register 0 of CCCR. */
3039 param.regAddr = CCCR_SDIO_REVISION;
3040 err = SdioRwDirect(cntlr, ¶m, &data);
3041 if (err != HDF_SUCCESS) {
3042 HDF_LOGE("SdioReadCccrSdioRev: read sdio rev fail!");
3043 return err;
3044 }
3045 /* bit3-bit0: CCCR_REVISION */
3046 *cccrRev = data & 0x0f;
3047 if ((*cccrRev) > SDIO_CCCR_VERSION_3_00) {
3048 HDF_LOGE("SdioReadCccrSdioRev: cccr rev error!");
3049 return HDF_FAILURE;
3050 }
3051 /* bit7-bit4: SDIO_REVISION */
3052 cccr->sdioRev = (data & 0xf0) >> 4;
3053 return HDF_SUCCESS;
3054 }
3055
SdioReadCccrCapbility(struct MmcCntlr * cntlr,struct SdioCccr * cccr)3056 static int32_t SdioReadCccrCapbility(struct MmcCntlr *cntlr, struct SdioCccr *cccr)
3057 {
3058 struct SdioCmdParam param = {0};
3059 int32_t error;
3060 uint8_t cap;
3061
3062 /* read register 8 of CCCR. */
3063 param.regAddr = CARD_CAPBILITY;
3064 error = SdioRwDirect(cntlr, ¶m, &cap);
3065 if (error != HDF_SUCCESS) {
3066 HDF_LOGE("SdioReadCccrCapbility: read card cap fail!");
3067 return error;
3068 }
3069
3070 if ((cap & SDIO_CCCR_CAP_4BLS) > 0) {
3071 cccr->lowSpeed4Bit = 1;
3072 }
3073 if ((cap & SDIO_CCCR_CAP_LSC) > 0) {
3074 cccr->lowSpeed = 1;
3075 }
3076 if ((cap & SDIO_CCCR_CAP_SMB) > 0) {
3077 cccr->multiBlock = 1;
3078 }
3079 return HDF_SUCCESS;
3080 }
3081
SdioReadCccrPowerControl(struct MmcCntlr * cntlr,struct SdioCccr * cccr)3082 static int32_t SdioReadCccrPowerControl(struct MmcCntlr *cntlr, struct SdioCccr *cccr)
3083 {
3084 struct SdioCmdParam param = {0};
3085 int32_t error;
3086 uint8_t ctrl;
3087
3088 /* read register 18 of CCCR. */
3089 param.regAddr = POWER_CONTROL;
3090 error = SdioRwDirect(cntlr, ¶m, &ctrl);
3091 if (error != HDF_SUCCESS) {
3092 HDF_LOGE("SdioReadCccrPowerControl: read power control fail!");
3093 return error;
3094 }
3095
3096 if ((ctrl & SDIO_CCCR_POWER_SMPC) > 0) {
3097 cccr->highPower = 1;
3098 }
3099 return HDF_SUCCESS;
3100 }
3101
SdioReadCccrBusSpeed(struct MmcCntlr * cntlr,struct SdioCccr * cccr)3102 static int32_t SdioReadCccrBusSpeed(struct MmcCntlr *cntlr, struct SdioCccr *cccr)
3103 {
3104 struct SdioCmdParam param = {0};
3105 int32_t error;
3106 uint8_t speed;
3107
3108 /* read register 19 of CCCR. */
3109 param.regAddr = BUS_SPEED_SELECT;
3110 error = SdioRwDirect(cntlr, ¶m, &speed);
3111 if (error != HDF_SUCCESS) {
3112 HDF_LOGE("SdioReadCccrBusSpeed: read bus speed select fail!");
3113 return error;
3114 }
3115
3116 if ((speed & SDIO_CCCR_BUS_SPEED_SHS) > 0) {
3117 cccr->highSpeed = 1;
3118 }
3119 return HDF_SUCCESS;
3120 }
3121
SdioReadCccrIoEnable(struct MmcCntlr * cntlr,uint8_t * val)3122 int32_t SdioReadCccrIoEnable(struct MmcCntlr *cntlr, uint8_t *val)
3123 {
3124 struct SdioCmdParam param = {0};
3125
3126 if (cntlr == NULL || val == NULL) {
3127 return HDF_ERR_INVALID_PARAM;
3128 }
3129
3130 /* read register 2(IOEx) of CCCR. */
3131 param.regAddr = IO_ENABLE;
3132 return SdioRwDirect(cntlr, ¶m, val);
3133 }
3134
SdioCccrIoEnable(struct MmcCntlr * cntlr)3135 int32_t SdioCccrIoEnable(struct MmcCntlr *cntlr)
3136 {
3137 struct SdioCmdParam param = {0};
3138 struct SdioDevice *dev = NULL;
3139 int32_t err;
3140 uint8_t data;
3141
3142 if (cntlr == NULL) {
3143 return HDF_ERR_INVALID_OBJECT;
3144 }
3145 dev = (struct SdioDevice *)cntlr->curDev;
3146 if (dev == NULL || dev->curFunction == NULL) {
3147 return HDF_ERR_INVALID_OBJECT;
3148 }
3149
3150 /* read register 2(IOEx) of CCCR. */
3151 param.regAddr = IO_ENABLE;
3152 err = SdioRwDirect(cntlr, ¶m, &data);
3153 if (err != HDF_SUCCESS) {
3154 HDF_LOGE("SdioCccrIoEnable: read io enable fail! err = %d.", err);
3155 return err;
3156 }
3157 /*
3158 * IOEx:Enable Function x.
3159 * If this bit is reset to 0, the function is disable. If this bit is set to 1, the function is enabled to start
3160 * its initialization. The complation of initialization is indicated in IORx. On power up or after a reset, the
3161 * card shall reset this bit to 0. The host can also use IOEx as a per function reset for error recovery. The host
3162 * sequence for a per function reset is to reset IOEx to 0, wait until IORx becomes 0 and then set IOEx to 1 again.
3163 */
3164 data |= (1 << dev->curFunction->funcNum);
3165 param.writeflag = true;
3166 param.writeData = data;
3167 /* write register 2(IOEx) of CCCR. */
3168 return SdioRwDirect(cntlr, ¶m, NULL);
3169 }
3170
SdioCccrIoDisable(struct MmcCntlr * cntlr)3171 int32_t SdioCccrIoDisable(struct MmcCntlr *cntlr)
3172 {
3173 struct SdioCmdParam param = {0};
3174 struct SdioDevice *dev = NULL;
3175 int32_t err;
3176 uint8_t data;
3177
3178 if (cntlr == NULL) {
3179 return HDF_ERR_INVALID_OBJECT;
3180 }
3181 dev = (struct SdioDevice *)cntlr->curDev;
3182 if (dev == NULL || dev->curFunction == NULL) {
3183 return HDF_ERR_INVALID_OBJECT;
3184 }
3185
3186 /* read register 2(IOEx) of CCCR. */
3187 param.regAddr = IO_ENABLE;
3188 err = SdioRwDirect(cntlr, ¶m, &data);
3189 if (err != HDF_SUCCESS) {
3190 HDF_LOGE("SdioCccrIoDisable: read io enable fail! err = %d.", err);
3191 return err;
3192 }
3193
3194 data &= (~(1 << dev->curFunction->funcNum));
3195 param.writeflag = true;
3196 param.writeData = data;
3197 /* write register 2(IOEx) of CCCR. */
3198 return SdioRwDirect(cntlr, ¶m, NULL);
3199 }
3200
SdioReadCccrIoReady(struct MmcCntlr * cntlr,uint8_t * val)3201 int32_t SdioReadCccrIoReady(struct MmcCntlr *cntlr, uint8_t *val)
3202 {
3203 struct SdioCmdParam param = {0};
3204
3205 if (cntlr == NULL || val == NULL) {
3206 return HDF_ERR_INVALID_PARAM;
3207 }
3208
3209 /* read register 3(IORx) of CCCR. */
3210 param.regAddr = IO_READY;
3211 /*
3212 * IORx: I/O Function x Ready.
3213 * If this bit is set to 0, the function is not ready to operate. This may be caused by the function being
3214 * disabled or not ready due to internal causes such as a built-in-self-test in progress. If this bit is set to 1,
3215 * the function is ready to operate. On power up or after a reset, this bit shall be set to 0.
3216 */
3217 return SdioRwDirect(cntlr, ¶m, val);
3218 }
3219
SdioReadCccrIntPending(struct MmcCntlr * cntlr,uint8_t * val)3220 int32_t SdioReadCccrIntPending(struct MmcCntlr *cntlr, uint8_t *val)
3221 {
3222 struct SdioCmdParam param = {0};
3223
3224 if (cntlr == NULL || val == NULL) {
3225 return HDF_ERR_INVALID_PARAM;
3226 }
3227
3228 /* read register 5(INTx) of CCCR. */
3229 param.regAddr = INT_PENDING;
3230 /*
3231 * INTx: Interrupt Pending for Function x.
3232 * If this bit is cleared to 0, this indicates that no Interrupts are pending from this function.
3233 * If this bit is set to 1, then this function has Interrupt pending.
3234 * Note that if the IENx or IENM bits are not set, the host cannot receive this pending Interrupt.
3235 */
3236 return SdioRwDirect(cntlr, ¶m, val);
3237 }
3238
SdioCccrIntEnable(struct MmcCntlr * cntlr)3239 int32_t SdioCccrIntEnable(struct MmcCntlr *cntlr)
3240 {
3241 int32_t err;
3242 uint8_t val;
3243 struct SdioCmdParam param = {0};
3244 struct SdioDevice *dev = NULL;
3245
3246 if (cntlr == NULL) {
3247 return HDF_ERR_INVALID_OBJECT;
3248 }
3249 dev = (struct SdioDevice *)cntlr->curDev;
3250 if (dev == NULL || dev->curFunction == NULL) {
3251 return HDF_ERR_INVALID_OBJECT;
3252 }
3253
3254 /* read register 4 of CCCR. */
3255 param.regAddr = INT_ENABLE;
3256 err = SdioRwDirect(cntlr, ¶m, &val);
3257 if (err != HDF_SUCCESS) {
3258 HDF_LOGE("SdioCccrIntEnable: read int enable fail! err = %d.", err);
3259 return err;
3260 }
3261 /*
3262 * [0]IENM: Interrupt Enable Master.
3263 * If this bit is cleared to 0, no interrupts from this card shall be sent to the host.
3264 * If this bit is set to 1, then any function's interrupt shall be sent to the host.
3265 */
3266 val |= 1;
3267 /*
3268 * [1-7]IENx:Interrupt Enable for Function x.
3269 * If this bit is cleared to 0, any interrupt form this function shall not be sent to the host.
3270 * If this bit is set to 1, function's interrupt shall be sent to the host if the IENM is also set to 1.
3271 */
3272 val |= (1 << dev->curFunction->funcNum);
3273 param.writeflag = true;
3274 param.writeData = val;
3275 /* write register 4 of CCCR. */
3276 return SdioRwDirect(cntlr, ¶m, NULL);
3277 }
3278
SdioCccrIntDisable(struct MmcCntlr * cntlr)3279 int32_t SdioCccrIntDisable(struct MmcCntlr *cntlr)
3280 {
3281 struct SdioDevice *dev = (struct SdioDevice *)cntlr->curDev;
3282 struct SdioCmdParam param = {0};
3283 int32_t err;
3284 uint8_t val;
3285
3286 if (dev == NULL || dev->curFunction == NULL) {
3287 return HDF_ERR_INVALID_OBJECT;
3288 }
3289
3290 /* read register 4 of CCCR. */
3291 param.regAddr = INT_ENABLE;
3292 err = SdioRwDirect(cntlr, ¶m, &val);
3293 if (err != HDF_SUCCESS) {
3294 HDF_LOGE("SdioCccrIntDisable: read int enable fail! err = %d.", err);
3295 return err;
3296 }
3297 /* clear the function's interrupt. */
3298 val &= (~(1U << dev->curFunction->funcNum));
3299 if ((val & 0xFE) == 0) {
3300 val = 0;
3301 }
3302 param.writeflag = true;
3303 param.writeData = val;
3304 /* write register 4 of CCCR. */
3305 return SdioRwDirect(cntlr, ¶m, NULL);
3306 }
3307
SdioReadCccr(struct MmcCntlr * cntlr)3308 static int32_t SdioReadCccr(struct MmcCntlr *cntlr)
3309 {
3310 int32_t ret;
3311 uint8_t cccrRev;
3312 struct SdioDevice *sdioDev = NULL;
3313 struct SdioCccr *cccr = NULL;
3314
3315 if (cntlr == NULL || cntlr->curDev == NULL) {
3316 return HDF_ERR_INVALID_PARAM;
3317 }
3318
3319 sdioDev = (struct SdioDevice *)cntlr->curDev;
3320 cccr = &(sdioDev->sdioReg.cccr);
3321 ret = SdioReadCccrSdioRev(cntlr, cccr, &cccrRev);
3322 if (ret != HDF_SUCCESS) {
3323 return ret;
3324 }
3325 ret = SdioReadCccrCapbility(cntlr, cccr);
3326 if (ret != HDF_SUCCESS) {
3327 return ret;
3328 }
3329
3330 if (cccrRev >= SDIO_CCCR_VERSION_1_10) {
3331 ret = SdioReadCccrPowerControl(cntlr, cccr);
3332 if (ret != HDF_SUCCESS) {
3333 return ret;
3334 }
3335 }
3336 /* SDIO version 1.20 cards indicate their support for High-Speed mode with the SHS bit in the CCCR. */
3337 if (cccrRev >= SDIO_CCCR_VERSION_1_20) {
3338 ret = SdioReadCccrBusSpeed(cntlr, cccr);
3339 }
3340 return ret;
3341 }
3342
SdioBusSpeedSelect(struct MmcCntlr * cntlr,bool enableHighSpeed)3343 static int32_t SdioBusSpeedSelect(struct MmcCntlr *cntlr, bool enableHighSpeed)
3344 {
3345 struct SdioCmdParam param = {0};
3346 int32_t error;
3347 uint8_t speed;
3348
3349 /* read register 19 of CCCR. */
3350 param.regAddr = BUS_SPEED_SELECT;
3351 error = SdioRwDirect(cntlr, ¶m, &speed);
3352 if (error != HDF_SUCCESS) {
3353 HDF_LOGE("SdioBusSpeedSelect: read bus speed select fail! err = %d.", error);
3354 return error;
3355 }
3356 /* fill BSS0. */
3357 if (enableHighSpeed == true) {
3358 speed |= SDIO_CCCR_BUS_SPEED_EHS;
3359 } else {
3360 speed &= (~SDIO_CCCR_BUS_SPEED_EHS);
3361 }
3362 /* write BSS0. */
3363 param.writeflag = true;
3364 param.writeData = speed;
3365 return SdioRwDirect(cntlr, ¶m, NULL);
3366 }
3367
SdioSwitchHighSpeed(struct MmcCntlr * cntlr)3368 static int32_t SdioSwitchHighSpeed(struct MmcCntlr *cntlr)
3369 {
3370 struct SdioDevice *sdioDev = NULL;
3371
3372 if (cntlr == NULL || cntlr->curDev == NULL) {
3373 return HDF_ERR_INVALID_PARAM;
3374 }
3375
3376 sdioDev = (struct SdioDevice *)cntlr->curDev;
3377 if (cntlr->caps.bits.highSpeed == 0 || sdioDev->sdioReg.cccr.highSpeed == 0) {
3378 return HDF_ERR_NOT_SUPPORT;
3379 }
3380 return SdioBusSpeedSelect(cntlr, true);
3381 }
3382
SdioEnableHighSpeed(struct MmcCntlr * cntlr)3383 static int32_t SdioEnableHighSpeed(struct MmcCntlr *cntlr)
3384 {
3385 int32_t err;
3386
3387 err = SdioSwitchHighSpeed(cntlr);
3388 if (cntlr->curDev->type == MMC_DEV_SDIO || err != HDF_SUCCESS) {
3389 return err;
3390 }
3391
3392 /* COMBO card, need switch SD memory. */
3393 err = SdSwitchHighSpeed(cntlr);
3394 if (err == HDF_SUCCESS) {
3395 return err;
3396 }
3397 /* sd switch fail, need switch sdio to default speed. */
3398 if (SdioBusSpeedSelect(cntlr, false) != HDF_SUCCESS) {
3399 HDF_LOGD("SdioEnableHighSpeed: switch sdio to default speed fail.");
3400 }
3401 return err;
3402 }
3403
SdioSetBusWidth(struct MmcCntlr * cntlr,uint8_t width)3404 static int32_t SdioSetBusWidth(struct MmcCntlr *cntlr, uint8_t width)
3405 {
3406 struct SdioCmdParam param = {0};
3407 int32_t error;
3408 uint8_t data;
3409
3410 /* read register 7 of CCCR. */
3411 param.regAddr = BUS_INTERFACE_CONTROL;
3412 error = SdioRwDirect(cntlr, ¶m, &data);
3413 if (error != HDF_SUCCESS) {
3414 HDF_LOGE("SdioSetBusWidth: read BIC fail, error = %d!", error);
3415 return error;
3416 }
3417
3418 data |= width;
3419 /* write bit1-bit0: Bus Width. */
3420 param.writeflag = true;
3421 param.writeData = data;
3422 return SdioRwDirect(cntlr, ¶m, NULL);
3423 }
3424
SdioSwitch4BitBusWidth(struct MmcCntlr * cntlr)3425 static int32_t SdioSwitch4BitBusWidth(struct MmcCntlr *cntlr)
3426 {
3427 struct SdioDevice *sdioDev = NULL;
3428
3429 if (cntlr == NULL || cntlr->curDev == NULL) {
3430 return HDF_ERR_INVALID_PARAM;
3431 }
3432
3433 sdioDev = (struct SdioDevice *)cntlr->curDev;
3434 if (cntlr->caps.bits.cap4Bit == 0) {
3435 return HDF_ERR_NOT_SUPPORT;
3436 }
3437 /*
3438 * Note that Low-Speed SDIO cards support 4-bit transfer as an optipn. When communicating with a
3439 * Low-Speed SDIO card, the host shall fist determine if the card supports 4-bit transfer prior to
3440 * attempting to select that mode.
3441 */
3442 if (sdioDev->sdioReg.cccr.lowSpeed > 0 && sdioDev->sdioReg.cccr.lowSpeed4Bit == 0) {
3443 return HDF_ERR_NOT_SUPPORT;
3444 }
3445 return SdioSetBusWidth(cntlr, SDIO_CCCR_WIDTH_4BIT);
3446 }
3447
SdioEnable4BitBusWidth(struct MmcCntlr * cntlr)3448 static int32_t SdioEnable4BitBusWidth(struct MmcCntlr *cntlr)
3449 {
3450 int32_t error;
3451 struct SdDevice *dev = (struct SdDevice *)cntlr->curDev;
3452
3453 /*
3454 * For an SD memory card, the bus width for SD mode is set using ACMD6.
3455 * For an SDIO card a write to the CCCR usingCMD52 is used to select bus width.
3456 * In the case of a combo card, both selection methods exist.
3457 */
3458 error = SdioSwitch4BitBusWidth(cntlr);
3459 if (cntlr->curDev->type == MMC_DEV_SDIO || error != HDF_SUCCESS) {
3460 return error;
3461 }
3462
3463 /* COMBO card, need switch SD memory. */
3464 if ((dev->reg.scr.sdBusWidths & SD_SCR_BUS_WIDTHS_4) > 0 &&
3465 (cntlr->caps.bits.cap4Bit > 0)) {
3466 error = SdAcmdSetBusWidth(cntlr, BUS_WIDTH4);
3467 }
3468
3469 return error;
3470 }
3471
SdioReadCisTplField(struct MmcCntlr * cntlr,uint32_t addr,uint8_t * data)3472 static int32_t SdioReadCisTplField(struct MmcCntlr *cntlr, uint32_t addr, uint8_t *data)
3473 {
3474 struct SdioCmdParam param = {0};
3475
3476 param.regAddr = addr;
3477 return SdioRwDirect(cntlr, ¶m, data);
3478 }
3479
SdioDecodeCisTplManfId(struct MmcCntlr * cntlr,struct SdioFunction * function,struct SdioCisTuple * tuple)3480 static void SdioDecodeCisTplManfId(struct MmcCntlr *cntlr, struct SdioFunction *function,
3481 struct SdioCisTuple *tuple)
3482 {
3483 uint16_t vendorId, deviceId;
3484 struct SdioDevice *dev = NULL;
3485
3486 if (tuple->tplLink < SDIO_CIS_TPL_MANFID_MIN_SIZE) {
3487 return;
3488 }
3489
3490 /*
3491 * CISTPL_MANFID Field: bit00[TPL_CODE(20)], bit01[TPL_LINK(at least 4)], bit02-03[SDIO Card manufacturer code],
3492 * bit04-05[manufacturer information(Part Number and /or Revision)].
3493 * bit02-03-->tplBody[0:1], bit04-05-->tplBody[2:3].
3494 */
3495 vendorId = (tuple->tplBody[1] << BITS_PER_BYTE) | tuple->tplBody[0];
3496 deviceId = (tuple->tplBody[3] << BITS_PER_BYTE) | tuple->tplBody[2];
3497
3498 /* function CISTPL_MANFID. */
3499 if (function != NULL) {
3500 function->deviceId = deviceId;
3501 function->vendorId = vendorId;
3502 return;
3503 }
3504
3505 /* common CISTPL_MANFID. */
3506 dev = (struct SdioDevice *)cntlr->curDev;
3507 dev->sdioReg.cis.deviceId = deviceId;
3508 dev->sdioReg.cis.vendorId = vendorId;
3509 }
3510
SdioDecodeCisTplFunceCommon(struct MmcCntlr * cntlr,struct SdioCisTuple * tuple)3511 static void SdioDecodeCisTplFunceCommon(struct MmcCntlr *cntlr, struct SdioCisTuple *tuple)
3512 {
3513 struct SdioDevice *dev = (struct SdioDevice *)cntlr->curDev;
3514 const uint8_t value[16] = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 };
3515 const uint32_t unit[8] = { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 };
3516
3517 if (tuple->tplLink < SDIO_CIS_TPL_FUNCE_COMMON_MIN_SIZE) {
3518 return;
3519 }
3520
3521 /*
3522 * CISTPL_FUNCE(common): bit00[TPL_CODE(22h)], bit01[TPL_LINK], bit02[TPLFE_TYPE(00h)],
3523 * bit03-04[TPLFE_FN0_BLK_SIZE], bit05[TPLFE_MAX_TRAN_SPEED].
3524 * bit2-->tplBody[0], bit03-04-->tplBody[1:2], bit05-->tplBody[3].
3525 */
3526 dev->sdioReg.cis.blkSize = (tuple->tplBody[2] << BITS_PER_BYTE) | tuple->tplBody[1];
3527
3528 /*
3529 * This byte indicates the maximum transfer rate per one data line during data transfer. This value applies to
3530 * all functions in the SDIO card. This value shall be 25Mb/Sec(32h) for all Full-Speed SDIO card. The minimum
3531 * value for Low-Speed SDIO cards shall be 400 Kb/Sec(48h). The format is identical to the TRAN_SPEED value stored
3532 * in the CSD of SD memory cards. The maximum data transfer rate is coded according to the following method:
3533 * Bits 2:0 contain the transfer rate unit coded as follows:
3534 * 0=100kbit/s, 1=1Mbit/s, 2=10Mbit/s, 3=100Mbit/s, ... 7=reserved.
3535 * Bits 6:3 contain the time value coded as follows:
3536 * 0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5, 5=2.0, 6=2.5, 7=3.0, 8= 3.5, 9=4.0, A=4.5, B=5.0, C=5.5, D=6.0, E=7.0,
3537 * F= 8.0.
3538 * Bit 7 is reserved and shall be 0.
3539 */
3540 dev->sdioReg.cis.maxDtr = unit[tuple->tplBody[3] & 7] * value[(tuple->tplBody[3] >> 3) & 15];
3541 }
3542
SdioDecodeCisTplFunceFunction(struct SdioFunction * function,struct SdioCisTuple * tuple)3543 static void SdioDecodeCisTplFunceFunction(struct SdioFunction *function, struct SdioCisTuple *tuple)
3544 {
3545 uint32_t minSize;
3546
3547 /* Rev 1.0, TPL_LINK 28bytes; >Rev 1.0, TPL_LINK 42bytes. */
3548 minSize = (function->dev->sdioReg.cccr.sdioRev == SDIO_CCCR_SDIO_REV_1_00) ?
3549 SDIO_CIS_TPL_FUNCE_FUNCTION_PC_MIN_SIZE : SDIO_CIS_TPL_FUNCE_FUNCTION_PC_MAX_SIZE;
3550 if (tuple->tplLink < minSize) {
3551 return;
3552 }
3553
3554 /*
3555 * CISTPL_FUNCE(function): bit00[TPL_CODE(22h)], bit01[TPL_LINK], bit02[TPLFE_TYPE(01h)],
3556 * bit0E-0F[TPLFE_MAX_BLK_SIZE], bit1E-1F[TPLFE_ENABLE_TIMEOUT_VAL].
3557 * bit2-->tplBody[0], bit0E-0F-->tplBody[12:13], bit1E-1F-->tplBody[28:29].
3558 */
3559 function->maxBlkSize = (tuple->tplBody[13] << BITS_PER_BYTE) | tuple->tplBody[12];
3560
3561 /*
3562 * TPLFE_ENABLE_TIMEOUT_VAL is added in SDIO Rev 1.1. This 16-bit value indicates the function's required time-out
3563 * value for coming ready after being enabled. This per-function value indicated the time a host should wait from
3564 * asserting IOEx until expecting the card to indicate ready by asserting IORx. Different SDIO functions take
3565 * different amounts of time to become raedy after being enabled due to different internal initialization
3566 * requirements. The required time-out limit is in 10mS steps. If the card required no time-out, this field shall
3567 * be set to 0000h.
3568 */
3569 if (function->dev->sdioReg.cccr.sdioRev > SDIO_CCCR_SDIO_REV_1_00) {
3570 function->timeOut = (tuple->tplBody[28] | (tuple->tplBody[29] << BITS_PER_BYTE)) * 10;
3571 } else {
3572 function->timeOut = SDIO_CIS_TPLFE_ENABLE_TIMEOUT_VAL_DEF;
3573 }
3574 }
3575
SdioDecodeCisTplFunce(struct MmcCntlr * cntlr,struct SdioFunction * function,struct SdioCisTuple * tuple)3576 static void SdioDecodeCisTplFunce(struct MmcCntlr *cntlr, struct SdioFunction *function,
3577 struct SdioCisTuple *tuple)
3578 {
3579 /*
3580 * The Function Extension Tuple provides standard information about the card(common) and each individual function.
3581 * There shall be one CISTPL_FUNCE in each function's CIS. There are two versions of the CISTPL_FUNCE tuple, one
3582 * for the common CIS(function 0) and a version uesd by the individual function's CIS(1-7).
3583 */
3584 if (tuple->tplBody[0] == SDIO_CIS_TPL_FUNCE_COMMON) {
3585 if (function != NULL) {
3586 return;
3587 }
3588 SdioDecodeCisTplFunceCommon(cntlr, tuple);
3589 return;
3590 }
3591
3592 if (tuple->tplBody[0] == SDIO_CIS_TPL_FUNCE_FUNCTION_PC) {
3593 if (function == NULL) {
3594 return;
3595 }
3596 SdioDecodeCisTplFunceFunction(function, tuple);
3597 }
3598 }
3599
SdioDecodeCisTplField(struct MmcCntlr * cntlr,struct SdioFunction * function,struct SdioCisTuple * tuple)3600 static void SdioDecodeCisTplField(struct MmcCntlr *cntlr, struct SdioFunction *function,
3601 struct SdioCisTuple *tuple)
3602 {
3603 /* decode MANFID. */
3604 if (tuple->tplCode == SDIO_CIS_TPL_MANFID) {
3605 SdioDecodeCisTplManfId(cntlr, function, tuple);
3606 return;
3607 }
3608 /* decode FUNCE. */
3609 if (tuple->tplCode == SDIO_CIS_TPL_FUNCE) {
3610 SdioDecodeCisTplFunce(cntlr, function, tuple);
3611 }
3612 }
3613
SdioFillTplInfo(struct MmcCntlr * cntlr,struct SdioCisTuple * tuple,uint32_t * addr,uint8_t tplCode,uint8_t tplLink)3614 static int32_t SdioFillTplInfo(struct MmcCntlr *cntlr, struct SdioCisTuple *tuple,
3615 uint32_t *addr, uint8_t tplCode, uint8_t tplLink)
3616 {
3617 int32_t ret;
3618 uint32_t i;
3619
3620 tuple->tplCode = tplCode;
3621 tuple->tplLink = tplLink;
3622 /* read tuple body. */
3623 for (i = 0; i < tplLink; i++) {
3624 (*addr)++;
3625 ret = SdioReadCisTplField(cntlr, *addr, &(tuple->tplBody[i]));
3626 if (ret != HDF_SUCCESS) {
3627 HDF_LOGE("SdioFillTplInfo: read tuple body fail, err = %d.", ret);
3628 return ret;
3629 }
3630 }
3631 return HDF_SUCCESS;
3632 }
3633
SdioDecodeCis(struct MmcCntlr * cntlr,struct SdioFunction * function,uint32_t cisStartAddr)3634 static int32_t SdioDecodeCis(struct MmcCntlr *cntlr, struct SdioFunction *function, uint32_t cisStartAddr)
3635 {
3636 int32_t ret = HDF_SUCCESS;
3637 uint8_t tplCode, tplLink;
3638 struct SdioCisTuple *tuple = NULL;
3639 uint32_t addr = cisStartAddr;
3640
3641 while (ret == HDF_SUCCESS) {
3642 /* read TPL_CODE. */
3643 ret = SdioReadCisTplField(cntlr, addr, &tplCode);
3644 if (ret != HDF_SUCCESS) {
3645 HDF_LOGE("SdioDecodeCis: read TPL_CODE fail, err = %d.", ret);
3646 return ret;
3647 }
3648 if (tplCode == SDIO_CIS_TPL_END || tplCode == SDIO_CIS_TPL_NULL) {
3649 return HDF_SUCCESS;
3650 }
3651 /* read TPL_LINK. */
3652 addr++;
3653 ret = SdioReadCisTplField(cntlr, addr, &tplLink);
3654 if (ret != HDF_SUCCESS) {
3655 HDF_LOGE("SdioDecodeCis: read TPL_LINK fail, err = %d.", ret);
3656 return ret;
3657 }
3658 if (tplLink == SDIO_CIS_TPL_END) {
3659 return HDF_SUCCESS;
3660 }
3661 /* If the link field is 0, the the tuple body is empty. */
3662 if (tplLink == SDIO_CIS_TPL_NULL) {
3663 continue;
3664 }
3665
3666 tuple = (struct SdioCisTuple *)OsalMemCalloc(sizeof(*tuple) + tplLink);
3667 if (tuple == NULL) {
3668 HDF_LOGE("SdioDecodeCis: mem alloc fail!");
3669 return HDF_ERR_MALLOC_FAIL;
3670 }
3671
3672 ret = SdioFillTplInfo(cntlr, tuple, &addr, tplCode, tplLink);
3673 if (ret != HDF_SUCCESS) {
3674 OsalMemFree(tuple);
3675 return ret;
3676 }
3677 /* decode. */
3678 SdioDecodeCisTplField(cntlr, function, tuple);
3679 OsalMemFree(tuple);
3680 tuple = NULL;
3681 addr++;
3682 }
3683 return ret;
3684 }
3685
SdioReadCis(struct MmcCntlr * cntlr,struct SdioFunction * function)3686 static int32_t SdioReadCis(struct MmcCntlr *cntlr, struct SdioFunction *function)
3687 {
3688 uint32_t funcNum, i, cisStartAddr;
3689 uint8_t data;
3690 int32_t ret;
3691 struct SdioCmdParam param = {0};
3692
3693 if (function == NULL) {
3694 funcNum = 0;
3695 } else {
3696 funcNum = function->funcNum;
3697 }
3698
3699 /* read CIS pointer. */
3700 cisStartAddr = 0;
3701 for (i = 0; i < SDIO_CCCR_CIS_START_ADDR_BYTES; i++) {
3702 /* read register 0xn09-0xn0B of FBR. */
3703 param.regAddr = SDIO_FBR_BASE_ADDR(funcNum) + SDIO_FBR_POINTER_CIS + i;
3704 ret = SdioRwDirect(cntlr, ¶m, &data);
3705 if (ret != HDF_SUCCESS) {
3706 HDF_LOGE("SdioReadCis: read CIS pointer fail, err = %d.", ret);
3707 return ret;
3708 }
3709 cisStartAddr |= (uint32_t)(data << (i * BITS_PER_BYTE));
3710 }
3711 return SdioDecodeCis(cntlr, function, cisStartAddr);
3712 }
3713
SdioReadFbr(struct MmcCntlr * cntlr,struct SdioFunction * func)3714 static int32_t SdioReadFbr(struct MmcCntlr *cntlr, struct SdioFunction *func)
3715 {
3716 struct SdioCmdParam param = {0};
3717 int32_t error;
3718 uint8_t data;
3719
3720 /* read register 0xn00 of FBR. */
3721 param.regAddr = SDIO_FBR_BASE_ADDR(func->funcNum) + SDIO_FBR_STD_FUNCTION_INTERFACE_CODE;
3722 error = SdioRwDirect(cntlr, ¶m, &data);
3723 if (error != HDF_SUCCESS) {
3724 HDF_LOGE("SdioReadFbr: read SFIC fail, err = %d.", error);
3725 return error;
3726 }
3727
3728 /* bit3-bit0: Standard SDIO Function Interface Code. */
3729 data &= 0x0f;
3730 if (data == SDIO_FBR_STD_SDIO_IF) {
3731 /* read register 0xn01 of FBR. */
3732 param.regAddr = SDIO_FBR_BASE_ADDR(func->funcNum) + SDIO_FBR_EXT_STD_FUNCTION_INTERFACE_CODE;
3733 error = SdioRwDirect(cntlr, ¶m, &data);
3734 if (error != HDF_SUCCESS) {
3735 HDF_LOGE("SdioReadFbr: read ESFIC fail, err = %d.", error);
3736 return error;
3737 }
3738 }
3739
3740 func->funcClass = data;
3741 return HDF_SUCCESS;
3742 }
3743
SdioSetFbrIoBlockSize(struct MmcCntlr * cntlr,uint32_t blkSize)3744 int32_t SdioSetFbrIoBlockSize(struct MmcCntlr *cntlr, uint32_t blkSize)
3745 {
3746 struct SdioCmdParam param = {0};
3747 struct SdioDevice *dev = NULL;
3748 int32_t ret;
3749
3750 if (cntlr == NULL) {
3751 return HDF_ERR_INVALID_OBJECT;
3752 }
3753 dev = (struct SdioDevice *)cntlr->curDev;
3754 if (dev == NULL || dev->curFunction == NULL) {
3755 return HDF_ERR_INVALID_OBJECT;
3756 }
3757
3758 /* write register 0xn10 of FBR. */
3759 param.regAddr = SDIO_FBR_BASE_ADDR(dev->curFunction->funcNum) + SDIO_FBR_IO_BLOCK_SIZE;
3760 param.writeflag = true;
3761 /*
3762 * Function 1-7 I/O Block Size.
3763 * This 16-bit register sets the block size for I/O block operations for each function(1-7).
3764 * The maximum block size is 2048 and the minimum is 1. At power-up or reset, this register
3765 * shall be initially loaded with a value of 0. The host is responsible for setting the appropriate
3766 * value for the block size supported by each function. This pointer is stored in little-endian format.
3767 */
3768 param.writeData = (blkSize & 0xff);
3769 ret = SdioRwDirect(cntlr, ¶m, NULL);
3770 if (ret != HDF_SUCCESS) {
3771 HDF_LOGE("SdioSetFbrIoBlockSize: write I/O Block Size fail, err = %d.", ret);
3772 return ret;
3773 }
3774
3775 /* write register 0xn11 of FBR. */
3776 param.regAddr++;
3777 param.writeData = ((blkSize >> BITS_PER_BYTE) & 0xff);
3778 return SdioRwDirect(cntlr, ¶m, NULL);
3779 }
3780
SdioGetMaxClock(struct MmcCntlr * cntlr)3781 static uint32_t SdioGetMaxClock(struct MmcCntlr *cntlr)
3782 {
3783 uint32_t clock;
3784 struct MmcDevice *mmcDev = cntlr->curDev;
3785 struct SdioDevice *sdioDev = (struct SdioDevice *)mmcDev;
3786
3787 if (mmcDev->state.bits.highSpeed == 1) {
3788 /* The card operates in High-Speed timing mode with a clock rate up to 50MHz. */
3789 clock = 50000000;
3790 } else {
3791 clock = sdioDev->sdioReg.cis.maxDtr;
3792 }
3793
3794 if (mmcDev->type == MMC_DEV_COMBO) {
3795 clock = (clock < SdGetMaxClock(cntlr)) ? clock : SdGetMaxClock(cntlr);
3796 }
3797
3798 if (clock > cntlr->freqMax) {
3799 clock = cntlr->freqMax;
3800 }
3801 return clock;
3802 }
3803
SdioAllocFunction(struct SdioDevice * sdioDev,uint32_t funcNum)3804 static struct SdioFunction *SdioAllocFunction(struct SdioDevice *sdioDev, uint32_t funcNum)
3805 {
3806 struct SdioFunction *function = NULL;
3807
3808 function = (struct SdioFunction *)OsalMemCalloc(sizeof(struct SdioFunction));
3809 if (function == NULL) {
3810 HDF_LOGE("SdioAllocFunction: alloc fail!");
3811 return NULL;
3812 }
3813 function->dev = sdioDev;
3814 function->funcNum = funcNum;
3815 return function;
3816 }
3817
SdioDeleteFunction(struct SdioFunction * function)3818 static void SdioDeleteFunction(struct SdioFunction *function)
3819 {
3820 if (function == NULL) {
3821 return;
3822 }
3823 OsalMemFree(function);
3824 }
3825
SdioAddFunctions(struct MmcCntlr * cntlr,uint32_t funcs)3826 static int32_t SdioAddFunctions(struct MmcCntlr *cntlr, uint32_t funcs)
3827 {
3828 struct SdioDevice *sdioDev = (struct SdioDevice *)cntlr->curDev;
3829 struct SdioFunction *function = NULL;
3830 uint32_t i;
3831 int32_t ret;
3832
3833 sdioDev->functions = 0;
3834 for (i = 0; i < funcs; i++) {
3835 function = SdioAllocFunction(sdioDev, i + 1);
3836 if (function == NULL) {
3837 return HDF_ERR_MALLOC_FAIL;
3838 }
3839 ret = SdioReadFbr(cntlr, function);
3840 if (ret != HDF_SUCCESS) {
3841 SdioDeleteFunction(function);
3842 return ret;
3843 }
3844 ret = SdioReadCis(cntlr, function);
3845 if (ret != HDF_SUCCESS) {
3846 SdioDeleteFunction(function);
3847 return ret;
3848 }
3849
3850 if (function->vendorId == 0) {
3851 function->vendorId = sdioDev->sdioReg.cis.vendorId;
3852 function->deviceId = sdioDev->sdioReg.cis.deviceId;
3853 }
3854 /* A value of zero is not valid and shall not be used. */
3855 if (function->maxBlkSize == 0) {
3856 function->maxBlkSize = sdioDev->sdioReg.cis.blkSize;
3857 }
3858
3859 sdioDev->sdioFunc[i] = function;
3860 (sdioDev->functions)++;
3861 }
3862 return HDF_SUCCESS;
3863 }
3864
SdioDelete(struct SdioDevice * sdioDev)3865 static void SdioDelete(struct SdioDevice *sdioDev)
3866 {
3867 uint32_t i;
3868
3869 for (i = 0; i < sdioDev->functions; i++) {
3870 SdioDeleteFunction(sdioDev->sdioFunc[i]);
3871 sdioDev->sdioFunc[i] = NULL;
3872 }
3873 }
3874
SdioDeviceAdd(struct MmcCntlr * cntlr)3875 static int32_t SdioDeviceAdd(struct MmcCntlr *cntlr)
3876 {
3877 /* add dev. */
3878 if (MmcDeviceAdd(cntlr->curDev) != HDF_SUCCESS) {
3879 HDF_LOGE("SdioDeviceAdd: Add device fail!");
3880 return HDF_FAILURE;
3881 }
3882 cntlr->curDev->state.bits.present = 1;
3883 return HDF_SUCCESS;
3884 }
3885
SdioSelect(struct MmcCntlr * cntlr,uint32_t * rocr)3886 static int32_t SdioSelect(struct MmcCntlr *cntlr, uint32_t *rocr)
3887 {
3888 int32_t error;
3889
3890 /* cmd5, set the support voltage. */
3891 error = SdioSendOpCond(cntlr, cntlr->curDev->reg.ocr.ocrData, rocr);
3892 if (error != HDF_SUCCESS) {
3893 HDF_LOGE("cmd5(set voltage) fail, err = %d.", error);
3894 return error;
3895 }
3896
3897 /* Judge Combo Card. */
3898 if (((*rocr) & SDIO_R4_MEMORY_PRESENT) > 0) {
3899 if (SdSelect(cntlr, rocr) == 0) {
3900 cntlr->curDev->type = MMC_DEV_COMBO;
3901 HDF_LOGD("combo dev!!");
3902 }
3903 }
3904 /* get RCA. */
3905 error = SdCmdSendRelativeAddr(cntlr, &(cntlr->curDev->reg.rca));
3906 if (error != HDF_SUCCESS) {
3907 HDF_LOGE("cmd3(get RCA) fail, err = %d.", error);
3908 return error;
3909 }
3910 if (cntlr->curDev->type == MMC_DEV_COMBO) {
3911 /* get CSD, CMD9 should send in stby. */
3912 error = SdReadCsd(cntlr);
3913 if (error != HDF_SUCCESS) {
3914 HDF_LOGE("combo dev, read csd fail, err = %d.", error);
3915 return error;
3916 }
3917 }
3918 /* select card. */
3919 error = MmcSelectCard(cntlr);
3920 if (error != HDF_SUCCESS) {
3921 HDF_LOGE("cmd7(select card) fail, err = %d.", error);
3922 return error;
3923 }
3924
3925 error = SdioReadCccr(cntlr);
3926 if (error != HDF_SUCCESS) {
3927 HDF_LOGE("read cccr fail, err = %d.", error);
3928 return error;
3929 }
3930 /* read common CIS. */
3931 error = SdioReadCis(cntlr, NULL);
3932 if (error != HDF_SUCCESS) {
3933 HDF_LOGE("SdioInit: read cis fail, err = %d.", error);
3934 return error;
3935 }
3936 if (cntlr->curDev->type == MMC_DEV_COMBO) {
3937 error = SdReadRegisters(cntlr);
3938 if (error != HDF_SUCCESS) {
3939 HDF_LOGE("combo dev, read registers fail, err = %d.", error);
3940 MmcGoIdleState(cntlr);
3941 cntlr->curDev->type = MMC_DEV_SDIO;
3942 }
3943 }
3944 return HDF_SUCCESS;
3945 }
3946
SdioInit(struct MmcCntlr * cntlr)3947 static int32_t SdioInit(struct MmcCntlr *cntlr)
3948 {
3949 int32_t error;
3950 union MmcOcr ocr = {0};
3951
3952 /* cmd5, detect sdio dev and get the voltage range. */
3953 error = SdioSendOpCond(cntlr, 0, &(ocr.ocrData));
3954 if (error != HDF_SUCCESS) {
3955 HDF_LOGE("cmd5(detect sdio) fail, err = %d", error);
3956 return error;
3957 }
3958
3959 MmcCntlrSelectWorkVoltage(cntlr, &ocr);
3960 if (cntlr->curDev->reg.ocr.ocrData == 0) {
3961 HDF_LOGE("SdioInit: ocr is invalid!");
3962 return HDF_ERR_INVALID_PARAM;
3963 }
3964
3965 error = SdioSelect(cntlr, &(ocr.ocrData));
3966 if (error != HDF_SUCCESS) {
3967 return error;
3968 }
3969
3970 error = SdioCdDisable(cntlr);
3971 if (error != HDF_SUCCESS) {
3972 HDF_LOGE("Cd disable fail, err = %d.", error);
3973 return error;
3974 }
3975 error = SdioEnableHighSpeed(cntlr);
3976 if (error == HDF_SUCCESS) {
3977 cntlr->curDev->state.bits.highSpeed = 1;
3978 MmcCntlrSetBusTiming(cntlr, BUS_TIMING_SD_HS);
3979 } else if (error != HDF_ERR_NOT_SUPPORT) {
3980 HDF_LOGE("Enable HS fail, err = %d.", error);
3981 return error;
3982 }
3983 MmcCntlrSetClock(cntlr, SdioGetMaxClock(cntlr));
3984
3985 error = SdioEnable4BitBusWidth(cntlr);
3986 if (error == HDF_SUCCESS) {
3987 MmcCntlrSetBusWidth(cntlr, BUS_WIDTH4);
3988 } else if (error != HDF_ERR_NOT_SUPPORT) {
3989 HDF_LOGE("Enable 4-bits bus width fail, err = %d.", error);
3990 return error;
3991 }
3992 /* R4, [30: 28] Number of I/O functions. */
3993 error = SdioAddFunctions(cntlr, ((ocr.ocrData >> 28) & SDIO_MAX_FUNCTION_NUMBER));
3994 if (error != HDF_SUCCESS) {
3995 HDF_LOGE("Add functions fail, err = %d.", error);
3996 return error;
3997 }
3998
3999 return SdioDeviceAdd(cntlr);
4000 }
4001
SdioReinit(struct MmcCntlr * cntlr)4002 int32_t SdioReinit(struct MmcCntlr *cntlr)
4003 {
4004 union MmcOcr ocr = {0};
4005 int error;
4006
4007 MmcGoIdleState(cntlr);
4008 MmcCntlrSetClock(cntlr, cntlr->freqMin);
4009
4010 /* cmd5, detect sdio dev and get the voltage range. */
4011 error = SdioSendOpCond(cntlr, 0, &(ocr.ocrData));
4012 if (error != HDF_SUCCESS) {
4013 return error;
4014 }
4015 /* cmd5, set the support voltage. */
4016 error = SdioSendOpCond(cntlr, cntlr->curDev->reg.ocr.ocrData, &(ocr.ocrData));
4017 if (error != HDF_SUCCESS) {
4018 return error;
4019 }
4020 /* get RCA. */
4021 error = SdCmdSendRelativeAddr(cntlr, &(cntlr->curDev->reg.rca));
4022 if (error != HDF_SUCCESS) {
4023 return error;
4024 }
4025 /* select card. */
4026 error = MmcSelectCard(cntlr);
4027 if (error != HDF_SUCCESS) {
4028 return error;
4029 }
4030 error = SdioEnableHighSpeed(cntlr);
4031 if (error != HDF_SUCCESS) {
4032 return error;
4033 }
4034 MmcCntlrSetClock(cntlr, SdioGetMaxClock(cntlr));
4035
4036 error = SdioEnable4BitBusWidth(cntlr);
4037 if (error == HDF_SUCCESS) {
4038 MmcCntlrSetBusWidth(cntlr, BUS_WIDTH4);
4039 }
4040 return error;
4041 }
4042
SdioDetect(struct MmcCntlr * cntlr)4043 static int32_t SdioDetect(struct MmcCntlr *cntlr)
4044 {
4045 int32_t err;
4046
4047 HDF_LOGD("Detect sdio dev start...");
4048 /*
4049 * After reset or power-up, all I/O functions on the card are disabled and the I/O portion of the card shall
4050 * not execute any operation except CMD5 or CMD0. If there is SD memory on the card, that memory shall
4051 * respond normally to all mandatory memory commands.
4052 */
4053 SdioIoReset(cntlr);
4054 MmcGoIdleState(cntlr);
4055 /* Initialize SDIO. */
4056 err = SdioInit(cntlr);
4057 if (err == HDF_SUCCESS) {
4058 HDF_LOGD("Detect sdio dev success! %s dev at address 0x%x!",
4059 cntlr->curDev->state.bits.highSpeed ? "High speed" : "", cntlr->curDev->reg.rca);
4060 return HDF_SUCCESS;
4061 }
4062 SdioDelete((struct SdioDevice *)cntlr->curDev);
4063 return err;
4064 }
4065
MmcDeleteDev(struct MmcCntlr * cntlr)4066 void MmcDeleteDev(struct MmcCntlr *cntlr)
4067 {
4068 if (cntlr == NULL || cntlr->curDev == NULL) {
4069 return;
4070 }
4071
4072 if (cntlr->curDev->state.bits.present == 0) {
4073 return;
4074 }
4075 cntlr->curDev->state.bits.present = 0;
4076
4077 if (cntlr->curDev->type == MMC_DEV_SDIO || cntlr->curDev->type == MMC_DEV_COMBO) {
4078 SdioDelete((struct SdioDevice *)cntlr->curDev);
4079 }
4080
4081 MmcDeviceRemove(cntlr->curDev);
4082 MmcCntlrFreeDev(cntlr);
4083 }
4084
MmcDoDetect(struct MmcCntlr * cntlr)4085 int32_t MmcDoDetect(struct MmcCntlr *cntlr)
4086 {
4087 int32_t error;
4088 enum MmcDevType devType;
4089
4090 if (cntlr == NULL) {
4091 return HDF_ERR_INVALID_PARAM;
4092 }
4093 devType = (enum MmcDevType)cntlr->devType;
4094 if (devType >= MMC_DEV_COMBO) {
4095 return HDF_ERR_INVALID_PARAM;
4096 }
4097
4098 if (MmcCntlrAllocDev(cntlr, devType) != HDF_SUCCESS) {
4099 return HDF_ERR_INVALID_PARAM;
4100 }
4101
4102 MmcCntlrPowerUp(cntlr);
4103 if (devType == MMC_DEV_SDIO) {
4104 error = SdioDetect(cntlr);
4105 } else if (devType == MMC_DEV_SD) {
4106 error = SdDetect(cntlr);
4107 } else {
4108 error = EmmcDetect(cntlr);
4109 }
4110
4111 if (error == HDF_SUCCESS) {
4112 HDF_LOGD("MmcDoDetect: host%d detect succ!", cntlr->index);
4113 return error;
4114 }
4115
4116 HDF_LOGD("MmcDoDetect: host%d detect fail!", cntlr->index);
4117 MmcCntlrFreeDev(cntlr);
4118 MmcCntlrPowerOff(cntlr);
4119 return error;
4120 }
4121