1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52 /*
53 * The PCI interface treats multi-function devices as independent
54 * devices. The slot/function address of each device is encoded
55 * in a single byte as follows:
56 *
57 * 7:3 = slot
58 * 2:0 = function
59 *
60 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
63 */
64 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
65 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
66 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
67
68 /* pci_slot represents a physical slot */
69 struct pci_slot {
70 struct pci_bus *bus; /* Bus this slot is on */
71 struct list_head list; /* Node in list of slots */
72 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
74 struct kobject kobj;
75 };
76
pci_slot_name(const struct pci_slot * slot)77 static inline const char *pci_slot_name(const struct pci_slot *slot)
78 {
79 return kobject_name(&slot->kobj);
80 }
81
82 /* File state for mmap()s on /proc/bus/pci/X/Y */
83 enum pci_mmap_state {
84 pci_mmap_io,
85 pci_mmap_mem
86 };
87
88 /* For PCI devices, the region numbers are assigned this way: */
89 enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* Device-specific resources */
98 #ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101 #endif
102
103 /* PCI-to-PCI (P2P) bridge windows */
104 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
105 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
106 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
107
108 /* CardBus bridge windows */
109 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
110 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
111 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
112 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
113
114 /* Total number of bridge resources for P2P and CardBus */
115 #define PCI_BRIDGE_RESOURCE_NUM 4
116
117 /* Resources assigned to buses behind the bridge */
118 PCI_BRIDGE_RESOURCES,
119 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
120 PCI_BRIDGE_RESOURCE_NUM - 1,
121
122 /* Total resources associated with a PCI device */
123 PCI_NUM_RESOURCES,
124
125 /* Preserve this for compatibility */
126 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
127 };
128
129 /**
130 * enum pci_interrupt_pin - PCI INTx interrupt values
131 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
132 * @PCI_INTERRUPT_INTA: PCI INTA pin
133 * @PCI_INTERRUPT_INTB: PCI INTB pin
134 * @PCI_INTERRUPT_INTC: PCI INTC pin
135 * @PCI_INTERRUPT_INTD: PCI INTD pin
136 *
137 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
138 * PCI_INTERRUPT_PIN register.
139 */
140 enum pci_interrupt_pin {
141 PCI_INTERRUPT_UNKNOWN,
142 PCI_INTERRUPT_INTA,
143 PCI_INTERRUPT_INTB,
144 PCI_INTERRUPT_INTC,
145 PCI_INTERRUPT_INTD,
146 };
147
148 /* The number of legacy PCI INTx interrupts */
149 #define PCI_NUM_INTX 4
150
151 /*
152 * pci_power_t values must match the bits in the Capabilities PME_Support
153 * and Control/Status PowerState fields in the Power Management capability.
154 */
155 typedef int __bitwise pci_power_t;
156
157 #define PCI_D0 ((pci_power_t __force) 0)
158 #define PCI_D1 ((pci_power_t __force) 1)
159 #define PCI_D2 ((pci_power_t __force) 2)
160 #define PCI_D3hot ((pci_power_t __force) 3)
161 #define PCI_D3cold ((pci_power_t __force) 4)
162 #define PCI_UNKNOWN ((pci_power_t __force) 5)
163 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
164
165 /* Remember to update this when the list above changes! */
166 extern const char *pci_power_names[];
167
pci_power_name(pci_power_t state)168 static inline const char *pci_power_name(pci_power_t state)
169 {
170 return pci_power_names[1 + (__force int) state];
171 }
172
173 /**
174 * typedef pci_channel_state_t
175 *
176 * The pci_channel state describes connectivity between the CPU and
177 * the PCI device. If some PCI bus between here and the PCI device
178 * has crashed or locked up, this info is reflected here.
179 */
180 typedef unsigned int __bitwise pci_channel_state_t;
181
182 enum {
183 /* I/O channel is in normal state */
184 pci_channel_io_normal = (__force pci_channel_state_t) 1,
185
186 /* I/O to channel is blocked */
187 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
188
189 /* PCI card is dead */
190 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
191 };
192
193 typedef unsigned int __bitwise pcie_reset_state_t;
194
195 enum pcie_reset_state {
196 /* Reset is NOT asserted (Use to deassert reset) */
197 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
198
199 /* Use #PERST to reset PCIe device */
200 pcie_warm_reset = (__force pcie_reset_state_t) 2,
201
202 /* Use PCIe Hot Reset to reset device */
203 pcie_hot_reset = (__force pcie_reset_state_t) 3
204 };
205
206 typedef unsigned short __bitwise pci_dev_flags_t;
207 enum pci_dev_flags {
208 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
209 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
210 /* Device configuration is irrevocably lost if disabled into D3 */
211 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
212 /* Provide indication device is assigned by a Virtual Machine Manager */
213 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
214 /* Flag for quirk use to store if quirk-specific ACS is enabled */
215 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
216 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
217 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
218 /* Do not use bus resets for device */
219 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
220 /* Do not use PM reset even if device advertises NoSoftRst- */
221 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
222 /* Get VPD from function 0 VPD */
223 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
224 /* A non-root bridge where translation occurs, stop alias search here */
225 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
226 /* Do not use FLR even if device advertises PCI_AF_CAP */
227 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
228 /* Don't use Relaxed Ordering for TLPs directed at this device */
229 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
230 };
231
232 enum pci_irq_reroute_variant {
233 INTEL_IRQ_REROUTE_VARIANT = 1,
234 MAX_IRQ_REROUTE_VARIANTS = 3
235 };
236
237 typedef unsigned short __bitwise pci_bus_flags_t;
238 enum pci_bus_flags {
239 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
240 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
241 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
242 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
243 };
244
245 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
246 enum pcie_link_width {
247 PCIE_LNK_WIDTH_RESRV = 0x00,
248 PCIE_LNK_X1 = 0x01,
249 PCIE_LNK_X2 = 0x02,
250 PCIE_LNK_X4 = 0x04,
251 PCIE_LNK_X8 = 0x08,
252 PCIE_LNK_X12 = 0x0c,
253 PCIE_LNK_X16 = 0x10,
254 PCIE_LNK_X32 = 0x20,
255 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
256 };
257
258 /* See matching string table in pci_speed_string() */
259 enum pci_bus_speed {
260 PCI_SPEED_33MHz = 0x00,
261 PCI_SPEED_66MHz = 0x01,
262 PCI_SPEED_66MHz_PCIX = 0x02,
263 PCI_SPEED_100MHz_PCIX = 0x03,
264 PCI_SPEED_133MHz_PCIX = 0x04,
265 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
266 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
267 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
268 PCI_SPEED_66MHz_PCIX_266 = 0x09,
269 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
270 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
271 AGP_UNKNOWN = 0x0c,
272 AGP_1X = 0x0d,
273 AGP_2X = 0x0e,
274 AGP_4X = 0x0f,
275 AGP_8X = 0x10,
276 PCI_SPEED_66MHz_PCIX_533 = 0x11,
277 PCI_SPEED_100MHz_PCIX_533 = 0x12,
278 PCI_SPEED_133MHz_PCIX_533 = 0x13,
279 PCIE_SPEED_2_5GT = 0x14,
280 PCIE_SPEED_5_0GT = 0x15,
281 PCIE_SPEED_8_0GT = 0x16,
282 PCIE_SPEED_16_0GT = 0x17,
283 PCIE_SPEED_32_0GT = 0x18,
284 PCI_SPEED_UNKNOWN = 0xff,
285 };
286
287 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
288 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
289
290 struct pci_cap_saved_data {
291 u16 cap_nr;
292 bool cap_extended;
293 unsigned int size;
294 u32 data[];
295 };
296
297 struct pci_cap_saved_state {
298 struct hlist_node next;
299 struct pci_cap_saved_data cap;
300 };
301
302 struct irq_affinity;
303 struct pcie_link_state;
304 struct pci_vpd;
305 struct pci_sriov;
306 struct pci_p2pdma;
307
308 /* The pci_dev structure describes PCI devices */
309 struct pci_dev {
310 struct list_head bus_list; /* Node in per-bus list */
311 struct pci_bus *bus; /* Bus this device is on */
312 struct pci_bus *subordinate; /* Bus this device bridges to */
313
314 void *sysdata; /* Hook for sys-specific extension */
315 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
316 struct pci_slot *slot; /* Physical slot this device is in */
317
318 unsigned int devfn; /* Encoded device & function index */
319 unsigned short vendor;
320 unsigned short device;
321 unsigned short subsystem_vendor;
322 unsigned short subsystem_device;
323 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
324 u8 revision; /* PCI revision, low byte of class word */
325 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
326 #ifdef CONFIG_PCIEAER
327 u16 aer_cap; /* AER capability offset */
328 struct aer_stats *aer_stats; /* AER stats for this device */
329 #endif
330 u8 pcie_cap; /* PCIe capability offset */
331 u8 msi_cap; /* MSI capability offset */
332 u8 msix_cap; /* MSI-X capability offset */
333 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
334 u8 rom_base_reg; /* Config register controlling ROM */
335 u8 pin; /* Interrupt pin this device uses */
336 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
337 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
338
339 struct pci_driver *driver; /* Driver bound to this device */
340 u64 dma_mask; /* Mask of the bits of bus address this
341 device implements. Normally this is
342 0xffffffff. You only need to change
343 this if your device has broken DMA
344 or supports 64-bit transfers. */
345
346 struct device_dma_parameters dma_parms;
347
348 pci_power_t current_state; /* Current operating state. In ACPI,
349 this is D0-D3, D0 being fully
350 functional, and D3 being off. */
351 unsigned int imm_ready:1; /* Supports Immediate Readiness */
352 u8 pm_cap; /* PM capability offset */
353 unsigned int pme_support:5; /* Bitmask of states from which PME#
354 can be generated */
355 unsigned int pme_poll:1; /* Poll device's PME status bit */
356 unsigned int d1_support:1; /* Low power state D1 is supported */
357 unsigned int d2_support:1; /* Low power state D2 is supported */
358 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
359 unsigned int no_d3cold:1; /* D3cold is forbidden */
360 unsigned int bridge_d3:1; /* Allow D3 for bridge */
361 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
362 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
363 decoding during BAR sizing */
364 unsigned int wakeup_prepared:1;
365 unsigned int runtime_d3cold:1; /* Whether go through runtime
366 D3cold, not set for devices
367 powered on/off by the
368 corresponding bridge */
369 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
370 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
371 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
372 controlled exclusively by
373 user sysfs */
374 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
375 bit manually */
376 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
377 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
378
379 #ifdef CONFIG_PCIEASPM
380 struct pcie_link_state *link_state; /* ASPM link state */
381 unsigned int ltr_path:1; /* Latency Tolerance Reporting
382 supported from root to here */
383 int l1ss; /* L1SS Capability pointer */
384 #endif
385 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
386
387 pci_channel_state_t error_state; /* Current connectivity state */
388 struct device dev; /* Generic device interface */
389
390 int cfg_size; /* Size of config space */
391
392 /*
393 * Instead of touching interrupt line and base address registers
394 * directly, use the values stored here. They might be different!
395 */
396 unsigned int irq;
397 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
398
399 bool match_driver; /* Skip attaching driver */
400
401 unsigned int transparent:1; /* Subtractive decode bridge */
402 unsigned int io_window:1; /* Bridge has I/O window */
403 unsigned int pref_window:1; /* Bridge has pref mem window */
404 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
405 unsigned int multifunction:1; /* Multi-function device */
406
407 unsigned int is_busmaster:1; /* Is busmaster */
408 unsigned int no_msi:1; /* May not use MSI */
409 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
410 unsigned int block_cfg_access:1; /* Config space access blocked */
411 unsigned int broken_parity_status:1; /* Generates false positive parity */
412 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
413 unsigned int msi_enabled:1;
414 unsigned int msix_enabled:1;
415 unsigned int ari_enabled:1; /* ARI forwarding */
416 unsigned int ats_enabled:1; /* Address Translation Svc */
417 unsigned int pasid_enabled:1; /* Process Address Space ID */
418 unsigned int pri_enabled:1; /* Page Request Interface */
419 unsigned int is_managed:1;
420 unsigned int needs_freset:1; /* Requires fundamental reset */
421 unsigned int state_saved:1;
422 unsigned int is_physfn:1;
423 unsigned int is_virtfn:1;
424 unsigned int reset_fn:1;
425 unsigned int is_hotplug_bridge:1;
426 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
427 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
428 /*
429 * Devices marked being untrusted are the ones that can potentially
430 * execute DMA attacks and similar. They are typically connected
431 * through external ports such as Thunderbolt but not limited to
432 * that. When an IOMMU is enabled they should be getting full
433 * mappings to make sure they cannot access arbitrary memory.
434 */
435 unsigned int untrusted:1;
436 /*
437 * Info from the platform, e.g., ACPI or device tree, may mark a
438 * device as "external-facing". An external-facing device is
439 * itself internal but devices downstream from it are external.
440 */
441 unsigned int external_facing:1;
442 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
443 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
444 unsigned int irq_managed:1;
445 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
446 unsigned int is_probed:1; /* Device probing in progress */
447 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
448 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
449 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
450 pci_dev_flags_t dev_flags;
451 atomic_t enable_cnt; /* pci_enable_device has been called */
452
453 u32 saved_config_space[16]; /* Config space saved at suspend time */
454 struct hlist_head saved_cap_space;
455 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
456 int rom_attr_enabled; /* Display of ROM attribute enabled? */
457 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
458 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
459
460 #ifdef CONFIG_HOTPLUG_PCI_PCIE
461 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
462 #endif
463 #ifdef CONFIG_PCIE_PTM
464 unsigned int ptm_root:1;
465 unsigned int ptm_enabled:1;
466 u8 ptm_granularity;
467 #endif
468 #ifdef CONFIG_PCI_MSI
469 const struct attribute_group **msi_irq_groups;
470 #endif
471 struct pci_vpd *vpd;
472 #ifdef CONFIG_PCIE_DPC
473 u16 dpc_cap;
474 unsigned int dpc_rp_extensions:1;
475 u8 dpc_rp_log_size;
476 #endif
477 #ifdef CONFIG_PCI_ATS
478 union {
479 struct pci_sriov *sriov; /* PF: SR-IOV info */
480 struct pci_dev *physfn; /* VF: related PF */
481 };
482 u16 ats_cap; /* ATS Capability offset */
483 u8 ats_stu; /* ATS Smallest Translation Unit */
484 #endif
485 #ifdef CONFIG_PCI_PRI
486 u16 pri_cap; /* PRI Capability offset */
487 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
488 unsigned int pasid_required:1; /* PRG Response PASID Required */
489 #endif
490 #ifdef CONFIG_PCI_PASID
491 u16 pasid_cap; /* PASID Capability offset */
492 u16 pasid_features;
493 #endif
494 #ifdef CONFIG_PCI_P2PDMA
495 struct pci_p2pdma *p2pdma;
496 #endif
497 u16 acs_cap; /* ACS Capability offset */
498 phys_addr_t rom; /* Physical address if not from BAR */
499 size_t romlen; /* Length if not from BAR */
500 char *driver_override; /* Driver name to force a match */
501
502 unsigned long priv_flags; /* Private flags for the PCI driver */
503 };
504
pci_physfn(struct pci_dev * dev)505 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
506 {
507 #ifdef CONFIG_PCI_IOV
508 if (dev->is_virtfn)
509 dev = dev->physfn;
510 #endif
511 return dev;
512 }
513
514 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
515
516 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
517 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
518
pci_channel_offline(struct pci_dev * pdev)519 static inline int pci_channel_offline(struct pci_dev *pdev)
520 {
521 return (pdev->error_state != pci_channel_io_normal);
522 }
523
524 struct pci_host_bridge {
525 struct device dev;
526 struct pci_bus *bus; /* Root bus */
527 struct pci_ops *ops;
528 struct pci_ops *child_ops;
529 void *sysdata;
530 int busnr;
531 struct list_head windows; /* resource_entry */
532 struct list_head dma_ranges; /* dma ranges resource list */
533 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
534 int (*map_irq)(const struct pci_dev *, u8, u8);
535 void (*release_fn)(struct pci_host_bridge *);
536 void *release_data;
537 struct msi_controller *msi;
538 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
539 unsigned int no_ext_tags:1; /* No Extended Tags */
540 unsigned int native_aer:1; /* OS may use PCIe AER */
541 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
542 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
543 unsigned int native_pme:1; /* OS may use PCIe PME */
544 unsigned int native_ltr:1; /* OS may use PCIe LTR */
545 unsigned int native_dpc:1; /* OS may use PCIe DPC */
546 unsigned int preserve_config:1; /* Preserve FW resource setup */
547 unsigned int size_windows:1; /* Enable root bus sizing */
548
549 /* Resource alignment requirements */
550 resource_size_t (*align_resource)(struct pci_dev *dev,
551 const struct resource *res,
552 resource_size_t start,
553 resource_size_t size,
554 resource_size_t align);
555 unsigned long private[] ____cacheline_aligned;
556 };
557
558 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
559
pci_host_bridge_priv(struct pci_host_bridge * bridge)560 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
561 {
562 return (void *)bridge->private;
563 }
564
pci_host_bridge_from_priv(void * priv)565 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
566 {
567 return container_of(priv, struct pci_host_bridge, private);
568 }
569
570 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
571 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
572 size_t priv);
573 void pci_free_host_bridge(struct pci_host_bridge *bridge);
574 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
575
576 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
577 void (*release_fn)(struct pci_host_bridge *),
578 void *release_data);
579
580 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
581
582 /*
583 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
584 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
585 * buses below host bridges or subtractive decode bridges) go in the list.
586 * Use pci_bus_for_each_resource() to iterate through all the resources.
587 */
588
589 /*
590 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
591 * and there's no way to program the bridge with the details of the window.
592 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
593 * decode bit set, because they are explicit and can be programmed with _SRS.
594 */
595 #define PCI_SUBTRACTIVE_DECODE 0x1
596
597 struct pci_bus_resource {
598 struct list_head list;
599 struct resource *res;
600 unsigned int flags;
601 };
602
603 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
604
605 struct pci_bus {
606 struct list_head node; /* Node in list of buses */
607 struct pci_bus *parent; /* Parent bus this bridge is on */
608 struct list_head children; /* List of child buses */
609 struct list_head devices; /* List of devices on this bus */
610 struct pci_dev *self; /* Bridge device as seen by parent */
611 struct list_head slots; /* List of slots on this bus;
612 protected by pci_slot_mutex */
613 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
614 struct list_head resources; /* Address space routed to this bus */
615 struct resource busn_res; /* Bus numbers routed to this bus */
616
617 struct pci_ops *ops; /* Configuration access functions */
618 struct pci_ops *backup_ops;
619 struct msi_controller *msi; /* MSI controller */
620 void *sysdata; /* Hook for sys-specific extension */
621 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
622
623 unsigned char number; /* Bus number */
624 unsigned char primary; /* Number of primary bridge */
625 unsigned char max_bus_speed; /* enum pci_bus_speed */
626 unsigned char cur_bus_speed; /* enum pci_bus_speed */
627 #ifdef CONFIG_PCI_DOMAINS_GENERIC
628 int domain_nr;
629 #endif
630
631 char name[48];
632
633 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
634 pci_bus_flags_t bus_flags; /* Inherited by child buses */
635 struct device *bridge;
636 struct device dev;
637 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
638 struct bin_attribute *legacy_mem; /* Legacy mem */
639 unsigned int is_added:1;
640 };
641
642 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
643
pci_dev_id(struct pci_dev * dev)644 static inline u16 pci_dev_id(struct pci_dev *dev)
645 {
646 return PCI_DEVID(dev->bus->number, dev->devfn);
647 }
648
649 /*
650 * Returns true if the PCI bus is root (behind host-PCI bridge),
651 * false otherwise
652 *
653 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
654 * This is incorrect because "virtual" buses added for SR-IOV (via
655 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
656 */
pci_is_root_bus(struct pci_bus * pbus)657 static inline bool pci_is_root_bus(struct pci_bus *pbus)
658 {
659 return !(pbus->parent);
660 }
661
662 /**
663 * pci_is_bridge - check if the PCI device is a bridge
664 * @dev: PCI device
665 *
666 * Return true if the PCI device is bridge whether it has subordinate
667 * or not.
668 */
pci_is_bridge(struct pci_dev * dev)669 static inline bool pci_is_bridge(struct pci_dev *dev)
670 {
671 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
672 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
673 }
674
675 #define for_each_pci_bridge(dev, bus) \
676 list_for_each_entry(dev, &bus->devices, bus_list) \
677 if (!pci_is_bridge(dev)) {} else
678
pci_upstream_bridge(struct pci_dev * dev)679 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
680 {
681 dev = pci_physfn(dev);
682 if (pci_is_root_bus(dev->bus))
683 return NULL;
684
685 return dev->bus->self;
686 }
687
688 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)689 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
690 {
691 return pci_dev->msi_enabled || pci_dev->msix_enabled;
692 }
693 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)694 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
695 #endif
696
697 /* Error values that may be returned by PCI functions */
698 #define PCIBIOS_SUCCESSFUL 0x00
699 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
700 #define PCIBIOS_BAD_VENDOR_ID 0x83
701 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
702 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
703 #define PCIBIOS_SET_FAILED 0x88
704 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
705
706 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)707 static inline int pcibios_err_to_errno(int err)
708 {
709 if (err <= PCIBIOS_SUCCESSFUL)
710 return err; /* Assume already errno */
711
712 switch (err) {
713 case PCIBIOS_FUNC_NOT_SUPPORTED:
714 return -ENOENT;
715 case PCIBIOS_BAD_VENDOR_ID:
716 return -ENOTTY;
717 case PCIBIOS_DEVICE_NOT_FOUND:
718 return -ENODEV;
719 case PCIBIOS_BAD_REGISTER_NUMBER:
720 return -EFAULT;
721 case PCIBIOS_SET_FAILED:
722 return -EIO;
723 case PCIBIOS_BUFFER_TOO_SMALL:
724 return -ENOSPC;
725 }
726
727 return -ERANGE;
728 }
729
730 /* Low-level architecture-dependent routines */
731
732 struct pci_ops {
733 int (*add_bus)(struct pci_bus *bus);
734 void (*remove_bus)(struct pci_bus *bus);
735 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
736 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
737 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
738 };
739
740 /*
741 * ACPI needs to be able to access PCI config space before we've done a
742 * PCI bus scan and created pci_bus structures.
743 */
744 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
745 int reg, int len, u32 *val);
746 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
747 int reg, int len, u32 val);
748
749 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
750 typedef u64 pci_bus_addr_t;
751 #else
752 typedef u32 pci_bus_addr_t;
753 #endif
754
755 struct pci_bus_region {
756 pci_bus_addr_t start;
757 pci_bus_addr_t end;
758 };
759
760 struct pci_dynids {
761 spinlock_t lock; /* Protects list, index */
762 struct list_head list; /* For IDs added at runtime */
763 };
764
765
766 /*
767 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
768 * a set of callbacks in struct pci_error_handlers, that device driver
769 * will be notified of PCI bus errors, and will be driven to recovery
770 * when an error occurs.
771 */
772
773 typedef unsigned int __bitwise pci_ers_result_t;
774
775 enum pci_ers_result {
776 /* No result/none/not supported in device driver */
777 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
778
779 /* Device driver can recover without slot reset */
780 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
781
782 /* Device driver wants slot to be reset */
783 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
784
785 /* Device has completely failed, is unrecoverable */
786 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
787
788 /* Device driver is fully recovered and operational */
789 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
790
791 /* No AER capabilities registered for the driver */
792 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
793 };
794
795 /* PCI bus error event callbacks */
796 struct pci_error_handlers {
797 /* PCI bus error detected on this device */
798 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
799 pci_channel_state_t error);
800
801 /* MMIO has been re-enabled, but not DMA */
802 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
803
804 /* PCI slot has been reset */
805 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
806
807 /* PCI function reset prepare or completed */
808 void (*reset_prepare)(struct pci_dev *dev);
809 void (*reset_done)(struct pci_dev *dev);
810
811 /* Device driver may resume normal operations */
812 void (*resume)(struct pci_dev *dev);
813 };
814
815
816 struct module;
817
818 /**
819 * struct pci_driver - PCI driver structure
820 * @node: List of driver structures.
821 * @name: Driver name.
822 * @id_table: Pointer to table of device IDs the driver is
823 * interested in. Most drivers should export this
824 * table using MODULE_DEVICE_TABLE(pci,...).
825 * @probe: This probing function gets called (during execution
826 * of pci_register_driver() for already existing
827 * devices or later if a new device gets inserted) for
828 * all PCI devices which match the ID table and are not
829 * "owned" by the other drivers yet. This function gets
830 * passed a "struct pci_dev \*" for each device whose
831 * entry in the ID table matches the device. The probe
832 * function returns zero when the driver chooses to
833 * take "ownership" of the device or an error code
834 * (negative number) otherwise.
835 * The probe function always gets called from process
836 * context, so it can sleep.
837 * @remove: The remove() function gets called whenever a device
838 * being handled by this driver is removed (either during
839 * deregistration of the driver or when it's manually
840 * pulled out of a hot-pluggable slot).
841 * The remove function always gets called from process
842 * context, so it can sleep.
843 * @suspend: Put device into low power state.
844 * @resume: Wake device from low power state.
845 * (Please see Documentation/power/pci.rst for descriptions
846 * of PCI Power Management and the related functions.)
847 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
848 * Intended to stop any idling DMA operations.
849 * Useful for enabling wake-on-lan (NIC) or changing
850 * the power state of a device before reboot.
851 * e.g. drivers/net/e100.c.
852 * @sriov_configure: Optional driver callback to allow configuration of
853 * number of VFs to enable via sysfs "sriov_numvfs" file.
854 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
855 * @groups: Sysfs attribute groups.
856 * @driver: Driver model structure.
857 * @dynids: List of dynamically added device IDs.
858 */
859 struct pci_driver {
860 struct list_head node;
861 const char *name;
862 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
863 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
864 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
865 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
866 int (*resume)(struct pci_dev *dev); /* Device woken up */
867 void (*shutdown)(struct pci_dev *dev);
868 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
869 const struct pci_error_handlers *err_handler;
870 const struct attribute_group **groups;
871 struct device_driver driver;
872 struct pci_dynids dynids;
873 };
874
875 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
876
877 /**
878 * PCI_DEVICE - macro used to describe a specific PCI device
879 * @vend: the 16 bit PCI Vendor ID
880 * @dev: the 16 bit PCI Device ID
881 *
882 * This macro is used to create a struct pci_device_id that matches a
883 * specific device. The subvendor and subdevice fields will be set to
884 * PCI_ANY_ID.
885 */
886 #define PCI_DEVICE(vend,dev) \
887 .vendor = (vend), .device = (dev), \
888 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
889
890 /**
891 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
892 * @vend: the 16 bit PCI Vendor ID
893 * @dev: the 16 bit PCI Device ID
894 * @subvend: the 16 bit PCI Subvendor ID
895 * @subdev: the 16 bit PCI Subdevice ID
896 *
897 * This macro is used to create a struct pci_device_id that matches a
898 * specific device with subsystem information.
899 */
900 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
901 .vendor = (vend), .device = (dev), \
902 .subvendor = (subvend), .subdevice = (subdev)
903
904 /**
905 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
906 * @dev_class: the class, subclass, prog-if triple for this device
907 * @dev_class_mask: the class mask for this device
908 *
909 * This macro is used to create a struct pci_device_id that matches a
910 * specific PCI class. The vendor, device, subvendor, and subdevice
911 * fields will be set to PCI_ANY_ID.
912 */
913 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
914 .class = (dev_class), .class_mask = (dev_class_mask), \
915 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
916 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
917
918 /**
919 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
920 * @vend: the vendor name
921 * @dev: the 16 bit PCI Device ID
922 *
923 * This macro is used to create a struct pci_device_id that matches a
924 * specific PCI device. The subvendor, and subdevice fields will be set
925 * to PCI_ANY_ID. The macro allows the next field to follow as the device
926 * private data.
927 */
928 #define PCI_VDEVICE(vend, dev) \
929 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
930 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
931
932 /**
933 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
934 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
935 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
936 * @data: the driver data to be filled
937 *
938 * This macro is used to create a struct pci_device_id that matches a
939 * specific PCI device. The subvendor, and subdevice fields will be set
940 * to PCI_ANY_ID.
941 */
942 #define PCI_DEVICE_DATA(vend, dev, data) \
943 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
944 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
945 .driver_data = (kernel_ulong_t)(data)
946
947 enum {
948 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
949 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
950 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
951 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
952 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
953 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
954 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
955 };
956
957 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
958 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
959 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
960 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
961
962 /* These external functions are only available when PCI support is enabled */
963 #ifdef CONFIG_PCI
964
965 extern unsigned int pci_flags;
966
pci_set_flags(int flags)967 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)968 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)969 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)970 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
971
972 void pcie_bus_configure_settings(struct pci_bus *bus);
973
974 enum pcie_bus_config_types {
975 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
976 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
977 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
978 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
979 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
980 };
981
982 extern enum pcie_bus_config_types pcie_bus_config;
983
984 extern struct bus_type pci_bus_type;
985
986 /* Do NOT directly access these two variables, unless you are arch-specific PCI
987 * code, or PCI core code. */
988 extern struct list_head pci_root_buses; /* List of all known PCI buses */
989 /* Some device drivers need know if PCI is initiated */
990 int no_pci_devices(void);
991
992 void pcibios_resource_survey_bus(struct pci_bus *bus);
993 void pcibios_bus_add_device(struct pci_dev *pdev);
994 void pcibios_add_bus(struct pci_bus *bus);
995 void pcibios_remove_bus(struct pci_bus *bus);
996 void pcibios_fixup_bus(struct pci_bus *);
997 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
998 /* Architecture-specific versions may override this (weak) */
999 char *pcibios_setup(char *str);
1000
1001 /* Used only when drivers/pci/setup.c is used */
1002 resource_size_t pcibios_align_resource(void *, const struct resource *,
1003 resource_size_t,
1004 resource_size_t);
1005
1006 /* Weak but can be overridden by arch */
1007 void pci_fixup_cardbus(struct pci_bus *);
1008
1009 /* Generic PCI functions used internally */
1010
1011 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1012 struct resource *res);
1013 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1014 struct pci_bus_region *region);
1015 void pcibios_scan_specific_bus(int busn);
1016 struct pci_bus *pci_find_bus(int domain, int busnr);
1017 void pci_bus_add_devices(const struct pci_bus *bus);
1018 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1019 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1020 struct pci_ops *ops, void *sysdata,
1021 struct list_head *resources);
1022 int pci_host_probe(struct pci_host_bridge *bridge);
1023 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1024 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1025 void pci_bus_release_busn_res(struct pci_bus *b);
1026 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1027 struct pci_ops *ops, void *sysdata,
1028 struct list_head *resources);
1029 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1030 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1031 int busnr);
1032 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1033 const char *name,
1034 struct hotplug_slot *hotplug);
1035 void pci_destroy_slot(struct pci_slot *slot);
1036 #ifdef CONFIG_SYSFS
1037 void pci_dev_assign_slot(struct pci_dev *dev);
1038 #else
pci_dev_assign_slot(struct pci_dev * dev)1039 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1040 #endif
1041 int pci_scan_slot(struct pci_bus *bus, int devfn);
1042 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1043 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1044 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1045 void pci_bus_add_device(struct pci_dev *dev);
1046 void pci_read_bridge_bases(struct pci_bus *child);
1047 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1048 struct resource *res);
1049 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1050 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1051 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1052 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1053 void pci_dev_put(struct pci_dev *dev);
1054 void pci_remove_bus(struct pci_bus *b);
1055 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1056 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1057 void pci_stop_root_bus(struct pci_bus *bus);
1058 void pci_remove_root_bus(struct pci_bus *bus);
1059 void pci_setup_cardbus(struct pci_bus *bus);
1060 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1061 void pci_sort_breadthfirst(void);
1062 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1063 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1064
1065 /* Generic PCI functions exported to card drivers */
1066
1067 int pci_find_capability(struct pci_dev *dev, int cap);
1068 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1069 int pci_find_ext_capability(struct pci_dev *dev, int cap);
1070 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
1071 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1072 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
1073 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1074
1075 u64 pci_get_dsn(struct pci_dev *dev);
1076
1077 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1078 struct pci_dev *from);
1079 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1080 unsigned int ss_vendor, unsigned int ss_device,
1081 struct pci_dev *from);
1082 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1083 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1084 unsigned int devfn);
1085 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1086 int pci_dev_present(const struct pci_device_id *ids);
1087
1088 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1089 int where, u8 *val);
1090 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1091 int where, u16 *val);
1092 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1093 int where, u32 *val);
1094 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1095 int where, u8 val);
1096 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1097 int where, u16 val);
1098 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1099 int where, u32 val);
1100
1101 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1102 int where, int size, u32 *val);
1103 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1104 int where, int size, u32 val);
1105 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1106 int where, int size, u32 *val);
1107 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1108 int where, int size, u32 val);
1109
1110 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1111
1112 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1113 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1114 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1115 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1116 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1117 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1118
1119 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1120 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1121 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1122 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1123 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1124 u16 clear, u16 set);
1125 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1126 u32 clear, u32 set);
1127
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1128 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1129 u16 set)
1130 {
1131 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1132 }
1133
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1134 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1135 u32 set)
1136 {
1137 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1138 }
1139
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1140 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1141 u16 clear)
1142 {
1143 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1144 }
1145
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1146 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1147 u32 clear)
1148 {
1149 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1150 }
1151
1152 /* User-space driven config access */
1153 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1154 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1155 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1156 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1157 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1158 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1159
1160 int __must_check pci_enable_device(struct pci_dev *dev);
1161 int __must_check pci_enable_device_io(struct pci_dev *dev);
1162 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1163 int __must_check pci_reenable_device(struct pci_dev *);
1164 int __must_check pcim_enable_device(struct pci_dev *pdev);
1165 void pcim_pin_device(struct pci_dev *pdev);
1166
pci_intx_mask_supported(struct pci_dev * pdev)1167 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1168 {
1169 /*
1170 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1171 * writable and no quirk has marked the feature broken.
1172 */
1173 return !pdev->broken_intx_masking;
1174 }
1175
pci_is_enabled(struct pci_dev * pdev)1176 static inline int pci_is_enabled(struct pci_dev *pdev)
1177 {
1178 return (atomic_read(&pdev->enable_cnt) > 0);
1179 }
1180
pci_is_managed(struct pci_dev * pdev)1181 static inline int pci_is_managed(struct pci_dev *pdev)
1182 {
1183 return pdev->is_managed;
1184 }
1185
1186 void pci_disable_device(struct pci_dev *dev);
1187
1188 extern unsigned int pcibios_max_latency;
1189 void pci_set_master(struct pci_dev *dev);
1190 void pci_clear_master(struct pci_dev *dev);
1191
1192 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1193 int pci_set_cacheline_size(struct pci_dev *dev);
1194 #define HAVE_PCI_SET_MWI
1195 int __must_check pci_set_mwi(struct pci_dev *dev);
1196 int __must_check pcim_set_mwi(struct pci_dev *dev);
1197 int pci_try_set_mwi(struct pci_dev *dev);
1198 void pci_clear_mwi(struct pci_dev *dev);
1199 void pci_intx(struct pci_dev *dev, int enable);
1200 bool pci_check_and_mask_intx(struct pci_dev *dev);
1201 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1202 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1203 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1204 int pcix_get_max_mmrbc(struct pci_dev *dev);
1205 int pcix_get_mmrbc(struct pci_dev *dev);
1206 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1207 int pcie_get_readrq(struct pci_dev *dev);
1208 int pcie_set_readrq(struct pci_dev *dev, int rq);
1209 int pcie_get_mps(struct pci_dev *dev);
1210 int pcie_set_mps(struct pci_dev *dev, int mps);
1211 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1212 enum pci_bus_speed *speed,
1213 enum pcie_link_width *width);
1214 void pcie_print_link_status(struct pci_dev *dev);
1215 bool pcie_has_flr(struct pci_dev *dev);
1216 int pcie_flr(struct pci_dev *dev);
1217 int __pci_reset_function_locked(struct pci_dev *dev);
1218 int pci_reset_function(struct pci_dev *dev);
1219 int pci_reset_function_locked(struct pci_dev *dev);
1220 int pci_try_reset_function(struct pci_dev *dev);
1221 int pci_probe_reset_slot(struct pci_slot *slot);
1222 int pci_probe_reset_bus(struct pci_bus *bus);
1223 int pci_reset_bus(struct pci_dev *dev);
1224 void pci_reset_secondary_bus(struct pci_dev *dev);
1225 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1226 void pci_update_resource(struct pci_dev *dev, int resno);
1227 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1228 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1229 void pci_release_resource(struct pci_dev *dev, int resno);
1230 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1231 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1232 bool pci_device_is_present(struct pci_dev *pdev);
1233 void pci_ignore_hotplug(struct pci_dev *dev);
1234 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1235 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1236
1237 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1238 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1239 const char *fmt, ...);
1240 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1241
1242 /* ROM control related routines */
1243 int pci_enable_rom(struct pci_dev *pdev);
1244 void pci_disable_rom(struct pci_dev *pdev);
1245 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1246 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1247
1248 /* Power management related routines */
1249 int pci_save_state(struct pci_dev *dev);
1250 void pci_restore_state(struct pci_dev *dev);
1251 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1252 int pci_load_saved_state(struct pci_dev *dev,
1253 struct pci_saved_state *state);
1254 int pci_load_and_free_saved_state(struct pci_dev *dev,
1255 struct pci_saved_state **state);
1256 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1257 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1258 u16 cap);
1259 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1260 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1261 u16 cap, unsigned int size);
1262 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1263 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1264 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1265 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1266 void pci_pme_active(struct pci_dev *dev, bool enable);
1267 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1268 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1269 int pci_prepare_to_sleep(struct pci_dev *dev);
1270 int pci_back_from_sleep(struct pci_dev *dev);
1271 bool pci_dev_run_wake(struct pci_dev *dev);
1272 void pci_d3cold_enable(struct pci_dev *dev);
1273 void pci_d3cold_disable(struct pci_dev *dev);
1274 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1275 void pci_wakeup_bus(struct pci_bus *bus);
1276 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1277
1278 /* For use by arch with custom probe code */
1279 void set_pcie_port_type(struct pci_dev *pdev);
1280 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1281
1282 /* Functions for PCI Hotplug drivers to use */
1283 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1284 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1285 unsigned int pci_rescan_bus(struct pci_bus *bus);
1286 void pci_lock_rescan_remove(void);
1287 void pci_unlock_rescan_remove(void);
1288
1289 /* Vital Product Data routines */
1290 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1291 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1292 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1293
1294 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1295 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1296 void pci_bus_assign_resources(const struct pci_bus *bus);
1297 void pci_bus_claim_resources(struct pci_bus *bus);
1298 void pci_bus_size_bridges(struct pci_bus *bus);
1299 int pci_claim_resource(struct pci_dev *, int);
1300 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1301 void pci_assign_unassigned_resources(void);
1302 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1303 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1304 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1305 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1306 void pdev_enable_device(struct pci_dev *);
1307 int pci_enable_resources(struct pci_dev *, int mask);
1308 void pci_assign_irq(struct pci_dev *dev);
1309 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1310 #define HAVE_PCI_REQ_REGIONS 2
1311 int __must_check pci_request_regions(struct pci_dev *, const char *);
1312 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1313 void pci_release_regions(struct pci_dev *);
1314 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1315 void pci_release_region(struct pci_dev *, int);
1316 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1317 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1318 void pci_release_selected_regions(struct pci_dev *, int);
1319
1320 /* drivers/pci/bus.c */
1321 void pci_add_resource(struct list_head *resources, struct resource *res);
1322 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1323 resource_size_t offset);
1324 void pci_free_resource_list(struct list_head *resources);
1325 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1326 unsigned int flags);
1327 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1328 void pci_bus_remove_resources(struct pci_bus *bus);
1329 int devm_request_pci_bus_resources(struct device *dev,
1330 struct list_head *resources);
1331
1332 /* Temporary until new and working PCI SBR API in place */
1333 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1334
1335 #define pci_bus_for_each_resource(bus, res, i) \
1336 for (i = 0; \
1337 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1338 i++)
1339
1340 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1341 struct resource *res, resource_size_t size,
1342 resource_size_t align, resource_size_t min,
1343 unsigned long type_mask,
1344 resource_size_t (*alignf)(void *,
1345 const struct resource *,
1346 resource_size_t,
1347 resource_size_t),
1348 void *alignf_data);
1349
1350
1351 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1352 resource_size_t size);
1353 unsigned long pci_address_to_pio(phys_addr_t addr);
1354 phys_addr_t pci_pio_to_address(unsigned long pio);
1355 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1356 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1357 phys_addr_t phys_addr);
1358 void pci_unmap_iospace(struct resource *res);
1359 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1360 resource_size_t offset,
1361 resource_size_t size);
1362 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1363 struct resource *res);
1364
pci_bus_address(struct pci_dev * pdev,int bar)1365 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1366 {
1367 struct pci_bus_region region;
1368
1369 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1370 return region.start;
1371 }
1372
1373 /* Proper probing supporting hot-pluggable devices */
1374 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1375 const char *mod_name);
1376
1377 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1378 #define pci_register_driver(driver) \
1379 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1380
1381 void pci_unregister_driver(struct pci_driver *dev);
1382
1383 /**
1384 * module_pci_driver() - Helper macro for registering a PCI driver
1385 * @__pci_driver: pci_driver struct
1386 *
1387 * Helper macro for PCI drivers which do not do anything special in module
1388 * init/exit. This eliminates a lot of boilerplate. Each module may only
1389 * use this macro once, and calling it replaces module_init() and module_exit()
1390 */
1391 #define module_pci_driver(__pci_driver) \
1392 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1393
1394 /**
1395 * builtin_pci_driver() - Helper macro for registering a PCI driver
1396 * @__pci_driver: pci_driver struct
1397 *
1398 * Helper macro for PCI drivers which do not do anything special in their
1399 * init code. This eliminates a lot of boilerplate. Each driver may only
1400 * use this macro once, and calling it replaces device_initcall(...)
1401 */
1402 #define builtin_pci_driver(__pci_driver) \
1403 builtin_driver(__pci_driver, pci_register_driver)
1404
1405 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1406 int pci_add_dynid(struct pci_driver *drv,
1407 unsigned int vendor, unsigned int device,
1408 unsigned int subvendor, unsigned int subdevice,
1409 unsigned int class, unsigned int class_mask,
1410 unsigned long driver_data);
1411 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1412 struct pci_dev *dev);
1413 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1414 int pass);
1415
1416 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1417 void *userdata);
1418 int pci_cfg_space_size(struct pci_dev *dev);
1419 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1420 void pci_setup_bridge(struct pci_bus *bus);
1421 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1422 unsigned long type);
1423
1424 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1425 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1426
1427 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1428 unsigned int command_bits, u32 flags);
1429
1430 /*
1431 * Virtual interrupts allow for more interrupts to be allocated
1432 * than the device has interrupts for. These are not programmed
1433 * into the device's MSI-X table and must be handled by some
1434 * other driver means.
1435 */
1436 #define PCI_IRQ_VIRTUAL (1 << 4)
1437
1438 #define PCI_IRQ_ALL_TYPES \
1439 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1440
1441 /* kmem_cache style wrapper around pci_alloc_consistent() */
1442
1443 #include <linux/dmapool.h>
1444
1445 #define pci_pool dma_pool
1446 #define pci_pool_create(name, pdev, size, align, allocation) \
1447 dma_pool_create(name, &pdev->dev, size, align, allocation)
1448 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1449 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1450 #define pci_pool_zalloc(pool, flags, handle) \
1451 dma_pool_zalloc(pool, flags, handle)
1452 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1453
1454 struct msix_entry {
1455 u32 vector; /* Kernel uses to write allocated vector */
1456 u16 entry; /* Driver uses to specify entry, OS writes */
1457 };
1458
1459 #ifdef CONFIG_PCI_MSI
1460 int pci_msi_vec_count(struct pci_dev *dev);
1461 void pci_disable_msi(struct pci_dev *dev);
1462 int pci_msix_vec_count(struct pci_dev *dev);
1463 void pci_disable_msix(struct pci_dev *dev);
1464 void pci_restore_msi_state(struct pci_dev *dev);
1465 int pci_msi_enabled(void);
1466 int pci_enable_msi(struct pci_dev *dev);
1467 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1468 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1469 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1470 struct msix_entry *entries, int nvec)
1471 {
1472 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1473 if (rc < 0)
1474 return rc;
1475 return 0;
1476 }
1477 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1478 unsigned int max_vecs, unsigned int flags,
1479 struct irq_affinity *affd);
1480
1481 void pci_free_irq_vectors(struct pci_dev *dev);
1482 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1483 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1484
1485 #else
pci_msi_vec_count(struct pci_dev * dev)1486 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1487 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1488 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1489 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1490 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1491 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1492 static inline int pci_enable_msi(struct pci_dev *dev)
1493 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1494 static inline int pci_enable_msix_range(struct pci_dev *dev,
1495 struct msix_entry *entries, int minvec, int maxvec)
1496 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1497 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1498 struct msix_entry *entries, int nvec)
1499 { return -ENOSYS; }
1500
1501 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1502 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1503 unsigned int max_vecs, unsigned int flags,
1504 struct irq_affinity *aff_desc)
1505 {
1506 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1507 return 1;
1508 return -ENOSPC;
1509 }
1510
pci_free_irq_vectors(struct pci_dev * dev)1511 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1512 {
1513 }
1514
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1515 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1516 {
1517 if (WARN_ON_ONCE(nr > 0))
1518 return -EINVAL;
1519 return dev->irq;
1520 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1521 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1522 int vec)
1523 {
1524 return cpu_possible_mask;
1525 }
1526 #endif
1527
1528 /**
1529 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1530 * @d: the INTx IRQ domain
1531 * @node: the DT node for the device whose interrupt we're translating
1532 * @intspec: the interrupt specifier data from the DT
1533 * @intsize: the number of entries in @intspec
1534 * @out_hwirq: pointer at which to write the hwirq number
1535 * @out_type: pointer at which to write the interrupt type
1536 *
1537 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1538 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1539 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1540 * INTx value to obtain the hwirq number.
1541 *
1542 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1543 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1544 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1545 struct device_node *node,
1546 const u32 *intspec,
1547 unsigned int intsize,
1548 unsigned long *out_hwirq,
1549 unsigned int *out_type)
1550 {
1551 const u32 intx = intspec[0];
1552
1553 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1554 return -EINVAL;
1555
1556 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1557 return 0;
1558 }
1559
1560 #ifdef CONFIG_PCIEPORTBUS
1561 extern bool pcie_ports_disabled;
1562 extern bool pcie_ports_native;
1563 #else
1564 #define pcie_ports_disabled true
1565 #define pcie_ports_native false
1566 #endif
1567
1568 #define PCIE_LINK_STATE_L0S BIT(0)
1569 #define PCIE_LINK_STATE_L1 BIT(1)
1570 #define PCIE_LINK_STATE_CLKPM BIT(2)
1571 #define PCIE_LINK_STATE_L1_1 BIT(3)
1572 #define PCIE_LINK_STATE_L1_2 BIT(4)
1573 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1574 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1575
1576 #ifdef CONFIG_PCIEASPM
1577 int pci_disable_link_state(struct pci_dev *pdev, int state);
1578 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1579 void pcie_no_aspm(void);
1580 bool pcie_aspm_support_enabled(void);
1581 bool pcie_aspm_enabled(struct pci_dev *pdev);
1582 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1583 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1584 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1585 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1586 { return 0; }
pcie_no_aspm(void)1587 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1588 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1589 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1590 #endif
1591
1592 #ifdef CONFIG_PCIEAER
1593 bool pci_aer_available(void);
1594 #else
pci_aer_available(void)1595 static inline bool pci_aer_available(void) { return false; }
1596 #endif
1597
1598 bool pci_ats_disabled(void);
1599
1600 void pci_cfg_access_lock(struct pci_dev *dev);
1601 bool pci_cfg_access_trylock(struct pci_dev *dev);
1602 void pci_cfg_access_unlock(struct pci_dev *dev);
1603
1604 /*
1605 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1606 * a PCI domain is defined to be a set of PCI buses which share
1607 * configuration space.
1608 */
1609 #ifdef CONFIG_PCI_DOMAINS
1610 extern int pci_domains_supported;
1611 #else
1612 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1613 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1614 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1615 #endif /* CONFIG_PCI_DOMAINS */
1616
1617 /*
1618 * Generic implementation for PCI domain support. If your
1619 * architecture does not need custom management of PCI
1620 * domains then this implementation will be used
1621 */
1622 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1623 static inline int pci_domain_nr(struct pci_bus *bus)
1624 {
1625 return bus->domain_nr;
1626 }
1627 #ifdef CONFIG_ACPI
1628 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1629 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1630 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1631 { return 0; }
1632 #endif
1633 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1634 #endif
1635
1636 /* Some architectures require additional setup to direct VGA traffic */
1637 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1638 unsigned int command_bits, u32 flags);
1639 void pci_register_set_vga_state(arch_set_vga_state_t func);
1640
1641 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1642 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1643 {
1644 return pci_request_selected_regions(pdev,
1645 pci_select_bars(pdev, IORESOURCE_IO), name);
1646 }
1647
1648 static inline void
pci_release_io_regions(struct pci_dev * pdev)1649 pci_release_io_regions(struct pci_dev *pdev)
1650 {
1651 return pci_release_selected_regions(pdev,
1652 pci_select_bars(pdev, IORESOURCE_IO));
1653 }
1654
1655 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1656 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1657 {
1658 return pci_request_selected_regions(pdev,
1659 pci_select_bars(pdev, IORESOURCE_MEM), name);
1660 }
1661
1662 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1663 pci_release_mem_regions(struct pci_dev *pdev)
1664 {
1665 return pci_release_selected_regions(pdev,
1666 pci_select_bars(pdev, IORESOURCE_MEM));
1667 }
1668
1669 #else /* CONFIG_PCI is not enabled */
1670
pci_set_flags(int flags)1671 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1672 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1673 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1674 static inline int pci_has_flag(int flag) { return 0; }
1675
1676 /*
1677 * If the system does not have PCI, clearly these return errors. Define
1678 * these as simple inline functions to avoid hair in drivers.
1679 */
1680 #define _PCI_NOP(o, s, t) \
1681 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1682 int where, t val) \
1683 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1684
1685 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1686 _PCI_NOP(o, word, u16 x) \
1687 _PCI_NOP(o, dword, u32 x)
1688 _PCI_NOP_ALL(read, *)
1689 _PCI_NOP_ALL(write,)
1690
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1691 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1692 unsigned int device,
1693 struct pci_dev *from)
1694 { return NULL; }
1695
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1696 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1697 unsigned int device,
1698 unsigned int ss_vendor,
1699 unsigned int ss_device,
1700 struct pci_dev *from)
1701 { return NULL; }
1702
pci_get_class(unsigned int class,struct pci_dev * from)1703 static inline struct pci_dev *pci_get_class(unsigned int class,
1704 struct pci_dev *from)
1705 { return NULL; }
1706
1707 #define pci_dev_present(ids) (0)
1708 #define no_pci_devices() (1)
1709 #define pci_dev_put(dev) do { } while (0)
1710
pci_set_master(struct pci_dev * dev)1711 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1712 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1713 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1714 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1715 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1716 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1717 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1718 struct module *owner,
1719 const char *mod_name)
1720 { return 0; }
pci_register_driver(struct pci_driver * drv)1721 static inline int pci_register_driver(struct pci_driver *drv)
1722 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1723 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1724 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1725 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1726 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1727 int cap)
1728 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1729 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1730 { return 0; }
1731
pci_get_dsn(struct pci_dev * dev)1732 static inline u64 pci_get_dsn(struct pci_dev *dev)
1733 { return 0; }
1734
1735 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1736 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1737 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1738 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1739 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1740 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1741 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1742 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1743 pm_message_t state)
1744 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1745 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1746 int enable)
1747 { return 0; }
1748
pci_find_resource(struct pci_dev * dev,struct resource * res)1749 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1750 struct resource *res)
1751 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1752 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1753 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1754 static inline void pci_release_regions(struct pci_dev *dev) { }
1755
pci_address_to_pio(phys_addr_t addr)1756 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1757
pci_find_next_bus(const struct pci_bus * from)1758 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1759 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1760 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1761 unsigned int devfn)
1762 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1763 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1764 unsigned int bus, unsigned int devfn)
1765 { return NULL; }
1766
pci_domain_nr(struct pci_bus * bus)1767 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1768 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1769
1770 #define dev_is_pci(d) (false)
1771 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1772 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1773 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1774 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1775 struct device_node *node,
1776 const u32 *intspec,
1777 unsigned int intsize,
1778 unsigned long *out_hwirq,
1779 unsigned int *out_type)
1780 { return -EINVAL; }
1781
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1782 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1783 struct pci_dev *dev)
1784 { return NULL; }
pci_ats_disabled(void)1785 static inline bool pci_ats_disabled(void) { return true; }
1786
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1787 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1788 {
1789 return -EINVAL;
1790 }
1791
1792 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1793 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1794 unsigned int max_vecs, unsigned int flags,
1795 struct irq_affinity *aff_desc)
1796 {
1797 return -ENOSPC;
1798 }
1799 #endif /* CONFIG_PCI */
1800
1801 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1802 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1803 unsigned int max_vecs, unsigned int flags)
1804 {
1805 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1806 NULL);
1807 }
1808
1809 /* Include architecture-dependent settings and functions */
1810
1811 #include <asm/pci.h>
1812
1813 /* These two functions provide almost identical functionality. Depending
1814 * on the architecture, one will be implemented as a wrapper around the
1815 * other (in drivers/pci/mmap.c).
1816 *
1817 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1818 * is expected to be an offset within that region.
1819 *
1820 * pci_mmap_page_range() is the legacy architecture-specific interface,
1821 * which accepts a "user visible" resource address converted by
1822 * pci_resource_to_user(), as used in the legacy mmap() interface in
1823 * /proc/bus/pci/.
1824 */
1825 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1826 struct vm_area_struct *vma,
1827 enum pci_mmap_state mmap_state, int write_combine);
1828 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1829 struct vm_area_struct *vma,
1830 enum pci_mmap_state mmap_state, int write_combine);
1831
1832 #ifndef arch_can_pci_mmap_wc
1833 #define arch_can_pci_mmap_wc() 0
1834 #endif
1835
1836 #ifndef arch_can_pci_mmap_io
1837 #define arch_can_pci_mmap_io() 0
1838 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1839 #else
1840 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1841 #endif
1842
1843 #ifndef pci_root_bus_fwnode
1844 #define pci_root_bus_fwnode(bus) NULL
1845 #endif
1846
1847 /*
1848 * These helpers provide future and backwards compatibility
1849 * for accessing popular PCI BAR info
1850 */
1851 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1852 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1853 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1854 #define pci_resource_len(dev,bar) \
1855 ((pci_resource_start((dev), (bar)) == 0 && \
1856 pci_resource_end((dev), (bar)) == \
1857 pci_resource_start((dev), (bar))) ? 0 : \
1858 \
1859 (pci_resource_end((dev), (bar)) - \
1860 pci_resource_start((dev), (bar)) + 1))
1861
1862 /*
1863 * Similar to the helpers above, these manipulate per-pci_dev
1864 * driver-specific data. They are really just a wrapper around
1865 * the generic device structure functions of these calls.
1866 */
pci_get_drvdata(struct pci_dev * pdev)1867 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1868 {
1869 return dev_get_drvdata(&pdev->dev);
1870 }
1871
pci_set_drvdata(struct pci_dev * pdev,void * data)1872 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1873 {
1874 dev_set_drvdata(&pdev->dev, data);
1875 }
1876
pci_name(const struct pci_dev * pdev)1877 static inline const char *pci_name(const struct pci_dev *pdev)
1878 {
1879 return dev_name(&pdev->dev);
1880 }
1881
1882 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1883 const struct resource *rsrc,
1884 resource_size_t *start, resource_size_t *end);
1885
1886 /*
1887 * The world is not perfect and supplies us with broken PCI devices.
1888 * For at least a part of these bugs we need a work-around, so both
1889 * generic (drivers/pci/quirks.c) and per-architecture code can define
1890 * fixup hooks to be called for particular buggy devices.
1891 */
1892
1893 struct pci_fixup {
1894 u16 vendor; /* Or PCI_ANY_ID */
1895 u16 device; /* Or PCI_ANY_ID */
1896 u32 class; /* Or PCI_ANY_ID */
1897 unsigned int class_shift; /* should be 0, 8, 16 */
1898 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1899 int hook_offset;
1900 #else
1901 void (*hook)(struct pci_dev *dev);
1902 #endif
1903 };
1904
1905 enum pci_fixup_pass {
1906 pci_fixup_early, /* Before probing BARs */
1907 pci_fixup_header, /* After reading configuration header */
1908 pci_fixup_final, /* Final phase of device fixups */
1909 pci_fixup_enable, /* pci_enable_device() time */
1910 pci_fixup_resume, /* pci_device_resume() */
1911 pci_fixup_suspend, /* pci_device_suspend() */
1912 pci_fixup_resume_early, /* pci_device_resume_early() */
1913 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1914 };
1915
1916 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1917 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1918 class_shift, hook) \
1919 __ADDRESSABLE(hook) \
1920 asm(".section " #sec ", \"a\" \n" \
1921 ".balign 16 \n" \
1922 ".short " #vendor ", " #device " \n" \
1923 ".long " #class ", " #class_shift " \n" \
1924 ".long " #hook " - . \n" \
1925 ".previous \n");
1926 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1927 class_shift, hook) \
1928 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1929 class_shift, hook)
1930 #else
1931 /* Anonymous variables would be nice... */
1932 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1933 class_shift, hook) \
1934 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1935 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1936 = { vendor, device, class, class_shift, hook };
1937 #endif
1938
1939 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1940 class_shift, hook) \
1941 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1942 hook, vendor, device, class, class_shift, hook)
1943 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1944 class_shift, hook) \
1945 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1946 hook, vendor, device, class, class_shift, hook)
1947 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1948 class_shift, hook) \
1949 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1950 hook, vendor, device, class, class_shift, hook)
1951 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1952 class_shift, hook) \
1953 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1954 hook, vendor, device, class, class_shift, hook)
1955 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1956 class_shift, hook) \
1957 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1958 resume##hook, vendor, device, class, class_shift, hook)
1959 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1960 class_shift, hook) \
1961 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1962 resume_early##hook, vendor, device, class, class_shift, hook)
1963 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1964 class_shift, hook) \
1965 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1966 suspend##hook, vendor, device, class, class_shift, hook)
1967 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1968 class_shift, hook) \
1969 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1970 suspend_late##hook, vendor, device, class, class_shift, hook)
1971
1972 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1973 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1974 hook, vendor, device, PCI_ANY_ID, 0, hook)
1975 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1976 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1977 hook, vendor, device, PCI_ANY_ID, 0, hook)
1978 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1979 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1980 hook, vendor, device, PCI_ANY_ID, 0, hook)
1981 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1982 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1983 hook, vendor, device, PCI_ANY_ID, 0, hook)
1984 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1985 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1986 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1987 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1988 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1989 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1990 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1991 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1992 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1993 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1994 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1995 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1996
1997 #ifdef CONFIG_PCI_QUIRKS
1998 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1999 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2000 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2001 struct pci_dev *dev) { }
2002 #endif
2003
2004 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2005 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2006 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2007 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2008 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2009 const char *name);
2010 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2011
2012 extern int pci_pci_problems;
2013 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2014 #define PCIPCI_TRITON 2
2015 #define PCIPCI_NATOMA 4
2016 #define PCIPCI_VIAETBF 8
2017 #define PCIPCI_VSFX 16
2018 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2019 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2020
2021 extern unsigned long pci_cardbus_io_size;
2022 extern unsigned long pci_cardbus_mem_size;
2023 extern u8 pci_dfl_cache_line_size;
2024 extern u8 pci_cache_line_size;
2025
2026 /* Architecture-specific versions may override these (weak) */
2027 void pcibios_disable_device(struct pci_dev *dev);
2028 void pcibios_set_master(struct pci_dev *dev);
2029 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2030 enum pcie_reset_state state);
2031 int pcibios_add_device(struct pci_dev *dev);
2032 void pcibios_release_device(struct pci_dev *dev);
2033 #ifdef CONFIG_PCI
2034 void pcibios_penalize_isa_irq(int irq, int active);
2035 #else
pcibios_penalize_isa_irq(int irq,int active)2036 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2037 #endif
2038 int pcibios_alloc_irq(struct pci_dev *dev);
2039 void pcibios_free_irq(struct pci_dev *dev);
2040 resource_size_t pcibios_default_alignment(void);
2041
2042 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2043 void __init pci_mmcfg_early_init(void);
2044 void __init pci_mmcfg_late_init(void);
2045 #else
pci_mmcfg_early_init(void)2046 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2047 static inline void pci_mmcfg_late_init(void) { }
2048 #endif
2049
2050 int pci_ext_cfg_avail(void);
2051
2052 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2053 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2054
2055 #ifdef CONFIG_PCI_IOV
2056 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2057 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2058
2059 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2060 void pci_disable_sriov(struct pci_dev *dev);
2061
2062 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2063 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2064 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2065 int pci_num_vf(struct pci_dev *dev);
2066 int pci_vfs_assigned(struct pci_dev *dev);
2067 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2068 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2069 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2070 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2071 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2072
2073 /* Arch may override these (weak) */
2074 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2075 int pcibios_sriov_disable(struct pci_dev *pdev);
2076 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2077 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2078 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2079 {
2080 return -ENOSYS;
2081 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2082 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2083 {
2084 return -ENOSYS;
2085 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2086 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2087 { return -ENODEV; }
2088
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2089 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2090 struct pci_dev *virtfn, int id)
2091 {
2092 return -ENODEV;
2093 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2094 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2095 {
2096 return -ENOSYS;
2097 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2098 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2099 int id) { }
pci_disable_sriov(struct pci_dev * dev)2100 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2101 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2102 static inline int pci_vfs_assigned(struct pci_dev *dev)
2103 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2104 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2105 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2106 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2107 { return 0; }
2108 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2109 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2110 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2111 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2112 #endif
2113
2114 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2115 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2116 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2117 #endif
2118
2119 /**
2120 * pci_pcie_cap - get the saved PCIe capability offset
2121 * @dev: PCI device
2122 *
2123 * PCIe capability offset is calculated at PCI device initialization
2124 * time and saved in the data structure. This function returns saved
2125 * PCIe capability offset. Using this instead of pci_find_capability()
2126 * reduces unnecessary search in the PCI configuration space. If you
2127 * need to calculate PCIe capability offset from raw device for some
2128 * reasons, please use pci_find_capability() instead.
2129 */
pci_pcie_cap(struct pci_dev * dev)2130 static inline int pci_pcie_cap(struct pci_dev *dev)
2131 {
2132 return dev->pcie_cap;
2133 }
2134
2135 /**
2136 * pci_is_pcie - check if the PCI device is PCI Express capable
2137 * @dev: PCI device
2138 *
2139 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2140 */
pci_is_pcie(struct pci_dev * dev)2141 static inline bool pci_is_pcie(struct pci_dev *dev)
2142 {
2143 return pci_pcie_cap(dev);
2144 }
2145
2146 /**
2147 * pcie_caps_reg - get the PCIe Capabilities Register
2148 * @dev: PCI device
2149 */
pcie_caps_reg(const struct pci_dev * dev)2150 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2151 {
2152 return dev->pcie_flags_reg;
2153 }
2154
2155 /**
2156 * pci_pcie_type - get the PCIe device/port type
2157 * @dev: PCI device
2158 */
pci_pcie_type(const struct pci_dev * dev)2159 static inline int pci_pcie_type(const struct pci_dev *dev)
2160 {
2161 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2162 }
2163
2164 /**
2165 * pcie_find_root_port - Get the PCIe root port device
2166 * @dev: PCI device
2167 *
2168 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2169 * for a given PCI/PCIe Device.
2170 */
pcie_find_root_port(struct pci_dev * dev)2171 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2172 {
2173 while (dev) {
2174 if (pci_is_pcie(dev) &&
2175 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2176 return dev;
2177 dev = pci_upstream_bridge(dev);
2178 }
2179
2180 return NULL;
2181 }
2182
2183 void pci_request_acs(void);
2184 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2185 bool pci_acs_path_enabled(struct pci_dev *start,
2186 struct pci_dev *end, u16 acs_flags);
2187 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2188
2189 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2190 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2191
2192 /* Large Resource Data Type Tag Item Names */
2193 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2194 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2195 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2196
2197 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2198 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2199 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2200
2201 /* Small Resource Data Type Tag Item Names */
2202 #define PCI_VPD_STIN_END 0x0f /* End */
2203
2204 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2205
2206 #define PCI_VPD_SRDT_TIN_MASK 0x78
2207 #define PCI_VPD_SRDT_LEN_MASK 0x07
2208 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2209
2210 #define PCI_VPD_LRDT_TAG_SIZE 3
2211 #define PCI_VPD_SRDT_TAG_SIZE 1
2212
2213 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2214
2215 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2216 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2217 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2218 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2219 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2220
2221 /**
2222 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2223 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2224 *
2225 * Returns the extracted Large Resource Data Type length.
2226 */
pci_vpd_lrdt_size(const u8 * lrdt)2227 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2228 {
2229 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2230 }
2231
2232 /**
2233 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2234 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2235 *
2236 * Returns the extracted Large Resource Data Type Tag item.
2237 */
pci_vpd_lrdt_tag(const u8 * lrdt)2238 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2239 {
2240 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2241 }
2242
2243 /**
2244 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2245 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2246 *
2247 * Returns the extracted Small Resource Data Type length.
2248 */
pci_vpd_srdt_size(const u8 * srdt)2249 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2250 {
2251 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2252 }
2253
2254 /**
2255 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2256 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2257 *
2258 * Returns the extracted Small Resource Data Type Tag Item.
2259 */
pci_vpd_srdt_tag(const u8 * srdt)2260 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2261 {
2262 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2263 }
2264
2265 /**
2266 * pci_vpd_info_field_size - Extracts the information field length
2267 * @info_field: Pointer to the beginning of an information field header
2268 *
2269 * Returns the extracted information field length.
2270 */
pci_vpd_info_field_size(const u8 * info_field)2271 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2272 {
2273 return info_field[2];
2274 }
2275
2276 /**
2277 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2278 * @buf: Pointer to buffered vpd data
2279 * @off: The offset into the buffer at which to begin the search
2280 * @len: The length of the vpd buffer
2281 * @rdt: The Resource Data Type to search for
2282 *
2283 * Returns the index where the Resource Data Type was found or
2284 * -ENOENT otherwise.
2285 */
2286 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2287
2288 /**
2289 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2290 * @buf: Pointer to buffered vpd data
2291 * @off: The offset into the buffer at which to begin the search
2292 * @len: The length of the buffer area, relative to off, in which to search
2293 * @kw: The keyword to search for
2294 *
2295 * Returns the index where the information field keyword was found or
2296 * -ENOENT otherwise.
2297 */
2298 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2299 unsigned int len, const char *kw);
2300
2301 /* PCI <-> OF binding helpers */
2302 #ifdef CONFIG_OF
2303 struct device_node;
2304 struct irq_domain;
2305 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2306
2307 /* Arch may override this (weak) */
2308 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2309
2310 #else /* CONFIG_OF */
2311 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2312 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2313 #endif /* CONFIG_OF */
2314
2315 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2316 pci_device_to_OF_node(const struct pci_dev *pdev)
2317 {
2318 return pdev ? pdev->dev.of_node : NULL;
2319 }
2320
pci_bus_to_OF_node(struct pci_bus * bus)2321 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2322 {
2323 return bus ? bus->dev.of_node : NULL;
2324 }
2325
2326 #ifdef CONFIG_ACPI
2327 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2328
2329 void
2330 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2331 bool pci_pr3_present(struct pci_dev *pdev);
2332 #else
2333 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2334 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2335 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2336 #endif
2337
2338 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2339 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2340 {
2341 return pdev->dev.archdata.edev;
2342 }
2343 #endif
2344
2345 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2346 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2347 int pci_for_each_dma_alias(struct pci_dev *pdev,
2348 int (*fn)(struct pci_dev *pdev,
2349 u16 alias, void *data), void *data);
2350
2351 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2352 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2353 {
2354 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2355 }
pci_clear_dev_assigned(struct pci_dev * pdev)2356 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2357 {
2358 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2359 }
pci_is_dev_assigned(struct pci_dev * pdev)2360 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2361 {
2362 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2363 }
2364
2365 /**
2366 * pci_ari_enabled - query ARI forwarding status
2367 * @bus: the PCI bus
2368 *
2369 * Returns true if ARI forwarding is enabled.
2370 */
pci_ari_enabled(struct pci_bus * bus)2371 static inline bool pci_ari_enabled(struct pci_bus *bus)
2372 {
2373 return bus->self && bus->self->ari_enabled;
2374 }
2375
2376 /**
2377 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2378 * @pdev: PCI device to check
2379 *
2380 * Walk upwards from @pdev and check for each encountered bridge if it's part
2381 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2382 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2383 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2384 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2385 {
2386 struct pci_dev *parent = pdev;
2387
2388 if (pdev->is_thunderbolt)
2389 return true;
2390
2391 while ((parent = pci_upstream_bridge(parent)))
2392 if (parent->is_thunderbolt)
2393 return true;
2394
2395 return false;
2396 }
2397
2398 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2399 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2400 #endif
2401
2402 /* Provide the legacy pci_dma_* API */
2403 #include <linux/pci-dma-compat.h>
2404
2405 #define pci_printk(level, pdev, fmt, arg...) \
2406 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2407
2408 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2409 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2410 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2411 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2412 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2413 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2414 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2415 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2416
2417 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2418 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2419
2420 #define pci_info_ratelimited(pdev, fmt, arg...) \
2421 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2422
2423 #define pci_WARN(pdev, condition, fmt, arg...) \
2424 WARN(condition, "%s %s: " fmt, \
2425 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2426
2427 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2428 WARN_ONCE(condition, "%s %s: " fmt, \
2429 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2430
2431 #endif /* LINUX_PCI_H */
2432