1 /* 2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __PLAT_ADDR_MAP_BEST2003_H__ 16 #define __PLAT_ADDR_MAP_BEST2003_H__ 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #define ROM_BASE 0x00020000 23 #define ROMD_BASE 0x24020000 24 25 #ifndef ROM_SIZE 26 #ifdef FPGA 27 #define ROM_SIZE 0x00020000 28 #else 29 #define ROM_SIZE 0x00010000 30 #endif 31 #endif 32 33 #define RAM0_BASE 0x20000000 34 #define RAMX0_BASE 0x00200000 35 #define RAM1_BASE 0x20040000 36 #define RAMX1_BASE 0x00240000 37 #define RAM2_BASE 0x20080000 38 #define RAMX2_BASE 0x00280000 39 #define RAM3_BASE 0x20100000 40 #define RAMX3_BASE 0x00300000 41 #define RAM4_BASE 0x20180000 42 #define RAMX4_BASE 0x00380000 43 #define RAM5_BASE 0x201C0000 44 #define RAMX5_BASE 0x003C0000 45 #define RAM_BASE RAM0_BASE 46 #define RAMX_BASE RAMX0_BASE 47 48 #define RAM5_SIZE 0x00040000 49 50 /* total ramv size is 0x30000 */ 51 #define RAMV_BASE 0x20200000 52 #ifndef RAMV_SIZE 53 #define RAMV_SIZE 0x00000000 54 #endif 55 56 #ifdef __BT_RAMRUN__ 57 #define BT_RAMRUN_BASE RAM3_BASE 58 #define BT_RAMRUNX_BASE RAMX3_BASE 59 #endif 60 61 #ifdef CHIP_HAS_CP 62 #ifdef LARGE_RAM 63 /*MCU use RAM0/1/2/3, CPX use RAM4, and CP use RAM5*/ 64 #define RAMCP_TOP (RAM5_BASE + RAM5_SIZE) 65 66 #ifndef RAMCP_SIZE 67 #define RAMCP_SIZE RAM5_SIZE 68 #endif 69 70 #ifndef RAMCP_BASE 71 #define RAMCP_BASE (RAMCP_TOP - RAMCP_SIZE) 72 #endif 73 74 #ifndef RAMCPX_SIZE 75 #define RAMCPX_SIZE (RAM5_BASE - RAM4_BASE) 76 #endif 77 78 #ifndef RAMCPX_BASE 79 #define RAMCPX_BASE (RAM_TO_RAMX(RAMCP_BASE) - RAMCPX_SIZE) 80 #endif 81 82 #else /*LARGE_RAM*/ 83 /*MCU use RAM0, CP and CPX use RAM1*/ 84 #define RAMCP_TOP RAM2_BASE 85 86 #ifndef RAMCP_SIZE 87 #define RAMCP_SIZE 0x20000 88 #endif 89 90 #ifndef RAMCP_BASE 91 #define RAMCP_BASE (RAMCP_TOP - RAMCP_SIZE) 92 #endif 93 94 #ifndef RAMCPX_SIZE 95 #define RAMCPX_SIZE (RAMX2_BASE - RAMX1_BASE - RAMCP_SIZE) 96 #endif 97 98 #ifndef RAMCPX_BASE 99 #define RAMCPX_BASE (RAM_TO_RAMX(RAMCP_BASE) - RAMCPX_SIZE) 100 #endif 101 102 #endif /*LARGE_RAM*/ 103 #endif 104 105 #define RAM_TOTAL_SIZE (RAM5_BASE + RAM5_SIZE - RAM0_BASE) // 0x00200000 106 107 #if defined(ARM_CMSE) || defined(ARM_CMNS) 108 #undef RAM_BASE 109 #undef RAMX_BASE 110 111 /*MPC: SRAM block size: 0x8000, FLASH block size 0x40000*/ 112 #ifndef RAM_S_SIZE 113 #define RAM_S_SIZE 0x00020000 114 #endif 115 #define RAM_NSC_SIZE 0 116 #ifndef FLASH_S_SIZE 117 #define FLASH_S_SIZE 0x00040000 118 #endif 119 120 #define RAM_NS_BASE (RAM0_BASE + RAM_S_SIZE) 121 #define RAMX_NS_BASE (RAMX0_BASE + RAM_S_SIZE) 122 123 #if defined(ARM_CMNS) 124 #define RAM_BASE RAM_NS_BASE 125 #define RAMX_BASE RAMX_NS_BASE 126 #else 127 #if ((RAM_S_SIZE) & (0x8000-1)) 128 #error "RAM_S_SIZE should be 0x8000 aligned" 129 #endif 130 #if (FLASH_S_SIZE & (0x40000-1)) 131 #error "FLASH_S_SIZE should be 0x40000 aligned" 132 #endif 133 #define RAM_BASE RAM0_BASE 134 #define RAMX_BASE RAMX0_BASE 135 #define RAM_SIZE RAM_S_SIZE 136 #ifndef NS_APP_START_OFFSET 137 #define NS_APP_START_OFFSET (FLASH_S_SIZE) 138 #endif 139 #ifndef FLASH_REGION_SIZE 140 #define FLASH_REGION_SIZE FLASH_S_SIZE 141 #endif 142 #endif 143 #endif /* defined(ARM_CMSE) || defined(ARM_CMNS) */ 144 145 #ifndef RAM_MCU_SIZE 146 /* secure and non-secure ram size */ 147 #ifdef LARGE_RAM 148 #ifdef CHIP_HAS_CP 149 #define RAM_MCU_SIZE (RAMCPX_BASE - RAMX_BASE) 150 #else 151 #define RAM_MCU_SIZE (RAM5_BASE + RAM5_SIZE - RAM_BASE) 152 #endif 153 #else 154 #ifdef CHIP_HAS_CP 155 #define RAM_MCU_SIZE (RAMCPX_BASE - RAMX_BASE) 156 #else 157 #define RAM_MCU_SIZE (RAM2_BASE - RAM_BASE) // 0x00080000 158 #endif 159 #endif 160 #endif /*RAM_MCU_SIZE*/ 161 162 #if defined(ARM_CMSE) 163 #ifndef RAM_NS_SIZE 164 #define RAM_NS_SIZE (RAM_BASE + RAM_MCU_SIZE - RAM_NS_BASE) 165 #endif /*RAM_NS_SIZE*/ 166 #endif 167 168 #ifndef RAM_SIZE 169 #define RAM_SIZE RAM_MCU_SIZE 170 #endif 171 172 #define FLASH_BASE 0x2C000000 173 #define FLASH_NC_BASE 0x28000000 174 #define FLASHX_BASE 0x0C000000 175 #define FLASHX_NC_BASE 0x08000000 176 #ifndef FLASH1_BASE 177 #define FLASH1_BASE 0x2D000000 178 #define FLASH1_NC_BASE 0x29000000 179 #define FLASH1X_BASE 0x0D000000 180 #define FLASH1X_NC_BASE 0x09000000 181 #endif 182 183 #define PSRAM_BASE 0x34000000 184 #define PSRAM_NC_BASE 0x30000000 185 #define PSRAMX_BASE 0x14000000 186 #define PSRAMX_NC_BASE 0x10000000 187 188 #define PSRAMUHS_BASE 0x3C000000 189 #define PSRAMUHS_NC_BASE 0x38000000 190 #define PSRAMUHSX_BASE 0x1C000000 191 #define PSRAMUHSX_NC_BASE 0x18000000 192 193 #define DCACHE_CTRL_BASE 0x27FFA000 194 #define ICACHE_CTRL_BASE 0x27FFC000 195 196 #define CMU_BASE 0x40000000 197 #define MCU_WDT_BASE 0x40001000 198 #define MCU_TIMER0_BASE 0x40002000 199 #define MCU_TIMER1_BASE 0x40003000 200 #define MCU_TIMER2_BASE 0x40004000 201 #define I2C0_BASE 0x40005000 202 #define I2C1_BASE 0x40006000 203 #define SPI_BASE 0x40007000 204 #define SPILCD_BASE 0x40008000 205 #define ISPI_BASE 0x40009000 206 #define SPIPHY_BASE 0x4000A000 207 #define UART0_BASE 0x4000B000 208 #define UART1_BASE 0x4000C000 209 #define UART2_BASE 0x4000D000 210 #define BTPCM_BASE 0x4000E000 211 #define I2S0_BASE 0x4000F000 212 #define SPDIF0_BASE 0x40010000 213 #define TRANSQW_BASE 0x40011000 214 #define TRANSQD_BASE 0x40012000 215 #define TRNG_BASE 0x40013000 216 #define IRDA_BASE 0x40014000 217 #define I2C2_BASE 0x40015000 218 #define UART3_BASE 0x40016000 219 #define I2S1_BASE 0x40017000 220 #define SEC_ENG_BASE 0x40020000 221 #define TRUST_ZONE_BASE 0X40030000 222 #define MPC_PSRAMUHS_BASE 0x40040000 223 #define SPY_PSRAMUHS_BASE 0x40041000 224 #define MPC_IMEM_LO_A7_BASE 0x40042000 225 #define SPY_IMEM_LO_A7_BASE 0x40043000 226 #define MPC_IMEM_HI_A7_BASE 0x40044000 227 #define SPY_IMEM_HI_A7_BASE 0x40045000 228 #define MPC_PSRAM0_BASE 0x40046000 229 #define SPY_PSRAM0_BASE 0x40047000 230 #define MPC_PSRAM1_BASE 0x40048000 231 #define SPY_PSRAM1_BASE 0x40049000 232 #define MPC_PSRAM_A7_BASE 0x4004A000 233 #define SPY_PSRAM_A7_BASE 0x4004B000 234 #define MPC_FLASH0_BASE 0x4004C000 235 #define SPY_FLASH0_BASE 0x4004D000 236 #define MPC_FLASH1_BASE 0x4004E000 237 #define SPY_FLASH1_BASE 0x4004F000 238 #define MPC_ROM0_BASE 0x40050000 239 #define SPY_ROM0_BASE 0x40051000 240 #define MPC_SRAM0_BASE 0x40052000 241 #define SPY_SRAM0_BASE 0x40053000 242 #define MPC_SRAM1_BASE 0x40054000 243 #define SPY_SRAM1_BASE 0x40055000 244 #define MPC_SRAM2_BASE 0x40056000 245 #define SPY_SRAM2_BASE 0x40057000 246 #define MPC_SRAM3_BASE 0x40058000 247 #define SPY_SRAM3_BASE 0x40059000 248 #define MPC_SRAM4_BASE 0x4005A000 249 #define SPY_SRAM4_BASE 0x4005B000 250 #define MPC_SRAM5_BASE 0x4005C000 251 #define SPY_SRAM5_BASE 0x4005D000 252 253 #define AON_CMU_BASE 0x40080000 254 #define AON_GPIO_BASE 0x40081000 255 #define AON_WDT_BASE 0x40082000 256 #define AON_PWM0_BASE 0x40083000 257 #define AON_TIMER_BASE 0x40084000 258 #define AON_IOMUX_BASE 0x40086000 259 #define AON_PSC_BASE 0x40088000 260 #define AON_PWM1_BASE 0x40089000 261 262 #define CHECKSUM_BASE 0x40100000 263 #define CRC_BASE 0x40108000 264 #define SDMMC_BASE 0x40110000 265 #define BES2003_AUDMA_BASE 0x40120000 266 #define BES2003_GPDMA_BASE 0x40130000 267 #define FLASH_CTRL_BASE 0x40140000 268 #define FLASH1_CTRL_BASE 0x40148000 269 #define PSRAM_CTRL_BASE 0x40150000 270 #define I2C_SLAVE_BASE 0x40160000 271 #define WFDUMP_BASE 0x40170000 272 #define USB_BASE 0x40180000 273 #define SEDMA_BASE 0x401D0000 274 #define BTDUMP_BASE 0x401E0000 275 #define PSRAMUHS_CTRL_BASE 0x401F0000 276 277 #define CODEC_BASE 0x40380000 278 279 #define PATCH_ENTRY_NUM 8 280 #define PATCH_CTRL_BASE 0x000FFE00 281 #define PATCH_DATA_BASE 0x000FFF00 282 #define WIFI_PATCH_CTRL_BASE 0x60040000 283 #define WIFI_PATCH_DATA_BASE 0x60040200 284 285 #define BT_SUBSYS_BASE 0xA0000000 286 #define BT_RAM_BASE 0xC0000000 287 #define BT_RAM_SIZE 0x00008000 288 #define BT_UART_BASE 0xD0300000 289 #define BT_CMU_BASE 0xD0330000 290 291 #define WIFI_SUBSYS_BASE 0x60000000 292 #define WIFI_RAM_BASE 0x80000000 293 #define WIFI_PAS_BASE 0x82000000 294 #define WIFI_TRANSQM_BASE 0x9000A000 295 #define WIFI_CMU_BASE 0x90000000 296 297 #define DSP_SUBSYS_BASE 0x50000000 298 299 #define DSP_BOOT_BASE 0x00000000 300 #define DSP_BOOT_SIZE (24 * 4) 301 302 #define DSP_RAM0_BASE 0x50000000 303 #define DSP_RAM1_BASE 0x50040000 304 #define DSP_RAM2_BASE 0x50080000 305 #define DSP_RAM3_BASE 0x50100000 306 #define DSP_RAM4_BASE 0x50180000 307 #define DSP_RAM5_BASE 0x501C0000 308 #define DSP_RAM_BASE DSP_RAM0_BASE 309 310 #define DSP_RAM5_SIZE 0x00040000 311 312 #define MAX_DSP_RAM_SIZE (DSP_RAM5_BASE + DSP_RAM5_SIZE - DSP_RAM1_BASE) 313 314 #ifndef DSP_RAM_SIZE 315 #ifdef LARGE_DSP_RAM 316 #define DSP_RAM_SIZE MAX_DSP_RAM_SIZE 317 #else /*LARGE_DSP_RAM*/ 318 #ifdef FPGA 319 #define DSP_RAM_SIZE (DSP_RAM1_BASE - DSP_RAM0_BASE) 320 #else /*FPGA*/ 321 #define DSP_RAM_SIZE (DSP_RAM3_BASE - DSP_RAM0_BASE) 322 #endif /*FPGA*/ 323 #endif /*LARGE_DSP_RAM*/ 324 #endif 325 326 #define GPV_MAIN_BASE 0x50300000 327 #define GPV_PSRAM1G_BASE 0x50400000 328 329 #define DSP_BOOT_REG 0x58000000 330 #define DSP_WDT_BASE 0x58001000 331 #define DSP_TIMER0_BASE 0x58002000 332 #define DSP_TIMER1_BASE 0x58003000 333 #define DSP_TRANSQM_BASE 0x58004000 334 #define DSP_TIMESTAMP_GEN_BASE 0x58020000 335 336 #define DSI_BASE 0x58005000 337 #define CSI_BASE 0x58006000 338 #define LCDC_BASE 0x58100000 339 340 #define DSP_DEBUGSYS_APB_BASE 0x58040000 341 342 #define DSP_XDMA_BASE 0x58200000 343 344 #define GIC_DISTRIBUTOR_BASE 0x58301000 345 #define GIC_INTERFACE_BASE 0x58302000 346 347 #define IOMUX_BASE AON_IOMUX_BASE 348 #define GPIO_BASE AON_GPIO_BASE 349 #define PWM_BASE AON_PWM0_BASE 350 #define PWM1_BASE AON_PWM1_BASE 351 352 #ifdef CHIP_BEST2003_DSP 353 #define TIMER0_BASE DSP_TIMER0_BASE 354 #define TIMER1_BASE DSP_TIMER1_BASE 355 #define TRANSQ0_BASE TRANSQW_BASE 356 #define TRANSQ0_PEER_BASE WIFI_TRANSQM_BASE 357 #define TRANSQ1_BASE DSP_TRANSQM_BASE 358 #define TRANSQ1_PEER_BASE TRANSQD_BASE 359 #define WDT_BASE DSP_WDT_BASE 360 #else 361 #define TIMER0_BASE MCU_TIMER0_BASE 362 #define TIMER1_BASE MCU_TIMER1_BASE 363 #define TIMER2_BASE MCU_TIMER2_BASE 364 #define TRANSQ0_BASE TRANSQW_BASE 365 #define TRANSQ0_PEER_BASE WIFI_TRANSQM_BASE 366 #define TRANSQ1_BASE TRANSQD_BASE 367 #define TRANSQ1_PEER_BASE DSP_TRANSQM_BASE 368 #define WDT_BASE AON_WDT_BASE 369 #endif 370 371 #ifndef DSP_USE_GPDMA 372 #define AUDMA_BASE BES2003_AUDMA_BASE 373 #define GPDMA_BASE BES2003_GPDMA_BASE 374 #else /*DSP_USE_GPDMA*/ 375 #ifdef CHIP_BEST2003_DSP 376 #define AUDMA_BASE BES2003_GPDMA_BASE //A7 use GPDMA 377 #else 378 #define AUDMA_BASE BES2003_AUDMA_BASE //MCU use AUDMA 379 #endif 380 #endif /*DSP_USE_GPDMA*/ 381 382 /* For linker scripts */ 383 #define VECTOR_SECTION_SIZE 360 384 #define REBOOT_PARAM_SECTION_SIZE 64 385 #define ROM_BUILD_INFO_SECTION_SIZE 40 386 #define ROM_EXPORT_FN_SECTION_SIZE 128 387 388 #define PSRAMX_TO_PSRAM(d) ((d) - PSRAMX_BASE + PSRAM_BASE) 389 #define PSRAM_TO_PSRAMX(d) ((d) - PSRAM_BASE + PSRAMX_BASE) 390 391 #define PSRAMUHSX_TO_PSRAMUHS(d) ((d) - PSRAMUHSX_BASE + PSRAMUHS_BASE) 392 #define PSRAMUHS_TO_PSRAMUHSX(d) ((d) - PSRAMUHS_BASE + PSRAMUHSX_BASE) 393 394 #define RAMCP_TO_RAMCPX(d) ((d) - (RAMCP_BASE) + (RAMCPX_BASE)) 395 #define RAMCPX_TO_RAMCP(d) ((d) - (RAMCPX_BASE) + (RAMCP_BASE)) 396 397 #define BT_INTESYS_MEM_OFFSET 0x00004000 398 399 /* For module features */ 400 #define I2S_TX_MULTI_CHAN 401 #define I2S_RX_MULTI_CHAN 402 #define SEC_ENG_HAS_HASH 403 404 /* For boot struct version */ 405 #ifndef SECURE_BOOT_VER 406 #define SECURE_BOOT_VER 4 407 #endif 408 409 #ifndef DSP_PSRAMUHS_SIZE 410 #define DSP_PSRAMUHS_SIZE (0) 411 #endif 412 413 #ifndef MCU_PSRAMUHS_SIZE 414 #define MCU_PSRAMUHS_SIZE (0) 415 #endif 416 417 #define DSP_PSRAMUHS_BASE (PSRAMUHS_BASE) 418 #define DSP_PSRAMUHS_NC_BASE (PSRAMUHS_NC_BASE) 419 #define DSP_PSRAMUHSX_BASE (PSRAMUHSX_BASE) 420 421 #define MCU_PSRAMUHS_BASE (PSRAMUHS_BASE + DSP_PSRAMUHS_SIZE) 422 #define MCU_PSRAMUHS_NC_BASE (PSRAMUHS_NC_BASE + DSP_PSRAMUHS_SIZE) 423 #define MCU_PSRAMUHSX_BASE (PSRAMUHSX_BASE + DSP_PSRAMUHS_SIZE) 424 425 #define PSRAMCP_BASE (PSRAM_BASE + PSRAM_SIZE) 426 #define PSRAMCPX_BASE (PSRAMX_BASE + PSRAM_SIZE) 427 428 /* For ROM export functions */ 429 #define NO_MEMMOVE 430 431 #ifdef __cplusplus 432 } 433 #endif 434 435 #endif 436