1 /****************************************************************************** 2 * @file demosoc.h 3 * @brief NMSIS Core Peripheral Access Layer Header File for 4 * Nuclei Demo SoC which support Nuclei N/NX class cores 5 * @version V1.00 6 * @date 22. Nov 2019 7 ******************************************************************************/ 8 /* 9 * Copyright (c) 2019 Nuclei Limited. All rights reserved. 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 #ifndef __DEMOSOC_H__ 27 #define __DEMOSOC_H__ 28 29 #include <stddef.h> 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /** @addtogroup Nuclei 36 * @{ 37 */ 38 39 40 /** @addtogroup demosoc 41 * @{ 42 */ 43 44 45 /** @addtogroup Configuration_of_NMSIS 46 * @{ 47 */ 48 49 50 51 /* =========================================================================================================================== */ 52 /* ================ Interrupt Number Definition ================ */ 53 /* =========================================================================================================================== */ 54 55 typedef enum IRQn { 56 /* ======================================= Nuclei Core Specific Interrupt Numbers ======================================== */ 57 58 Reserved0_IRQn = 0, /*!< Internal reserved */ 59 Reserved1_IRQn = 1, /*!< Internal reserved */ 60 Reserved2_IRQn = 2, /*!< Internal reserved */ 61 SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */ 62 Reserved3_IRQn = 4, /*!< Internal reserved */ 63 Reserved4_IRQn = 5, /*!< Internal reserved */ 64 Reserved5_IRQn = 6, /*!< Internal reserved */ 65 SysTimer_IRQn = 7, /*!< System Timer Interrupt */ 66 Reserved6_IRQn = 8, /*!< Internal reserved */ 67 Reserved7_IRQn = 9, /*!< Internal reserved */ 68 Reserved8_IRQn = 10, /*!< Internal reserved */ 69 Reserved9_IRQn = 11, /*!< Internal reserved */ 70 Reserved10_IRQn = 12, /*!< Internal reserved */ 71 Reserved11_IRQn = 13, /*!< Internal reserved */ 72 Reserved12_IRQn = 14, /*!< Internal reserved */ 73 Reserved13_IRQn = 15, /*!< Internal reserved */ 74 Reserved14_IRQn = 16, /*!< Internal reserved */ 75 Reserved15_IRQn = 17, /*!< Internal reserved */ 76 Reserved16_IRQn = 18, /*!< Internal reserved */ 77 78 /* =========================================== demosoc Specific Interrupt Numbers ========================================= */ 79 /* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported 80 could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s 81 eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */ 82 SOC_INT19_IRQn = 19, /*!< Device Interrupt */ 83 SOC_INT20_IRQn = 20, /*!< Device Interrupt */ 84 SOC_INT21_IRQn = 21, /*!< Device Interrupt */ 85 SOC_INT22_IRQn = 22, /*!< Device Interrupt */ 86 SOC_INT23_IRQn = 23, /*!< Device Interrupt */ 87 SOC_INT24_IRQn = 24, /*!< Device Interrupt */ 88 SOC_INT25_IRQn = 25, /*!< Device Interrupt */ 89 SOC_INT26_IRQn = 26, /*!< Device Interrupt */ 90 SOC_INT27_IRQn = 27, /*!< Device Interrupt */ 91 SOC_INT28_IRQn = 28, /*!< Device Interrupt */ 92 SOC_INT29_IRQn = 29, /*!< Device Interrupt */ 93 SOC_INT30_IRQn = 30, /*!< Device Interrupt */ 94 SOC_INT31_IRQn = 31, /*!< Device Interrupt */ 95 SOC_INT32_IRQn = 32, /*!< Device Interrupt */ 96 SOC_INT33_IRQn = 33, /*!< Device Interrupt */ 97 SOC_INT34_IRQn = 34, /*!< Device Interrupt */ 98 SOC_INT35_IRQn = 35, /*!< Device Interrupt */ 99 SOC_INT36_IRQn = 36, /*!< Device Interrupt */ 100 SOC_INT37_IRQn = 37, /*!< Device Interrupt */ 101 SOC_INT38_IRQn = 38, /*!< Device Interrupt */ 102 SOC_INT39_IRQn = 39, /*!< Device Interrupt */ 103 SOC_INT40_IRQn = 40, /*!< Device Interrupt */ 104 SOC_INT41_IRQn = 41, /*!< Device Interrupt */ 105 SOC_INT42_IRQn = 42, /*!< Device Interrupt */ 106 SOC_INT43_IRQn = 43, /*!< Device Interrupt */ 107 SOC_INT44_IRQn = 44, /*!< Device Interrupt */ 108 SOC_INT45_IRQn = 45, /*!< Device Interrupt */ 109 SOC_INT46_IRQn = 46, /*!< Device Interrupt */ 110 SOC_INT47_IRQn = 47, /*!< Device Interrupt */ 111 SOC_INT48_IRQn = 48, /*!< Device Interrupt */ 112 SOC_INT49_IRQn = 49, /*!< Device Interrupt */ 113 SOC_INT50_IRQn = 50, /*!< Device Interrupt */ 114 SOC_INT_MAX, 115 } IRQn_Type; 116 117 /* =========================================================================================================================== */ 118 /* ================ Exception Code Definition ================ */ 119 /* =========================================================================================================================== */ 120 121 typedef enum EXCn { 122 /* ======================================= Nuclei N/NX Specific Exception Code ======================================== */ 123 InsUnalign_EXCn = 0, /*!< Instruction address misaligned */ 124 InsAccFault_EXCn = 1, /*!< Instruction access fault */ 125 IlleIns_EXCn = 2, /*!< Illegal instruction */ 126 Break_EXCn = 3, /*!< Beakpoint */ 127 LdAddrUnalign_EXCn = 4, /*!< Load address misaligned */ 128 LdFault_EXCn = 5, /*!< Load access fault */ 129 StAddrUnalign_EXCn = 6, /*!< Store or AMO address misaligned */ 130 StAccessFault_EXCn = 7, /*!< Store or AMO access fault */ 131 UmodeEcall_EXCn = 8, /*!< Environment call from User mode */ 132 MmodeEcall_EXCn = 11, /*!< Environment call from Machine mode */ 133 NMI_EXCn = 0xfff, /*!< NMI interrupt */ 134 } EXCn_Type; 135 136 /* =========================================================================================================================== */ 137 /* ================ Processor and Core Peripheral Section ================ */ 138 /* =========================================================================================================================== */ 139 140 /* ToDo: set the defines according your Device */ 141 /* ToDo: define the correct core revision */ 142 #if __riscv_xlen == 32 143 144 #ifndef __NUCLEI_CORE_REV 145 #define __NUCLEI_N_REV 0x0104 /*!< Core Revision r1p4 */ 146 #else 147 #define __NUCLEI_N_REV __NUCLEI_CORE_REV 148 #endif 149 150 #elif __riscv_xlen == 64 151 152 #ifndef __NUCLEI_CORE_REV 153 #define __NUCLEI_NX_REV 0x0100 /*!< Core Revision r1p0 */ 154 #else 155 #define __NUCLEI_NX_REV __NUCLEI_CORE_REV 156 #endif 157 158 #endif /* __riscv_xlen == 64 */ 159 160 /* ToDo: define the correct core features for the demosoc */ 161 #define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */ 162 #define __ECLIC_BASEADDR 0x0C000000UL /*!< Set to ECLIC baseaddr of your device */ 163 164 //#define __ECLIC_INTCTLBITS 3 /*!< Set to 1 - 8, the number of hardware bits are actually implemented in the clicintctl registers. */ 165 #define __ECLIC_INTNUM 51 /*!< Set to 1 - 1024, total interrupt number of ECLIC Unit */ 166 #define __SYSTIMER_PRESENT 1 /*!< Set to 1 if System Timer is present */ 167 #define __SYSTIMER_BASEADDR 0x02000000UL /*!< Set to SysTimer baseaddr of your device */ 168 169 /*!< Set to 0, 1, or 2, 0 not present, 1 single floating point unit present, 2 double floating point unit present */ 170 #if !defined(__riscv_flen) 171 #define __FPU_PRESENT 0 172 #elif __riscv_flen == 32 173 #define __FPU_PRESENT 1 174 #else 175 #define __FPU_PRESENT 2 176 #endif 177 178 #define __DSP_PRESENT 1 /*!< Set to 1 if DSP is present */ 179 #define __PMP_PRESENT 1 /*!< Set to 1 if PMP is present */ 180 #define __PMP_ENTRY_NUM 16 /*!< Set to 8 or 16, the number of PMP entries */ 181 #define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ 182 #define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ 183 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 184 #define __Vendor_EXCEPTION 0 /*!< Set to 1 if vendor exception hander is present */ 185 186 /** @} */ /* End of group Configuration_of_CMSIS */ 187 188 189 #include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */ 190 /* ToDo: include your system_demosoc.h file 191 replace 'Device' with your device name */ 192 #include "system_demosoc.h" /*!< demosoc System */ 193 194 195 /* ======================================== Start of section using anonymous unions ======================================== */ 196 #if defined (__GNUC__) 197 /* anonymous unions are enabled by default */ 198 #else 199 #warning Not supported compiler type 200 #endif 201 202 #define RTC_FREQ 32768 203 // The TIMER frequency is just the RTC frequency 204 #define SOC_TIMER_FREQ RTC_FREQ 205 /* =========================================================================================================================== */ 206 /* ================ Device Specific Peripheral Section ================ */ 207 /* =========================================================================================================================== */ 208 209 210 /** @addtogroup Device_Peripheral_peripherals 211 * @{ 212 */ 213 214 /**************************************************************************** 215 * Platform definitions 216 *****************************************************************************/ 217 // IOF Mappings 218 #define IOF0_SPI1_MASK _AC(0x000007FC,UL) 219 #define SPI11_NUM_SS (4) 220 #define IOF_SPI1_SS0 (2u) 221 #define IOF_SPI1_SS1 (8u) 222 #define IOF_SPI1_SS2 (9u) 223 #define IOF_SPI1_SS3 (10u) 224 #define IOF_SPI1_MOSI (3u) 225 #define IOF_SPI1_MISO (4u) 226 #define IOF_SPI1_SCK (5u) 227 #define IOF_SPI1_DQ0 (3u) 228 #define IOF_SPI1_DQ1 (4u) 229 #define IOF_SPI1_DQ2 (6u) 230 #define IOF_SPI1_DQ3 (7u) 231 232 #define IOF0_SPI2_MASK _AC(0xFC000000,UL) 233 #define SPI2_NUM_SS (1) 234 #define IOF_SPI2_SS0 (26u) 235 #define IOF_SPI2_MOSI (27u) 236 #define IOF_SPI2_MISO (28u) 237 #define IOF_SPI2_SCK (29u) 238 #define IOF_SPI2_DQ0 (27u) 239 #define IOF_SPI2_DQ1 (28u) 240 #define IOF_SPI2_DQ2 (30u) 241 #define IOF_SPI2_DQ3 (31u) 242 243 #define IOF0_UART0_MASK _AC(0x00030000, UL) 244 #define IOF_UART0_RX (16u) 245 #define IOF_UART0_TX (17u) 246 247 #define IOF0_UART1_MASK _AC(0x03000000, UL) 248 #define IOF_UART1_RX (24u) 249 #define IOF_UART1_TX (25u) 250 251 #define IOF0_I2C_MASK _AC(0x00003000, UL) 252 #define IOF_I2C_SDA (12u) 253 #define IOF_I2C_SCL (13u) 254 255 #define IOF1_PWM0_MASK _AC(0x0000000F, UL) 256 #define IOF1_PWM1_MASK _AC(0x00780000, UL) 257 #define IOF1_PWM2_MASK _AC(0x00003C00, UL) 258 259 // Interrupt Numbers 260 #define SOC_ECLIC_NUM_INTERRUPTS 32 261 #define SOC_ECLIC_INT_GPIO_BASE 19 262 263 // Interrupt Handler Definitions 264 #define SOC_MTIMER_HANDLER eclic_mtip_handler 265 #define SOC_SOFTINT_HANDLER eclic_msip_handler 266 267 #define GPIO_BIT_ALL_ZERO (0x0) 268 #define GPIO_BIT_ALL_ONE (0xFFFFFFFF) 269 270 /** 271 * @brief GPIO 272 */ 273 typedef struct { /*!< GPIO Structure */ 274 __IOM uint32_t INPUT_VAL; 275 __IOM uint32_t INPUT_EN; 276 __IOM uint32_t OUTPUT_EN; 277 __IOM uint32_t OUTPUT_VAL; 278 __IOM uint32_t PULLUP_EN; 279 __IOM uint32_t DRIVE; 280 __IOM uint32_t RISE_IE; 281 __IOM uint32_t RISE_IP; 282 __IOM uint32_t FALL_IE; 283 __IOM uint32_t FALL_IP; 284 __IOM uint32_t HIGH_IE; 285 __IOM uint32_t HIGH_IP; 286 __IOM uint32_t LOW_IE; 287 __IOM uint32_t LOW_IP; 288 __IOM uint32_t IOF_EN; 289 __IOM uint32_t IOF_SEL; 290 __IOM uint32_t OUTPUT_XOR; 291 } GPIO_TypeDef; 292 293 /** 294 * @brief UART 295 */ 296 typedef struct { 297 __IOM uint32_t TXFIFO; 298 __IOM uint32_t RXFIFO; 299 __IOM uint32_t TXCTRL; 300 __IOM uint32_t RXCTRL; 301 __IOM uint32_t IE; 302 __IOM uint32_t IP; 303 __IOM uint32_t DIV; 304 } UART_TypeDef; 305 306 /** 307 * @brief PWM 308 */ 309 typedef struct { 310 __IOM uint32_t CFG; 311 uint32_t RESERVED0; 312 __IOM uint32_t COUNT; 313 uint32_t RESERVED1; 314 __IOM uint32_t S; 315 uint32_t RESERVED2[3]; 316 __IOM uint32_t CMP0; 317 __IOM uint32_t CMP1; 318 __IOM uint32_t CMP2; 319 __IOM uint32_t CMP3; 320 } PWM_TypeDef; 321 322 /** 323 * @brief QSPI 324 */ 325 typedef struct { 326 __IOM uint32_t SCKDIV; 327 __IOM uint32_t SCKMODE; 328 __IOM uint32_t RESERVED0[2]; 329 __IOM uint32_t CSID; 330 __IOM uint32_t CSDEF; 331 __IOM uint32_t CSMODE; 332 __IOM uint32_t RESERVED1[3]; 333 __IOM uint32_t DELAY0; 334 __IOM uint32_t DELAY1; 335 __IOM uint32_t RESERVED2[4]; 336 __IOM uint32_t FMT; 337 __IOM uint32_t RESERVED3; 338 __IOM uint32_t TXDATA; 339 __IOM uint32_t RXDATA; 340 __IOM uint32_t TXMARK; 341 __IOM uint32_t RXMARK; 342 __IOM uint32_t RESERVED4[2]; 343 __IOM uint32_t FCTRL; 344 __IOM uint32_t FFMT; 345 __IOM uint32_t RESERVED5[2]; 346 __IOM uint32_t IE; 347 __IOM uint32_t IP; 348 } QSPI_TypeDef; 349 350 /** 351 * @brief I2C 352 */ 353 typedef struct { 354 __IOM uint8_t PRERlo; 355 __IOM uint8_t PRERhi; 356 __IOM uint8_t CTR; 357 __IOM uint8_t TXRXR; /* TXR and RXR in same address */ 358 __IOM uint8_t CSR; /* CR and SR in same address */ 359 } I2C_TypeDef; 360 361 /*@}*/ /* end of group demosoc_Peripherals */ 362 363 364 /* ========================================= End of section using anonymous unions ========================================= */ 365 #if defined (__GNUC__) 366 /* anonymous unions are enabled by default */ 367 #else 368 #warning Not supported compiler type 369 #endif 370 371 372 /* =========================================================================================================================== */ 373 /* ================ Device Specific Peripheral Address Map ================ */ 374 /* =========================================================================================================================== */ 375 376 377 /* ToDo: add here your device peripherals base addresses 378 following is an example for timer */ 379 /** @addtogroup Device_Peripheral_peripheralAddr 380 * @{ 381 */ 382 /* Peripheral and SRAM base address */ 383 #define QSPI_FLASH_BASE (0x20000000UL) /*!< (FLASH ) Base Address */ 384 #define ONCHIP_ROM_BASE (0x00001000UL) /*!< (ROM ) Base Address */ 385 #define ONCHIP_ILM_BASE (0x80000000UL) /*!< (ILM ) Base Address */ 386 #define ONCHIP_DLM_BASE (0x90000000UL) /*!< (DLM ) Base Address */ 387 #define DEMOSOC_PERIPH_BASE (0x10000000UL) /*!< (Peripheral) Base Address */ 388 389 /* Peripheral memory map */ 390 /* Fast-IO Interfaced IP */ 391 #define GPIO_BASE (DEMOSOC_PERIPH_BASE + 0x12000) /*!< (GPIO) Base Address */ 392 /* PPI Interfaced IP */ 393 #define UART0_BASE (DEMOSOC_PERIPH_BASE + 0x13000) /*!< (UART0) Base Address */ 394 #define QSPI0_BASE (DEMOSOC_PERIPH_BASE + 0x14000) /*!< (QSPI0) Base Address */ 395 #define PWM0_BASE (DEMOSOC_PERIPH_BASE + 0x15000) /*!< (PWM0) Base Address */ 396 #define UART1_BASE (DEMOSOC_PERIPH_BASE + 0x23000) /*!< (UART1) Base Address */ 397 #define QSPI1_BASE (DEMOSOC_PERIPH_BASE + 0x24000) /*!< (QSPI1) Base Address */ 398 #define PWM1_BASE (DEMOSOC_PERIPH_BASE + 0x25000) /*!< (PWM1) Base Address */ 399 #define QSPI2_BASE (DEMOSOC_PERIPH_BASE + 0x34000) /*!< (QSPI2) Base Address */ 400 #define PWM2_BASE (DEMOSOC_PERIPH_BASE + 0x35000) /*!< (PWM2) Base Address */ 401 #define I2C_BASE (DEMOSOC_PERIPH_BASE + 0x42000) /*!< (I2C Master) Base Address */ 402 403 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 404 405 406 /* =========================================================================================================================== */ 407 /* ================ Peripheral declaration ================ */ 408 /* =========================================================================================================================== */ 409 410 411 /* ToDo: add here your device peripherals pointer definitions 412 following is an example for timer */ 413 /** @addtogroup Device_Peripheral_declaration 414 * @{ 415 */ 416 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) 417 #define UART0 ((UART_TypeDef *) UART0_BASE) 418 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) 419 #define PWM0 ((PWM_TypeDef *) PWM0_BASE) 420 #define UART1 ((UART_TypeDef *) UART1_BASE) 421 #define QSPI1 ((QSPI_TypeDef *) QSPI1_BASE) 422 #define PWM1 ((PWM_TypeDef *) PWM1_BASE) 423 #define QSPI2 ((QSPI_TypeDef *) QSPI2_BASE) 424 #define PWM2 ((PWM_TypeDef *) PWM2_BASE) 425 #define I2C ((I2C_TypeDef *) I2C_BASE) 426 427 // Helper functions 428 #define _REG8(p, i) (*(volatile uint8_t *) ((p) + (i))) 429 #define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) 430 #define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) 431 432 #define GPIO_REG(offset) _REG32(GPIO_BASE, offset) 433 #define PWM0_REG(offset) _REG32(PWM0_BASE, offset) 434 #define PWM1_REG(offset) _REG32(PWM1_BASE, offset) 435 #define PWM2_REG(offset) _REG32(PWM2_BASE, offset) 436 #define SPI0_REG(offset) _REG32(QSPI0_BASE, offset) 437 #define SPI1_REG(offset) _REG32(QSPI1_BASE, offset) 438 #define SPI2_REG(offset) _REG32(QSPI2_BASE, offset) 439 #define UART0_REG(offset) _REG32(UART0_BASE, offset) 440 #define UART1_REG(offset) _REG32(UART1_BASE, offset) 441 #define I2C_REG(offset) _REG8(I2C_BASE, offset) 442 443 // Misc 444 445 #define NUM_GPIO 32 446 447 uint32_t get_cpu_freq(); 448 void delay_1ms(uint32_t count); 449 450 /** @} */ /* End of group demosoc */ 451 452 /** @} */ /* End of group Nuclei */ 453 454 #ifdef __cplusplus 455 } 456 #endif 457 458 #endif /* __DEMOSOC_H__ */ 459