1 2 #ifndef __PLATFORM_H__ 3 #define __PLATFORM_H__ 4 5 /* fpga memory map */ 6 #define REG_BASE_EMMC0 0xBF3FB000 7 8 #define REG_BASE_USB_OTG 0x10180000 9 #define REG_BASE_USB_OTG_BC 0XBF200000 10 #define REG_BASE_LP_RAM 0x00020000 11 12 #define REG_BASE_UFS_SYS 0xBF3B1000 13 #define REG_BASE_UFS 0xBF3B0000 14 15 #define REG_BASE_PCTRL 0xA8A09000 16 #define REG_BASE_IOC 0xA896C000 17 #define REG_BASE_PMC 0x40231000 18 #define REG_BASE_UART6 0x40232000 19 #define REG_BASE_PERI_CRG 0x40235000 20 #define REG_BASE_LP_TIMER 0x4023E000 21 #define REG_BASE_SCTRL 0x4020A000 22 #define REG_BASE_AO_IOC 0x40211000 23 24 #define REG_BASE_GPIO 0xA8A0B000 /* GPIO0~21 */ 25 #define REG_GPIO(x) (REG_BASE_GPIO + (0x1000 * (x))) 26 #define REG_GPIO22 0x4020B000 27 28 #define LP_RAM_SIZE (96*1024) 29 30 #define REG_BASE_LP_RAM_ACORE 0xFFF50000 31 32 #endif /* end of __PLATFORM_H__ */ 33 34 35