1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2007 Freescale Semiconductor, Inc. 4 * Dave Liu <daveliu@freescale.com> 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * High Level Configuration Options 12 */ 13 #define CONFIG_E300 1 /* E300 family */ 14 15 /* 16 * IP blocks clock configuration 17 */ 18 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 19 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 20 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 21 22 /* 23 * System IO Config 24 */ 25 #define CONFIG_SYS_SICRH 0x00000000 26 #define CONFIG_SYS_SICRL 0x00000000 27 28 /* 29 * Output Buffer Impedance 30 */ 31 #define CONFIG_SYS_OBIR 0x31100000 32 33 #define CONFIG_HWCONFIG 34 35 /* 36 * DDR Setup 37 */ 38 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ 39 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 40 #define CONFIG_SYS_83XX_DDR_USES_CS0 41 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 42 | DDRCDR_ODT \ 43 | DDRCDR_Q_DRN) 44 /* 0x80080001 */ /* ODT 150ohm on SoC */ 45 46 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 47 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 48 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 50 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 51 52 #if defined(CONFIG_SPD_EEPROM) 53 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 54 #else 55 /* 56 * Manually set up DDR parameters 57 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 58 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 59 */ 60 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 61 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 62 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 63 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 64 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 65 | CSCONFIG_ROW_BIT_14 \ 66 | CSCONFIG_COL_BIT_10) 67 /* 0x80010202 */ 68 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 69 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 70 | (0 << TIMING_CFG0_WRT_SHIFT) \ 71 | (0 << TIMING_CFG0_RRT_SHIFT) \ 72 | (0 << TIMING_CFG0_WWT_SHIFT) \ 73 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 74 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 75 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 76 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 77 /* 0x00620802 */ 78 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 79 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 80 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 81 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 82 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 83 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 84 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 85 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 86 /* 0x3935d322 */ 87 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 88 | (6 << TIMING_CFG2_CPO_SHIFT) \ 89 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 90 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 91 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 92 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 93 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 94 /* 0x131088c8 */ 95 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 96 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 97 /* 0x03E00100 */ 98 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 99 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 100 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 101 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 102 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 103 #define CONFIG_SYS_DDR_MODE2 0x00000000 104 #endif 105 106 /* 107 * Memory test 108 */ 109 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 110 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 111 #define CONFIG_SYS_MEMTEST_END 0x00140000 112 113 /* 114 * The reserved memory 115 */ 116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 117 118 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 119 #define CONFIG_SYS_RAMBOOT 120 #else 121 #undef CONFIG_SYS_RAMBOOT 122 #endif 123 124 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 125 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 126 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 127 128 /* 129 * Initial RAM Base Address Setup 130 */ 131 #define CONFIG_SYS_INIT_RAM_LOCK 1 132 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 133 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 134 #define CONFIG_SYS_GBL_DATA_OFFSET \ 135 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 136 137 #define CONFIG_FSL_ELBC 1 138 139 /* 140 * FLASH on the Local Bus 141 */ 142 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 143 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 144 145 146 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 147 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 148 149 #undef CONFIG_SYS_FLASH_CHECKSUM 150 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 151 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 152 153 /* 154 * BCSR on the Local Bus 155 */ 156 #define CONFIG_SYS_BCSR 0xF8000000 157 /* Access window base at BCSR base */ 158 159 /* 160 * NAND Flash on the Local Bus 161 */ 162 #define CONFIG_SYS_MAX_NAND_DEVICE 1 163 #define CONFIG_NAND_FSL_ELBC 1 164 165 #define CONFIG_SYS_NAND_BASE 0xE0600000 166 167 168 /* 169 * Serial Port 170 */ 171 #define CONFIG_SYS_NS16550_SERIAL 172 #define CONFIG_SYS_NS16550_REG_SIZE 1 173 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 174 175 #define CONFIG_SYS_BAUDRATE_TABLE \ 176 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 177 178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 180 181 /* I2C */ 182 #define CONFIG_SYS_I2C 183 #define CONFIG_SYS_I2C_FSL 184 #define CONFIG_SYS_FSL_I2C_SPEED 400000 185 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 186 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 187 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 188 189 /* 190 * Config on-board RTC 191 */ 192 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 193 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 194 195 /* 196 * General PCI 197 * Addresses are mapped 1-1. 198 */ 199 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 200 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 201 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 202 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 203 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 204 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 205 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 206 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 207 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 208 209 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 210 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 211 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 212 213 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 214 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 215 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 216 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 217 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 218 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 219 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 220 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 221 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 222 223 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 224 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 225 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 226 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 227 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 228 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 229 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 230 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 231 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 232 233 #ifdef CONFIG_PCI 234 #define CONFIG_PCI_INDIRECT_BRIDGE 235 #ifndef __ASSEMBLY__ 236 extern int board_pci_host_broken(void); 237 #endif 238 #define CONFIG_PCIE 239 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 240 241 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 242 #define CONFIG_USB_EHCI_FSL 243 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 244 245 #undef CONFIG_EEPRO100 246 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 247 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 248 #endif /* CONFIG_PCI */ 249 250 /* 251 * TSEC 252 */ 253 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 254 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 255 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 256 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 257 258 /* 259 * TSEC ethernet configuration 260 */ 261 #define CONFIG_TSEC1 1 262 #define CONFIG_TSEC1_NAME "eTSEC0" 263 #define CONFIG_TSEC2 1 264 #define CONFIG_TSEC2_NAME "eTSEC1" 265 #define TSEC1_PHY_ADDR 2 266 #define TSEC2_PHY_ADDR 3 267 #define TSEC1_PHY_ADDR_SGMII 8 268 #define TSEC2_PHY_ADDR_SGMII 4 269 #define TSEC1_PHYIDX 0 270 #define TSEC2_PHYIDX 0 271 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 272 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 273 274 /* Options are: TSEC[0-1] */ 275 #define CONFIG_ETHPRIME "eTSEC1" 276 277 /* SERDES */ 278 #define CONFIG_FSL_SERDES 279 #define CONFIG_FSL_SERDES1 0xe3000 280 #define CONFIG_FSL_SERDES2 0xe3100 281 282 /* 283 * SATA 284 */ 285 #define CONFIG_SYS_SATA_MAX_DEVICE 2 286 #define CONFIG_SATA1 287 #define CONFIG_SYS_SATA1_OFFSET 0x18000 288 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 289 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 290 #define CONFIG_SATA2 291 #define CONFIG_SYS_SATA2_OFFSET 0x19000 292 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 293 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 294 295 #ifdef CONFIG_FSL_SATA 296 #define CONFIG_LBA48 297 #endif 298 299 /* 300 * Environment 301 */ 302 303 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 304 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 305 306 /* 307 * BOOTP options 308 */ 309 #define CONFIG_BOOTP_BOOTFILESIZE 310 311 /* 312 * Command line configuration. 313 */ 314 315 #undef CONFIG_WATCHDOG /* watchdog disabled */ 316 317 #ifdef CONFIG_MMC 318 #define CONFIG_FSL_ESDHC_PIN_MUX 319 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 320 #endif 321 322 /* 323 * Miscellaneous configurable options 324 */ 325 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 326 327 /* 328 * For booting Linux, the board info and command line data 329 * have to be in the first 256 MB of memory, since this is 330 * the maximum mapped by the Linux kernel during initialization. 331 */ 332 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 333 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 334 335 #if defined(CONFIG_CMD_KGDB) 336 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 337 #endif 338 339 /* 340 * Environment Configuration 341 */ 342 343 #define CONFIG_ENV_OVERWRITE 344 345 #if defined(CONFIG_TSEC_ENET) 346 #define CONFIG_HAS_ETH0 347 #define CONFIG_HAS_ETH1 348 #endif 349 350 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 351 352 #define CONFIG_EXTRA_ENV_SETTINGS \ 353 "netdev=eth0\0" \ 354 "consoledev=ttyS0\0" \ 355 "ramdiskaddr=1000000\0" \ 356 "ramdiskfile=ramfs.83xx\0" \ 357 "fdtaddr=780000\0" \ 358 "fdtfile=mpc8379_mds.dtb\0" \ 359 "" 360 361 #define CONFIG_NFSBOOTCOMMAND \ 362 "setenv bootargs root=/dev/nfs rw " \ 363 "nfsroot=$serverip:$rootpath " \ 364 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 365 "$netdev:off " \ 366 "console=$consoledev,$baudrate $othbootargs;" \ 367 "tftp $loadaddr $bootfile;" \ 368 "tftp $fdtaddr $fdtfile;" \ 369 "bootm $loadaddr - $fdtaddr" 370 371 #define CONFIG_RAMBOOTCOMMAND \ 372 "setenv bootargs root=/dev/ram rw " \ 373 "console=$consoledev,$baudrate $othbootargs;" \ 374 "tftp $ramdiskaddr $ramdiskfile;" \ 375 "tftp $loadaddr $bootfile;" \ 376 "tftp $fdtaddr $fdtfile;" \ 377 "bootm $loadaddr $ramdiskaddr $fdtaddr" 378 379 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 380 381 #endif /* __CONFIG_H */ 382