1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2011 The Chromium Authors
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <asm/io.h>
9 #include <asm/mrc_common.h>
10 #include <asm/arch/iomap.h>
11 #include <asm/arch/pch.h>
12 #include <asm/arch/pei_data.h>
13
sdram_console_tx_byte(unsigned char byte)14 __weak asmlinkage void sdram_console_tx_byte(unsigned char byte)
15 {
16 #ifdef DEBUG
17 putc(byte);
18 #endif
19 }
20
broadwell_fill_pei_data(struct pei_data * pei_data)21 void broadwell_fill_pei_data(struct pei_data *pei_data)
22 {
23 pei_data->pei_version = PEI_VERSION;
24 pei_data->board_type = BOARD_TYPE_ULT;
25 pei_data->pciexbar = MCFG_BASE_ADDRESS;
26 pei_data->smbusbar = SMBUS_BASE_ADDRESS;
27 pei_data->ehcibar = EARLY_EHCI_BAR;
28 pei_data->xhcibar = EARLY_XHCI_BAR;
29 pei_data->gttbar = EARLY_GTT_BAR;
30 pei_data->pmbase = ACPI_BASE_ADDRESS;
31 pei_data->gpiobase = GPIO_BASE_ADDRESS;
32 pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
33 pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
34 pei_data->tx_byte = sdram_console_tx_byte;
35 pei_data->ddr_refresh_2x = 1;
36 }
37
pei_data_usb2_port(struct pei_data * pei_data,int port,uint length,uint enable,uint oc_pin,uint location)38 static void pei_data_usb2_port(struct pei_data *pei_data, int port, uint length,
39 uint enable, uint oc_pin, uint location)
40 {
41 pei_data->usb2_ports[port].length = length;
42 pei_data->usb2_ports[port].enable = enable;
43 pei_data->usb2_ports[port].oc_pin = oc_pin;
44 pei_data->usb2_ports[port].location = location;
45 }
46
pei_data_usb3_port(struct pei_data * pei_data,int port,uint enable,uint oc_pin,uint fixed_eq)47 static void pei_data_usb3_port(struct pei_data *pei_data, int port, uint enable,
48 uint oc_pin, uint fixed_eq)
49 {
50 pei_data->usb3_ports[port].enable = enable;
51 pei_data->usb3_ports[port].oc_pin = oc_pin;
52 pei_data->usb3_ports[port].fixed_eq = fixed_eq;
53 }
54
mainboard_fill_pei_data(struct pei_data * pei_data)55 void mainboard_fill_pei_data(struct pei_data *pei_data)
56 {
57 /* DQ byte map for Samus board */
58 const u8 dq_map[2][6][2] = {
59 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
60 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
61 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
62 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
63 /* DQS CPU<>DRAM map for Samus board */
64 const u8 dqs_map[2][8] = {
65 { 2, 0, 1, 3, 6, 4, 7, 5 },
66 { 2, 1, 0, 3, 6, 5, 4, 7 } };
67
68 pei_data->ec_present = 1;
69
70 /* One installed DIMM per channel */
71 pei_data->dimm_channel0_disabled = 2;
72 pei_data->dimm_channel1_disabled = 2;
73
74 memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
75 memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
76
77 /* P0: HOST PORT */
78 pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
79 USB_PORT_BACK_PANEL);
80 /* P1: HOST PORT */
81 pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
82 USB_PORT_BACK_PANEL);
83 /* P2: RAIDEN */
84 pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
85 USB_PORT_BACK_PANEL);
86 /* P3: SD CARD */
87 pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
88 USB_PORT_INTERNAL);
89 /* P4: RAIDEN */
90 pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
91 USB_PORT_BACK_PANEL);
92 /* P5: WWAN (Disabled) */
93 pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
94 USB_PORT_SKIP);
95 /* P6: CAMERA */
96 pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
97 USB_PORT_INTERNAL);
98 /* P7: BT */
99 pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
100 USB_PORT_INTERNAL);
101
102 /* P1: HOST PORT */
103 pei_data_usb3_port(pei_data, 0, 1, 0, 0);
104 /* P2: HOST PORT */
105 pei_data_usb3_port(pei_data, 1, 1, 1, 0);
106 /* P3: RAIDEN */
107 pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
108 /* P4: RAIDEN */
109 pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
110 }
111
broadwell_northbridge_early_init(struct udevice * dev)112 static int broadwell_northbridge_early_init(struct udevice *dev)
113 {
114 /* Move earlier? */
115 dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
116 /* 64MiB - 0-63 buses */
117 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
118
119 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
120 dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
121 dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
122 writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
123 writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
124
125 /* Set C0000-FFFFF to access RAM on both reads and writes */
126 dm_pci_write_config8(dev, PAM0, 0x30);
127 dm_pci_write_config8(dev, PAM1, 0x33);
128 dm_pci_write_config8(dev, PAM2, 0x33);
129 dm_pci_write_config8(dev, PAM3, 0x33);
130 dm_pci_write_config8(dev, PAM4, 0x33);
131 dm_pci_write_config8(dev, PAM5, 0x33);
132 dm_pci_write_config8(dev, PAM6, 0x33);
133
134 /* Device enable: IGD and Mini-HD */
135 dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
136
137 return 0;
138 }
139
broadwell_northbridge_probe(struct udevice * dev)140 static int broadwell_northbridge_probe(struct udevice *dev)
141 {
142 if (!(gd->flags & GD_FLG_RELOC))
143 return broadwell_northbridge_early_init(dev);
144
145 return 0;
146 }
147
148 static const struct udevice_id broadwell_northbridge_ids[] = {
149 { .compatible = "intel,broadwell-northbridge" },
150 { }
151 };
152
153 U_BOOT_DRIVER(broadwell_northbridge_drv) = {
154 .name = "broadwell_northbridge",
155 .id = UCLASS_NORTHBRIDGE,
156 .of_match = broadwell_northbridge_ids,
157 .probe = broadwell_northbridge_probe,
158 };
159