1 /* 2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __RK_VENC_CMD_H__ 17 #define __RK_VENC_CMD_H__ 18 19 #include "mpp_frame.h" 20 #include "rk_venc_rc.h" 21 22 /* 23 * Configure of encoder is very complicated. So we divide configures into 24 * four parts: 25 * 26 * 1. Rate control parameter 27 * This is quality and bitrate request from user. 28 * 29 * 2. Data source MppFrame parameter 30 * This is data source buffer information. 31 * Now it is PreP config 32 * PreP : Encoder Preprocess configuration 33 * 34 * 3. Video codec infomation 35 * This is user custormized stream information. 36 * including: 37 * H.264 / H.265 / vp8 / mjpeg 38 * 39 * 4. Misc parameter 40 * including: 41 * Split : Slice split configuration 42 * GopRef: Reference gop configuration 43 * ROI : Region Of Interest 44 * OSD : On Screen Display 45 * MD : Motion Detection 46 * 47 * The module transcation flow is as follows: 48 * 49 * + + 50 * User | Mpi/Mpp | EncImpl 51 * | | Hal 52 * | | 53 * +----------+ | +---------+ | +-----------+ 54 * | | | | +-----RcCfg-----> | 55 * | RcCfg +---------> | | | EncImpl | 56 * | | | | | +-Frame-----> | 57 * +----------+ | | | | | +--+-----^--+ 58 * | | | | | | | 59 * | | | | | | | 60 * +----------+ | | | | | syntax | 61 * | | | | | | | | | 62 * | MppFrame +---------> MppEnc +---+ | | result 63 * | | | | | | | | | 64 * +----------+ | | | | | | | 65 * | | | | | +--v-----+--+ 66 * | | | +-Frame-----> | 67 * +----------+ | | | | | | 68 * | | | | +---CodecCfg----> Hal | 69 * | CodecCfg +---------> | | | | 70 * | | | | <-----Extra-----> | 71 * +----------+ | +---------+ | +-----------+ 72 * | | 73 * | | 74 * + + 75 * 76 * The function call flow is shown below: 77 * 78 * mpi mpp_enc controller hal 79 * + + + + 80 * | | | | 81 * | | | | 82 * +----------init------------> | | 83 * | | | | 84 * | | | | 85 * | PrepCfg | | | 86 * +---------control----------> PrepCfg | | 87 * | +-----control-----> | 88 * | | | PrepCfg | 89 * | +--------------------------control--------> 90 * | | | allocate 91 * | | | buffer 92 * | | | | 93 * | RcCfg | | | 94 * +---------control----------> RcCfg | | 95 * | +-----control-----> | 96 * | | rc_init | 97 * | | | | 98 * | | | | 99 * | CodecCfg | | | 100 * +---------control----------> | CodecCfg | 101 * | +--------------------------control--------> 102 * | | | generate 103 * | | | sps/pps 104 * | | | Get extra info | 105 * | +--------------------------control--------> 106 * | Get extra info | | | 107 * +---------control----------> | | 108 * | | | | 109 * | | | | 110 * | ROICfg | | | 111 * +---------control----------> | ROICfg | 112 * | +--------------------------control--------> 113 * | | | | 114 * | OSDCfg | | | 115 * +---------control----------> | OSDCfg | 116 * | +--------------------------control--------> 117 * | | | | 118 * | MDCfg | | | 119 * +---------control----------> | MDCfg | 120 * | +--------------------------control--------> 121 * | | | | 122 * | Set extra info | | | 123 * +---------control----------> | Set extra info | 124 * | +--------------------------control--------> 125 * | | | | 126 * | task | | | 127 * +----------encode----------> task | | 128 * | +-----encode------> | 129 * | | encode | 130 * | | | syntax | 131 * | +--------------------------gen_reg--------> 132 * | | | | 133 * | | | | 134 * | +---------------------------start---------> 135 * | | | | 136 * | | | | 137 * | +---------------------------wait----------> 138 * | | | | 139 * | | callback | | 140 * | +-----------------> | 141 * +--OSD-MD--encode----------> | | 142 * | . | | | 143 * | . | | | 144 * | . | | | 145 * +--OSD-MD--encode----------> | | 146 * | | | | 147 * +----------deinit----------> | | 148 * + + + + 149 */ 150 151 /* 152 * base working mode parameter 153 */ 154 typedef enum MppEncBaseCfgChange_e { 155 MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY = (1 << 0), 156 MPP_ENC_BASE_CFG_CHANGE_ALL = (0xFFFFFFFF), 157 } MppEncBaseCfgChange; 158 159 typedef struct MppEncBaseCfg_t { 160 RK_U32 change; 161 162 RK_S32 low_delay; 163 } MppEncBaseCfg; 164 165 /* 166 * Rate control parameter 167 */ 168 typedef enum MppEncRcCfgChange_e { 169 MPP_ENC_RC_CFG_CHANGE_RC_MODE = (1 << 0), 170 MPP_ENC_RC_CFG_CHANGE_QUALITY = (1 << 1), 171 MPP_ENC_RC_CFG_CHANGE_BPS = (1 << 2), /* change on bps target / max / min */ 172 MPP_ENC_RC_CFG_CHANGE_FPS_IN = (1 << 5), /* change on fps in flex / numerator / denorminator */ 173 MPP_ENC_RC_CFG_CHANGE_FPS_OUT = (1 << 6), /* change on fps out flex / numerator / denorminator */ 174 MPP_ENC_RC_CFG_CHANGE_GOP = (1 << 7), 175 MPP_ENC_RC_CFG_CHANGE_SKIP_CNT = (1 << 8), 176 MPP_ENC_RC_CFG_CHANGE_MAX_REENC = (1 << 9), 177 MPP_ENC_RC_CFG_CHANGE_DROP_FRM = (1 << 10), 178 MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP = (1 << 11), 179 MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP = (1 << 12), 180 MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO = (1 << 13), 181 MPP_ENC_RC_CFG_CHANGE_PRIORITY = (1 << 14), 182 MPP_ENC_RC_CFG_CHANGE_SUPER_FRM = (1 << 15), 183 /* qp related change flag */ 184 MPP_ENC_RC_CFG_CHANGE_QP_INIT = (1 << 16), 185 MPP_ENC_RC_CFG_CHANGE_QP_RANGE = (1 << 17), 186 MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I = (1 << 18), 187 MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP = (1 << 19), 188 MPP_ENC_RC_CFG_CHANGE_QP_IP = (1 << 20), 189 MPP_ENC_RC_CFG_CHANGE_QP_VI = (1 << 21), 190 MPP_ENC_RC_CFG_CHANGE_QP_ROW = (1 << 22), 191 MPP_ENC_RC_CFG_CHANGE_QP_ROW_I = (1 << 23), 192 MPP_ENC_RC_CFG_CHANGE_DEBREATH = (1 << 24), 193 MPP_ENC_RC_CFG_CHANGE_HIER_QP = (1 << 25), 194 MPP_ENC_RC_CFG_CHANGE_ST_TIME = (1 << 26), 195 MPP_ENC_RC_CFG_CHANGE_ALL = (0xFFFFFFFF), 196 } MppEncRcCfgChange; 197 198 typedef enum MppEncRcQuality_e { 199 MPP_ENC_RC_QUALITY_WORST, 200 MPP_ENC_RC_QUALITY_WORSE, 201 MPP_ENC_RC_QUALITY_MEDIUM, 202 MPP_ENC_RC_QUALITY_BETTER, 203 MPP_ENC_RC_QUALITY_BEST, 204 MPP_ENC_RC_QUALITY_CQP, 205 MPP_ENC_RC_QUALITY_AQ_ONLY, 206 MPP_ENC_RC_QUALITY_BUTT 207 } MppEncRcQuality; 208 209 typedef struct MppEncRcCfg_t { 210 RK_U32 change; 211 212 /* 213 * rc_mode - rate control mode 214 * 215 * mpp provide two rate control mode: 216 * 217 * Constant Bit Rate (CBR) mode 218 * - paramter 'bps*' define target bps 219 * - paramter quality and qp will not take effect 220 * 221 * Variable Bit Rate (VBR) mode 222 * - paramter 'quality' define 5 quality levels 223 * - paramter 'bps*' is used as reference but not strict condition 224 * - special Constant QP (CQP) mode is under VBR mode 225 * CQP mode will work with qp in CodecCfg. But only use for test 226 * 227 * default: CBR 228 */ 229 MppEncRcMode rc_mode; 230 231 /* 232 * quality - quality parameter, only takes effect in VBR mode 233 * 234 * Mpp does not give the direct parameter in different protocol. 235 * 236 * Mpp provide total 5 quality level: 237 * Worst - worse - Medium - better - best 238 * 239 * extra CQP level means special constant-qp (CQP) mode 240 * 241 * default value: Medium 242 */ 243 MppEncRcQuality quality; 244 245 /* 246 * bit rate parameters 247 * mpp gives three bit rate control parameter for control 248 * bps_target - target bit rate, unit: bit per second 249 * bps_max - maximun bit rate, unit: bit per second 250 * bps_min - minimun bit rate, unit: bit per second 251 * if user need constant bit rate set parameters to the similar value 252 * if user need variable bit rate set parameters as they need 253 */ 254 RK_S32 bps_target; 255 RK_S32 bps_max; 256 RK_S32 bps_min; 257 258 /* 259 * frame rate parameters have great effect on rate control 260 * 261 * fps_in_flex 262 * 0 - fix input frame rate 263 * 1 - variable input frame rate 264 * 265 * fps_in_num 266 * input frame rate numerator, if 0 then default 30 267 * 268 * fps_in_denorm 269 * input frame rate denorminator, if 0 then default 1 270 * 271 * fps_out_flex 272 * 0 - fix output frame rate 273 * 1 - variable output frame rate 274 * 275 * fps_out_num 276 * output frame rate numerator, if 0 then default 30 277 * 278 * fps_out_denorm 279 * output frame rate denorminator, if 0 then default 1 280 */ 281 RK_S32 fps_in_flex; 282 RK_S32 fps_in_num; 283 RK_S32 fps_in_denorm; 284 RK_S32 fps_out_flex; 285 RK_S32 fps_out_num; 286 RK_S32 fps_out_denorm; 287 288 /* 289 * gop - group of picture, gap between Intra frame 290 * 0 for only 1 I frame the rest are all P frames 291 * 1 for all I frame 292 * 2 for I P I P I P 293 * 3 for I P P I P P 294 * etc... 295 */ 296 RK_S32 gop; 297 298 /* 299 * skip_cnt - max continuous frame skip count 300 * 0 - frame skip is not allow 301 */ 302 RK_S32 skip_cnt; 303 304 /* 305 * max_reenc_times - max reencode time for one frame 306 * 0 - reencode is not allowed 307 * 1~3 max reencode time is limited to 3 308 */ 309 RK_U32 max_reenc_times; 310 311 /* 312 * stats_time - the time of bitrate statistics 313 */ 314 RK_S32 stats_time; 315 316 /* 317 * drop frame parameters 318 * used on bitrate is far over the max bitrate 319 * 320 * drop_mode 321 * 322 * MPP_ENC_RC_DROP_FRM_DISABLED 323 * - do not drop frame when bitrate overflow. 324 * MPP_ENC_RC_DROP_FRM_NORMAL 325 * - do not encode the dropped frame when bitrate overflow. 326 * MPP_ENC_RC_DROP_FRM_PSKIP 327 * - encode a all skip frame when bitrate overflow. 328 * 329 * drop_threshold 330 * 331 * The percentage threshold over max_bitrate for trigger frame drop. 332 * 333 * drop_gap 334 * The max continuous frame drop number 335 */ 336 MppEncRcDropFrmMode drop_mode; 337 RK_U32 drop_threshold; 338 RK_U32 drop_gap; 339 340 MppEncRcSuperFrameMode super_mode; 341 RK_U32 super_i_thd; 342 RK_U32 super_p_thd; 343 344 MppEncRcPriority rc_priority; 345 346 RK_U32 debreath_en; 347 RK_U32 debre_strength; 348 RK_S32 max_i_prop; 349 RK_S32 min_i_prop; 350 RK_S32 init_ip_ratio; 351 352 /* general qp control */ 353 RK_S32 qp_init; 354 RK_S32 qp_max; 355 RK_S32 qp_max_i; 356 RK_S32 qp_min; 357 RK_S32 qp_min_i; 358 RK_S32 qp_max_step; /* delta qp between each two P frame */ 359 RK_S32 qp_delta_ip; /* delta qp between I and P */ 360 RK_S32 qp_delta_vi; /* delta qp between vi and P */ 361 362 RK_S32 hier_qp_en; 363 RK_S32 hier_qp_delta[4]; 364 RK_S32 hier_frame_num[4]; 365 } MppEncRcCfg; 366 367 368 typedef enum MppEncHwCfgChange_e { 369 /* qp related hardware config flag */ 370 MPP_ENC_HW_CFG_CHANGE_QP_ROW = (1 << 0), 371 MPP_ENC_HW_CFG_CHANGE_QP_ROW_I = (1 << 1), 372 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I = (1 << 2), 373 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3), 374 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4), 375 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5), 376 MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF), 377 } MppEncHwCfgChange; 378 379 /* 380 * Hardware related rate control config 381 * 382 * This config will open some detail feature to external user to control 383 * hardware behavior directly. 384 */ 385 typedef struct MppEncHwCfg_t { 386 RK_U32 change; 387 388 /* vepu541/vepu540 */ 389 RK_S32 qp_delta_row; /* delta qp between two row in P frame */ 390 RK_S32 qp_delta_row_i; /* delta qp between two row in I frame */ 391 RK_U32 aq_thrd_i[16]; 392 RK_U32 aq_thrd_p[16]; 393 RK_S32 aq_step_i[16]; 394 RK_S32 aq_step_p[16]; 395 } MppEncHwCfg; 396 397 /* 398 * Mpp preprocess parameter 399 */ 400 typedef enum MppEncPrepCfgChange_e { 401 MPP_ENC_PREP_CFG_CHANGE_INPUT = (1 << 0), /* change on input config */ 402 MPP_ENC_PREP_CFG_CHANGE_FORMAT = (1 << 2), /* change on format */ 403 /* transform parameter */ 404 MPP_ENC_PREP_CFG_CHANGE_ROTATION = (1 << 4), /* change on ration */ 405 MPP_ENC_PREP_CFG_CHANGE_MIRRORING = (1 << 5), /* change on mirroring */ 406 /* enhancement parameter */ 407 MPP_ENC_PREP_CFG_CHANGE_DENOISE = (1 << 8), /* change on denoise */ 408 MPP_ENC_PREP_CFG_CHANGE_SHARPEN = (1 << 9), /* change on denoise */ 409 /* color related parameter */ 410 MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE = (1 << 16), /* change on color range */ 411 MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE = (1 << 17), /* change on color range */ 412 MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME = (1 << 18), /* change on color primaries */ 413 MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC = (1 << 19), /* change on color transfer */ 414 415 MPP_ENC_PREP_CFG_CHANGE_ALL = (0xFFFFFFFF), 416 } MppEncPrepCfgChange; 417 418 /* 419 * Preprocess sharpen parameter 420 * 421 * 5x5 sharpen core 422 * 423 * enable_y - enable luma sharpen 424 * enable_uv - enable chroma sharpen 425 */ 426 typedef struct { 427 RK_U32 enable_y; 428 RK_U32 enable_uv; 429 RK_S32 coef[5]; 430 RK_S32 div; 431 RK_S32 threshold; 432 } MppEncPrepSharpenCfg; 433 434 /* 435 * input frame rotation parameter 436 * 0 - disable rotation 437 * 1 - 90 degree 438 * 2 - 180 degree 439 * 3 - 270 degree 440 */ 441 typedef enum MppEncRotationCfg_e { 442 MPP_ENC_ROT_0, 443 MPP_ENC_ROT_90, 444 MPP_ENC_ROT_180, 445 MPP_ENC_ROT_270, 446 MPP_ENC_ROT_BUTT 447 } MppEncRotationCfg; 448 449 typedef struct MppEncPrepCfg_t { 450 RK_U32 change; 451 452 /* 453 * Mpp encoder input data dimension config 454 * 455 * width / height / hor_stride / ver_stride / format 456 * These information will be used for buffer allocation and rc config init 457 * The output format is always YUV420. So if input is RGB then color 458 * conversion will be done internally 459 */ 460 RK_S32 width; 461 RK_S32 height; 462 RK_S32 hor_stride; 463 RK_S32 ver_stride; 464 465 /* 466 * Mpp encoder input data format config 467 */ 468 MppFrameFormat format; 469 MppFrameColorSpace color; 470 MppFrameColorPrimaries colorprim; 471 MppFrameColorTransferCharacteristic colortrc; 472 MppFrameColorRange range; 473 474 MppEncRotationCfg rotation; 475 476 /* 477 * input frame mirroring parameter 478 * 0 - disable mirroring 479 * 1 - horizontal mirroring 480 * 2 - vertical mirroring 481 */ 482 RK_S32 mirroring; 483 484 RK_S32 denoise; 485 486 MppEncPrepSharpenCfg sharpen; 487 } MppEncPrepCfg; 488 489 /* 490 * Mpp Motion Detection parameter 491 * 492 * Mpp can output Motion Detection infomation for each frame. 493 * If user euqueue a encode task with KEY_MOTION_INFO by following function 494 * then encoder will output Motion Detection information to the buffer. 495 * 496 * mpp_task_meta_set_buffer(task, KEY_MOTION_INFO, buffer); 497 * 498 * Motion Detection information will be organized in this way: 499 * 1. Each 16x16 block will have a 32 bit block information which contains 500 * 15 bit SAD(Sum of Abstract Difference value 501 * 9 bit signed horizontal motion vector 502 * 8 bit signed vertical motion vector 503 * 2. The sequence of MD information in the buffer is corresponding to the 504 * block position in the frame, left-to right, top-to-bottom. 505 * 3. If the width of the frame is not a multiple of 256 pixels (16 macro 506 * blocks), DMA would extend the frame to a multiple of 256 pixels and 507 * the extended blocks' MD information are 32'h0000_0000. 508 * 4. Buffer must be ion buffer and 1024 byte aligned. 509 */ 510 typedef struct MppEncMDBlkInfo_t { 511 RK_U32 sad : 15; /* bit 0~14 - SAD */ 512 RK_S32 mvx : 9; /* bit 15~23 - signed horizontal mv */ 513 RK_S32 mvy : 8; /* bit 24~31 - signed vertical mv */ 514 } MppEncMDBlkInfo; 515 516 typedef enum MppEncHeaderMode_e { 517 /* default mode: attach vps/sps/pps only on first frame */ 518 MPP_ENC_HEADER_MODE_DEFAULT, 519 /* IDR mode: attach vps/sps/pps on each IDR frame */ 520 MPP_ENC_HEADER_MODE_EACH_IDR, 521 MPP_ENC_HEADER_MODE_BUTT, 522 } MppEncHeaderMode; 523 524 typedef enum MppEncSeiMode_e { 525 MPP_ENC_SEI_MODE_DISABLE, /* default mode, SEI writing is disabled */ 526 MPP_ENC_SEI_MODE_ONE_SEQ, /* one sequence has only one SEI */ 527 MPP_ENC_SEI_MODE_ONE_FRAME /* one frame may have one SEI, if SEI info has changed */ 528 } MppEncSeiMode; 529 530 /* 531 * Mpp codec parameter 532 * parameter is defined from here 533 */ 534 535 /* 536 * H.264 configurable parameter 537 */ 538 typedef enum MppEncH264CfgChange_e { 539 /* change on stream type */ 540 MPP_ENC_H264_CFG_STREAM_TYPE = (1 << 0), 541 /* change on svc / profile / level */ 542 MPP_ENC_H264_CFG_CHANGE_PROFILE = (1 << 1), 543 /* change on entropy_coding_mode / cabac_init_idc */ 544 MPP_ENC_H264_CFG_CHANGE_ENTROPY = (1 << 2), 545 546 /* change on transform8x8_mode */ 547 MPP_ENC_H264_CFG_CHANGE_TRANS_8x8 = (1 << 4), 548 /* change on constrained_intra_pred_mode */ 549 MPP_ENC_H264_CFG_CHANGE_CONST_INTRA = (1 << 5), 550 /* change on chroma_cb_qp_offset/ chroma_cr_qp_offset */ 551 MPP_ENC_H264_CFG_CHANGE_CHROMA_QP = (1 << 6), 552 /* change on deblock_disable / deblock_offset_alpha / deblock_offset_beta */ 553 MPP_ENC_H264_CFG_CHANGE_DEBLOCKING = (1 << 7), 554 /* change on use_longterm */ 555 MPP_ENC_H264_CFG_CHANGE_LONG_TERM = (1 << 8), 556 /* change on scaling_list_mode */ 557 MPP_ENC_H264_CFG_CHANGE_SCALING_LIST = (1 << 9), 558 /* change on poc type */ 559 MPP_ENC_H264_CFG_CHANGE_POC_TYPE = (1 << 10), 560 /* change on log2 max poc lsb minus 4 */ 561 MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB = (1 << 11), 562 /* change on log2 max frame number minus 4 */ 563 MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM = (1 << 12), 564 /* change on gaps_in_frame_num_value_allowed_flag */ 565 MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM = (1 << 13), 566 567 /* change on max_qp / min_qp */ 568 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT = (1 << 16), 569 /* change on max_qp_i / min_qp_i */ 570 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT_I = (1 << 17), 571 /* change on max_qp_step */ 572 MPP_ENC_H264_CFG_CHANGE_MAX_QP_STEP = (1 << 18), 573 /* change on qp_delta_ip */ 574 MPP_ENC_H264_CFG_CHANGE_QP_DELTA = (1 << 19), 575 /* change on intra_refresh_mode / intra_refresh_arg */ 576 MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH = (1 << 20), 577 /* change on max long-term reference frame count */ 578 MPP_ENC_H264_CFG_CHANGE_MAX_LTR = (1 << 21), 579 /* change on max temporal id */ 580 MPP_ENC_H264_CFG_CHANGE_MAX_TID = (1 << 22), 581 /* change on adding prefix nal */ 582 MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX = (1 << 23), 583 /* change on base layer priority id */ 584 MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID = (1 << 24), 585 586 /* change on vui */ 587 MPP_ENC_H264_CFG_CHANGE_VUI = (1 << 28), 588 MPP_ENC_H264_CFG_CHANGE_ALL = (0xFFFFFFFF), 589 } MppEncH264CfgChange; 590 591 typedef struct MppEncH264Cfg_t { 592 RK_U32 change; 593 594 /* 595 * H.264 stream format 596 * 0 - H.264 Annex B: NAL unit starts with '00 00 00 01' 597 * 1 - Plain NAL units without startcode 598 */ 599 RK_S32 stream_type; 600 601 /* 602 * H.264 codec syntax config 603 * 604 * do NOT setup the three option below unless you are familiar with encoder detail 605 * poc_type - picture order count type 0 ~ 2 606 * log2_max_poc_lsb - used in sps with poc_type 0, 607 * log2_max_frame_num - used in sps 608 */ 609 RK_U32 poc_type; 610 RK_U32 log2_max_poc_lsb; 611 RK_U32 log2_max_frame_num; 612 RK_U32 gaps_not_allowed; 613 614 /* 615 * H.264 profile_idc parameter 616 * 66 - Baseline profile 617 * 77 - Main profile 618 * 100 - High profile 619 */ 620 RK_S32 profile; 621 622 /* 623 * H.264 level_idc parameter 624 * 10 / 11 / 12 / 13 - qcif@15fps / cif@7.5fps / cif@15fps / cif@30fps 625 * 20 / 21 / 22 - cif@30fps / half-D1@@25fps / D1@12.5fps 626 * 30 / 31 / 32 - D1@25fps / 720p@30fps / 720p@60fps 627 * 40 / 41 / 42 - 1080p@30fps / 1080p@30fps / 1080p@60fps 628 * 50 / 51 / 52 - 4K@30fps 629 */ 630 RK_S32 level; 631 632 /* 633 * H.264 entropy coding method 634 * 0 - CAVLC 635 * 1 - CABAC 636 * When CABAC is select cabac_init_idc can be range 0~2 637 */ 638 RK_S32 entropy_coding_mode; 639 RK_S32 cabac_init_idc; 640 641 /* 642 * 8x8 intra prediction and 8x8 transform enable flag 643 * This flag can only be enable under High profile 644 * 0 : disable (BP/MP) 645 * 1 : enable (HP) 646 */ 647 RK_S32 transform8x8_mode; 648 649 /* 650 * 0 : disable 651 * 1 : enable 652 */ 653 RK_S32 constrained_intra_pred_mode; 654 655 /* 656 * 0 : flat scaling list 657 * 1 : default scaling list for all cases 658 * 2 : customized scaling list (not supported) 659 */ 660 RK_S32 scaling_list_mode; 661 662 /* 663 * chroma qp offset (-12 - 12) 664 */ 665 RK_S32 chroma_cb_qp_offset; 666 RK_S32 chroma_cr_qp_offset; 667 668 /* 669 * H.264 deblock filter mode flag 670 * 0 : enable 671 * 1 : disable 672 * 2 : disable deblocking filter at slice boundaries 673 * 674 * deblock filter offset alpha (-6 - 6) 675 * deblock filter offset beta (-6 - 6) 676 */ 677 RK_S32 deblock_disable; 678 RK_S32 deblock_offset_alpha; 679 RK_S32 deblock_offset_beta; 680 681 /* 682 * H.264 long term reference picture enable flag 683 * 0 - disable 684 * 1 - enable 685 */ 686 RK_S32 use_longterm; 687 688 /* 689 * quality config 690 * qp_max - 8 ~ 51 691 * qp_max_i - 10 ~ 40 692 * qp_min - 8 ~ 48 693 * qp_min_i - 10 ~ 40 694 * qp_max_step - max delta qp step between two frames 695 */ 696 RK_S32 qp_init; 697 RK_S16 qp_max; 698 RK_S16 qp_max_i; 699 RK_S16 qp_min; 700 RK_S16 qp_min_i; 701 RK_S16 qp_max_step; 702 RK_S16 qp_delta_ip; 703 704 /* 705 * intra fresh config 706 * 707 * intra_refresh_mode 708 * 0 - no intra refresh 709 * 1 - intra refresh by MB row 710 * 2 - intra refresh by MB column 711 * 3 - intra refresh by MB gap 712 * 713 * intra_refresh_arg 714 * mode 0 - no effect 715 * mode 1 - refresh MB row number 716 * mode 2 - refresh MB colmn number 717 * mode 3 - refresh MB gap count 718 */ 719 RK_S32 intra_refresh_mode; 720 RK_S32 intra_refresh_arg; 721 722 /* extra mode config */ 723 RK_S32 max_ltr_frames; 724 RK_S32 max_tid; 725 RK_S32 prefix_mode; 726 RK_S32 base_layer_pid; 727 } MppEncH264Cfg; 728 729 #define H265E_MAX_ROI_NUMBER 64 730 731 typedef struct H265eRect_t { 732 RK_S32 left; 733 RK_S32 right; 734 RK_S32 top; 735 RK_S32 bottom; 736 } H265eRect; 737 738 typedef struct H265eRoi_Region_t { 739 RK_U8 level; 740 H265eRect rect; 741 } H265eRoiRegion; 742 743 /* 744 * roi region only can be setting when rc_enable = 1 745 */ 746 typedef struct MppEncH265RoiCfg_t { 747 /* 748 * the value is defined by H265eCtuMethod 749 */ 750 751 RK_U8 method; 752 /* 753 * the number of roi,the value must less than H265E_MAX_ROI_NUMBER 754 */ 755 RK_S32 num; 756 757 /* delat qp using in roi region */ 758 RK_U32 delta_qp; 759 760 /* roi region */ 761 H265eRoiRegion region[H265E_MAX_ROI_NUMBER]; 762 } MppEncH265RoiCfg; 763 764 typedef struct H265eCtuQp_t { 765 /* the qp value using in ctu region */ 766 RK_U32 qp; 767 768 /* 769 * define the ctu region 770 * method = H265E_METHOD_CUT_SIZE, the value of rect is in ctu size 771 * method = H264E_METHOD_COORDINATE,the value of rect is in coordinates 772 */ 773 H265eRect rect; 774 } H265eCtu; 775 776 typedef struct H265eCtuRegion_t { 777 /* 778 * the value is defined by H265eCtuMethod 779 */ 780 RK_U8 method; 781 782 /* 783 * the number of ctu,the value must less than H265E_MAX_ROI_NUMBER 784 */ 785 RK_S32 num; 786 787 /* ctu region */ 788 H265eCtu ctu[H265E_MAX_ROI_NUMBER]; 789 } MppEncH265CtuCfg; 790 791 /* 792 * define the method when set CTU/ROI parameters 793 * this value is using by method in H265eCtuRegion or H265eRoi struct 794 */ 795 typedef enum { 796 H265E_METHOD_CTU_SIZE, 797 H264E_METHOD_COORDINATE, 798 } H265eCtuMethod; 799 800 /* 801 * H.265 configurable parameter 802 */ 803 typedef struct MppEncH265VuiCfg_t { 804 RK_U32 change; 805 RK_S32 vui_present; 806 RK_S32 vui_aspect_ratio; 807 RK_S32 vui_sar_size; 808 RK_S32 full_range; 809 RK_S32 time_scale; 810 } MppEncH265VuiCfg; 811 812 typedef enum MppEncH265CfgChange_e { 813 /* change on stream type */ 814 MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE = (1 << 0), 815 MPP_ENC_H265_CFG_INTRA_QP_CHANGE = (1 << 1), 816 MPP_ENC_H265_CFG_FRAME_RATE_CHANGE = (1 << 2), 817 MPP_ENC_H265_CFG_BITRATE_CHANGE = (1 << 3), 818 MPP_ENC_H265_CFG_GOP_SIZE = (1 << 4), 819 MPP_ENC_H265_CFG_RC_QP_CHANGE = (1 << 5), 820 MPP_ENC_H265_CFG_INTRA_REFRESH_CHANGE = (1 << 6), 821 MPP_ENC_H265_CFG_INDEPEND_SLICE_CHANGE = (1 << 7), 822 MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8), 823 MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9), 824 MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10), 825 MPP_ENC_H265_CFG_CU_CHANGE = (1 << 11), 826 MPP_ENC_H265_CFG_DBLK_CHANGE = (1 << 12), 827 MPP_ENC_H265_CFG_SAO_CHANGE = (1 << 13), 828 MPP_ENC_H265_CFG_TRANS_CHANGE = (1 << 14), 829 MPP_ENC_H265_CFG_SLICE_CHANGE = (1 << 15), 830 MPP_ENC_H265_CFG_ENTROPY_CHANGE = (1 << 16), 831 MPP_ENC_H265_CFG_MERGE_CHANGE = (1 << 17), 832 MPP_ENC_H265_CFG_CHANGE_VUI = (1 << 18), 833 MPP_ENC_H265_CFG_RC_I_QP_CHANGE = (1 << 19), 834 MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE = (1 << 21), 835 MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE = (1 << 20), 836 MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF), 837 } MppEncH265CfgChange; 838 839 typedef struct MppEncH265SliceCfg_t { 840 /* default value: 0, means no slice split */ 841 RK_U32 split_enable; 842 843 /* 0: by bits number; 1: by lcu line number */ 844 RK_U32 split_mode; 845 846 /* 847 * when splitmode is 0, this value presents bits number, 848 * when splitmode is 1, this value presents lcu line number 849 */ 850 RK_U32 slice_size; 851 RK_U32 loop_filter_across_slices_enabled_flag; 852 } MppEncH265SliceCfg; 853 854 typedef struct MppEncH265CuCfg_t { 855 RK_U32 cu32x32_en; /* default: 1 */ 856 RK_U32 cu16x16_en; /* default: 1 */ 857 RK_U32 cu8x8_en; /* default: 1 */ 858 RK_U32 cu4x4_en; /* default: 1 */ 859 860 // intra pred 861 RK_U32 constrained_intra_pred_flag; /* default: 0 */ 862 RK_U32 strong_intra_smoothing_enabled_flag; /* INTRA_SMOOTH */ 863 RK_U32 pcm_enabled_flag; /* default: 0, enable ipcm */ 864 RK_U32 pcm_loop_filter_disabled_flag; 865 } MppEncH265CuCfg; 866 867 typedef struct MppEncH265RefCfg_t { 868 RK_U32 num_lt_ref_pic; /* default: 0 */ 869 } MppEncH265RefCfg; 870 871 typedef struct MppEncH265DblkCfg_t { 872 RK_U32 slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */ 873 RK_S32 slice_beta_offset_div2; /* default value: 0. [-6,+6] */ 874 RK_S32 slice_tc_offset_div2; /* default value: 0. [-6,+6] */ 875 } MppEncH265DblkCfg_t; 876 877 typedef struct MppEncH265SaoCfg_t { 878 RK_U32 slice_sao_luma_flag; 879 RK_U32 slice_sao_chroma_flag; 880 } MppEncH265SaoCfg; 881 882 typedef struct MppEncH265TransCfg_t { 883 RK_U32 transquant_bypass_enabled_flag; 884 RK_U32 transform_skip_enabled_flag; 885 RK_U32 defalut_ScalingList_enable; /* default: 0 */ 886 RK_S32 cb_qp_offset; 887 RK_S32 cr_qp_offset; 888 } MppEncH265TransCfg; 889 890 typedef struct MppEncH265MergeCfg_t { 891 RK_U32 max_mrg_cnd; 892 RK_U32 merge_up_flag; 893 RK_U32 merge_left_flag; 894 } MppEncH265MergesCfg; 895 896 typedef struct MppEncH265EntropyCfg_t { 897 RK_U32 cabac_init_flag; /* default: 0 */ 898 } MppEncH265EntropyCfg; 899 900 typedef struct MppEncH265Cfg_t { 901 RK_U32 change; 902 903 /* H.265 codec syntax config */ 904 RK_S32 profile; 905 RK_S32 level; 906 RK_S32 tier; 907 908 /* constraint intra prediction flag */ 909 RK_S32 const_intra_pred; 910 RK_S32 ctu_size; 911 RK_S32 max_cu_size; 912 RK_S32 tmvp_enable; 913 RK_S32 amp_enable; 914 RK_S32 wpp_enable; 915 RK_S32 merge_range; 916 RK_S32 sao_enable; 917 RK_U32 num_ref; 918 919 /* quality config */ 920 RK_S32 max_qp; 921 RK_S32 min_qp; 922 RK_S32 max_i_qp; 923 RK_S32 min_i_qp; 924 RK_S32 ip_qp_delta; 925 RK_S32 max_delta_qp; 926 RK_S32 intra_qp; 927 RK_S32 gop_delta_qp; 928 RK_S32 qp_init; 929 RK_S32 qp_max_step; 930 RK_S32 raw_dealt_qp; 931 RK_U8 qpmax_map[8]; 932 RK_U8 qpmin_map[8]; 933 RK_S32 qpmap_mode; 934 935 /* intra fresh config */ 936 RK_S32 intra_refresh_mode; 937 RK_S32 intra_refresh_arg; 938 939 /* slice mode config */ 940 RK_S32 independ_slice_mode; 941 RK_S32 independ_slice_arg; 942 RK_S32 depend_slice_mode; 943 RK_S32 depend_slice_arg; 944 945 MppEncH265CuCfg cu_cfg; 946 MppEncH265SliceCfg slice_cfg; 947 MppEncH265EntropyCfg entropy_cfg; 948 MppEncH265TransCfg trans_cfg; 949 MppEncH265SaoCfg sao_cfg; 950 MppEncH265DblkCfg_t dblk_cfg; 951 MppEncH265RefCfg ref_cfg; 952 MppEncH265MergesCfg merge_cfg; 953 954 /* extra info */ 955 MppEncH265VuiCfg vui; 956 957 MppEncH265CtuCfg ctu; 958 MppEncH265RoiCfg roi; 959 } MppEncH265Cfg; 960 961 /* 962 * motion jpeg configurable parameter 963 */ 964 typedef enum MppEncJpegCfgChange_e { 965 /* change on quant parameter */ 966 MPP_ENC_JPEG_CFG_CHANGE_QP = (1 << 0), 967 MPP_ENC_JPEG_CFG_CHANGE_QTABLE = (1 << 1), 968 MPP_ENC_JPEG_CFG_CHANGE_QFACTOR = (1 << 2), 969 MPP_ENC_JPEG_CFG_CHANGE_ALL = (0xFFFFFFFF), 970 } MppEncJpegCfgChange; 971 972 typedef struct MppEncJpegCfg_t { 973 RK_U32 change; 974 RK_S32 quant; 975 /* 976 * quality factor config 977 * 978 * q_factor - 1 ~ 99 979 * qf_max - 1 ~ 99 980 * qf_min - 1 ~ 99 981 * qtable_y: qtable for luma 982 * qtable_u: qtable for chroma 983 * qtable_v: default equal qtable_u 984 */ 985 RK_S32 q_factor; 986 RK_S32 qf_max; 987 RK_S32 qf_min; 988 RK_U8 *qtable_y; 989 RK_U8 *qtable_u; 990 RK_U8 *qtable_v; 991 } MppEncJpegCfg; 992 993 /* 994 * vp8 configurable parameter 995 */ 996 typedef enum MppEncVP8CfgChange_e { 997 MPP_ENC_VP8_CFG_CHANGE_QP = (1 << 0), 998 MPP_ENC_VP8_CFG_CHANGE_DIS_IVF = (1 << 1), 999 MPP_ENC_VP8_CFG_CHANGE_ALL = (0xFFFFFFFF), 1000 } MppEncVP8CfgChange; 1001 1002 typedef struct MppEncVp8Cfg_t { 1003 RK_U32 change; 1004 RK_S32 quant; 1005 1006 RK_S32 qp_init; 1007 RK_S32 qp_max; 1008 RK_S32 qp_max_i; 1009 RK_S32 qp_min; 1010 RK_S32 qp_min_i; 1011 RK_S32 qp_max_step; 1012 RK_S32 disable_ivf; 1013 } MppEncVp8Cfg; 1014 1015 /** 1016 * @ingroup rk_mpi 1017 * @brief MPP encoder codec configuration parameters 1018 * @details The encoder codec configuration parameters are different for each 1019 * compression codings. For example, H.264 encoder can configure 1020 * profile, level, qp, etc. while jpeg encoder can configure qp 1021 * only. The detailed parameters can refer the corresponding data 1022 * structure such as MppEncH264Cfg and MppEncJpegCfg. This data 1023 * structure is associated with MPP_ENC_SET_CODEC_CFG command. 1024 */ 1025 typedef struct MppEncCodecCfg_t { 1026 MppCodingType coding; 1027 1028 union { 1029 RK_U32 change; 1030 MppEncH264Cfg h264; 1031 MppEncH265Cfg h265; 1032 MppEncJpegCfg jpeg; 1033 MppEncVp8Cfg vp8; 1034 }; 1035 } MppEncCodecCfg; 1036 1037 typedef enum MppEncSliceSplit_e { 1038 /* change on quant parameter */ 1039 MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0), 1040 MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1), 1041 MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1042 } MppEncSliceSplitChange; 1043 1044 typedef enum MppEncSplitMode_e { 1045 MPP_ENC_SPLIT_NONE, 1046 MPP_ENC_SPLIT_BY_BYTE, 1047 MPP_ENC_SPLIT_BY_CTU, 1048 } MppEncSplitMode; 1049 1050 typedef struct MppEncSliceSplit_t { 1051 RK_U32 change; 1052 1053 /* 1054 * slice split mode 1055 * 1056 * MPP_ENC_SPLIT_NONE - No slice is split 1057 * MPP_ENC_SPLIT_BY_BYTE - Slice is split by byte number 1058 * MPP_ENC_SPLIT_BY_CTU - Slice is split by macroblock / ctu number 1059 */ 1060 RK_U32 split_mode; 1061 1062 /* 1063 * slice split size parameter 1064 * 1065 * When split by byte number this value is the max byte number for each 1066 * slice. 1067 * When split by macroblock / ctu number this value is the MB/CTU number 1068 * for each slice. 1069 */ 1070 RK_U32 split_arg; 1071 } MppEncSliceSplit; 1072 1073 /** 1074 * @brief Mpp ROI parameter 1075 * Region configure define a rectangle as ROI 1076 * @note x, y, w, h are calculated in pixels, which had better be 16-pixel aligned. 1077 * These parameters MUST retain in memory when encoder is running. 1078 * Both absolute qp and relative qp are supported in vepu541. 1079 * Only absolute qp is supported in rv1108 1080 */ 1081 typedef struct MppEncROIRegion_t { 1082 RK_U16 x; /**< horizontal position of top left corner */ 1083 RK_U16 y; /**< vertical position of top left corner */ 1084 RK_U16 w; /**< width of ROI rectangle */ 1085 RK_U16 h; /**< height of ROI rectangle */ 1086 RK_U16 intra; /**< flag of forced intra macroblock */ 1087 RK_S16 quality; /**< absolute / relative qp of macroblock */ 1088 RK_U16 qp_area_idx; /**< qp min max area select*/ 1089 RK_U8 area_map_en; /**< enable area map */ 1090 RK_U8 abs_qp_en; /**< absolute qp enable flag*/ 1091 } MppEncROIRegion; 1092 1093 /** 1094 * @brief MPP encoder's ROI configuration 1095 */ 1096 typedef struct MppEncROICfg_t { 1097 RK_U32 number; /**< ROI rectangle number */ 1098 MppEncROIRegion *regions; /**< ROI parameters */ 1099 } MppEncROICfg; 1100 1101 /* 1102 * Mpp OSD parameter 1103 * 1104 * Mpp OSD support total 8 regions 1105 * Mpp OSD support 256-color palette two mode palette: 1106 * 1. Configurable OSD palette 1107 * When palette is set. 1108 * 2. fixed OSD palette 1109 * When palette is NULL. 1110 * 1111 * if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels, 1112 * every level composed of 32 bits defined below: 1113 * Y : 8 bits 1114 * U : 8 bits 1115 * V : 8 bits 1116 * alpha : 8 bits 1117 */ 1118 #define MPP_ENC_OSD_PLT_WHITE ((255<<24)|(128<<16)|(128<<8)|235) 1119 #define MPP_ENC_OSD_PLT_YELLOW ((255<<24)|(146<<16)|(16<<8)|210) 1120 #define MPP_ENC_OSD_PLT_CYAN ((255<<24)|(16<<16)|(166<<8)|170) 1121 #define MPP_ENC_OSD_PLT_GREEN ((255<<24)|(34<<16)|(54<<8)|145) 1122 #define MPP_ENC_OSD_PLT_TRANS ((0<<24)|(222<<16)|(202<<8)|106) 1123 #define MPP_ENC_OSD_PLT_RED ((255<<24)|(240<<16)|(90<<8)| 81) 1124 #define MPP_ENC_OSD_PLT_BLUE ((255<<24)|(110<<16)|(240<<8)| 41) 1125 #define MPP_ENC_OSD_PLT_BLACK ((255<<24)|(128<<16)|(128<<8)| 16) 1126 1127 typedef enum MppEncOSDPltType_e { 1128 MPP_ENC_OSD_PLT_TYPE_DEFAULT, 1129 MPP_ENC_OSD_PLT_TYPE_USERDEF, 1130 MPP_ENC_OSD_PLT_TYPE_BUTT, 1131 } MppEncOSDPltType; 1132 1133 /* OSD palette value define */ 1134 typedef union MppEncOSDPltVal_u { 1135 struct { 1136 RK_U32 v : 8; 1137 RK_U32 u : 8; 1138 RK_U32 y : 8; 1139 RK_U32 alpha : 8; 1140 }; 1141 RK_U32 val; 1142 } MppEncOSDPltVal; 1143 1144 typedef struct MppEncOSDPlt_t { 1145 MppEncOSDPltVal data[256]; 1146 } MppEncOSDPlt; 1147 1148 typedef enum MppEncOSDPltCfgChange_e { 1149 MPP_ENC_OSD_PLT_CFG_CHANGE_MODE = (1 << 0), /* change osd plt type */ 1150 MPP_ENC_OSD_PLT_CFG_CHANGE_PLT_VAL = (1 << 1), /* change osd plt table value */ 1151 MPP_ENC_OSD_PLT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1152 } MppEncOSDPltCfgChange; 1153 1154 typedef struct MppEncOSDPltCfg_t { 1155 RK_U32 change; 1156 MppEncOSDPltType type; 1157 MppEncOSDPlt *plt; 1158 } MppEncOSDPltCfg; 1159 1160 /* position info is unit in 16 pixels(one MB), and 1161 * x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16; 1162 * y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16; 1163 */ 1164 typedef struct MppEncOSDRegion_t { 1165 RK_U32 enable; 1166 RK_U32 inverse; 1167 RK_U32 start_mb_x; 1168 RK_U32 start_mb_y; 1169 RK_U32 num_mb_x; 1170 RK_U32 num_mb_y; 1171 RK_U32 buf_offset; 1172 } MppEncOSDRegion; 1173 1174 /* if num_region > 0 && region==NULL 1175 * use old osd data 1176 */ 1177 typedef struct MppEncOSDData_t { 1178 MppBuffer buf; 1179 RK_U32 num_region; 1180 MppEncOSDRegion region[8]; 1181 } MppEncOSDData; 1182 1183 typedef struct MppEncOSDRegion2_t { 1184 RK_U32 enable; 1185 RK_U32 inverse; 1186 RK_U32 start_mb_x; 1187 RK_U32 start_mb_y; 1188 RK_U32 num_mb_x; 1189 RK_U32 num_mb_y; 1190 RK_U32 buf_offset; 1191 MppBuffer buf; 1192 } MppEncOSDRegion2; 1193 1194 typedef struct MppEncOSDData2_t { 1195 RK_U32 num_region; 1196 MppEncOSDRegion2 region[8]; 1197 } MppEncOSDData2; 1198 1199 typedef struct MppEncUserData_t { 1200 RK_U32 len; 1201 void *pdata; 1202 } MppEncUserData; 1203 1204 typedef struct MppEncUserDataFull_t { 1205 RK_U32 len; 1206 RK_U8 *uuid; 1207 void *pdata; 1208 } MppEncUserDataFull; 1209 1210 typedef struct MppEncUserDataSet_t { 1211 RK_U32 count; 1212 MppEncUserDataFull *datas; 1213 } MppEncUserDataSet; 1214 1215 #endif /* __RK_VENC_CMD_H__ */ 1216