1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2016 Google, Inc
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <asm/io.h>
10 #include <asm/arch/scu_ast2500.h>
11 #include <dm/lists.h>
12 #include <dt-bindings/clock/ast2500-scu.h>
13
14 /*
15 * MAC Clock Delay settings, taken from Aspeed SDK
16 */
17 #define RGMII_TXCLK_ODLY 8
18 #define RMII_RXCLK_IDLY 2
19
20 /*
21 * TGMII Clock Duty constants, taken from Aspeed SDK
22 */
23 #define RGMII2_TXCK_DUTY 0x66
24 #define RGMII1_TXCK_DUTY 0x64
25
26 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 /*
31 * Clock divider/multiplier configuration struct.
32 * For H-PLL and M-PLL the formula is
33 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
34 * M - Numerator
35 * N - Denumerator
36 * P - Post Divider
37 * They have the same layout in their control register.
38 *
39 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
40 * yet needed and ignored by clock configurations.
41 */
42 struct ast2500_div_config {
43 unsigned int num;
44 unsigned int denum;
45 unsigned int post_div;
46 };
47
48 /*
49 * Get the rate of the M-PLL clock from input clock frequency and
50 * the value of the M-PLL Parameter Register.
51 */
ast2500_get_mpll_rate(ulong clkin,u32 mpll_reg)52 static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
53 {
54 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
55 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
56 >> SCU_MPLL_DENUM_SHIFT;
57 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
58 >> SCU_MPLL_POST_SHIFT;
59
60 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
61 }
62
63 /*
64 * Get the rate of the H-PLL clock from input clock frequency and
65 * the value of the H-PLL Parameter Register.
66 */
ast2500_get_hpll_rate(ulong clkin,u32 hpll_reg)67 static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
68 {
69 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
70 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
71 >> SCU_HPLL_DENUM_SHIFT;
72 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
73 >> SCU_HPLL_POST_SHIFT;
74
75 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
76 }
77
ast2500_get_clkin(struct ast2500_scu * scu)78 static ulong ast2500_get_clkin(struct ast2500_scu *scu)
79 {
80 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
81 ? 25 * 1000 * 1000 : 24 * 1000 * 1000;
82 }
83
84 /**
85 * Get current rate or uart clock
86 *
87 * @scu SCU registers
88 * @uart_index UART index, 1-5
89 *
90 * @return current setting for uart clock rate
91 */
ast2500_get_uart_clk_rate(struct ast2500_scu * scu,int uart_index)92 static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
93 {
94 /*
95 * ast2500 datasheet is very confusing when it comes to UART clocks,
96 * especially when CLKIN = 25 MHz. The settings are in
97 * different registers and it is unclear how they interact.
98 *
99 * This has only been tested with default settings and CLKIN = 24 MHz.
100 */
101 ulong uart_clkin;
102
103 if (readl(&scu->misc_ctrl2) &
104 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
105 uart_clkin = 192 * 1000 * 1000;
106 else
107 uart_clkin = 24 * 1000 * 1000;
108
109 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
110 uart_clkin /= 13;
111
112 return uart_clkin;
113 }
114
ast2500_clk_get_rate(struct clk * clk)115 static ulong ast2500_clk_get_rate(struct clk *clk)
116 {
117 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
118 ulong clkin = ast2500_get_clkin(priv->scu);
119 ulong rate;
120
121 switch (clk->id) {
122 case PLL_HPLL:
123 case ARMCLK:
124 /*
125 * This ignores dynamic/static slowdown of ARMCLK and may
126 * be inaccurate.
127 */
128 rate = ast2500_get_hpll_rate(clkin,
129 readl(&priv->scu->h_pll_param));
130 break;
131 case MCLK_DDR:
132 rate = ast2500_get_mpll_rate(clkin,
133 readl(&priv->scu->m_pll_param));
134 break;
135 case BCLK_PCLK:
136 {
137 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
138 & SCU_PCLK_DIV_MASK)
139 >> SCU_PCLK_DIV_SHIFT);
140 rate = ast2500_get_hpll_rate(clkin,
141 readl(&priv->
142 scu->h_pll_param));
143 rate = rate / apb_div;
144 }
145 break;
146 case BCLK_SDCLK:
147 {
148 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
149 & SCU_SDCLK_DIV_MASK)
150 >> SCU_SDCLK_DIV_SHIFT);
151 rate = ast2500_get_hpll_rate(clkin,
152 readl(&priv->
153 scu->h_pll_param));
154 rate = rate / apb_div;
155 }
156 break;
157 case PCLK_UART1:
158 rate = ast2500_get_uart_clk_rate(priv->scu, 1);
159 break;
160 case PCLK_UART2:
161 rate = ast2500_get_uart_clk_rate(priv->scu, 2);
162 break;
163 case PCLK_UART3:
164 rate = ast2500_get_uart_clk_rate(priv->scu, 3);
165 break;
166 case PCLK_UART4:
167 rate = ast2500_get_uart_clk_rate(priv->scu, 4);
168 break;
169 case PCLK_UART5:
170 rate = ast2500_get_uart_clk_rate(priv->scu, 5);
171 break;
172 default:
173 return -ENOENT;
174 }
175
176 return rate;
177 }
178
179 struct ast2500_clock_config {
180 ulong input_rate;
181 ulong rate;
182 struct ast2500_div_config cfg;
183 };
184
185 static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
186 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
187 };
188
ast2500_get_clock_config_default(ulong input_rate,ulong requested_rate,struct ast2500_div_config * cfg)189 static bool ast2500_get_clock_config_default(ulong input_rate,
190 ulong requested_rate,
191 struct ast2500_div_config *cfg)
192 {
193 int i;
194
195 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
196 const struct ast2500_clock_config *default_cfg =
197 &ast2500_clock_config_defaults[i];
198 if (default_cfg->input_rate == input_rate &&
199 default_cfg->rate == requested_rate) {
200 *cfg = default_cfg->cfg;
201 return true;
202 }
203 }
204
205 return false;
206 }
207
208 /*
209 * @input_rate - the rate of input clock in Hz
210 * @requested_rate - desired output rate in Hz
211 * @div - this is an IN/OUT parameter, at input all fields of the config
212 * need to be set to their maximum allowed values.
213 * The result (the best config we could find), would also be returned
214 * in this structure.
215 *
216 * @return The clock rate, when the resulting div_config is used.
217 */
ast2500_calc_clock_config(ulong input_rate,ulong requested_rate,struct ast2500_div_config * cfg)218 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
219 struct ast2500_div_config *cfg)
220 {
221 /*
222 * The assumption is that kHz precision is good enough and
223 * also enough to avoid overflow when multiplying.
224 */
225 const ulong input_rate_khz = input_rate / 1000;
226 const ulong rate_khz = requested_rate / 1000;
227 const struct ast2500_div_config max_vals = *cfg;
228 struct ast2500_div_config it = { 0, 0, 0 };
229 ulong delta = rate_khz;
230 ulong new_rate_khz = 0;
231
232 /*
233 * Look for a well known frequency first.
234 */
235 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
236 return requested_rate;
237
238 for (; it.denum <= max_vals.denum; ++it.denum) {
239 for (it.post_div = 0; it.post_div <= max_vals.post_div;
240 ++it.post_div) {
241 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz)
242 * (it.denum + 1);
243 if (it.num > max_vals.num)
244 continue;
245
246 new_rate_khz = (input_rate_khz
247 * ((it.num + 1) / (it.denum + 1)))
248 / (it.post_div + 1);
249
250 /* Keep the rate below requested one. */
251 if (new_rate_khz > rate_khz)
252 continue;
253
254 if (new_rate_khz - rate_khz < delta) {
255 delta = new_rate_khz - rate_khz;
256 *cfg = it;
257 if (delta == 0)
258 return new_rate_khz * 1000;
259 }
260 }
261 }
262
263 return new_rate_khz * 1000;
264 }
265
ast2500_configure_ddr(struct ast2500_scu * scu,ulong rate)266 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
267 {
268 ulong clkin = ast2500_get_clkin(scu);
269 u32 mpll_reg;
270 struct ast2500_div_config div_cfg = {
271 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
272 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
273 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
274 };
275
276 ast2500_calc_clock_config(clkin, rate, &div_cfg);
277
278 mpll_reg = readl(&scu->m_pll_param);
279 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
280 | SCU_MPLL_DENUM_MASK);
281 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
282 | (div_cfg.num << SCU_MPLL_NUM_SHIFT)
283 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);
284
285 ast_scu_unlock(scu);
286 writel(mpll_reg, &scu->m_pll_param);
287 ast_scu_lock(scu);
288
289 return ast2500_get_mpll_rate(clkin, mpll_reg);
290 }
291
ast2500_configure_mac(struct ast2500_scu * scu,int index)292 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index)
293 {
294 ulong clkin = ast2500_get_clkin(scu);
295 ulong hpll_rate = ast2500_get_hpll_rate(clkin,
296 readl(&scu->h_pll_param));
297 ulong required_rate;
298 u32 hwstrap;
299 u32 divisor;
300 u32 reset_bit;
301 u32 clkstop_bit;
302
303 /*
304 * According to data sheet, for 10/100 mode the MAC clock frequency
305 * should be at least 25MHz and for 1000 mode at least 100MHz
306 */
307 hwstrap = readl(&scu->hwstrap);
308 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII))
309 required_rate = 100 * 1000 * 1000;
310 else
311 required_rate = 25 * 1000 * 1000;
312
313 divisor = hpll_rate / required_rate;
314
315 if (divisor < 4) {
316 /* Clock can't run fast enough, but let's try anyway */
317 debug("MAC clock too slow\n");
318 divisor = 4;
319 } else if (divisor > 16) {
320 /* Can't slow down the clock enough, but let's try anyway */
321 debug("MAC clock too fast\n");
322 divisor = 16;
323 }
324
325 switch (index) {
326 case 1:
327 reset_bit = SCU_SYSRESET_MAC1;
328 clkstop_bit = SCU_CLKSTOP_MAC1;
329 break;
330 case 2:
331 reset_bit = SCU_SYSRESET_MAC2;
332 clkstop_bit = SCU_CLKSTOP_MAC2;
333 break;
334 default:
335 return -EINVAL;
336 }
337
338 ast_scu_unlock(scu);
339 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,
340 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT);
341
342 /*
343 * Disable MAC, start its clock and re-enable it.
344 * The procedure and the delays (100us & 10ms) are
345 * specified in the datasheet.
346 */
347 setbits_le32(&scu->sysreset_ctrl1, reset_bit);
348 udelay(100);
349 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
350 mdelay(10);
351 clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
352
353 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
354 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT),
355 &scu->clk_duty_sel);
356
357 ast_scu_lock(scu);
358
359 return required_rate;
360 }
361
ast2500_configure_d2pll(struct ast2500_scu * scu,ulong rate)362 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
363 {
364 /*
365 * The values and the meaning of the next three
366 * parameters are undocumented. Taken from Aspeed SDK.
367 *
368 * TODO(clg@kaod.org): the SIP and SIC values depend on the
369 * Numerator value
370 */
371 const u32 d2_pll_ext_param = 0x2c;
372 const u32 d2_pll_sip = 0x11;
373 const u32 d2_pll_sic = 0x18;
374 u32 clk_delay_settings =
375 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
376 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
377 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
378 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT);
379 struct ast2500_div_config div_cfg = {
380 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT,
381 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT,
382 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT,
383 };
384 ulong clkin = ast2500_get_clkin(scu);
385 ulong new_rate;
386
387 ast_scu_unlock(scu);
388 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT)
389 | SCU_D2PLL_EXT1_OFF
390 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);
391
392 /*
393 * Select USB2.0 port1 PHY clock as a clock source for GCRT.
394 * This would disconnect it from D2-PLL.
395 */
396 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,
397 SCU_MISC_GCRT_USB20CLK);
398
399 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);
400 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT)
401 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT)
402 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT)
403 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT)
404 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT),
405 &scu->d2_pll_param);
406
407 clrbits_le32(&scu->d2_pll_ext_param[0],
408 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET);
409
410 clrsetbits_le32(&scu->misc_ctrl2,
411 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL
412 | SCU_MISC2_RGMII_CLKDIV_MASK |
413 SCU_MISC2_RMII_CLKDIV_MASK,
414 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT));
415
416 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);
417 writel(clk_delay_settings, &scu->mac_clk_delay_100M);
418 writel(clk_delay_settings, &scu->mac_clk_delay_10M);
419
420 ast_scu_lock(scu);
421
422 return new_rate;
423 }
424
ast2500_clk_set_rate(struct clk * clk,ulong rate)425 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
426 {
427 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
428
429 ulong new_rate;
430 switch (clk->id) {
431 case PLL_MPLL:
432 case MCLK_DDR:
433 new_rate = ast2500_configure_ddr(priv->scu, rate);
434 break;
435 case PLL_D2PLL:
436 new_rate = ast2500_configure_d2pll(priv->scu, rate);
437 break;
438 default:
439 return -ENOENT;
440 }
441
442 return new_rate;
443 }
444
ast2500_clk_enable(struct clk * clk)445 static int ast2500_clk_enable(struct clk *clk)
446 {
447 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
448
449 switch (clk->id) {
450 case BCLK_SDCLK:
451 if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
452 ast_scu_unlock(priv->scu);
453
454 setbits_le32(&priv->scu->sysreset_ctrl1,
455 SCU_SYSRESET_SDIO);
456 udelay(100);
457 clrbits_le32(&priv->scu->clk_stop_ctrl1,
458 SCU_CLKSTOP_SDCLK);
459 mdelay(10);
460 clrbits_le32(&priv->scu->sysreset_ctrl1,
461 SCU_SYSRESET_SDIO);
462
463 ast_scu_lock(priv->scu);
464 }
465 break;
466 /*
467 * For MAC clocks the clock rate is
468 * configured based on whether RGMII or RMII mode has been selected
469 * through hardware strapping.
470 */
471 case PCLK_MAC1:
472 ast2500_configure_mac(priv->scu, 1);
473 break;
474 case PCLK_MAC2:
475 ast2500_configure_mac(priv->scu, 2);
476 break;
477 case PLL_D2PLL:
478 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
479 break;
480 default:
481 return -ENOENT;
482 }
483
484 return 0;
485 }
486
487 struct clk_ops ast2500_clk_ops = {
488 .get_rate = ast2500_clk_get_rate,
489 .set_rate = ast2500_clk_set_rate,
490 .enable = ast2500_clk_enable,
491 };
492
ast2500_clk_probe(struct udevice * dev)493 static int ast2500_clk_probe(struct udevice *dev)
494 {
495 struct ast2500_clk_priv *priv = dev_get_priv(dev);
496
497 priv->scu = devfdt_get_addr_ptr(dev);
498 if (IS_ERR(priv->scu))
499 return PTR_ERR(priv->scu);
500
501 return 0;
502 }
503
ast2500_clk_bind(struct udevice * dev)504 static int ast2500_clk_bind(struct udevice *dev)
505 {
506 int ret;
507
508 /* The reset driver does not have a device node, so bind it here */
509 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
510 if (ret)
511 debug("Warning: No reset driver: ret=%d\n", ret);
512
513 return 0;
514 }
515
516 static const struct udevice_id ast2500_clk_ids[] = {
517 { .compatible = "aspeed,ast2500-scu" },
518 { }
519 };
520
521 U_BOOT_DRIVER(aspeed_ast2500_scu) = {
522 .name = "aspeed_ast2500_scu",
523 .id = UCLASS_CLK,
524 .of_match = ast2500_clk_ids,
525 .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
526 .ops = &ast2500_clk_ops,
527 .bind = ast2500_clk_bind,
528 .probe = ast2500_clk_probe,
529 };
530