1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/version.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_dp_mst_helper.h>
29 #include <drm/drm_dp_helper.h>
30 #include "dm_services.h"
31 #include "amdgpu.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_mst_types.h"
34
35 #include "dc.h"
36 #include "dm_helpers.h"
37
38 #include "dc_link_ddc.h"
39
40 #include "i2caux_interface.h"
41 #if defined(CONFIG_DEBUG_FS)
42 #include "amdgpu_dm_debugfs.h"
43 #endif
44
45 #if defined(CONFIG_DRM_AMD_DC_DCN)
46 #include "dc/dcn20/dcn20_resource.h"
47 #endif
48
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)49 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
50 struct drm_dp_aux_msg *msg)
51 {
52 ssize_t result = 0;
53 struct aux_payload payload;
54 enum aux_channel_operation_result operation_result;
55
56 if (WARN_ON(msg->size > 16))
57 return -E2BIG;
58
59 payload.address = msg->address;
60 payload.data = msg->buffer;
61 payload.length = msg->size;
62 payload.reply = &msg->reply;
63 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
64 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
65 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
66 payload.defer_delay = 0;
67
68 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
69 &operation_result);
70
71 if (payload.write && result >= 0)
72 result = msg->size;
73
74 if (result < 0)
75 switch (operation_result) {
76 case AUX_CHANNEL_OPERATION_SUCCEEDED:
77 break;
78 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
79 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
80 result = -EIO;
81 break;
82 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
83 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
84 result = -EBUSY;
85 break;
86 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
87 result = -ETIMEDOUT;
88 break;
89 }
90
91 return result;
92 }
93
94 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)95 dm_dp_mst_connector_destroy(struct drm_connector *connector)
96 {
97 struct amdgpu_dm_connector *aconnector =
98 to_amdgpu_dm_connector(connector);
99
100 if (aconnector->dc_sink) {
101 dc_link_remove_remote_sink(aconnector->dc_link,
102 aconnector->dc_sink);
103 dc_sink_release(aconnector->dc_sink);
104 }
105
106 kfree(aconnector->edid);
107
108 drm_connector_cleanup(connector);
109 drm_dp_mst_put_port_malloc(aconnector->port);
110 kfree(aconnector);
111 }
112
113 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)114 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
115 {
116 struct amdgpu_dm_connector *amdgpu_dm_connector =
117 to_amdgpu_dm_connector(connector);
118 int r;
119
120 r = drm_dp_mst_connector_late_register(connector,
121 amdgpu_dm_connector->port);
122 if (r < 0)
123 return r;
124
125 #if defined(CONFIG_DEBUG_FS)
126 connector_debugfs_init(amdgpu_dm_connector);
127 #endif
128
129 return 0;
130 }
131
132 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)133 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
134 {
135 struct amdgpu_dm_connector *amdgpu_dm_connector =
136 to_amdgpu_dm_connector(connector);
137 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
138
139 drm_dp_mst_connector_early_unregister(connector, port);
140 }
141
142 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
143 .fill_modes = drm_helper_probe_single_connector_modes,
144 .destroy = dm_dp_mst_connector_destroy,
145 .reset = amdgpu_dm_connector_funcs_reset,
146 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
147 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
148 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
149 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
150 .late_register = amdgpu_dm_mst_connector_late_register,
151 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
152 };
153
154 #if defined(CONFIG_DRM_AMD_DC_DCN)
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)155 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
156 {
157 struct dc_sink *dc_sink = aconnector->dc_sink;
158 struct drm_dp_mst_port *port = aconnector->port;
159 u8 dsc_caps[16] = { 0 };
160
161 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
162 #if defined(CONFIG_HP_HOOK_WORKAROUND)
163 /*
164 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
165 * because it only check the dsc/fec caps of the "port variable" and not the dock
166 *
167 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
168 *
169 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
170 *
171 */
172
173 if (!aconnector->dsc_aux && !port->parent->port_parent)
174 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
175 #endif
176 if (!aconnector->dsc_aux)
177 return false;
178
179 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
180 return false;
181
182 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
183 dsc_caps, NULL,
184 &dc_sink->dsc_caps.dsc_dec_caps))
185 return false;
186
187 return true;
188 }
189 #endif
190
dm_dp_mst_get_modes(struct drm_connector * connector)191 static int dm_dp_mst_get_modes(struct drm_connector *connector)
192 {
193 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
194 int ret = 0;
195
196 if (!aconnector)
197 return drm_add_edid_modes(connector, NULL);
198
199 if (!aconnector->edid) {
200 struct edid *edid;
201 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
202
203 if (!edid) {
204 drm_connector_update_edid_property(
205 &aconnector->base,
206 NULL);
207 return ret;
208 }
209
210 aconnector->edid = edid;
211 }
212
213 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
214 dc_sink_release(aconnector->dc_sink);
215 aconnector->dc_sink = NULL;
216 }
217
218 if (!aconnector->dc_sink) {
219 struct dc_sink *dc_sink;
220 struct dc_sink_init_data init_params = {
221 .link = aconnector->dc_link,
222 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
223 dc_sink = dc_link_add_remote_sink(
224 aconnector->dc_link,
225 (uint8_t *)aconnector->edid,
226 (aconnector->edid->extensions + 1) * EDID_LENGTH,
227 &init_params);
228
229 dc_sink->priv = aconnector;
230 /* dc_link_add_remote_sink returns a new reference */
231 aconnector->dc_sink = dc_sink;
232
233 if (aconnector->dc_sink) {
234 amdgpu_dm_update_freesync_caps(
235 connector, aconnector->edid);
236
237 #if defined(CONFIG_DRM_AMD_DC_DCN)
238 if (!validate_dsc_caps_on_connector(aconnector))
239 memset(&aconnector->dc_sink->dsc_caps,
240 0, sizeof(aconnector->dc_sink->dsc_caps));
241 #endif
242 }
243 }
244
245 drm_connector_update_edid_property(
246 &aconnector->base, aconnector->edid);
247
248 ret = drm_add_edid_modes(connector, aconnector->edid);
249
250 return ret;
251 }
252
253 static struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_connector_state * connector_state)254 dm_mst_atomic_best_encoder(struct drm_connector *connector,
255 struct drm_connector_state *connector_state)
256 {
257 struct drm_device *dev = connector->dev;
258 struct amdgpu_device *adev = drm_to_adev(dev);
259 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
260
261 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
262 }
263
264 static int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)265 dm_dp_mst_detect(struct drm_connector *connector,
266 struct drm_modeset_acquire_ctx *ctx, bool force)
267 {
268 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
269 struct amdgpu_dm_connector *master = aconnector->mst_port;
270
271 if (drm_connector_is_unregistered(connector))
272 return connector_status_disconnected;
273
274 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
275 aconnector->port);
276 }
277
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)278 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
279 struct drm_atomic_state *state)
280 {
281 struct drm_connector_state *new_conn_state =
282 drm_atomic_get_new_connector_state(state, connector);
283 struct drm_connector_state *old_conn_state =
284 drm_atomic_get_old_connector_state(state, connector);
285 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
286 struct drm_crtc_state *new_crtc_state;
287 struct drm_dp_mst_topology_mgr *mst_mgr;
288 struct drm_dp_mst_port *mst_port;
289
290 mst_port = aconnector->port;
291 mst_mgr = &aconnector->mst_port->mst_mgr;
292
293 if (!old_conn_state->crtc)
294 return 0;
295
296 if (new_conn_state->crtc) {
297 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
298 if (!new_crtc_state ||
299 !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
300 new_crtc_state->enable)
301 return 0;
302 }
303
304 return drm_dp_atomic_release_vcpi_slots(state,
305 mst_mgr,
306 mst_port);
307 }
308
309 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
310 .get_modes = dm_dp_mst_get_modes,
311 .mode_valid = amdgpu_dm_connector_mode_valid,
312 .atomic_best_encoder = dm_mst_atomic_best_encoder,
313 .detect_ctx = dm_dp_mst_detect,
314 .atomic_check = dm_dp_mst_atomic_check,
315 };
316
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)317 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
318 {
319 drm_encoder_cleanup(encoder);
320 kfree(encoder);
321 }
322
323 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
324 .destroy = amdgpu_dm_encoder_destroy,
325 };
326
327 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)328 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
329 {
330 struct drm_device *dev = adev_to_drm(adev);
331 int i;
332
333 for (i = 0; i < adev->dm.display_indexes_num; i++) {
334 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
335 struct drm_encoder *encoder = &amdgpu_encoder->base;
336
337 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
338
339 drm_encoder_init(
340 dev,
341 &amdgpu_encoder->base,
342 &amdgpu_dm_encoder_funcs,
343 DRM_MODE_ENCODER_DPMST,
344 NULL);
345
346 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
347 }
348 }
349
350 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)351 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
352 struct drm_dp_mst_port *port,
353 const char *pathprop)
354 {
355 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
356 struct drm_device *dev = master->base.dev;
357 struct amdgpu_device *adev = drm_to_adev(dev);
358 struct amdgpu_dm_connector *aconnector;
359 struct drm_connector *connector;
360 int i;
361
362 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
363 if (!aconnector)
364 return NULL;
365
366 connector = &aconnector->base;
367 aconnector->port = port;
368 aconnector->mst_port = master;
369
370 if (drm_connector_init(
371 dev,
372 connector,
373 &dm_dp_mst_connector_funcs,
374 DRM_MODE_CONNECTOR_DisplayPort)) {
375 kfree(aconnector);
376 return NULL;
377 }
378 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
379
380 amdgpu_dm_connector_init_helper(
381 &adev->dm,
382 aconnector,
383 DRM_MODE_CONNECTOR_DisplayPort,
384 master->dc_link,
385 master->connector_id);
386
387 for (i = 0; i < adev->dm.display_indexes_num; i++) {
388 drm_connector_attach_encoder(&aconnector->base,
389 &adev->dm.mst_encoders[i].base);
390 }
391
392 connector->max_bpc_property = master->base.max_bpc_property;
393 if (connector->max_bpc_property)
394 drm_connector_attach_max_bpc_property(connector, 8, 16);
395
396 connector->vrr_capable_property = master->base.vrr_capable_property;
397 if (connector->vrr_capable_property)
398 drm_connector_attach_vrr_capable_property(connector);
399
400 drm_object_attach_property(
401 &connector->base,
402 dev->mode_config.path_property,
403 0);
404 drm_object_attach_property(
405 &connector->base,
406 dev->mode_config.tile_property,
407 0);
408
409 drm_connector_set_path_property(connector, pathprop);
410
411 /*
412 * Initialize connector state before adding the connectror to drm and
413 * framebuffer lists
414 */
415 amdgpu_dm_connector_funcs_reset(connector);
416
417 drm_dp_mst_get_port_malloc(port);
418
419 return connector;
420 }
421
422 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
423 .add_connector = dm_dp_add_mst_connector,
424 };
425
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)426 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
427 struct amdgpu_dm_connector *aconnector,
428 int link_index)
429 {
430 aconnector->dm_dp_aux.aux.name =
431 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
432 link_index);
433 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
434 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
435
436 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
437 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
438 &aconnector->base);
439
440 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
441 return;
442
443 aconnector->mst_mgr.cbs = &dm_mst_cbs;
444 drm_dp_mst_topology_mgr_init(
445 &aconnector->mst_mgr,
446 adev_to_drm(dm->adev),
447 &aconnector->dm_dp_aux.aux,
448 16,
449 4,
450 aconnector->connector_id);
451
452 drm_connector_attach_dp_subconnector_property(&aconnector->base);
453 }
454
dm_mst_get_pbn_divider(struct dc_link * link)455 int dm_mst_get_pbn_divider(struct dc_link *link)
456 {
457 if (!link)
458 return 0;
459
460 return dc_link_bandwidth_kbps(link,
461 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
462 }
463
464 #if defined(CONFIG_DRM_AMD_DC_DCN)
465
466 struct dsc_mst_fairness_params {
467 struct dc_crtc_timing *timing;
468 struct dc_sink *sink;
469 struct dc_dsc_bw_range bw_range;
470 bool compression_possible;
471 struct drm_dp_mst_port *port;
472 enum dsc_clock_force_state clock_force_enable;
473 uint32_t num_slices_h;
474 uint32_t num_slices_v;
475 uint32_t bpp_overwrite;
476 };
477
478 struct dsc_mst_fairness_vars {
479 int pbn;
480 bool dsc_enabled;
481 int bpp_x16;
482 };
483
kbps_to_peak_pbn(int kbps)484 static int kbps_to_peak_pbn(int kbps)
485 {
486 u64 peak_kbps = kbps;
487
488 peak_kbps *= 1006;
489 peak_kbps = div_u64(peak_kbps, 1000);
490 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
491 }
492
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)493 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
494 struct dsc_mst_fairness_vars *vars,
495 int count)
496 {
497 int i;
498
499 for (i = 0; i < count; i++) {
500 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
501 if (vars[i].dsc_enabled && dc_dsc_compute_config(
502 params[i].sink->ctx->dc->res_pool->dscs[0],
503 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
504 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
505 0,
506 params[i].timing,
507 ¶ms[i].timing->dsc_cfg)) {
508 params[i].timing->flags.DSC = 1;
509
510 if (params[i].bpp_overwrite)
511 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
512 else
513 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
514
515 if (params[i].num_slices_h)
516 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
517
518 if (params[i].num_slices_v)
519 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
520 } else {
521 params[i].timing->flags.DSC = 0;
522 }
523 }
524 }
525
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)526 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
527 {
528 struct dc_dsc_config dsc_config;
529 u64 kbps;
530
531 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
532 dc_dsc_compute_config(
533 param.sink->ctx->dc->res_pool->dscs[0],
534 ¶m.sink->dsc_caps.dsc_dec_caps,
535 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
536 (int) kbps, param.timing, &dsc_config);
537
538 return dsc_config.bits_per_pixel;
539 }
540
increase_dsc_bpp(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)541 static void increase_dsc_bpp(struct drm_atomic_state *state,
542 struct dc_link *dc_link,
543 struct dsc_mst_fairness_params *params,
544 struct dsc_mst_fairness_vars *vars,
545 int count)
546 {
547 int i;
548 bool bpp_increased[MAX_PIPES];
549 int initial_slack[MAX_PIPES];
550 int min_initial_slack;
551 int next_index;
552 int remaining_to_increase = 0;
553 int pbn_per_timeslot;
554 int link_timeslots_used;
555 int fair_pbn_alloc;
556
557 pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
558
559 for (i = 0; i < count; i++) {
560 if (vars[i].dsc_enabled) {
561 initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
562 bpp_increased[i] = false;
563 remaining_to_increase += 1;
564 } else {
565 initial_slack[i] = 0;
566 bpp_increased[i] = true;
567 }
568 }
569
570 while (remaining_to_increase) {
571 next_index = -1;
572 min_initial_slack = -1;
573 for (i = 0; i < count; i++) {
574 if (!bpp_increased[i]) {
575 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
576 min_initial_slack = initial_slack[i];
577 next_index = i;
578 }
579 }
580 }
581
582 if (next_index == -1)
583 break;
584
585 link_timeslots_used = 0;
586
587 for (i = 0; i < count; i++)
588 link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
589
590 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
591
592 if (initial_slack[next_index] > fair_pbn_alloc) {
593 vars[next_index].pbn += fair_pbn_alloc;
594 if (drm_dp_atomic_find_vcpi_slots(state,
595 params[next_index].port->mgr,
596 params[next_index].port,
597 vars[next_index].pbn,
598 pbn_per_timeslot) < 0)
599 return;
600 if (!drm_dp_mst_atomic_check(state)) {
601 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
602 } else {
603 vars[next_index].pbn -= fair_pbn_alloc;
604 if (drm_dp_atomic_find_vcpi_slots(state,
605 params[next_index].port->mgr,
606 params[next_index].port,
607 vars[next_index].pbn,
608 pbn_per_timeslot) < 0)
609 return;
610 }
611 } else {
612 vars[next_index].pbn += initial_slack[next_index];
613 if (drm_dp_atomic_find_vcpi_slots(state,
614 params[next_index].port->mgr,
615 params[next_index].port,
616 vars[next_index].pbn,
617 pbn_per_timeslot) < 0)
618 return;
619 if (!drm_dp_mst_atomic_check(state)) {
620 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
621 } else {
622 vars[next_index].pbn -= initial_slack[next_index];
623 if (drm_dp_atomic_find_vcpi_slots(state,
624 params[next_index].port->mgr,
625 params[next_index].port,
626 vars[next_index].pbn,
627 pbn_per_timeslot) < 0)
628 return;
629 }
630 }
631
632 bpp_increased[next_index] = true;
633 remaining_to_increase--;
634 }
635 }
636
try_disable_dsc(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)637 static void try_disable_dsc(struct drm_atomic_state *state,
638 struct dc_link *dc_link,
639 struct dsc_mst_fairness_params *params,
640 struct dsc_mst_fairness_vars *vars,
641 int count)
642 {
643 int i;
644 bool tried[MAX_PIPES];
645 int kbps_increase[MAX_PIPES];
646 int max_kbps_increase;
647 int next_index;
648 int remaining_to_try = 0;
649
650 for (i = 0; i < count; i++) {
651 if (vars[i].dsc_enabled
652 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
653 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
654 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
655 tried[i] = false;
656 remaining_to_try += 1;
657 } else {
658 kbps_increase[i] = 0;
659 tried[i] = true;
660 }
661 }
662
663 while (remaining_to_try) {
664 next_index = -1;
665 max_kbps_increase = -1;
666 for (i = 0; i < count; i++) {
667 if (!tried[i]) {
668 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
669 max_kbps_increase = kbps_increase[i];
670 next_index = i;
671 }
672 }
673 }
674
675 if (next_index == -1)
676 break;
677
678 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
679 if (drm_dp_atomic_find_vcpi_slots(state,
680 params[next_index].port->mgr,
681 params[next_index].port,
682 vars[next_index].pbn,
683 dm_mst_get_pbn_divider(dc_link)) < 0)
684 return;
685
686 if (!drm_dp_mst_atomic_check(state)) {
687 vars[next_index].dsc_enabled = false;
688 vars[next_index].bpp_x16 = 0;
689 } else {
690 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
691 if (drm_dp_atomic_find_vcpi_slots(state,
692 params[next_index].port->mgr,
693 params[next_index].port,
694 vars[next_index].pbn,
695 dm_mst_get_pbn_divider(dc_link)) < 0)
696 return;
697 }
698
699 tried[next_index] = true;
700 remaining_to_try--;
701 }
702 }
703
compute_mst_dsc_configs_for_link(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link)704 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
705 struct dc_state *dc_state,
706 struct dc_link *dc_link)
707 {
708 int i;
709 struct dc_stream_state *stream;
710 struct dsc_mst_fairness_params params[MAX_PIPES];
711 struct dsc_mst_fairness_vars vars[MAX_PIPES];
712 struct amdgpu_dm_connector *aconnector;
713 int count = 0;
714 bool debugfs_overwrite = false;
715
716 memset(params, 0, sizeof(params));
717
718 /* Set up params */
719 for (i = 0; i < dc_state->stream_count; i++) {
720 struct dc_dsc_policy dsc_policy = {0};
721
722 stream = dc_state->streams[i];
723
724 if (stream->link != dc_link)
725 continue;
726
727 stream->timing.flags.DSC = 0;
728
729 params[count].timing = &stream->timing;
730 params[count].sink = stream->sink;
731 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
732 params[count].port = aconnector->port;
733 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
734 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
735 debugfs_overwrite = true;
736 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
737 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
738 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
739 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
740 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
741 if (!dc_dsc_compute_bandwidth_range(
742 stream->sink->ctx->dc->res_pool->dscs[0],
743 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
744 dsc_policy.min_target_bpp,
745 dsc_policy.max_target_bpp,
746 &stream->sink->dsc_caps.dsc_dec_caps,
747 &stream->timing, ¶ms[count].bw_range))
748 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
749
750 count++;
751 }
752 /* Try no compression */
753 for (i = 0; i < count; i++) {
754 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
755 vars[i].dsc_enabled = false;
756 vars[i].bpp_x16 = 0;
757 if (drm_dp_atomic_find_vcpi_slots(state,
758 params[i].port->mgr,
759 params[i].port,
760 vars[i].pbn,
761 dm_mst_get_pbn_divider(dc_link)) < 0)
762 return false;
763 }
764 if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
765 set_dsc_configs_from_fairness_vars(params, vars, count);
766 return true;
767 }
768
769 /* Try max compression */
770 for (i = 0; i < count; i++) {
771 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
772 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
773 vars[i].dsc_enabled = true;
774 vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
775 if (drm_dp_atomic_find_vcpi_slots(state,
776 params[i].port->mgr,
777 params[i].port,
778 vars[i].pbn,
779 dm_mst_get_pbn_divider(dc_link)) < 0)
780 return false;
781 } else {
782 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
783 vars[i].dsc_enabled = false;
784 vars[i].bpp_x16 = 0;
785 if (drm_dp_atomic_find_vcpi_slots(state,
786 params[i].port->mgr,
787 params[i].port,
788 vars[i].pbn,
789 dm_mst_get_pbn_divider(dc_link)) < 0)
790 return false;
791 }
792 }
793 if (drm_dp_mst_atomic_check(state))
794 return false;
795
796 /* Optimize degree of compression */
797 increase_dsc_bpp(state, dc_link, params, vars, count);
798
799 try_disable_dsc(state, dc_link, params, vars, count);
800
801 set_dsc_configs_from_fairness_vars(params, vars, count);
802
803 return true;
804 }
805
compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state)806 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
807 struct dc_state *dc_state)
808 {
809 int i, j;
810 struct dc_stream_state *stream;
811 bool computed_streams[MAX_PIPES];
812 struct amdgpu_dm_connector *aconnector;
813
814 for (i = 0; i < dc_state->stream_count; i++)
815 computed_streams[i] = false;
816
817 for (i = 0; i < dc_state->stream_count; i++) {
818 stream = dc_state->streams[i];
819
820 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
821 continue;
822
823 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
824
825 if (!aconnector || !aconnector->dc_sink)
826 continue;
827
828 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
829 continue;
830
831 if (computed_streams[i])
832 continue;
833
834 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
835 return false;
836
837 mutex_lock(&aconnector->mst_mgr.lock);
838 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
839 mutex_unlock(&aconnector->mst_mgr.lock);
840 return false;
841 }
842 mutex_unlock(&aconnector->mst_mgr.lock);
843
844 for (j = 0; j < dc_state->stream_count; j++) {
845 if (dc_state->streams[j]->link == stream->link)
846 computed_streams[j] = true;
847 }
848 }
849
850 for (i = 0; i < dc_state->stream_count; i++) {
851 stream = dc_state->streams[i];
852
853 if (stream->timing.flags.DSC == 1)
854 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
855 return false;
856 }
857
858 return true;
859 }
860
861 #endif
862