1 /*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
36 #include <linux/mm.h>
37
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
47 #include <asm/apic.h>
48 #include <asm/io_apic.h>
49 #include <asm/desc.h>
50 #include <asm/hpet.h>
51 #include <asm/mtrr.h>
52 #include <asm/time.h>
53 #include <asm/smp.h>
54 #include <asm/mce.h>
55 #include <asm/tsc.h>
56 #include <asm/hypervisor.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/intel-family.h>
59 #include <asm/irq_regs.h>
60
61 unsigned int num_processors;
62
63 unsigned disabled_cpus;
64
65 /* Processor that is doing the boot up */
66 unsigned int boot_cpu_physical_apicid = -1U;
67 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
68
69 u8 boot_cpu_apic_version;
70
71 /*
72 * The highest APIC ID seen during enumeration.
73 */
74 static unsigned int max_physical_apicid;
75
76 /*
77 * Bitmask of physically existing CPUs:
78 */
79 physid_mask_t phys_cpu_present_map;
80
81 /*
82 * Processor to be disabled specified by kernel parameter
83 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
84 * avoid undefined behaviour caused by sending INIT from AP to BSP.
85 */
86 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
87
88 /*
89 * This variable controls which CPUs receive external NMIs. By default,
90 * external NMIs are delivered only to the BSP.
91 */
92 static int apic_extnmi = APIC_EXTNMI_BSP;
93
94 /*
95 * Map cpu index to physical APIC ID
96 */
97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
103
104 #ifdef CONFIG_X86_32
105
106 /*
107 * On x86_32, the mapping between cpu and logical apicid may vary
108 * depending on apic in use. The following early percpu variable is
109 * used for the mapping. This is where the behaviors of x86_64 and 32
110 * actually diverge. Let's keep it ugly for now.
111 */
112 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
113
114 /* Local APIC was disabled by the BIOS and enabled by the kernel */
115 static int enabled_via_apicbase;
116
117 /*
118 * Handle interrupt mode configuration register (IMCR).
119 * This register controls whether the interrupt signals
120 * that reach the BSP come from the master PIC or from the
121 * local APIC. Before entering Symmetric I/O Mode, either
122 * the BIOS or the operating system must switch out of
123 * PIC Mode by changing the IMCR.
124 */
imcr_pic_to_apic(void)125 static inline void imcr_pic_to_apic(void)
126 {
127 /* select IMCR register */
128 outb(0x70, 0x22);
129 /* NMI and 8259 INTR go through APIC */
130 outb(0x01, 0x23);
131 }
132
imcr_apic_to_pic(void)133 static inline void imcr_apic_to_pic(void)
134 {
135 /* select IMCR register */
136 outb(0x70, 0x22);
137 /* NMI and 8259 INTR go directly to BSP */
138 outb(0x00, 0x23);
139 }
140 #endif
141
142 /*
143 * Knob to control our willingness to enable the local APIC.
144 *
145 * +1=force-enable
146 */
147 static int force_enable_local_apic __initdata;
148
149 /*
150 * APIC command line parameters
151 */
parse_lapic(char * arg)152 static int __init parse_lapic(char *arg)
153 {
154 if (IS_ENABLED(CONFIG_X86_32) && !arg)
155 force_enable_local_apic = 1;
156 else if (arg && !strncmp(arg, "notscdeadline", 13))
157 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
158 return 0;
159 }
160 early_param("lapic", parse_lapic);
161
162 #ifdef CONFIG_X86_64
163 static int apic_calibrate_pmtmr __initdata;
setup_apicpmtimer(char * s)164 static __init int setup_apicpmtimer(char *s)
165 {
166 apic_calibrate_pmtmr = 1;
167 notsc_setup(NULL);
168 return 0;
169 }
170 __setup("apicpmtimer", setup_apicpmtimer);
171 #endif
172
173 unsigned long mp_lapic_addr;
174 int disable_apic;
175 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
176 static int disable_apic_timer __initdata;
177 /* Local APIC timer works in C2 */
178 int local_apic_timer_c2_ok;
179 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
180
181 /*
182 * Debug level, exported for io_apic.c
183 */
184 int apic_verbosity;
185
186 int pic_mode;
187
188 /* Have we found an MP table */
189 int smp_found_config;
190
191 static struct resource lapic_resource = {
192 .name = "Local APIC",
193 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
194 };
195
196 unsigned int lapic_timer_frequency = 0;
197
198 static void apic_pm_activate(void);
199
200 static unsigned long apic_phys;
201
202 /*
203 * Get the LAPIC version
204 */
lapic_get_version(void)205 static inline int lapic_get_version(void)
206 {
207 return GET_APIC_VERSION(apic_read(APIC_LVR));
208 }
209
210 /*
211 * Check, if the APIC is integrated or a separate chip
212 */
lapic_is_integrated(void)213 static inline int lapic_is_integrated(void)
214 {
215 return APIC_INTEGRATED(lapic_get_version());
216 }
217
218 /*
219 * Check, whether this is a modern or a first generation APIC
220 */
modern_apic(void)221 static int modern_apic(void)
222 {
223 /* AMD systems use old APIC versions, so check the CPU */
224 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
225 boot_cpu_data.x86 >= 0xf)
226 return 1;
227 return lapic_get_version() >= 0x14;
228 }
229
230 /*
231 * right after this call apic become NOOP driven
232 * so apic->write/read doesn't do anything
233 */
apic_disable(void)234 static void __init apic_disable(void)
235 {
236 pr_info("APIC: switched to apic NOOP\n");
237 apic = &apic_noop;
238 }
239
native_apic_wait_icr_idle(void)240 void native_apic_wait_icr_idle(void)
241 {
242 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
243 cpu_relax();
244 }
245
native_safe_apic_wait_icr_idle(void)246 u32 native_safe_apic_wait_icr_idle(void)
247 {
248 u32 send_status;
249 int timeout;
250
251 timeout = 0;
252 do {
253 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
254 if (!send_status)
255 break;
256 inc_irq_stat(icr_read_retry_count);
257 udelay(100);
258 } while (timeout++ < 1000);
259
260 return send_status;
261 }
262
native_apic_icr_write(u32 low,u32 id)263 void native_apic_icr_write(u32 low, u32 id)
264 {
265 unsigned long flags;
266
267 local_irq_save(flags);
268 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
269 apic_write(APIC_ICR, low);
270 local_irq_restore(flags);
271 }
272
native_apic_icr_read(void)273 u64 native_apic_icr_read(void)
274 {
275 u32 icr1, icr2;
276
277 icr2 = apic_read(APIC_ICR2);
278 icr1 = apic_read(APIC_ICR);
279
280 return icr1 | ((u64)icr2 << 32);
281 }
282
283 #ifdef CONFIG_X86_32
284 /**
285 * get_physical_broadcast - Get number of physical broadcast IDs
286 */
get_physical_broadcast(void)287 int get_physical_broadcast(void)
288 {
289 return modern_apic() ? 0xff : 0xf;
290 }
291 #endif
292
293 /**
294 * lapic_get_maxlvt - get the maximum number of local vector table entries
295 */
lapic_get_maxlvt(void)296 int lapic_get_maxlvt(void)
297 {
298 /*
299 * - we always have APIC integrated on 64bit mode
300 * - 82489DXs do not report # of LVT entries
301 */
302 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
303 }
304
305 /*
306 * Local APIC timer
307 */
308
309 /* Clock divisor */
310 #define APIC_DIVISOR 16
311 #define TSC_DIVISOR 8
312
313 /*
314 * This function sets up the local APIC timer, with a timeout of
315 * 'clocks' APIC bus clock. During calibration we actually call
316 * this function twice on the boot CPU, once with a bogus timeout
317 * value, second time for real. The other (noncalibrating) CPUs
318 * call this function only once, with the real, calibrated value.
319 *
320 * We do reads before writes even if unnecessary, to get around the
321 * P5 APIC double write bug.
322 */
__setup_APIC_LVTT(unsigned int clocks,int oneshot,int irqen)323 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
324 {
325 unsigned int lvtt_value, tmp_value;
326
327 lvtt_value = LOCAL_TIMER_VECTOR;
328 if (!oneshot)
329 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
330 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
331 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
332
333 if (!lapic_is_integrated())
334 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
335
336 if (!irqen)
337 lvtt_value |= APIC_LVT_MASKED;
338
339 apic_write(APIC_LVTT, lvtt_value);
340
341 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
342 /*
343 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
344 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
345 * According to Intel, MFENCE can do the serialization here.
346 */
347 asm volatile("mfence" : : : "memory");
348 return;
349 }
350
351 /*
352 * Divide PICLK by 16
353 */
354 tmp_value = apic_read(APIC_TDCR);
355 apic_write(APIC_TDCR,
356 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
357 APIC_TDR_DIV_16);
358
359 if (!oneshot)
360 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
361 }
362
363 /*
364 * Setup extended LVT, AMD specific
365 *
366 * Software should use the LVT offsets the BIOS provides. The offsets
367 * are determined by the subsystems using it like those for MCE
368 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
369 * are supported. Beginning with family 10h at least 4 offsets are
370 * available.
371 *
372 * Since the offsets must be consistent for all cores, we keep track
373 * of the LVT offsets in software and reserve the offset for the same
374 * vector also to be used on other cores. An offset is freed by
375 * setting the entry to APIC_EILVT_MASKED.
376 *
377 * If the BIOS is right, there should be no conflicts. Otherwise a
378 * "[Firmware Bug]: ..." error message is generated. However, if
379 * software does not properly determines the offsets, it is not
380 * necessarily a BIOS bug.
381 */
382
383 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
384
eilvt_entry_is_changeable(unsigned int old,unsigned int new)385 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
386 {
387 return (old & APIC_EILVT_MASKED)
388 || (new == APIC_EILVT_MASKED)
389 || ((new & ~APIC_EILVT_MASKED) == old);
390 }
391
reserve_eilvt_offset(int offset,unsigned int new)392 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
393 {
394 unsigned int rsvd, vector;
395
396 if (offset >= APIC_EILVT_NR_MAX)
397 return ~0;
398
399 rsvd = atomic_read(&eilvt_offsets[offset]);
400 do {
401 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
402 if (vector && !eilvt_entry_is_changeable(vector, new))
403 /* may not change if vectors are different */
404 return rsvd;
405 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
406 } while (rsvd != new);
407
408 rsvd &= ~APIC_EILVT_MASKED;
409 if (rsvd && rsvd != vector)
410 pr_info("LVT offset %d assigned for vector 0x%02x\n",
411 offset, rsvd);
412
413 return new;
414 }
415
416 /*
417 * If mask=1, the LVT entry does not generate interrupts while mask=0
418 * enables the vector. See also the BKDGs. Must be called with
419 * preemption disabled.
420 */
421
setup_APIC_eilvt(u8 offset,u8 vector,u8 msg_type,u8 mask)422 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
423 {
424 unsigned long reg = APIC_EILVTn(offset);
425 unsigned int new, old, reserved;
426
427 new = (mask << 16) | (msg_type << 8) | vector;
428 old = apic_read(reg);
429 reserved = reserve_eilvt_offset(offset, new);
430
431 if (reserved != new) {
432 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
433 "vector 0x%x, but the register is already in use for "
434 "vector 0x%x on another cpu\n",
435 smp_processor_id(), reg, offset, new, reserved);
436 return -EINVAL;
437 }
438
439 if (!eilvt_entry_is_changeable(old, new)) {
440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
441 "vector 0x%x, but the register is already in use for "
442 "vector 0x%x on this cpu\n",
443 smp_processor_id(), reg, offset, new, old);
444 return -EBUSY;
445 }
446
447 apic_write(reg, new);
448
449 return 0;
450 }
451 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
452
453 /*
454 * Program the next event, relative to now
455 */
lapic_next_event(unsigned long delta,struct clock_event_device * evt)456 static int lapic_next_event(unsigned long delta,
457 struct clock_event_device *evt)
458 {
459 apic_write(APIC_TMICT, delta);
460 return 0;
461 }
462
lapic_next_deadline(unsigned long delta,struct clock_event_device * evt)463 static int lapic_next_deadline(unsigned long delta,
464 struct clock_event_device *evt)
465 {
466 u64 tsc;
467
468 tsc = rdtsc();
469 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
470 return 0;
471 }
472
lapic_timer_shutdown(struct clock_event_device * evt)473 static int lapic_timer_shutdown(struct clock_event_device *evt)
474 {
475 unsigned int v;
476
477 /* Lapic used as dummy for broadcast ? */
478 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
479 return 0;
480
481 v = apic_read(APIC_LVTT);
482 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
483 apic_write(APIC_LVTT, v);
484 apic_write(APIC_TMICT, 0);
485 return 0;
486 }
487
488 static inline int
lapic_timer_set_periodic_oneshot(struct clock_event_device * evt,bool oneshot)489 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
490 {
491 /* Lapic used as dummy for broadcast ? */
492 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
493 return 0;
494
495 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
496 return 0;
497 }
498
lapic_timer_set_periodic(struct clock_event_device * evt)499 static int lapic_timer_set_periodic(struct clock_event_device *evt)
500 {
501 return lapic_timer_set_periodic_oneshot(evt, false);
502 }
503
lapic_timer_set_oneshot(struct clock_event_device * evt)504 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
505 {
506 return lapic_timer_set_periodic_oneshot(evt, true);
507 }
508
509 /*
510 * Local APIC timer broadcast function
511 */
lapic_timer_broadcast(const struct cpumask * mask)512 static void lapic_timer_broadcast(const struct cpumask *mask)
513 {
514 #ifdef CONFIG_SMP
515 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
516 #endif
517 }
518
519
520 /*
521 * The local apic timer can be used for any function which is CPU local.
522 */
523 static struct clock_event_device lapic_clockevent = {
524 .name = "lapic",
525 .features = CLOCK_EVT_FEAT_PERIODIC |
526 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
527 | CLOCK_EVT_FEAT_DUMMY,
528 .shift = 32,
529 .set_state_shutdown = lapic_timer_shutdown,
530 .set_state_periodic = lapic_timer_set_periodic,
531 .set_state_oneshot = lapic_timer_set_oneshot,
532 .set_state_oneshot_stopped = lapic_timer_shutdown,
533 .set_next_event = lapic_next_event,
534 .broadcast = lapic_timer_broadcast,
535 .rating = 100,
536 .irq = -1,
537 };
538 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
539
540 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
541 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
542
543 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
544 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
545
hsx_deadline_rev(void)546 static __init u32 hsx_deadline_rev(void)
547 {
548 switch (boot_cpu_data.x86_stepping) {
549 case 0x02: return 0x3a; /* EP */
550 case 0x04: return 0x0f; /* EX */
551 }
552
553 return ~0U;
554 }
555
bdx_deadline_rev(void)556 static __init u32 bdx_deadline_rev(void)
557 {
558 switch (boot_cpu_data.x86_stepping) {
559 case 0x02: return 0x00000011;
560 case 0x03: return 0x0700000e;
561 case 0x04: return 0x0f00000c;
562 case 0x05: return 0x0e000003;
563 }
564
565 return ~0U;
566 }
567
skx_deadline_rev(void)568 static __init u32 skx_deadline_rev(void)
569 {
570 switch (boot_cpu_data.x86_stepping) {
571 case 0x03: return 0x01000136;
572 case 0x04: return 0x02000014;
573 }
574
575 if (boot_cpu_data.x86_stepping > 4)
576 return 0;
577
578 return ~0U;
579 }
580
581 static const struct x86_cpu_id deadline_match[] __initconst = {
582 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
583 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
584 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
585 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
586
587 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
588 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
590
591 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
593
594 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
596
597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
599
600 {},
601 };
602
apic_validate_deadline_timer(void)603 static __init bool apic_validate_deadline_timer(void)
604 {
605 const struct x86_cpu_id *m;
606 u32 rev;
607
608 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
609 return false;
610 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
611 return true;
612
613 m = x86_match_cpu(deadline_match);
614 if (!m)
615 return true;
616
617 /*
618 * Function pointers will have the MSB set due to address layout,
619 * immediate revisions will not.
620 */
621 if ((long)m->driver_data < 0)
622 rev = ((u32 (*)(void))(m->driver_data))();
623 else
624 rev = (u32)m->driver_data;
625
626 if (boot_cpu_data.microcode >= rev)
627 return true;
628
629 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
630 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
631 "please update microcode to version: 0x%x (or later)\n", rev);
632 return false;
633 }
634
635 /*
636 * Setup the local APIC timer for this CPU. Copy the initialized values
637 * of the boot CPU and register the clock event in the framework.
638 */
setup_APIC_timer(void)639 static void setup_APIC_timer(void)
640 {
641 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
642
643 if (this_cpu_has(X86_FEATURE_ARAT)) {
644 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
645 /* Make LAPIC timer preferrable over percpu HPET */
646 lapic_clockevent.rating = 150;
647 }
648
649 memcpy(levt, &lapic_clockevent, sizeof(*levt));
650 levt->cpumask = cpumask_of(smp_processor_id());
651
652 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
653 levt->name = "lapic-deadline";
654 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
655 CLOCK_EVT_FEAT_DUMMY);
656 levt->set_next_event = lapic_next_deadline;
657 clockevents_config_and_register(levt,
658 tsc_khz * (1000 / TSC_DIVISOR),
659 0xF, ~0UL);
660 } else
661 clockevents_register_device(levt);
662 }
663
664 /*
665 * Install the updated TSC frequency from recalibration at the TSC
666 * deadline clockevent devices.
667 */
__lapic_update_tsc_freq(void * info)668 static void __lapic_update_tsc_freq(void *info)
669 {
670 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
671
672 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
673 return;
674
675 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
676 }
677
lapic_update_tsc_freq(void)678 void lapic_update_tsc_freq(void)
679 {
680 /*
681 * The clockevent device's ->mult and ->shift can both be
682 * changed. In order to avoid races, schedule the frequency
683 * update code on each CPU.
684 */
685 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
686 }
687
688 /*
689 * In this functions we calibrate APIC bus clocks to the external timer.
690 *
691 * We want to do the calibration only once since we want to have local timer
692 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
693 * frequency.
694 *
695 * This was previously done by reading the PIT/HPET and waiting for a wrap
696 * around to find out, that a tick has elapsed. I have a box, where the PIT
697 * readout is broken, so it never gets out of the wait loop again. This was
698 * also reported by others.
699 *
700 * Monitoring the jiffies value is inaccurate and the clockevents
701 * infrastructure allows us to do a simple substitution of the interrupt
702 * handler.
703 *
704 * The calibration routine also uses the pm_timer when possible, as the PIT
705 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
706 * back to normal later in the boot process).
707 */
708
709 #define LAPIC_CAL_LOOPS (HZ/10)
710
711 static __initdata int lapic_cal_loops = -1;
712 static __initdata long lapic_cal_t1, lapic_cal_t2;
713 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
714 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
715 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
716
717 /*
718 * Temporary interrupt handler and polled calibration function.
719 */
lapic_cal_handler(struct clock_event_device * dev)720 static void __init lapic_cal_handler(struct clock_event_device *dev)
721 {
722 unsigned long long tsc = 0;
723 long tapic = apic_read(APIC_TMCCT);
724 unsigned long pm = acpi_pm_read_early();
725
726 if (boot_cpu_has(X86_FEATURE_TSC))
727 tsc = rdtsc();
728
729 switch (lapic_cal_loops++) {
730 case 0:
731 lapic_cal_t1 = tapic;
732 lapic_cal_tsc1 = tsc;
733 lapic_cal_pm1 = pm;
734 lapic_cal_j1 = jiffies;
735 break;
736
737 case LAPIC_CAL_LOOPS:
738 lapic_cal_t2 = tapic;
739 lapic_cal_tsc2 = tsc;
740 if (pm < lapic_cal_pm1)
741 pm += ACPI_PM_OVRRUN;
742 lapic_cal_pm2 = pm;
743 lapic_cal_j2 = jiffies;
744 break;
745 }
746 }
747
748 static int __init
calibrate_by_pmtimer(long deltapm,long * delta,long * deltatsc)749 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
750 {
751 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
752 const long pm_thresh = pm_100ms / 100;
753 unsigned long mult;
754 u64 res;
755
756 #ifndef CONFIG_X86_PM_TIMER
757 return -1;
758 #endif
759
760 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
761
762 /* Check, if the PM timer is available */
763 if (!deltapm)
764 return -1;
765
766 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
767
768 if (deltapm > (pm_100ms - pm_thresh) &&
769 deltapm < (pm_100ms + pm_thresh)) {
770 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
771 return 0;
772 }
773
774 res = (((u64)deltapm) * mult) >> 22;
775 do_div(res, 1000000);
776 pr_warning("APIC calibration not consistent "
777 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
778
779 /* Correct the lapic counter value */
780 res = (((u64)(*delta)) * pm_100ms);
781 do_div(res, deltapm);
782 pr_info("APIC delta adjusted to PM-Timer: "
783 "%lu (%ld)\n", (unsigned long)res, *delta);
784 *delta = (long)res;
785
786 /* Correct the tsc counter value */
787 if (boot_cpu_has(X86_FEATURE_TSC)) {
788 res = (((u64)(*deltatsc)) * pm_100ms);
789 do_div(res, deltapm);
790 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
791 "PM-Timer: %lu (%ld)\n",
792 (unsigned long)res, *deltatsc);
793 *deltatsc = (long)res;
794 }
795
796 return 0;
797 }
798
calibrate_APIC_clock(void)799 static int __init calibrate_APIC_clock(void)
800 {
801 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
802 u64 tsc_perj = 0, tsc_start = 0;
803 unsigned long jif_start;
804 unsigned long deltaj;
805 long delta, deltatsc;
806 int pm_referenced = 0;
807
808 /**
809 * check if lapic timer has already been calibrated by platform
810 * specific routine, such as tsc calibration code. if so, we just fill
811 * in the clockevent structure and return.
812 */
813
814 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
815 return 0;
816 } else if (lapic_timer_frequency) {
817 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
818 lapic_timer_frequency);
819 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
820 TICK_NSEC, lapic_clockevent.shift);
821 lapic_clockevent.max_delta_ns =
822 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
823 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
824 lapic_clockevent.min_delta_ns =
825 clockevent_delta2ns(0xF, &lapic_clockevent);
826 lapic_clockevent.min_delta_ticks = 0xF;
827 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
828 return 0;
829 }
830
831 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
832 "calibrating APIC timer ...\n");
833
834 /*
835 * There are platforms w/o global clockevent devices. Instead of
836 * making the calibration conditional on that, use a polling based
837 * approach everywhere.
838 */
839 local_irq_disable();
840
841 /*
842 * Setup the APIC counter to maximum. There is no way the lapic
843 * can underflow in the 100ms detection time frame
844 */
845 __setup_APIC_LVTT(0xffffffff, 0, 0);
846
847 /*
848 * Methods to terminate the calibration loop:
849 * 1) Global clockevent if available (jiffies)
850 * 2) TSC if available and frequency is known
851 */
852 jif_start = READ_ONCE(jiffies);
853
854 if (tsc_khz) {
855 tsc_start = rdtsc();
856 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
857 }
858
859 /*
860 * Enable interrupts so the tick can fire, if a global
861 * clockevent device is available
862 */
863 local_irq_enable();
864
865 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
866 /* Wait for a tick to elapse */
867 while (1) {
868 if (tsc_khz) {
869 u64 tsc_now = rdtsc();
870 if ((tsc_now - tsc_start) >= tsc_perj) {
871 tsc_start += tsc_perj;
872 break;
873 }
874 } else {
875 unsigned long jif_now = READ_ONCE(jiffies);
876
877 if (time_after(jif_now, jif_start)) {
878 jif_start = jif_now;
879 break;
880 }
881 }
882 cpu_relax();
883 }
884
885 /* Invoke the calibration routine */
886 local_irq_disable();
887 lapic_cal_handler(NULL);
888 local_irq_enable();
889 }
890
891 local_irq_disable();
892
893 /* Build delta t1-t2 as apic timer counts down */
894 delta = lapic_cal_t1 - lapic_cal_t2;
895 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
896
897 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
898
899 /* we trust the PM based calibration if possible */
900 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
901 &delta, &deltatsc);
902
903 /* Calculate the scaled math multiplication factor */
904 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
905 lapic_clockevent.shift);
906 lapic_clockevent.max_delta_ns =
907 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
908 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
909 lapic_clockevent.min_delta_ns =
910 clockevent_delta2ns(0xF, &lapic_clockevent);
911 lapic_clockevent.min_delta_ticks = 0xF;
912
913 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
914
915 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
916 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
917 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
918 lapic_timer_frequency);
919
920 if (boot_cpu_has(X86_FEATURE_TSC)) {
921 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
922 "%ld.%04ld MHz.\n",
923 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
924 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
925 }
926
927 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
928 "%u.%04u MHz.\n",
929 lapic_timer_frequency / (1000000 / HZ),
930 lapic_timer_frequency % (1000000 / HZ));
931
932 /*
933 * Do a sanity check on the APIC calibration result
934 */
935 if (lapic_timer_frequency < (1000000 / HZ)) {
936 local_irq_enable();
937 pr_warning("APIC frequency too slow, disabling apic timer\n");
938 return -1;
939 }
940
941 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
942
943 /*
944 * PM timer calibration failed or not turned on so lets try APIC
945 * timer based calibration, if a global clockevent device is
946 * available.
947 */
948 if (!pm_referenced && global_clock_event) {
949 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
950
951 /*
952 * Setup the apic timer manually
953 */
954 levt->event_handler = lapic_cal_handler;
955 lapic_timer_set_periodic(levt);
956 lapic_cal_loops = -1;
957
958 /* Let the interrupts run */
959 local_irq_enable();
960
961 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
962 cpu_relax();
963
964 /* Stop the lapic timer */
965 local_irq_disable();
966 lapic_timer_shutdown(levt);
967
968 /* Jiffies delta */
969 deltaj = lapic_cal_j2 - lapic_cal_j1;
970 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
971
972 /* Check, if the jiffies result is consistent */
973 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
974 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
975 else
976 levt->features |= CLOCK_EVT_FEAT_DUMMY;
977 }
978 local_irq_enable();
979
980 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
981 pr_warning("APIC timer disabled due to verification failure\n");
982 return -1;
983 }
984
985 return 0;
986 }
987
988 /*
989 * Setup the boot APIC
990 *
991 * Calibrate and verify the result.
992 */
setup_boot_APIC_clock(void)993 void __init setup_boot_APIC_clock(void)
994 {
995 /*
996 * The local apic timer can be disabled via the kernel
997 * commandline or from the CPU detection code. Register the lapic
998 * timer as a dummy clock event source on SMP systems, so the
999 * broadcast mechanism is used. On UP systems simply ignore it.
1000 */
1001 if (disable_apic_timer) {
1002 pr_info("Disabling APIC timer\n");
1003 /* No broadcast on UP ! */
1004 if (num_possible_cpus() > 1) {
1005 lapic_clockevent.mult = 1;
1006 setup_APIC_timer();
1007 }
1008 return;
1009 }
1010
1011 if (calibrate_APIC_clock()) {
1012 /* No broadcast on UP ! */
1013 if (num_possible_cpus() > 1)
1014 setup_APIC_timer();
1015 return;
1016 }
1017
1018 /*
1019 * If nmi_watchdog is set to IO_APIC, we need the
1020 * PIT/HPET going. Otherwise register lapic as a dummy
1021 * device.
1022 */
1023 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1024
1025 /* Setup the lapic or request the broadcast */
1026 setup_APIC_timer();
1027 amd_e400_c1e_apic_setup();
1028 }
1029
setup_secondary_APIC_clock(void)1030 void setup_secondary_APIC_clock(void)
1031 {
1032 setup_APIC_timer();
1033 amd_e400_c1e_apic_setup();
1034 }
1035
1036 /*
1037 * The guts of the apic timer interrupt
1038 */
local_apic_timer_interrupt(void)1039 static void local_apic_timer_interrupt(void)
1040 {
1041 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1042
1043 /*
1044 * Normally we should not be here till LAPIC has been initialized but
1045 * in some cases like kdump, its possible that there is a pending LAPIC
1046 * timer interrupt from previous kernel's context and is delivered in
1047 * new kernel the moment interrupts are enabled.
1048 *
1049 * Interrupts are enabled early and LAPIC is setup much later, hence
1050 * its possible that when we get here evt->event_handler is NULL.
1051 * Check for event_handler being NULL and discard the interrupt as
1052 * spurious.
1053 */
1054 if (!evt->event_handler) {
1055 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1056 smp_processor_id());
1057 /* Switch it off */
1058 lapic_timer_shutdown(evt);
1059 return;
1060 }
1061
1062 /*
1063 * the NMI deadlock-detector uses this.
1064 */
1065 inc_irq_stat(apic_timer_irqs);
1066
1067 evt->event_handler(evt);
1068 }
1069
1070 /*
1071 * Local APIC timer interrupt. This is the most natural way for doing
1072 * local interrupts, but local timer interrupts can be emulated by
1073 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1074 *
1075 * [ if a single-CPU system runs an SMP kernel then we call the local
1076 * interrupt as well. Thus we cannot inline the local irq ... ]
1077 */
smp_apic_timer_interrupt(struct pt_regs * regs)1078 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1079 {
1080 struct pt_regs *old_regs = set_irq_regs(regs);
1081
1082 /*
1083 * NOTE! We'd better ACK the irq immediately,
1084 * because timer handling can be slow.
1085 *
1086 * update_process_times() expects us to have done irq_enter().
1087 * Besides, if we don't timer interrupts ignore the global
1088 * interrupt lock, which is the WrongThing (tm) to do.
1089 */
1090 entering_ack_irq();
1091 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1092 local_apic_timer_interrupt();
1093 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1094 exiting_irq();
1095
1096 set_irq_regs(old_regs);
1097 }
1098
setup_profiling_timer(unsigned int multiplier)1099 int setup_profiling_timer(unsigned int multiplier)
1100 {
1101 return -EINVAL;
1102 }
1103
1104 /*
1105 * Local APIC start and shutdown
1106 */
1107
1108 /**
1109 * clear_local_APIC - shutdown the local APIC
1110 *
1111 * This is called, when a CPU is disabled and before rebooting, so the state of
1112 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1113 * leftovers during boot.
1114 */
clear_local_APIC(void)1115 void clear_local_APIC(void)
1116 {
1117 int maxlvt;
1118 u32 v;
1119
1120 /* APIC hasn't been mapped yet */
1121 if (!x2apic_mode && !apic_phys)
1122 return;
1123
1124 maxlvt = lapic_get_maxlvt();
1125 /*
1126 * Masking an LVT entry can trigger a local APIC error
1127 * if the vector is zero. Mask LVTERR first to prevent this.
1128 */
1129 if (maxlvt >= 3) {
1130 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1131 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1132 }
1133 /*
1134 * Careful: we have to set masks only first to deassert
1135 * any level-triggered sources.
1136 */
1137 v = apic_read(APIC_LVTT);
1138 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1139 v = apic_read(APIC_LVT0);
1140 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1141 v = apic_read(APIC_LVT1);
1142 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1143 if (maxlvt >= 4) {
1144 v = apic_read(APIC_LVTPC);
1145 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1146 }
1147
1148 /* lets not touch this if we didn't frob it */
1149 #ifdef CONFIG_X86_THERMAL_VECTOR
1150 if (maxlvt >= 5) {
1151 v = apic_read(APIC_LVTTHMR);
1152 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1153 }
1154 #endif
1155 #ifdef CONFIG_X86_MCE_INTEL
1156 if (maxlvt >= 6) {
1157 v = apic_read(APIC_LVTCMCI);
1158 if (!(v & APIC_LVT_MASKED))
1159 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1160 }
1161 #endif
1162
1163 /*
1164 * Clean APIC state for other OSs:
1165 */
1166 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1167 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1168 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1169 if (maxlvt >= 3)
1170 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1171 if (maxlvt >= 4)
1172 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1173
1174 /* Integrated APIC (!82489DX) ? */
1175 if (lapic_is_integrated()) {
1176 if (maxlvt > 3)
1177 /* Clear ESR due to Pentium errata 3AP and 11AP */
1178 apic_write(APIC_ESR, 0);
1179 apic_read(APIC_ESR);
1180 }
1181 }
1182
1183 /**
1184 * disable_local_APIC - clear and disable the local APIC
1185 */
disable_local_APIC(void)1186 void disable_local_APIC(void)
1187 {
1188 unsigned int value;
1189
1190 /* APIC hasn't been mapped yet */
1191 if (!x2apic_mode && !apic_phys)
1192 return;
1193
1194 clear_local_APIC();
1195
1196 /*
1197 * Disable APIC (implies clearing of registers
1198 * for 82489DX!).
1199 */
1200 value = apic_read(APIC_SPIV);
1201 value &= ~APIC_SPIV_APIC_ENABLED;
1202 apic_write(APIC_SPIV, value);
1203
1204 #ifdef CONFIG_X86_32
1205 /*
1206 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1207 * restore the disabled state.
1208 */
1209 if (enabled_via_apicbase) {
1210 unsigned int l, h;
1211
1212 rdmsr(MSR_IA32_APICBASE, l, h);
1213 l &= ~MSR_IA32_APICBASE_ENABLE;
1214 wrmsr(MSR_IA32_APICBASE, l, h);
1215 }
1216 #endif
1217 }
1218
1219 /*
1220 * If Linux enabled the LAPIC against the BIOS default disable it down before
1221 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1222 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1223 * for the case where Linux didn't enable the LAPIC.
1224 */
lapic_shutdown(void)1225 void lapic_shutdown(void)
1226 {
1227 unsigned long flags;
1228
1229 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1230 return;
1231
1232 local_irq_save(flags);
1233
1234 #ifdef CONFIG_X86_32
1235 if (!enabled_via_apicbase)
1236 clear_local_APIC();
1237 else
1238 #endif
1239 disable_local_APIC();
1240
1241
1242 local_irq_restore(flags);
1243 }
1244
1245 /**
1246 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1247 */
sync_Arb_IDs(void)1248 void __init sync_Arb_IDs(void)
1249 {
1250 /*
1251 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1252 * needed on AMD.
1253 */
1254 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1255 return;
1256
1257 /*
1258 * Wait for idle.
1259 */
1260 apic_wait_icr_idle();
1261
1262 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1263 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1264 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1265 }
1266
1267 enum apic_intr_mode_id apic_intr_mode;
1268
apic_intr_mode_select(void)1269 static int __init apic_intr_mode_select(void)
1270 {
1271 /* Check kernel option */
1272 if (disable_apic) {
1273 pr_info("APIC disabled via kernel command line\n");
1274 return APIC_PIC;
1275 }
1276
1277 /* Check BIOS */
1278 #ifdef CONFIG_X86_64
1279 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1280 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1281 disable_apic = 1;
1282 pr_info("APIC disabled by BIOS\n");
1283 return APIC_PIC;
1284 }
1285 #else
1286 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1287
1288 /* Neither 82489DX nor integrated APIC ? */
1289 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1290 disable_apic = 1;
1291 return APIC_PIC;
1292 }
1293
1294 /* If the BIOS pretends there is an integrated APIC ? */
1295 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1296 APIC_INTEGRATED(boot_cpu_apic_version)) {
1297 disable_apic = 1;
1298 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1299 boot_cpu_physical_apicid);
1300 return APIC_PIC;
1301 }
1302 #endif
1303
1304 /* Check MP table or ACPI MADT configuration */
1305 if (!smp_found_config) {
1306 disable_ioapic_support();
1307 if (!acpi_lapic) {
1308 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1309 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1310 }
1311 return APIC_VIRTUAL_WIRE;
1312 }
1313
1314 #ifdef CONFIG_SMP
1315 /* If SMP should be disabled, then really disable it! */
1316 if (!setup_max_cpus) {
1317 pr_info("APIC: SMP mode deactivated\n");
1318 return APIC_SYMMETRIC_IO_NO_ROUTING;
1319 }
1320
1321 if (read_apic_id() != boot_cpu_physical_apicid) {
1322 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1323 read_apic_id(), boot_cpu_physical_apicid);
1324 /* Or can we switch back to PIC here? */
1325 }
1326 #endif
1327
1328 return APIC_SYMMETRIC_IO;
1329 }
1330
1331 /*
1332 * An initial setup of the virtual wire mode.
1333 */
init_bsp_APIC(void)1334 void __init init_bsp_APIC(void)
1335 {
1336 unsigned int value;
1337
1338 /*
1339 * Don't do the setup now if we have a SMP BIOS as the
1340 * through-I/O-APIC virtual wire mode might be active.
1341 */
1342 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1343 return;
1344
1345 /*
1346 * Do not trust the local APIC being empty at bootup.
1347 */
1348 clear_local_APIC();
1349
1350 /*
1351 * Enable APIC.
1352 */
1353 value = apic_read(APIC_SPIV);
1354 value &= ~APIC_VECTOR_MASK;
1355 value |= APIC_SPIV_APIC_ENABLED;
1356
1357 #ifdef CONFIG_X86_32
1358 /* This bit is reserved on P4/Xeon and should be cleared */
1359 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1360 (boot_cpu_data.x86 == 15))
1361 value &= ~APIC_SPIV_FOCUS_DISABLED;
1362 else
1363 #endif
1364 value |= APIC_SPIV_FOCUS_DISABLED;
1365 value |= SPURIOUS_APIC_VECTOR;
1366 apic_write(APIC_SPIV, value);
1367
1368 /*
1369 * Set up the virtual wire mode.
1370 */
1371 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1372 value = APIC_DM_NMI;
1373 if (!lapic_is_integrated()) /* 82489DX */
1374 value |= APIC_LVT_LEVEL_TRIGGER;
1375 if (apic_extnmi == APIC_EXTNMI_NONE)
1376 value |= APIC_LVT_MASKED;
1377 apic_write(APIC_LVT1, value);
1378 }
1379
1380 /* Init the interrupt delivery mode for the BSP */
apic_intr_mode_init(void)1381 void __init apic_intr_mode_init(void)
1382 {
1383 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1384
1385 apic_intr_mode = apic_intr_mode_select();
1386
1387 switch (apic_intr_mode) {
1388 case APIC_PIC:
1389 pr_info("APIC: Keep in PIC mode(8259)\n");
1390 return;
1391 case APIC_VIRTUAL_WIRE:
1392 pr_info("APIC: Switch to virtual wire mode setup\n");
1393 default_setup_apic_routing();
1394 break;
1395 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1396 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1397 upmode = true;
1398 default_setup_apic_routing();
1399 break;
1400 case APIC_SYMMETRIC_IO:
1401 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1402 default_setup_apic_routing();
1403 break;
1404 case APIC_SYMMETRIC_IO_NO_ROUTING:
1405 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1406 break;
1407 }
1408
1409 apic_bsp_setup(upmode);
1410 }
1411
lapic_setup_esr(void)1412 static void lapic_setup_esr(void)
1413 {
1414 unsigned int oldvalue, value, maxlvt;
1415
1416 if (!lapic_is_integrated()) {
1417 pr_info("No ESR for 82489DX.\n");
1418 return;
1419 }
1420
1421 if (apic->disable_esr) {
1422 /*
1423 * Something untraceable is creating bad interrupts on
1424 * secondary quads ... for the moment, just leave the
1425 * ESR disabled - we can't do anything useful with the
1426 * errors anyway - mbligh
1427 */
1428 pr_info("Leaving ESR disabled.\n");
1429 return;
1430 }
1431
1432 maxlvt = lapic_get_maxlvt();
1433 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1434 apic_write(APIC_ESR, 0);
1435 oldvalue = apic_read(APIC_ESR);
1436
1437 /* enables sending errors */
1438 value = ERROR_APIC_VECTOR;
1439 apic_write(APIC_LVTERR, value);
1440
1441 /*
1442 * spec says clear errors after enabling vector.
1443 */
1444 if (maxlvt > 3)
1445 apic_write(APIC_ESR, 0);
1446 value = apic_read(APIC_ESR);
1447 if (value != oldvalue)
1448 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1449 "vector: 0x%08x after: 0x%08x\n",
1450 oldvalue, value);
1451 }
1452
1453 #define APIC_IR_REGS APIC_ISR_NR
1454 #define APIC_IR_BITS (APIC_IR_REGS * 32)
1455 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1456
1457 union apic_ir {
1458 unsigned long map[APIC_IR_MAPSIZE];
1459 u32 regs[APIC_IR_REGS];
1460 };
1461
apic_check_and_ack(union apic_ir * irr,union apic_ir * isr)1462 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1463 {
1464 int i, bit;
1465
1466 /* Read the IRRs */
1467 for (i = 0; i < APIC_IR_REGS; i++)
1468 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1469
1470 /* Read the ISRs */
1471 for (i = 0; i < APIC_IR_REGS; i++)
1472 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1473
1474 /*
1475 * If the ISR map is not empty. ACK the APIC and run another round
1476 * to verify whether a pending IRR has been unblocked and turned
1477 * into a ISR.
1478 */
1479 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1480 /*
1481 * There can be multiple ISR bits set when a high priority
1482 * interrupt preempted a lower priority one. Issue an ACK
1483 * per set bit.
1484 */
1485 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1486 ack_APIC_irq();
1487 return true;
1488 }
1489
1490 return !bitmap_empty(irr->map, APIC_IR_BITS);
1491 }
1492
1493 /*
1494 * After a crash, we no longer service the interrupts and a pending
1495 * interrupt from previous kernel might still have ISR bit set.
1496 *
1497 * Most probably by now the CPU has serviced that pending interrupt and it
1498 * might not have done the ack_APIC_irq() because it thought, interrupt
1499 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1500 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
1501 * a vector might get locked. It was noticed for timer irq (vector
1502 * 0x31). Issue an extra EOI to clear ISR.
1503 *
1504 * If there are pending IRR bits they turn into ISR bits after a higher
1505 * priority ISR bit has been acked.
1506 */
apic_pending_intr_clear(void)1507 static void apic_pending_intr_clear(void)
1508 {
1509 union apic_ir irr, isr;
1510 unsigned int i;
1511
1512 /* 512 loops are way oversized and give the APIC a chance to obey. */
1513 for (i = 0; i < 512; i++) {
1514 if (!apic_check_and_ack(&irr, &isr))
1515 return;
1516 }
1517 /* Dump the IRR/ISR content if that failed */
1518 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1519 }
1520
1521 /**
1522 * setup_local_APIC - setup the local APIC
1523 *
1524 * Used to setup local APIC while initializing BSP or bringing up APs.
1525 * Always called with preemption disabled.
1526 */
setup_local_APIC(void)1527 static void setup_local_APIC(void)
1528 {
1529 int cpu = smp_processor_id();
1530 unsigned int value;
1531
1532
1533 if (disable_apic) {
1534 disable_ioapic_support();
1535 return;
1536 }
1537
1538 /*
1539 * If this comes from kexec/kcrash the APIC might be enabled in
1540 * SPIV. Soft disable it before doing further initialization.
1541 */
1542 value = apic_read(APIC_SPIV);
1543 value &= ~APIC_SPIV_APIC_ENABLED;
1544 apic_write(APIC_SPIV, value);
1545
1546 #ifdef CONFIG_X86_32
1547 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1548 if (lapic_is_integrated() && apic->disable_esr) {
1549 apic_write(APIC_ESR, 0);
1550 apic_write(APIC_ESR, 0);
1551 apic_write(APIC_ESR, 0);
1552 apic_write(APIC_ESR, 0);
1553 }
1554 #endif
1555 perf_events_lapic_init();
1556
1557 /*
1558 * Double-check whether this APIC is really registered.
1559 * This is meaningless in clustered apic mode, so we skip it.
1560 */
1561 BUG_ON(!apic->apic_id_registered());
1562
1563 /*
1564 * Intel recommends to set DFR, LDR and TPR before enabling
1565 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1566 * document number 292116). So here it goes...
1567 */
1568 apic->init_apic_ldr();
1569
1570 #ifdef CONFIG_X86_32
1571 if (apic->dest_logical) {
1572 int logical_apicid, ldr_apicid;
1573
1574 /*
1575 * APIC LDR is initialized. If logical_apicid mapping was
1576 * initialized during get_smp_config(), make sure it matches
1577 * the actual value.
1578 */
1579 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1580 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1581 if (logical_apicid != BAD_APICID)
1582 WARN_ON(logical_apicid != ldr_apicid);
1583 /* Always use the value from LDR. */
1584 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1585 }
1586 #endif
1587
1588 /*
1589 * Set Task Priority to 'accept all'. We never change this
1590 * later on.
1591 */
1592 value = apic_read(APIC_TASKPRI);
1593 value &= ~APIC_TPRI_MASK;
1594 apic_write(APIC_TASKPRI, value);
1595
1596 /* Clear eventually stale ISR/IRR bits */
1597 apic_pending_intr_clear();
1598
1599 /*
1600 * Now that we are all set up, enable the APIC
1601 */
1602 value = apic_read(APIC_SPIV);
1603 value &= ~APIC_VECTOR_MASK;
1604 /*
1605 * Enable APIC
1606 */
1607 value |= APIC_SPIV_APIC_ENABLED;
1608
1609 #ifdef CONFIG_X86_32
1610 /*
1611 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1612 * certain networking cards. If high frequency interrupts are
1613 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1614 * entry is masked/unmasked at a high rate as well then sooner or
1615 * later IOAPIC line gets 'stuck', no more interrupts are received
1616 * from the device. If focus CPU is disabled then the hang goes
1617 * away, oh well :-(
1618 *
1619 * [ This bug can be reproduced easily with a level-triggered
1620 * PCI Ne2000 networking cards and PII/PIII processors, dual
1621 * BX chipset. ]
1622 */
1623 /*
1624 * Actually disabling the focus CPU check just makes the hang less
1625 * frequent as it makes the interrupt distributon model be more
1626 * like LRU than MRU (the short-term load is more even across CPUs).
1627 */
1628
1629 /*
1630 * - enable focus processor (bit==0)
1631 * - 64bit mode always use processor focus
1632 * so no need to set it
1633 */
1634 value &= ~APIC_SPIV_FOCUS_DISABLED;
1635 #endif
1636
1637 /*
1638 * Set spurious IRQ vector
1639 */
1640 value |= SPURIOUS_APIC_VECTOR;
1641 apic_write(APIC_SPIV, value);
1642
1643 /*
1644 * Set up LVT0, LVT1:
1645 *
1646 * set up through-local-APIC on the boot CPU's LINT0. This is not
1647 * strictly necessary in pure symmetric-IO mode, but sometimes
1648 * we delegate interrupts to the 8259A.
1649 */
1650 /*
1651 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1652 */
1653 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1654 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1655 value = APIC_DM_EXTINT;
1656 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1657 } else {
1658 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1659 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1660 }
1661 apic_write(APIC_LVT0, value);
1662
1663 /*
1664 * Only the BSP sees the LINT1 NMI signal by default. This can be
1665 * modified by apic_extnmi= boot option.
1666 */
1667 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1668 apic_extnmi == APIC_EXTNMI_ALL)
1669 value = APIC_DM_NMI;
1670 else
1671 value = APIC_DM_NMI | APIC_LVT_MASKED;
1672
1673 /* Is 82489DX ? */
1674 if (!lapic_is_integrated())
1675 value |= APIC_LVT_LEVEL_TRIGGER;
1676 apic_write(APIC_LVT1, value);
1677
1678 #ifdef CONFIG_X86_MCE_INTEL
1679 /* Recheck CMCI information after local APIC is up on CPU #0 */
1680 if (!cpu)
1681 cmci_recheck();
1682 #endif
1683 }
1684
end_local_APIC_setup(void)1685 static void end_local_APIC_setup(void)
1686 {
1687 lapic_setup_esr();
1688
1689 #ifdef CONFIG_X86_32
1690 {
1691 unsigned int value;
1692 /* Disable the local apic timer */
1693 value = apic_read(APIC_LVTT);
1694 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1695 apic_write(APIC_LVTT, value);
1696 }
1697 #endif
1698
1699 apic_pm_activate();
1700 }
1701
1702 /*
1703 * APIC setup function for application processors. Called from smpboot.c
1704 */
apic_ap_setup(void)1705 void apic_ap_setup(void)
1706 {
1707 setup_local_APIC();
1708 end_local_APIC_setup();
1709 }
1710
1711 #ifdef CONFIG_X86_X2APIC
1712 int x2apic_mode;
1713
1714 enum {
1715 X2APIC_OFF,
1716 X2APIC_ON,
1717 X2APIC_DISABLED,
1718 };
1719 static int x2apic_state;
1720
__x2apic_disable(void)1721 static void __x2apic_disable(void)
1722 {
1723 u64 msr;
1724
1725 if (!boot_cpu_has(X86_FEATURE_APIC))
1726 return;
1727
1728 rdmsrl(MSR_IA32_APICBASE, msr);
1729 if (!(msr & X2APIC_ENABLE))
1730 return;
1731 /* Disable xapic and x2apic first and then reenable xapic mode */
1732 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1733 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1734 printk_once(KERN_INFO "x2apic disabled\n");
1735 }
1736
__x2apic_enable(void)1737 static void __x2apic_enable(void)
1738 {
1739 u64 msr;
1740
1741 rdmsrl(MSR_IA32_APICBASE, msr);
1742 if (msr & X2APIC_ENABLE)
1743 return;
1744 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1745 printk_once(KERN_INFO "x2apic enabled\n");
1746 }
1747
setup_nox2apic(char * str)1748 static int __init setup_nox2apic(char *str)
1749 {
1750 if (x2apic_enabled()) {
1751 int apicid = native_apic_msr_read(APIC_ID);
1752
1753 if (apicid >= 255) {
1754 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1755 apicid);
1756 return 0;
1757 }
1758 pr_warning("x2apic already enabled.\n");
1759 __x2apic_disable();
1760 }
1761 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1762 x2apic_state = X2APIC_DISABLED;
1763 x2apic_mode = 0;
1764 return 0;
1765 }
1766 early_param("nox2apic", setup_nox2apic);
1767
1768 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
x2apic_setup(void)1769 void x2apic_setup(void)
1770 {
1771 /*
1772 * If x2apic is not in ON state, disable it if already enabled
1773 * from BIOS.
1774 */
1775 if (x2apic_state != X2APIC_ON) {
1776 __x2apic_disable();
1777 return;
1778 }
1779 __x2apic_enable();
1780 }
1781
x2apic_disable(void)1782 static __init void x2apic_disable(void)
1783 {
1784 u32 x2apic_id, state = x2apic_state;
1785
1786 x2apic_mode = 0;
1787 x2apic_state = X2APIC_DISABLED;
1788
1789 if (state != X2APIC_ON)
1790 return;
1791
1792 x2apic_id = read_apic_id();
1793 if (x2apic_id >= 255)
1794 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1795
1796 __x2apic_disable();
1797 register_lapic_address(mp_lapic_addr);
1798 }
1799
x2apic_enable(void)1800 static __init void x2apic_enable(void)
1801 {
1802 if (x2apic_state != X2APIC_OFF)
1803 return;
1804
1805 x2apic_mode = 1;
1806 x2apic_state = X2APIC_ON;
1807 __x2apic_enable();
1808 }
1809
try_to_enable_x2apic(int remap_mode)1810 static __init void try_to_enable_x2apic(int remap_mode)
1811 {
1812 if (x2apic_state == X2APIC_DISABLED)
1813 return;
1814
1815 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1816 /* IR is required if there is APIC ID > 255 even when running
1817 * under KVM
1818 */
1819 if (max_physical_apicid > 255 ||
1820 !x86_init.hyper.x2apic_available()) {
1821 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1822 x2apic_disable();
1823 return;
1824 }
1825
1826 /*
1827 * without IR all CPUs can be addressed by IOAPIC/MSI
1828 * only in physical mode
1829 */
1830 x2apic_phys = 1;
1831 }
1832 x2apic_enable();
1833 }
1834
check_x2apic(void)1835 void __init check_x2apic(void)
1836 {
1837 if (x2apic_enabled()) {
1838 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1839 x2apic_mode = 1;
1840 x2apic_state = X2APIC_ON;
1841 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1842 x2apic_state = X2APIC_DISABLED;
1843 }
1844 }
1845 #else /* CONFIG_X86_X2APIC */
validate_x2apic(void)1846 static int __init validate_x2apic(void)
1847 {
1848 if (!apic_is_x2apic_enabled())
1849 return 0;
1850 /*
1851 * Checkme: Can we simply turn off x2apic here instead of panic?
1852 */
1853 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1854 }
1855 early_initcall(validate_x2apic);
1856
try_to_enable_x2apic(int remap_mode)1857 static inline void try_to_enable_x2apic(int remap_mode) { }
__x2apic_enable(void)1858 static inline void __x2apic_enable(void) { }
1859 #endif /* !CONFIG_X86_X2APIC */
1860
enable_IR_x2apic(void)1861 void __init enable_IR_x2apic(void)
1862 {
1863 unsigned long flags;
1864 int ret, ir_stat;
1865
1866 if (skip_ioapic_setup) {
1867 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1868 return;
1869 }
1870
1871 ir_stat = irq_remapping_prepare();
1872 if (ir_stat < 0 && !x2apic_supported())
1873 return;
1874
1875 ret = save_ioapic_entries();
1876 if (ret) {
1877 pr_info("Saving IO-APIC state failed: %d\n", ret);
1878 return;
1879 }
1880
1881 local_irq_save(flags);
1882 legacy_pic->mask_all();
1883 mask_ioapic_entries();
1884
1885 /* If irq_remapping_prepare() succeeded, try to enable it */
1886 if (ir_stat >= 0)
1887 ir_stat = irq_remapping_enable();
1888 /* ir_stat contains the remap mode or an error code */
1889 try_to_enable_x2apic(ir_stat);
1890
1891 if (ir_stat < 0)
1892 restore_ioapic_entries();
1893 legacy_pic->restore_mask();
1894 local_irq_restore(flags);
1895 }
1896
1897 #ifdef CONFIG_X86_64
1898 /*
1899 * Detect and enable local APICs on non-SMP boards.
1900 * Original code written by Keir Fraser.
1901 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1902 * not correctly set up (usually the APIC timer won't work etc.)
1903 */
detect_init_APIC(void)1904 static int __init detect_init_APIC(void)
1905 {
1906 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1907 pr_info("No local APIC present\n");
1908 return -1;
1909 }
1910
1911 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1912 return 0;
1913 }
1914 #else
1915
apic_verify(void)1916 static int __init apic_verify(void)
1917 {
1918 u32 features, h, l;
1919
1920 /*
1921 * The APIC feature bit should now be enabled
1922 * in `cpuid'
1923 */
1924 features = cpuid_edx(1);
1925 if (!(features & (1 << X86_FEATURE_APIC))) {
1926 pr_warning("Could not enable APIC!\n");
1927 return -1;
1928 }
1929 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1930 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1931
1932 /* The BIOS may have set up the APIC at some other address */
1933 if (boot_cpu_data.x86 >= 6) {
1934 rdmsr(MSR_IA32_APICBASE, l, h);
1935 if (l & MSR_IA32_APICBASE_ENABLE)
1936 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1937 }
1938
1939 pr_info("Found and enabled local APIC!\n");
1940 return 0;
1941 }
1942
apic_force_enable(unsigned long addr)1943 int __init apic_force_enable(unsigned long addr)
1944 {
1945 u32 h, l;
1946
1947 if (disable_apic)
1948 return -1;
1949
1950 /*
1951 * Some BIOSes disable the local APIC in the APIC_BASE
1952 * MSR. This can only be done in software for Intel P6 or later
1953 * and AMD K7 (Model > 1) or later.
1954 */
1955 if (boot_cpu_data.x86 >= 6) {
1956 rdmsr(MSR_IA32_APICBASE, l, h);
1957 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1958 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1959 l &= ~MSR_IA32_APICBASE_BASE;
1960 l |= MSR_IA32_APICBASE_ENABLE | addr;
1961 wrmsr(MSR_IA32_APICBASE, l, h);
1962 enabled_via_apicbase = 1;
1963 }
1964 }
1965 return apic_verify();
1966 }
1967
1968 /*
1969 * Detect and initialize APIC
1970 */
detect_init_APIC(void)1971 static int __init detect_init_APIC(void)
1972 {
1973 /* Disabled by kernel option? */
1974 if (disable_apic)
1975 return -1;
1976
1977 switch (boot_cpu_data.x86_vendor) {
1978 case X86_VENDOR_AMD:
1979 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1980 (boot_cpu_data.x86 >= 15))
1981 break;
1982 goto no_apic;
1983 case X86_VENDOR_INTEL:
1984 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1985 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1986 break;
1987 goto no_apic;
1988 default:
1989 goto no_apic;
1990 }
1991
1992 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1993 /*
1994 * Over-ride BIOS and try to enable the local APIC only if
1995 * "lapic" specified.
1996 */
1997 if (!force_enable_local_apic) {
1998 pr_info("Local APIC disabled by BIOS -- "
1999 "you can enable it with \"lapic\"\n");
2000 return -1;
2001 }
2002 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2003 return -1;
2004 } else {
2005 if (apic_verify())
2006 return -1;
2007 }
2008
2009 apic_pm_activate();
2010
2011 return 0;
2012
2013 no_apic:
2014 pr_info("No local APIC present or hardware disabled\n");
2015 return -1;
2016 }
2017 #endif
2018
2019 /**
2020 * init_apic_mappings - initialize APIC mappings
2021 */
init_apic_mappings(void)2022 void __init init_apic_mappings(void)
2023 {
2024 unsigned int new_apicid;
2025
2026 if (apic_validate_deadline_timer())
2027 pr_info("TSC deadline timer available\n");
2028
2029 if (x2apic_mode) {
2030 boot_cpu_physical_apicid = read_apic_id();
2031 return;
2032 }
2033
2034 /* If no local APIC can be found return early */
2035 if (!smp_found_config && detect_init_APIC()) {
2036 /* lets NOP'ify apic operations */
2037 pr_info("APIC: disable apic facility\n");
2038 apic_disable();
2039 } else {
2040 apic_phys = mp_lapic_addr;
2041
2042 /*
2043 * If the system has ACPI MADT tables or MP info, the LAPIC
2044 * address is already registered.
2045 */
2046 if (!acpi_lapic && !smp_found_config)
2047 register_lapic_address(apic_phys);
2048 }
2049
2050 /*
2051 * Fetch the APIC ID of the BSP in case we have a
2052 * default configuration (or the MP table is broken).
2053 */
2054 new_apicid = read_apic_id();
2055 if (boot_cpu_physical_apicid != new_apicid) {
2056 boot_cpu_physical_apicid = new_apicid;
2057 /*
2058 * yeah -- we lie about apic_version
2059 * in case if apic was disabled via boot option
2060 * but it's not a problem for SMP compiled kernel
2061 * since apic_intr_mode_select is prepared for such
2062 * a case and disable smp mode
2063 */
2064 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2065 }
2066 }
2067
register_lapic_address(unsigned long address)2068 void __init register_lapic_address(unsigned long address)
2069 {
2070 mp_lapic_addr = address;
2071
2072 if (!x2apic_mode) {
2073 set_fixmap_nocache(FIX_APIC_BASE, address);
2074 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2075 APIC_BASE, address);
2076 }
2077 if (boot_cpu_physical_apicid == -1U) {
2078 boot_cpu_physical_apicid = read_apic_id();
2079 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2080 }
2081 }
2082
2083 /*
2084 * Local APIC interrupts
2085 */
2086
2087 /*
2088 * This interrupt should _never_ happen with our APIC/SMP architecture
2089 */
smp_spurious_interrupt(struct pt_regs * regs)2090 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2091 {
2092 u8 vector = ~regs->orig_ax;
2093 u32 v;
2094
2095 entering_irq();
2096 trace_spurious_apic_entry(vector);
2097
2098 inc_irq_stat(irq_spurious_count);
2099
2100 /*
2101 * If this is a spurious interrupt then do not acknowledge
2102 */
2103 if (vector == SPURIOUS_APIC_VECTOR) {
2104 /* See SDM vol 3 */
2105 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2106 smp_processor_id());
2107 goto out;
2108 }
2109
2110 /*
2111 * If it is a vectored one, verify it's set in the ISR. If set,
2112 * acknowledge it.
2113 */
2114 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2115 if (v & (1 << (vector & 0x1f))) {
2116 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2117 vector, smp_processor_id());
2118 ack_APIC_irq();
2119 } else {
2120 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2121 vector, smp_processor_id());
2122 }
2123 out:
2124 trace_spurious_apic_exit(vector);
2125 exiting_irq();
2126 }
2127
2128 /*
2129 * This interrupt should never happen with our APIC/SMP architecture
2130 */
smp_error_interrupt(struct pt_regs * regs)2131 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2132 {
2133 static const char * const error_interrupt_reason[] = {
2134 "Send CS error", /* APIC Error Bit 0 */
2135 "Receive CS error", /* APIC Error Bit 1 */
2136 "Send accept error", /* APIC Error Bit 2 */
2137 "Receive accept error", /* APIC Error Bit 3 */
2138 "Redirectable IPI", /* APIC Error Bit 4 */
2139 "Send illegal vector", /* APIC Error Bit 5 */
2140 "Received illegal vector", /* APIC Error Bit 6 */
2141 "Illegal register address", /* APIC Error Bit 7 */
2142 };
2143 u32 v, i = 0;
2144
2145 entering_irq();
2146 trace_error_apic_entry(ERROR_APIC_VECTOR);
2147
2148 /* First tickle the hardware, only then report what went on. -- REW */
2149 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2150 apic_write(APIC_ESR, 0);
2151 v = apic_read(APIC_ESR);
2152 ack_APIC_irq();
2153 atomic_inc(&irq_err_count);
2154
2155 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2156 smp_processor_id(), v);
2157
2158 v &= 0xff;
2159 while (v) {
2160 if (v & 0x1)
2161 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2162 i++;
2163 v >>= 1;
2164 }
2165
2166 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2167
2168 trace_error_apic_exit(ERROR_APIC_VECTOR);
2169 exiting_irq();
2170 }
2171
2172 /**
2173 * connect_bsp_APIC - attach the APIC to the interrupt system
2174 */
connect_bsp_APIC(void)2175 static void __init connect_bsp_APIC(void)
2176 {
2177 #ifdef CONFIG_X86_32
2178 if (pic_mode) {
2179 /*
2180 * Do not trust the local APIC being empty at bootup.
2181 */
2182 clear_local_APIC();
2183 /*
2184 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2185 * local APIC to INT and NMI lines.
2186 */
2187 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2188 "enabling APIC mode.\n");
2189 imcr_pic_to_apic();
2190 }
2191 #endif
2192 }
2193
2194 /**
2195 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2196 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2197 *
2198 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2199 * APIC is disabled.
2200 */
disconnect_bsp_APIC(int virt_wire_setup)2201 void disconnect_bsp_APIC(int virt_wire_setup)
2202 {
2203 unsigned int value;
2204
2205 #ifdef CONFIG_X86_32
2206 if (pic_mode) {
2207 /*
2208 * Put the board back into PIC mode (has an effect only on
2209 * certain older boards). Note that APIC interrupts, including
2210 * IPIs, won't work beyond this point! The only exception are
2211 * INIT IPIs.
2212 */
2213 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2214 "entering PIC mode.\n");
2215 imcr_apic_to_pic();
2216 return;
2217 }
2218 #endif
2219
2220 /* Go back to Virtual Wire compatibility mode */
2221
2222 /* For the spurious interrupt use vector F, and enable it */
2223 value = apic_read(APIC_SPIV);
2224 value &= ~APIC_VECTOR_MASK;
2225 value |= APIC_SPIV_APIC_ENABLED;
2226 value |= 0xf;
2227 apic_write(APIC_SPIV, value);
2228
2229 if (!virt_wire_setup) {
2230 /*
2231 * For LVT0 make it edge triggered, active high,
2232 * external and enabled
2233 */
2234 value = apic_read(APIC_LVT0);
2235 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2236 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2237 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2238 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2239 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2240 apic_write(APIC_LVT0, value);
2241 } else {
2242 /* Disable LVT0 */
2243 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2244 }
2245
2246 /*
2247 * For LVT1 make it edge triggered, active high,
2248 * nmi and enabled
2249 */
2250 value = apic_read(APIC_LVT1);
2251 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2252 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2253 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2254 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2255 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2256 apic_write(APIC_LVT1, value);
2257 }
2258
2259 /*
2260 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2261 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2262 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2263 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2264 *
2265 * NOTE: Reserve 0 for BSP.
2266 */
2267 static int nr_logical_cpuids = 1;
2268
2269 /*
2270 * Used to store mapping between logical CPU IDs and APIC IDs.
2271 */
2272 static int cpuid_to_apicid[] = {
2273 [0 ... NR_CPUS - 1] = -1,
2274 };
2275
2276 #ifdef CONFIG_SMP
2277 /**
2278 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2279 * @id: APIC ID to check
2280 */
apic_id_is_primary_thread(unsigned int apicid)2281 bool apic_id_is_primary_thread(unsigned int apicid)
2282 {
2283 u32 mask;
2284
2285 if (smp_num_siblings == 1)
2286 return true;
2287 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2288 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2289 return !(apicid & mask);
2290 }
2291 #endif
2292
2293 /*
2294 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2295 * and cpuid_to_apicid[] synchronized.
2296 */
allocate_logical_cpuid(int apicid)2297 static int allocate_logical_cpuid(int apicid)
2298 {
2299 int i;
2300
2301 /*
2302 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2303 * check if the kernel has allocated a cpuid for it.
2304 */
2305 for (i = 0; i < nr_logical_cpuids; i++) {
2306 if (cpuid_to_apicid[i] == apicid)
2307 return i;
2308 }
2309
2310 /* Allocate a new cpuid. */
2311 if (nr_logical_cpuids >= nr_cpu_ids) {
2312 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2313 "Processor %d/0x%x and the rest are ignored.\n",
2314 nr_cpu_ids, nr_logical_cpuids, apicid);
2315 return -EINVAL;
2316 }
2317
2318 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2319 return nr_logical_cpuids++;
2320 }
2321
generic_processor_info(int apicid,int version)2322 int generic_processor_info(int apicid, int version)
2323 {
2324 int cpu, max = nr_cpu_ids;
2325 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2326 phys_cpu_present_map);
2327
2328 /*
2329 * boot_cpu_physical_apicid is designed to have the apicid
2330 * returned by read_apic_id(), i.e, the apicid of the
2331 * currently booting-up processor. However, on some platforms,
2332 * it is temporarily modified by the apicid reported as BSP
2333 * through MP table. Concretely:
2334 *
2335 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2336 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2337 *
2338 * This function is executed with the modified
2339 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2340 * parameter doesn't work to disable APs on kdump 2nd kernel.
2341 *
2342 * Since fixing handling of boot_cpu_physical_apicid requires
2343 * another discussion and tests on each platform, we leave it
2344 * for now and here we use read_apic_id() directly in this
2345 * function, generic_processor_info().
2346 */
2347 if (disabled_cpu_apicid != BAD_APICID &&
2348 disabled_cpu_apicid != read_apic_id() &&
2349 disabled_cpu_apicid == apicid) {
2350 int thiscpu = num_processors + disabled_cpus;
2351
2352 pr_warning("APIC: Disabling requested cpu."
2353 " Processor %d/0x%x ignored.\n",
2354 thiscpu, apicid);
2355
2356 disabled_cpus++;
2357 return -ENODEV;
2358 }
2359
2360 /*
2361 * If boot cpu has not been detected yet, then only allow upto
2362 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2363 */
2364 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2365 apicid != boot_cpu_physical_apicid) {
2366 int thiscpu = max + disabled_cpus - 1;
2367
2368 pr_warning(
2369 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2370 " reached. Keeping one slot for boot cpu."
2371 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2372
2373 disabled_cpus++;
2374 return -ENODEV;
2375 }
2376
2377 if (num_processors >= nr_cpu_ids) {
2378 int thiscpu = max + disabled_cpus;
2379
2380 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2381 "reached. Processor %d/0x%x ignored.\n",
2382 max, thiscpu, apicid);
2383
2384 disabled_cpus++;
2385 return -EINVAL;
2386 }
2387
2388 if (apicid == boot_cpu_physical_apicid) {
2389 /*
2390 * x86_bios_cpu_apicid is required to have processors listed
2391 * in same order as logical cpu numbers. Hence the first
2392 * entry is BSP, and so on.
2393 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2394 * for BSP.
2395 */
2396 cpu = 0;
2397
2398 /* Logical cpuid 0 is reserved for BSP. */
2399 cpuid_to_apicid[0] = apicid;
2400 } else {
2401 cpu = allocate_logical_cpuid(apicid);
2402 if (cpu < 0) {
2403 disabled_cpus++;
2404 return -EINVAL;
2405 }
2406 }
2407
2408 /*
2409 * Validate version
2410 */
2411 if (version == 0x0) {
2412 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2413 cpu, apicid);
2414 version = 0x10;
2415 }
2416
2417 if (version != boot_cpu_apic_version) {
2418 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2419 boot_cpu_apic_version, cpu, version);
2420 }
2421
2422 if (apicid > max_physical_apicid)
2423 max_physical_apicid = apicid;
2424
2425 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2426 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2427 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2428 #endif
2429 #ifdef CONFIG_X86_32
2430 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2431 apic->x86_32_early_logical_apicid(cpu);
2432 #endif
2433 set_cpu_possible(cpu, true);
2434 physid_set(apicid, phys_cpu_present_map);
2435 set_cpu_present(cpu, true);
2436 num_processors++;
2437
2438 return cpu;
2439 }
2440
hard_smp_processor_id(void)2441 int hard_smp_processor_id(void)
2442 {
2443 return read_apic_id();
2444 }
2445
2446 /*
2447 * Override the generic EOI implementation with an optimized version.
2448 * Only called during early boot when only one CPU is active and with
2449 * interrupts disabled, so we know this does not race with actual APIC driver
2450 * use.
2451 */
apic_set_eoi_write(void (* eoi_write)(u32 reg,u32 v))2452 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2453 {
2454 struct apic **drv;
2455
2456 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2457 /* Should happen once for each apic */
2458 WARN_ON((*drv)->eoi_write == eoi_write);
2459 (*drv)->native_eoi_write = (*drv)->eoi_write;
2460 (*drv)->eoi_write = eoi_write;
2461 }
2462 }
2463
apic_bsp_up_setup(void)2464 static void __init apic_bsp_up_setup(void)
2465 {
2466 #ifdef CONFIG_X86_64
2467 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2468 #else
2469 /*
2470 * Hack: In case of kdump, after a crash, kernel might be booting
2471 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2472 * might be zero if read from MP tables. Get it from LAPIC.
2473 */
2474 # ifdef CONFIG_CRASH_DUMP
2475 boot_cpu_physical_apicid = read_apic_id();
2476 # endif
2477 #endif
2478 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2479 }
2480
2481 /**
2482 * apic_bsp_setup - Setup function for local apic and io-apic
2483 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2484 *
2485 * Returns:
2486 * apic_id of BSP APIC
2487 */
apic_bsp_setup(bool upmode)2488 void __init apic_bsp_setup(bool upmode)
2489 {
2490 connect_bsp_APIC();
2491 if (upmode)
2492 apic_bsp_up_setup();
2493 setup_local_APIC();
2494
2495 enable_IO_APIC();
2496 end_local_APIC_setup();
2497 irq_remap_enable_fault_handling();
2498 setup_IO_APIC();
2499 }
2500
2501 #ifdef CONFIG_UP_LATE_INIT
up_late_init(void)2502 void __init up_late_init(void)
2503 {
2504 if (apic_intr_mode == APIC_PIC)
2505 return;
2506
2507 /* Setup local timer */
2508 x86_init.timers.setup_percpu_clockev();
2509 }
2510 #endif
2511
2512 /*
2513 * Power management
2514 */
2515 #ifdef CONFIG_PM
2516
2517 static struct {
2518 /*
2519 * 'active' is true if the local APIC was enabled by us and
2520 * not the BIOS; this signifies that we are also responsible
2521 * for disabling it before entering apm/acpi suspend
2522 */
2523 int active;
2524 /* r/w apic fields */
2525 unsigned int apic_id;
2526 unsigned int apic_taskpri;
2527 unsigned int apic_ldr;
2528 unsigned int apic_dfr;
2529 unsigned int apic_spiv;
2530 unsigned int apic_lvtt;
2531 unsigned int apic_lvtpc;
2532 unsigned int apic_lvt0;
2533 unsigned int apic_lvt1;
2534 unsigned int apic_lvterr;
2535 unsigned int apic_tmict;
2536 unsigned int apic_tdcr;
2537 unsigned int apic_thmr;
2538 unsigned int apic_cmci;
2539 } apic_pm_state;
2540
lapic_suspend(void)2541 static int lapic_suspend(void)
2542 {
2543 unsigned long flags;
2544 int maxlvt;
2545
2546 if (!apic_pm_state.active)
2547 return 0;
2548
2549 maxlvt = lapic_get_maxlvt();
2550
2551 apic_pm_state.apic_id = apic_read(APIC_ID);
2552 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2553 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2554 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2555 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2556 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2557 if (maxlvt >= 4)
2558 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2559 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2560 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2561 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2562 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2563 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2564 #ifdef CONFIG_X86_THERMAL_VECTOR
2565 if (maxlvt >= 5)
2566 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2567 #endif
2568 #ifdef CONFIG_X86_MCE_INTEL
2569 if (maxlvt >= 6)
2570 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2571 #endif
2572
2573 local_irq_save(flags);
2574 disable_local_APIC();
2575
2576 irq_remapping_disable();
2577
2578 local_irq_restore(flags);
2579 return 0;
2580 }
2581
lapic_resume(void)2582 static void lapic_resume(void)
2583 {
2584 unsigned int l, h;
2585 unsigned long flags;
2586 int maxlvt;
2587
2588 if (!apic_pm_state.active)
2589 return;
2590
2591 local_irq_save(flags);
2592
2593 /*
2594 * IO-APIC and PIC have their own resume routines.
2595 * We just mask them here to make sure the interrupt
2596 * subsystem is completely quiet while we enable x2apic
2597 * and interrupt-remapping.
2598 */
2599 mask_ioapic_entries();
2600 legacy_pic->mask_all();
2601
2602 if (x2apic_mode) {
2603 __x2apic_enable();
2604 } else {
2605 /*
2606 * Make sure the APICBASE points to the right address
2607 *
2608 * FIXME! This will be wrong if we ever support suspend on
2609 * SMP! We'll need to do this as part of the CPU restore!
2610 */
2611 if (boot_cpu_data.x86 >= 6) {
2612 rdmsr(MSR_IA32_APICBASE, l, h);
2613 l &= ~MSR_IA32_APICBASE_BASE;
2614 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2615 wrmsr(MSR_IA32_APICBASE, l, h);
2616 }
2617 }
2618
2619 maxlvt = lapic_get_maxlvt();
2620 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2621 apic_write(APIC_ID, apic_pm_state.apic_id);
2622 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2623 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2624 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2625 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2626 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2627 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2628 #ifdef CONFIG_X86_THERMAL_VECTOR
2629 if (maxlvt >= 5)
2630 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2631 #endif
2632 #ifdef CONFIG_X86_MCE_INTEL
2633 if (maxlvt >= 6)
2634 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2635 #endif
2636 if (maxlvt >= 4)
2637 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2638 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2639 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2640 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2641 apic_write(APIC_ESR, 0);
2642 apic_read(APIC_ESR);
2643 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2644 apic_write(APIC_ESR, 0);
2645 apic_read(APIC_ESR);
2646
2647 irq_remapping_reenable(x2apic_mode);
2648
2649 local_irq_restore(flags);
2650 }
2651
2652 /*
2653 * This device has no shutdown method - fully functioning local APICs
2654 * are needed on every CPU up until machine_halt/restart/poweroff.
2655 */
2656
2657 static struct syscore_ops lapic_syscore_ops = {
2658 .resume = lapic_resume,
2659 .suspend = lapic_suspend,
2660 };
2661
apic_pm_activate(void)2662 static void apic_pm_activate(void)
2663 {
2664 apic_pm_state.active = 1;
2665 }
2666
init_lapic_sysfs(void)2667 static int __init init_lapic_sysfs(void)
2668 {
2669 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2670 if (boot_cpu_has(X86_FEATURE_APIC))
2671 register_syscore_ops(&lapic_syscore_ops);
2672
2673 return 0;
2674 }
2675
2676 /* local apic needs to resume before other devices access its registers. */
2677 core_initcall(init_lapic_sysfs);
2678
2679 #else /* CONFIG_PM */
2680
apic_pm_activate(void)2681 static void apic_pm_activate(void) { }
2682
2683 #endif /* CONFIG_PM */
2684
2685 #ifdef CONFIG_X86_64
2686
2687 static int multi_checked;
2688 static int multi;
2689
set_multi(const struct dmi_system_id * d)2690 static int set_multi(const struct dmi_system_id *d)
2691 {
2692 if (multi)
2693 return 0;
2694 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2695 multi = 1;
2696 return 0;
2697 }
2698
2699 static const struct dmi_system_id multi_dmi_table[] = {
2700 {
2701 .callback = set_multi,
2702 .ident = "IBM System Summit2",
2703 .matches = {
2704 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2705 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2706 },
2707 },
2708 {}
2709 };
2710
dmi_check_multi(void)2711 static void dmi_check_multi(void)
2712 {
2713 if (multi_checked)
2714 return;
2715
2716 dmi_check_system(multi_dmi_table);
2717 multi_checked = 1;
2718 }
2719
2720 /*
2721 * apic_is_clustered_box() -- Check if we can expect good TSC
2722 *
2723 * Thus far, the major user of this is IBM's Summit2 series:
2724 * Clustered boxes may have unsynced TSC problems if they are
2725 * multi-chassis.
2726 * Use DMI to check them
2727 */
apic_is_clustered_box(void)2728 int apic_is_clustered_box(void)
2729 {
2730 dmi_check_multi();
2731 return multi;
2732 }
2733 #endif
2734
2735 /*
2736 * APIC command line parameters
2737 */
setup_disableapic(char * arg)2738 static int __init setup_disableapic(char *arg)
2739 {
2740 disable_apic = 1;
2741 setup_clear_cpu_cap(X86_FEATURE_APIC);
2742 return 0;
2743 }
2744 early_param("disableapic", setup_disableapic);
2745
2746 /* same as disableapic, for compatibility */
setup_nolapic(char * arg)2747 static int __init setup_nolapic(char *arg)
2748 {
2749 return setup_disableapic(arg);
2750 }
2751 early_param("nolapic", setup_nolapic);
2752
parse_lapic_timer_c2_ok(char * arg)2753 static int __init parse_lapic_timer_c2_ok(char *arg)
2754 {
2755 local_apic_timer_c2_ok = 1;
2756 return 0;
2757 }
2758 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2759
parse_disable_apic_timer(char * arg)2760 static int __init parse_disable_apic_timer(char *arg)
2761 {
2762 disable_apic_timer = 1;
2763 return 0;
2764 }
2765 early_param("noapictimer", parse_disable_apic_timer);
2766
parse_nolapic_timer(char * arg)2767 static int __init parse_nolapic_timer(char *arg)
2768 {
2769 disable_apic_timer = 1;
2770 return 0;
2771 }
2772 early_param("nolapic_timer", parse_nolapic_timer);
2773
apic_set_verbosity(char * arg)2774 static int __init apic_set_verbosity(char *arg)
2775 {
2776 if (!arg) {
2777 #ifdef CONFIG_X86_64
2778 skip_ioapic_setup = 0;
2779 return 0;
2780 #endif
2781 return -EINVAL;
2782 }
2783
2784 if (strcmp("debug", arg) == 0)
2785 apic_verbosity = APIC_DEBUG;
2786 else if (strcmp("verbose", arg) == 0)
2787 apic_verbosity = APIC_VERBOSE;
2788 #ifdef CONFIG_X86_64
2789 else {
2790 pr_warning("APIC Verbosity level %s not recognised"
2791 " use apic=verbose or apic=debug\n", arg);
2792 return -EINVAL;
2793 }
2794 #endif
2795
2796 return 0;
2797 }
2798 early_param("apic", apic_set_verbosity);
2799
lapic_insert_resource(void)2800 static int __init lapic_insert_resource(void)
2801 {
2802 if (!apic_phys)
2803 return -1;
2804
2805 /* Put local APIC into the resource map. */
2806 lapic_resource.start = apic_phys;
2807 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2808 insert_resource(&iomem_resource, &lapic_resource);
2809
2810 return 0;
2811 }
2812
2813 /*
2814 * need call insert after e820__reserve_resources()
2815 * that is using request_resource
2816 */
2817 late_initcall(lapic_insert_resource);
2818
apic_set_disabled_cpu_apicid(char * arg)2819 static int __init apic_set_disabled_cpu_apicid(char *arg)
2820 {
2821 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2822 return -EINVAL;
2823
2824 return 0;
2825 }
2826 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2827
apic_set_extnmi(char * arg)2828 static int __init apic_set_extnmi(char *arg)
2829 {
2830 if (!arg)
2831 return -EINVAL;
2832
2833 if (!strncmp("all", arg, 3))
2834 apic_extnmi = APIC_EXTNMI_ALL;
2835 else if (!strncmp("none", arg, 4))
2836 apic_extnmi = APIC_EXTNMI_NONE;
2837 else if (!strncmp("bsp", arg, 3))
2838 apic_extnmi = APIC_EXTNMI_BSP;
2839 else {
2840 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2841 return -EINVAL;
2842 }
2843
2844 return 0;
2845 }
2846 early_param("apic_extnmi", apic_set_extnmi);
2847