1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3
4 #ifndef _ICE_TYPE_H_
5 #define _ICE_TYPE_H_
6
7 #include "ice_status.h"
8 #include "ice_hw_autogen.h"
9 #include "ice_osdep.h"
10 #include "ice_controlq.h"
11 #include "ice_lan_tx_rx.h"
12
13 #define ICE_BYTES_PER_WORD 2
14 #define ICE_BYTES_PER_DWORD 4
15
ice_is_tc_ena(u8 bitmap,u8 tc)16 static inline bool ice_is_tc_ena(u8 bitmap, u8 tc)
17 {
18 return test_bit(tc, (unsigned long *)&bitmap);
19 }
20
21 /* debug masks - set these bits in hw->debug_mask to control output */
22 #define ICE_DBG_INIT BIT_ULL(1)
23 #define ICE_DBG_LINK BIT_ULL(4)
24 #define ICE_DBG_QCTX BIT_ULL(6)
25 #define ICE_DBG_NVM BIT_ULL(7)
26 #define ICE_DBG_LAN BIT_ULL(8)
27 #define ICE_DBG_SW BIT_ULL(13)
28 #define ICE_DBG_SCHED BIT_ULL(14)
29 #define ICE_DBG_RES BIT_ULL(17)
30 #define ICE_DBG_AQ_MSG BIT_ULL(24)
31 #define ICE_DBG_AQ_CMD BIT_ULL(27)
32 #define ICE_DBG_USER BIT_ULL(31)
33
34 enum ice_aq_res_ids {
35 ICE_NVM_RES_ID = 1,
36 ICE_SPD_RES_ID,
37 ICE_CHANGE_LOCK_RES_ID,
38 ICE_GLOBAL_CFG_LOCK_RES_ID
39 };
40
41 /* FW update timeout definitions are in milliseconds */
42 #define ICE_NVM_TIMEOUT 180000
43 #define ICE_CHANGE_LOCK_TIMEOUT 1000
44 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
45
46 enum ice_aq_res_access_type {
47 ICE_RES_READ = 1,
48 ICE_RES_WRITE
49 };
50
51 enum ice_fc_mode {
52 ICE_FC_NONE = 0,
53 ICE_FC_RX_PAUSE,
54 ICE_FC_TX_PAUSE,
55 ICE_FC_FULL,
56 ICE_FC_PFC,
57 ICE_FC_DFLT
58 };
59
60 enum ice_set_fc_aq_failures {
61 ICE_SET_FC_AQ_FAIL_NONE = 0,
62 ICE_SET_FC_AQ_FAIL_GET,
63 ICE_SET_FC_AQ_FAIL_SET,
64 ICE_SET_FC_AQ_FAIL_UPDATE
65 };
66
67 /* Various MAC types */
68 enum ice_mac_type {
69 ICE_MAC_UNKNOWN = 0,
70 ICE_MAC_GENERIC,
71 };
72
73 /* Media Types */
74 enum ice_media_type {
75 ICE_MEDIA_UNKNOWN = 0,
76 ICE_MEDIA_FIBER,
77 ICE_MEDIA_BASET,
78 ICE_MEDIA_BACKPLANE,
79 ICE_MEDIA_DA,
80 };
81
82 enum ice_vsi_type {
83 ICE_VSI_PF = 0,
84 };
85
86 struct ice_link_status {
87 /* Refer to ice_aq_phy_type for bits definition */
88 u64 phy_type_low;
89 u16 max_frame_size;
90 u16 link_speed;
91 u16 req_speeds;
92 u8 lse_ena; /* Link Status Event notification */
93 u8 link_info;
94 u8 an_info;
95 u8 ext_info;
96 u8 pacing;
97 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
98 * ice_aqc_get_phy_caps structure
99 */
100 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
101 };
102
103 /* PHY info such as phy_type, etc... */
104 struct ice_phy_info {
105 struct ice_link_status link_info;
106 struct ice_link_status link_info_old;
107 u64 phy_type_low;
108 enum ice_media_type media_type;
109 u8 get_link_info;
110 };
111
112 /* Common HW capabilities for SW use */
113 struct ice_hw_common_caps {
114 /* TX/RX queues */
115 u16 num_rxq; /* Number/Total RX queues */
116 u16 rxq_first_id; /* First queue ID for RX queues */
117 u16 num_txq; /* Number/Total TX queues */
118 u16 txq_first_id; /* First queue ID for TX queues */
119
120 /* MSI-X vectors */
121 u16 num_msix_vectors;
122 u16 msix_vector_first_id;
123
124 /* Max MTU for function or device */
125 u16 max_mtu;
126
127 /* RSS related capabilities */
128 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
129 u8 rss_table_entry_width; /* RSS Entry width in bits */
130 };
131
132 /* Function specific capabilities */
133 struct ice_hw_func_caps {
134 struct ice_hw_common_caps common_cap;
135 u32 guaranteed_num_vsi;
136 };
137
138 /* Device wide capabilities */
139 struct ice_hw_dev_caps {
140 struct ice_hw_common_caps common_cap;
141 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
142 };
143
144 /* MAC info */
145 struct ice_mac_info {
146 u8 lan_addr[ETH_ALEN];
147 u8 perm_addr[ETH_ALEN];
148 };
149
150 /* Various RESET request, These are not tied with HW reset types */
151 enum ice_reset_req {
152 ICE_RESET_PFR = 0,
153 ICE_RESET_CORER = 1,
154 ICE_RESET_GLOBR = 2,
155 };
156
157 /* Bus parameters */
158 struct ice_bus_info {
159 u16 device;
160 u8 func;
161 };
162
163 /* Flow control (FC) parameters */
164 struct ice_fc_info {
165 enum ice_fc_mode current_mode; /* FC mode in effect */
166 enum ice_fc_mode req_mode; /* FC mode requested by caller */
167 };
168
169 /* NVM Information */
170 struct ice_nvm_info {
171 u32 eetrack; /* NVM data version */
172 u32 oem_ver; /* OEM version info */
173 u16 sr_words; /* Shadow RAM size in words */
174 u16 ver; /* NVM package version */
175 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
176 };
177
178 /* Max number of port to queue branches w.r.t topology */
179 #define ICE_MAX_TRAFFIC_CLASS 8
180 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
181
182 struct ice_sched_node {
183 struct ice_sched_node *parent;
184 struct ice_sched_node *sibling; /* next sibling in the same layer */
185 struct ice_sched_node **children;
186 struct ice_aqc_txsched_elem_data info;
187 u32 agg_id; /* aggregator group id */
188 u16 vsi_id;
189 u8 in_use; /* suspended or in use */
190 u8 tx_sched_layer; /* Logical Layer (1-9) */
191 u8 num_children;
192 u8 tc_num;
193 u8 owner;
194 #define ICE_SCHED_NODE_OWNER_LAN 0
195 };
196
197 /* Access Macros for Tx Sched Elements data */
198 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
199
200 /* The aggregator type determines if identifier is for a VSI group,
201 * aggregator group, aggregator of queues, or queue group.
202 */
203 enum ice_agg_type {
204 ICE_AGG_TYPE_UNKNOWN = 0,
205 ICE_AGG_TYPE_VSI,
206 ICE_AGG_TYPE_AGG, /* aggregator */
207 ICE_AGG_TYPE_Q,
208 ICE_AGG_TYPE_QG
209 };
210
211 #define ICE_SCHED_DFLT_RL_PROF_ID 0
212
213 /* vsi type list entry to locate corresponding vsi/ag nodes */
214 struct ice_sched_vsi_info {
215 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
216 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
217 struct list_head list_entry;
218 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
219 u16 vsi_id;
220 };
221
222 /* driver defines the policy */
223 struct ice_sched_tx_policy {
224 u16 max_num_vsis;
225 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
226 u8 rdma_ena;
227 };
228
229 struct ice_port_info {
230 struct ice_sched_node *root; /* Root Node per Port */
231 struct ice_hw *hw; /* back pointer to hw instance */
232 u32 last_node_teid; /* scheduler last node info */
233 u16 sw_id; /* Initial switch ID belongs to port */
234 u16 pf_vf_num;
235 u8 port_state;
236 #define ICE_SCHED_PORT_STATE_INIT 0x0
237 #define ICE_SCHED_PORT_STATE_READY 0x1
238 u16 dflt_tx_vsi_rule_id;
239 u16 dflt_tx_vsi_num;
240 u16 dflt_rx_vsi_rule_id;
241 u16 dflt_rx_vsi_num;
242 struct ice_fc_info fc;
243 struct ice_mac_info mac;
244 struct ice_phy_info phy;
245 struct mutex sched_lock; /* protect access to TXSched tree */
246 struct ice_sched_tx_policy sched_policy;
247 struct list_head vsi_info_list;
248 struct list_head agg_list; /* lists all aggregator */
249 u8 lport;
250 #define ICE_LPORT_MASK 0xff
251 u8 is_vf;
252 };
253
254 struct ice_switch_info {
255 /* Switch VSI lists to MAC/VLAN translation */
256 struct mutex mac_list_lock; /* protect MAC list */
257 struct list_head mac_list_head;
258 struct mutex vlan_list_lock; /* protect VLAN list */
259 struct list_head vlan_list_head;
260 struct mutex eth_m_list_lock; /* protect ethtype list */
261 struct list_head eth_m_list_head;
262 struct mutex promisc_list_lock; /* protect promisc mode list */
263 struct list_head promisc_list_head;
264 struct mutex mac_vlan_list_lock; /* protect MAC-VLAN list */
265 struct list_head mac_vlan_list_head;
266
267 struct list_head vsi_list_map_head;
268 };
269
270 /* Port hardware description */
271 struct ice_hw {
272 u8 __iomem *hw_addr;
273 void *back;
274 struct ice_aqc_layer_props *layer_info;
275 struct ice_port_info *port_info;
276 u64 debug_mask; /* bitmap for debug mask */
277 enum ice_mac_type mac_type;
278
279 /* pci info */
280 u16 device_id;
281 u16 vendor_id;
282 u16 subsystem_device_id;
283 u16 subsystem_vendor_id;
284 u8 revision_id;
285
286 u8 pf_id; /* device profile info */
287
288 /* TX Scheduler values */
289 u16 num_tx_sched_layers;
290 u16 num_tx_sched_phys_layers;
291 u8 flattened_layers;
292 u8 max_cgds;
293 u8 sw_entry_point_layer;
294
295 u8 evb_veb; /* true for VEB, false for VEPA */
296 u8 reset_ongoing; /* true if hw is in reset, false otherwise */
297 struct ice_bus_info bus;
298 struct ice_nvm_info nvm;
299 struct ice_hw_dev_caps dev_caps; /* device capabilities */
300 struct ice_hw_func_caps func_caps; /* function capabilities */
301
302 struct ice_switch_info *switch_info; /* switch filter lists */
303
304 /* Control Queue info */
305 struct ice_ctl_q_info adminq;
306
307 u8 api_branch; /* API branch version */
308 u8 api_maj_ver; /* API major version */
309 u8 api_min_ver; /* API minor version */
310 u8 api_patch; /* API patch version */
311 u8 fw_branch; /* firmware branch version */
312 u8 fw_maj_ver; /* firmware major version */
313 u8 fw_min_ver; /* firmware minor version */
314 u8 fw_patch; /* firmware patch version */
315 u32 fw_build; /* firmware build number */
316
317 /* minimum allowed value for different speeds */
318 #define ICE_ITR_GRAN_MIN_200 1
319 #define ICE_ITR_GRAN_MIN_100 1
320 #define ICE_ITR_GRAN_MIN_50 2
321 #define ICE_ITR_GRAN_MIN_25 4
322 /* ITR granularity in 1 us */
323 u8 itr_gran_200;
324 u8 itr_gran_100;
325 u8 itr_gran_50;
326 u8 itr_gran_25;
327 u8 ucast_shared; /* true if VSIs can share unicast addr */
328
329 };
330
331 /* Statistics collected by each port, VSI, VEB, and S-channel */
332 struct ice_eth_stats {
333 u64 rx_bytes; /* gorc */
334 u64 rx_unicast; /* uprc */
335 u64 rx_multicast; /* mprc */
336 u64 rx_broadcast; /* bprc */
337 u64 rx_discards; /* rdpc */
338 u64 rx_unknown_protocol; /* rupp */
339 u64 tx_bytes; /* gotc */
340 u64 tx_unicast; /* uptc */
341 u64 tx_multicast; /* mptc */
342 u64 tx_broadcast; /* bptc */
343 u64 tx_discards; /* tdpc */
344 u64 tx_errors; /* tepc */
345 };
346
347 /* Statistics collected by the MAC */
348 struct ice_hw_port_stats {
349 /* eth stats collected by the port */
350 struct ice_eth_stats eth;
351 /* additional port specific stats */
352 u64 tx_dropped_link_down; /* tdold */
353 u64 crc_errors; /* crcerrs */
354 u64 illegal_bytes; /* illerrc */
355 u64 error_bytes; /* errbc */
356 u64 mac_local_faults; /* mlfc */
357 u64 mac_remote_faults; /* mrfc */
358 u64 rx_len_errors; /* rlec */
359 u64 link_xon_rx; /* lxonrxc */
360 u64 link_xoff_rx; /* lxoffrxc */
361 u64 link_xon_tx; /* lxontxc */
362 u64 link_xoff_tx; /* lxofftxc */
363 u64 rx_size_64; /* prc64 */
364 u64 rx_size_127; /* prc127 */
365 u64 rx_size_255; /* prc255 */
366 u64 rx_size_511; /* prc511 */
367 u64 rx_size_1023; /* prc1023 */
368 u64 rx_size_1522; /* prc1522 */
369 u64 rx_size_big; /* prc9522 */
370 u64 rx_undersize; /* ruc */
371 u64 rx_fragments; /* rfc */
372 u64 rx_oversize; /* roc */
373 u64 rx_jabber; /* rjc */
374 u64 tx_size_64; /* ptc64 */
375 u64 tx_size_127; /* ptc127 */
376 u64 tx_size_255; /* ptc255 */
377 u64 tx_size_511; /* ptc511 */
378 u64 tx_size_1023; /* ptc1023 */
379 u64 tx_size_1522; /* ptc1522 */
380 u64 tx_size_big; /* ptc9522 */
381 };
382
383 /* Checksum and Shadow RAM pointers */
384 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
385 #define ICE_SR_NVM_EETRACK_LO 0x2D
386 #define ICE_SR_NVM_EETRACK_HI 0x2E
387 #define ICE_NVM_VER_LO_SHIFT 0
388 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
389 #define ICE_NVM_VER_HI_SHIFT 12
390 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
391 #define ICE_OEM_VER_PATCH_SHIFT 0
392 #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT)
393 #define ICE_OEM_VER_BUILD_SHIFT 8
394 #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT)
395 #define ICE_OEM_VER_SHIFT 24
396 #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT)
397 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
398 #define ICE_SR_WORDS_IN_1KB 512
399
400 #endif /* _ICE_TYPE_H_ */
401