1 /*
2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include "plat_addr_map.h"
16 #include CHIP_SPECIFIC_HDR(reg_cmu)
17 #include CHIP_SPECIFIC_HDR(reg_aoncmu)
18 #include CHIP_SPECIFIC_HDR(reg_btcmu)
19 #include CHIP_SPECIFIC_HDR(reg_wfcmu)
20 #include "hal_cmu.h"
21 #include "hal_aud.h"
22 #include "hal_bootmode.h"
23 #include "hal_chipid.h"
24 #include "hal_codec.h"
25 #include "hal_location.h"
26 #include "hal_psc.h"
27 #include "hal_sec.h"
28 #include "hal_sysfreq.h"
29 #include "hal_timer.h"
30 #include "hal_trace.h"
31 #include "cmsis_nvic.h"
32 #include "pmu.h"
33 #include "analog.h"
34 #include "system_cp.h"
35 #include "hal_psram.h"
36 #include "hal_psramuhs.h"
37 #include "hal_norflash.h"
38 #include "hal_wdt.h"
39 #include "tgt_hardware.h"
40 #include "hal_dma.h"
41 #include CHIP_SPECIFIC_HDR(hal_dmacfg)
42
43 #ifdef FLASH_SUSPEND
44 #include "norflash_api.h"
45 #endif
46
47 #define HAL_CMU_USB_PLL_CLOCK (192 * 1000 * 1000)
48 #define HAL_CMU_AUD_PLL_CLOCK (CODEC_FREQ_48K_SERIES * CODEC_CMU_DIV)
49
50 #define HAL_CMU_USB_CLOCK_60M (60 * 1000 * 1000)
51 #define HAL_CMU_USB_CLOCK_48M (48 * 1000 * 1000)
52
53 #define HAL_CMU_PWM_SLOW_CLOCK (32 * 1000)
54
55 #define HAL_CMU_PLL_LOCKED_TIMEOUT US_TO_TICKS(200)
56 #define HAL_CMU_26M_READY_TIMEOUT MS_TO_TICKS(3)
57 #define HAL_CMU_LPU_EXTRA_TIMEOUT MS_TO_TICKS(1)
58
59 enum CMU_USB_CLK_SRC_T {
60 CMU_USB_CLK_SRC_PLL_48M = 0,
61 CMU_USB_CLK_SRC_PLL_60M = 1,
62 CMU_USB_CLK_SRC_OSC_24M_X2 = 2,
63 };
64
65 enum CMU_AUD_26M_X4_USER_T {
66 CMU_AUD_26M_X4_USER_IIR,
67 CMU_AUD_26M_X4_USER_RS,
68
69 CMU_AUD_26M_X4_USER_QTY,
70 };
71
72 enum CMU_DEBUG_REG_SEL_T {
73 CMU_DEBUG_REG_SEL_MCU_PC = 0,
74 CMU_DEBUG_REG_SEL_MCU_LR = 1,
75 CMU_DEBUG_REG_SEL_MCU_SP = 2,
76 CMU_DEBUG_REG_SEL_CP_PC = 3,
77 CMU_DEBUG_REG_SEL_CP_LR = 4,
78 CMU_DEBUG_REG_SEL_CP_SP = 5,
79 CMU_DEBUG_REG_SEL_DEBUG = 7,
80 };
81
82 enum CMU_DMA_REQ_T {
83 CMU_DMA_REQ_CODEC_RX = 0,
84 CMU_DMA_REQ_CODEC_TX = 1,
85 CMU_DMA_REQ_DSD_RX = 2,
86 CMU_DMA_REQ_DSD_TX = 3,
87 CMU_DMA_REQ_IR_RX = 6,
88 CMU_DMA_REQ_IR_TX = 7,
89 CMU_DMA_REQ_FLS1 = 8,
90 CMU_DMA_REQ_FLS0 = 10,
91 CMU_DMA_REQ_BTDUMP = 12,
92 CMU_DMA_REQ_SDEMMC = 13,
93 CMU_DMA_REQ_I2C0_RX = 14,
94 CMU_DMA_REQ_I2C0_TX = 15,
95 CMU_DMA_REQ_I2C1_RX = 16,
96 CMU_DMA_REQ_I2C1_TX = 17,
97 CMU_DMA_REQ_SPILCD0_RX = 18,
98 CMU_DMA_REQ_SPILCD0_TX = 19,
99 CMU_DMA_REQ_SPILCD1_RX = 20,
100 CMU_DMA_REQ_SPILCD1_TX = 21,
101 CMU_DMA_REQ_SPI_ITN_RX = 22,
102 CMU_DMA_REQ_SPI_ITN_TX = 23,
103 CMU_DMA_REQ_UART0_RX = 24,
104 CMU_DMA_REQ_UART0_TX = 25,
105 CMU_DMA_REQ_UART1_RX = 26,
106 CMU_DMA_REQ_UART1_TX = 27,
107 CMU_DMA_REQ_UART2_RX = 28,
108 CMU_DMA_REQ_UART2_TX = 29,
109 CMU_DMA_REQ_PCM_RX = 30,
110 CMU_DMA_REQ_PCM_TX = 31,
111 CMU_DMA_REQ_I2S0_RX = 32,
112 CMU_DMA_REQ_I2S0_TX = 33,
113 CMU_DMA_REQ_SPDIF0_RX = 34,
114 CMU_DMA_REQ_SPDIF0_TX = 35,
115 CMU_DMA_REQ_I2C2_RX = 36,
116 CMU_DMA_REQ_I2C2_TX = 37,
117 CMU_DMA_REQ_UART3_RX = 38,
118 CMU_DMA_REQ_UART3_TX = 39,
119 CMU_DMA_REQ_I2S1_RX = 40,
120 CMU_DMA_REQ_I2S1_TX = 41,
121
122 CMU_DMA_REQ_NULL = 5,
123 };
124
125 struct CP_STARTUP_CFG_T {
126 __IO uint32_t stack;
127 __IO uint32_t reset_hdlr;
128 };
129
130 static struct CMU_T * const cmu = (struct CMU_T *)CMU_BASE;
131
132 static struct AONCMU_T * const aoncmu = (struct AONCMU_T *)AON_CMU_BASE;
133
134 static struct BTCMU_T * const POSSIBLY_UNUSED btcmu = (struct BTCMU_T *)BT_CMU_BASE;
135
136 static struct WLANCMU_T * const POSSIBLY_UNUSED wlancmu = (struct WLANCMU_T *)WIFI_CMU_BASE;
137
138 static uint32_t cp_entry;
139
140 static uint8_t BOOT_BSS_LOC pll_user_map[HAL_CMU_PLL_QTY];
141 STATIC_ASSERT(HAL_CMU_PLL_USER_QTY <= sizeof(pll_user_map[0]) * 8, "Too many PLL users");
142
143 #ifdef __AUDIO_RESAMPLE__
144 static bool aud_resample_en = true;
145 #ifdef ANA_26M_X4_ENABLE
146 static uint8_t aud_26m_x4_map;
147 STATIC_ASSERT(CMU_AUD_26M_X4_USER_QTY <= sizeof(aud_26m_x4_map) * 8, "Too many aud_26m_x4 users");
148 #endif
149 #endif
150
151 #ifdef ANA_26M_X4_ENABLE
152 #error "CHIP_BEST2003 don't support X4"
153 #endif
154
155 #ifdef LOW_SYS_FREQ
156 static enum HAL_CMU_FREQ_T BOOT_BSS_LOC cmu_sys_freq;
157 #endif
158
hal_cmu_audio_resample_enable(void)159 void hal_cmu_audio_resample_enable(void)
160 {
161 #ifdef __AUDIO_RESAMPLE__
162 aud_resample_en = true;
163 #endif
164 }
165
hal_cmu_audio_resample_disable(void)166 void hal_cmu_audio_resample_disable(void)
167 {
168 #ifdef __AUDIO_RESAMPLE__
169 aud_resample_en = false;
170 #endif
171 }
172
hal_cmu_get_audio_resample_status(void)173 int hal_cmu_get_audio_resample_status(void)
174 {
175 #ifdef __AUDIO_RESAMPLE__
176 return aud_resample_en;
177 #else
178 return false;
179 #endif
180 }
181
aocmu_reg_update_wait(void)182 static inline void aocmu_reg_update_wait(void)
183 {
184 // Make sure AOCMU (26M clock domain) write opertions finish before return
185 aoncmu->CHIP_ID;
186 }
187
hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id)188 int hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id)
189 {
190 if (id >= HAL_CMU_AON_A7) {
191 return 1;
192 }
193
194 if (id < HAL_CMU_MOD_P_CMU) {
195 cmu->HCLK_ENABLE = (1 << id);
196 } else if (id < HAL_CMU_MOD_O_SLEEP) {
197 cmu->PCLK_ENABLE = (1 << (id - HAL_CMU_MOD_P_CMU));
198 } else if (id < HAL_CMU_MOD_Q_NULL) {
199 cmu->OCLK_ENABLE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
200 } else if (id < HAL_CMU_AON_A_CMU) {
201 cmu->QCLK_ENABLE = (1 << (id - HAL_CMU_MOD_Q_NULL));
202 } else {
203 aoncmu->MOD_CLK_ENABLE = (1 << (id - HAL_CMU_AON_A_CMU));
204 aocmu_reg_update_wait();
205 }
206
207 return 0;
208 }
209
hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id)210 int hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id)
211 {
212 if (id >= HAL_CMU_AON_A7) {
213 return 1;
214 }
215
216 if (id == HAL_CMU_MOD_P_TZC)
217 return 0;
218
219 if (id < HAL_CMU_MOD_P_CMU) {
220 cmu->HCLK_DISABLE = (1 << id);
221 } else if (id < HAL_CMU_MOD_O_SLEEP) {
222 cmu->PCLK_DISABLE = (1 << (id - HAL_CMU_MOD_P_CMU));
223 } else if (id < HAL_CMU_MOD_Q_NULL) {
224 cmu->OCLK_DISABLE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
225 } else if (id < HAL_CMU_AON_A_CMU) {
226 cmu->QCLK_DISABLE = (1 << (id - HAL_CMU_MOD_Q_NULL));
227 } else {
228 aoncmu->MOD_CLK_DISABLE = (1 << (id - HAL_CMU_AON_A_CMU));
229 }
230
231 return 0;
232 }
233
hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id)234 enum HAL_CMU_CLK_STATUS_T hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id)
235 {
236 uint32_t status;
237
238 if (id >= HAL_CMU_AON_A7) {
239 return HAL_CMU_CLK_DISABLED;
240 }
241
242 if (id < HAL_CMU_MOD_P_CMU) {
243 status = cmu->HCLK_ENABLE & (1 << id);
244 } else if (id < HAL_CMU_MOD_O_SLEEP) {
245 status = cmu->PCLK_ENABLE & (1 << (id - HAL_CMU_MOD_P_CMU));
246 } else if (id < HAL_CMU_MOD_Q_NULL) {
247 status = cmu->OCLK_ENABLE & (1 << (id - HAL_CMU_MOD_O_SLEEP));
248 } else if (id < HAL_CMU_AON_A_CMU) {
249 status = cmu->QCLK_ENABLE & (1 << (id - HAL_CMU_MOD_Q_NULL));
250 } else {
251 status = aoncmu->MOD_CLK_ENABLE & (1 << (id - HAL_CMU_AON_A_CMU));
252 }
253
254 return status ? HAL_CMU_CLK_ENABLED : HAL_CMU_CLK_DISABLED;
255 }
256
hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id,enum HAL_CMU_CLK_MODE_T mode)257 int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id, enum HAL_CMU_CLK_MODE_T mode)
258 {
259 __IO uint32_t *reg;
260 uint32_t val;
261 uint32_t lock;
262
263 if (id >= HAL_CMU_AON_A7) {
264 return 1;
265 }
266
267 if (id < HAL_CMU_MOD_P_CMU) {
268 reg = &cmu->HCLK_MODE;
269 val = (1 << id);
270 } else if (id < HAL_CMU_MOD_O_SLEEP) {
271 reg = &cmu->PCLK_MODE;
272 val = (1 << (id - HAL_CMU_MOD_P_CMU));
273 } else if (id < HAL_CMU_MOD_Q_NULL) {
274 reg = &cmu->OCLK_MODE;
275 val = (1 << (id - HAL_CMU_MOD_O_SLEEP));
276 } else if (id < HAL_CMU_AON_A_CMU) {
277 reg = &cmu->QCLK_MODE;
278 val = (1 << (id - HAL_CMU_MOD_Q_NULL));
279 } else {
280 reg = &aoncmu->MOD_CLK_MODE;
281 val = (1 << (id - HAL_CMU_AON_A_CMU));
282 }
283
284 lock = int_lock();
285 if (mode == HAL_CMU_CLK_MANUAL) {
286 *reg |= val;
287 } else {
288 *reg &= ~val;
289 }
290 int_unlock(lock);
291
292 return 0;
293 }
294
hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id)295 enum HAL_CMU_CLK_MODE_T hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id)
296 {
297 uint32_t mode;
298
299 if (id >= HAL_CMU_AON_A7) {
300 return HAL_CMU_CLK_AUTO;
301 }
302
303 if (id < HAL_CMU_MOD_P_CMU) {
304 mode = cmu->HCLK_MODE & (1 << id);
305 } else if (id < HAL_CMU_MOD_O_SLEEP) {
306 mode = cmu->PCLK_MODE & (1 << (id - HAL_CMU_MOD_P_CMU));
307 } else if (id < HAL_CMU_MOD_Q_NULL) {
308 mode = cmu->OCLK_MODE & (1 << (id - HAL_CMU_MOD_O_SLEEP));
309 } else if (id < HAL_CMU_AON_A_CMU) {
310 mode = cmu->QCLK_MODE & (1 << (id - HAL_CMU_MOD_Q_NULL));
311 } else {
312 mode = aoncmu->MOD_CLK_MODE & (1 << (id - HAL_CMU_AON_A_CMU));
313 }
314
315 return mode ? HAL_CMU_CLK_MANUAL : HAL_CMU_CLK_AUTO;
316 }
317
hal_cmu_reset_set(enum HAL_CMU_MOD_ID_T id)318 int hal_cmu_reset_set(enum HAL_CMU_MOD_ID_T id)
319 {
320 if (id >= HAL_CMU_MOD_QTY) {
321 return 1;
322 }
323
324 if (id == HAL_CMU_MOD_P_TZC)
325 return 0;
326
327 if (id < HAL_CMU_MOD_P_CMU) {
328 cmu->HRESET_SET = (1 << id);
329 } else if (id < HAL_CMU_MOD_O_SLEEP) {
330 cmu->PRESET_SET = (1 << (id - HAL_CMU_MOD_P_CMU));
331 } else if (id < HAL_CMU_MOD_Q_NULL) {
332 cmu->ORESET_SET = (1 << (id - HAL_CMU_MOD_O_SLEEP));
333 } else if (id < HAL_CMU_AON_A_CMU) {
334 cmu->QRESET_SET = (1 << (id - HAL_CMU_MOD_Q_NULL));
335 } else if (id < HAL_CMU_AON_A7) {
336 aoncmu->RESET_SET = (1 << (id - HAL_CMU_AON_A_CMU));
337 } else {
338 aoncmu->SOFT_RSTN_SET = (1 << (id - HAL_CMU_AON_A7));
339 }
340
341 return 0;
342 }
343
hal_cmu_reset_clear(enum HAL_CMU_MOD_ID_T id)344 int hal_cmu_reset_clear(enum HAL_CMU_MOD_ID_T id)
345 {
346 if (id >= HAL_CMU_MOD_QTY) {
347 return 1;
348 }
349
350 if (id < HAL_CMU_MOD_P_CMU) {
351 cmu->HRESET_CLR = (1 << id);
352 asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
353 asm volatile("nop; nop; nop; nop;");
354 } else if (id < HAL_CMU_MOD_O_SLEEP) {
355 cmu->PRESET_CLR = (1 << (id - HAL_CMU_MOD_P_CMU));
356 asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
357 asm volatile("nop; nop; nop; nop;");
358 } else if (id < HAL_CMU_MOD_Q_NULL) {
359 cmu->ORESET_CLR = (1 << (id - HAL_CMU_MOD_O_SLEEP));
360 asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
361 asm volatile("nop; nop; nop; nop;");
362 } else if (id < HAL_CMU_AON_A_CMU) {
363 cmu->QRESET_CLR = (1 << (id - HAL_CMU_MOD_Q_NULL));
364 asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
365 asm volatile("nop; nop; nop; nop;");
366 } else if (id < HAL_CMU_AON_A7) {
367 aoncmu->RESET_CLR = (1 << (id - HAL_CMU_AON_A_CMU));
368 aocmu_reg_update_wait();
369 } else {
370 aoncmu->SOFT_RSTN_CLR = (1 << (id - HAL_CMU_AON_A7));
371 aocmu_reg_update_wait();
372 }
373
374 return 0;
375 }
376
hal_cmu_reset_get_status(enum HAL_CMU_MOD_ID_T id)377 enum HAL_CMU_RST_STATUS_T hal_cmu_reset_get_status(enum HAL_CMU_MOD_ID_T id)
378 {
379 uint32_t status;
380
381 if (id >= HAL_CMU_MOD_QTY) {
382 return HAL_CMU_RST_SET;
383 }
384
385 if (id < HAL_CMU_MOD_P_CMU) {
386 status = cmu->HRESET_SET & (1 << id);
387 } else if (id < HAL_CMU_MOD_O_SLEEP) {
388 status = cmu->PRESET_SET & (1 << (id - HAL_CMU_MOD_P_CMU));
389 } else if (id < HAL_CMU_MOD_Q_NULL) {
390 status = cmu->ORESET_SET & (1 << (id - HAL_CMU_MOD_O_SLEEP));
391 } else if (id < HAL_CMU_AON_A_CMU) {
392 status = cmu->QRESET_SET & (1 << (id - HAL_CMU_MOD_Q_NULL));
393 } else if (id < HAL_CMU_AON_A7) {
394 status = aoncmu->RESET_SET & (1 << (id - HAL_CMU_AON_A_CMU));
395 } else {
396 status = aoncmu->SOFT_RSTN_SET & (1 << (id - HAL_CMU_AON_A7));
397 }
398
399 return status ? HAL_CMU_RST_CLR : HAL_CMU_RST_SET;
400 }
401
hal_cmu_reset_pulse(enum HAL_CMU_MOD_ID_T id)402 int hal_cmu_reset_pulse(enum HAL_CMU_MOD_ID_T id)
403 {
404 volatile int i;
405
406 if (id >= HAL_CMU_MOD_QTY) {
407 return 1;
408 }
409
410 if (hal_cmu_reset_get_status(id) == HAL_CMU_RST_SET) {
411 return hal_cmu_reset_clear(id);
412 }
413
414 if (id < HAL_CMU_MOD_P_CMU) {
415 cmu->HRESET_PULSE = (1 << id);
416 } else if (id < HAL_CMU_MOD_O_SLEEP) {
417 cmu->PRESET_PULSE = (1 << (id - HAL_CMU_MOD_P_CMU));
418 } else if (id < HAL_CMU_MOD_Q_NULL) {
419 cmu->ORESET_PULSE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
420 } else if (id < HAL_CMU_AON_A_CMU) {
421 cmu->QRESET_PULSE = (1 << (id - HAL_CMU_MOD_Q_NULL));
422 } else if (id < HAL_CMU_AON_A7) {
423 aoncmu->RESET_PULSE = (1 << (id - HAL_CMU_AON_A_CMU));
424 // Total 3 CLK-26M cycles needed
425 // AOCMU runs in 26M clock domain and its read operations consume at least 1 26M-clock cycle.
426 // (Whereas its write operations will finish at 1 HCLK cycle -- finish once in async bridge fifo)
427 aoncmu->CHIP_ID;
428 aoncmu->CHIP_ID;
429 aoncmu->CHIP_ID;
430 } else {
431 aoncmu->SOFT_RSTN_PULSE = (1 << (id - HAL_CMU_AON_A7));
432 // Total 3 CLK-26M cycles needed
433 // AOCMU runs in 26M clock domain and its read operations consume at least 1 26M-clock cycle.
434 // (Whereas its write operations will finish at 1 HCLK cycle -- finish once in async bridge fifo)
435 aoncmu->CHIP_ID;
436 aoncmu->CHIP_ID;
437 aoncmu->CHIP_ID;
438 }
439 // Delay 5+ PCLK cycles (10+ HCLK cycles)
440 for (i = 0; i < 3; i++);
441
442 return 0;
443 }
444
hal_cmu_timer_set_div(enum HAL_CMU_TIMER_ID_T id,uint32_t div)445 int hal_cmu_timer_set_div(enum HAL_CMU_TIMER_ID_T id, uint32_t div)
446 {
447 uint32_t lock;
448
449 if (div < 1) {
450 return 1;
451 }
452
453 div -= 1;
454 if ((div & (CMU_CFG_DIV_TIMER00_MASK >> CMU_CFG_DIV_TIMER00_SHIFT)) != div) {
455 return 1;
456 }
457
458 lock = int_lock();
459 if (id == HAL_CMU_TIMER_ID_00) {
460 cmu->TIMER0_CLK = SET_BITFIELD(cmu->TIMER0_CLK, CMU_CFG_DIV_TIMER00, div);
461 } else if (id == HAL_CMU_TIMER_ID_01) {
462 cmu->TIMER0_CLK = SET_BITFIELD(cmu->TIMER0_CLK, CMU_CFG_DIV_TIMER01, div);
463 } else if (id == HAL_CMU_TIMER_ID_10) {
464 cmu->TIMER1_CLK = SET_BITFIELD(cmu->TIMER1_CLK, CMU_CFG_DIV_TIMER10, div);
465 } else if (id == HAL_CMU_TIMER_ID_11) {
466 cmu->TIMER1_CLK = SET_BITFIELD(cmu->TIMER1_CLK, CMU_CFG_DIV_TIMER11, div);
467 } else if (id == HAL_CMU_TIMER_ID_20) {
468 cmu->TIMER2_CLK = SET_BITFIELD(cmu->TIMER2_CLK, CMU_CFG_DIV_TIMER20, div);
469 } else if (id == HAL_CMU_TIMER_ID_21) {
470 cmu->TIMER2_CLK = SET_BITFIELD(cmu->TIMER2_CLK, CMU_CFG_DIV_TIMER21, div);
471 }
472 int_unlock(lock);
473
474 return 0;
475 }
476
hal_cmu_timer0_select_fast(void)477 void hal_cmu_timer0_select_fast(void)
478 {
479 uint32_t lock;
480
481 lock = int_lock();
482 // 6.5M
483 cmu->PERIPH_CLK |= (1 << CMU_SEL_TIMER_FAST_SHIFT);
484 // AON Timer
485 aoncmu->TIMER_CLK |= AON_CMU_SEL_TIMER_FAST;
486 int_unlock(lock);
487 }
488
hal_cmu_timer0_select_slow(void)489 void BOOT_TEXT_FLASH_LOC hal_cmu_timer0_select_slow(void)
490 {
491 uint32_t lock;
492
493 lock = int_lock();
494 // 16K
495 cmu->PERIPH_CLK &= ~(1 << CMU_SEL_TIMER_FAST_SHIFT);
496 // AON Timer
497 aoncmu->TIMER_CLK &= ~AON_CMU_SEL_TIMER_FAST;
498 int_unlock(lock);
499 }
500
hal_cmu_timer1_select_fast(void)501 void BOOT_TEXT_FLASH_LOC hal_cmu_timer1_select_fast(void)
502 {
503 uint32_t lock;
504
505 lock = int_lock();
506 // 6.5M
507 cmu->PERIPH_CLK |= (1 << (CMU_SEL_TIMER_FAST_SHIFT + 1));
508 int_unlock(lock);
509 }
510
hal_cmu_timer1_select_slow(void)511 void BOOT_TEXT_FLASH_LOC hal_cmu_timer1_select_slow(void)
512 {
513 uint32_t lock;
514
515 lock = int_lock();
516 // 16K
517 cmu->PERIPH_CLK &= ~(1 << (CMU_SEL_TIMER_FAST_SHIFT + 1));
518 int_unlock(lock);
519 }
520
hal_cmu_timer2_select_fast(void)521 void hal_cmu_timer2_select_fast(void)
522 {
523 uint32_t lock;
524
525 lock = int_lock();
526 // 6.5M
527 cmu->PERIPH_CLK |= (1 << (CMU_SEL_TIMER_FAST_SHIFT + 2));
528 int_unlock(lock);
529 }
530
hal_cmu_timer2_select_slow(void)531 void hal_cmu_timer2_select_slow(void)
532 {
533 uint32_t lock;
534
535 lock = int_lock();
536 // 16K
537 cmu->PERIPH_CLK &= ~(1 << (CMU_SEL_TIMER_FAST_SHIFT + 2));
538 int_unlock(lock);
539 }
540
hal_cmu_dsp_timer0_select_fast(void)541 void hal_cmu_dsp_timer0_select_fast(void)
542 {
543 uint32_t lock;
544
545 lock = int_lock();
546 // 6.5M
547 cmu->DSP_DIV |= (1 << CMU_SEL_TIMER_FAST_AP_SHIFT);
548 int_unlock(lock);
549 }
550
hal_cmu_dsp_timer0_select_slow(void)551 void hal_cmu_dsp_timer0_select_slow(void)
552 {
553 uint32_t lock;
554
555 lock = int_lock();
556 // 16K
557 cmu->DSP_DIV &= ~(1 << CMU_SEL_TIMER_FAST_AP_SHIFT);
558 int_unlock(lock);
559 }
560
hal_cmu_dsp_timer1_select_fast(void)561 void hal_cmu_dsp_timer1_select_fast(void)
562 {
563 uint32_t lock;
564
565 lock = int_lock();
566 // 6.5M
567 cmu->DSP_DIV |= (1 << (CMU_SEL_TIMER_FAST_AP_SHIFT + 1));
568 int_unlock(lock);
569 }
570
hal_cmu_dsp_timer1_select_slow(void)571 void hal_cmu_dsp_timer1_select_slow(void)
572 {
573 uint32_t lock;
574
575 lock = int_lock();
576 // 16K
577 cmu->DSP_DIV &= ~(1 << (CMU_SEL_TIMER_FAST_AP_SHIFT + 1));
578 int_unlock(lock);
579 }
580
hal_cmu_sdmmc_set_pll_div(uint32_t div)581 int hal_cmu_sdmmc_set_pll_div(uint32_t div)
582 {
583 uint32_t lock;
584 if (div < 2) {
585 return 1;
586 }
587 div -= 2;
588 if ((div & (CMU_CFG_DIV_SDMMC_MASK >> CMU_CFG_DIV_SDMMC_SHIFT)) != div) {
589 return 1;
590 }
591 lock = int_lock();
592 cmu->PERIPH_CLK = SET_BITFIELD(cmu->PERIPH_CLK, CMU_CFG_DIV_SDMMC, div) |
593 CMU_SEL_OSCX2_SDMMC | CMU_SEL_PLL_SDMMC | CMU_EN_PLL_SDMMC;
594 int_unlock(lock);
595 return 0;
596 }
597
hal_cmu_flash_set_freq(enum HAL_CMU_FREQ_T freq)598 int BOOT_TEXT_SRAM_LOC hal_cmu_flash_set_freq(enum HAL_CMU_FREQ_T freq)
599 {
600 uint32_t set;
601 uint32_t clr;
602 uint32_t lock;
603 bool clk_en;
604
605 if (freq >= HAL_CMU_FREQ_QTY) {
606 return 1;
607 }
608 if (freq == HAL_CMU_FREQ_32K) {
609 return 2;
610 }
611
612 switch (freq) {
613 case HAL_CMU_FREQ_26M:
614 set = 0;
615 clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4 | AON_CMU_SEL_FLS_PLL;
616 break;
617 case HAL_CMU_FREQ_52M:
618 set = AON_CMU_SEL_FLS_OSCX2;
619 clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX4 | AON_CMU_SEL_FLS_PLL;
620 break;
621 case HAL_CMU_FREQ_78M:
622 case HAL_CMU_FREQ_104M:
623 #ifdef OSC_26M_X4_AUD2BB
624 set = AON_CMU_SEL_FLS_OSCX4;
625 clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_PLL;
626 break;
627 #endif
628 case HAL_CMU_FREQ_156M:
629 case HAL_CMU_FREQ_208M:
630 case HAL_CMU_FREQ_260M:
631 set = AON_CMU_RSTN_DIV_FLS | AON_CMU_SEL_FLS_PLL;
632 clr = AON_CMU_CFG_DIV_FLS_MASK | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4;
633 if (0) {
634 #ifndef OSC_26M_X4_AUD2BB
635 } else if (freq <= HAL_CMU_FREQ_78M) {
636 set |= AON_CMU_CFG_DIV_FLS(3);
637 } else if (freq <= HAL_CMU_FREQ_104M) {
638 set |= AON_CMU_CFG_DIV_FLS(2);
639 #endif
640 } else if (freq <= HAL_CMU_FREQ_156M) {
641 set |= AON_CMU_CFG_DIV_FLS(1);
642 } else { // 208M or 260M
643 set |= AON_CMU_CFG_DIV_FLS(0);
644 }
645 break;
646 case HAL_CMU_FREQ_390M:
647 case HAL_CMU_FREQ_780M:
648 default:
649 set = AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_PLL;
650 clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4;
651 break;
652 };
653
654 lock = int_lock();
655 clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_FLASH);
656 if (clk_en) {
657 cmu->OCLK_DISABLE = SYS_OCLK_FLASH;
658 cmu->HCLK_DISABLE = SYS_HCLK_FLASH;
659 // Wait at least 2 cycles of flash controller. The min freq is 26M, the same as AON.
660 aocmu_reg_update_wait();
661 aocmu_reg_update_wait();
662 }
663 aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
664 if (clk_en) {
665 cmu->HCLK_ENABLE = SYS_HCLK_FLASH;
666 cmu->OCLK_ENABLE = SYS_OCLK_FLASH;
667 }
668 int_unlock(lock);
669
670 return 0;
671 }
672
hal_cmu_flash1_set_freq(enum HAL_CMU_FREQ_T freq)673 int BOOT_TEXT_SRAM_LOC hal_cmu_flash1_set_freq(enum HAL_CMU_FREQ_T freq)
674 {
675 aoncmu->FLASH_IOCFG |= AON_CMU_PU_FLASH1_IO;
676 //TODO: 2003 flash0 and flash1 use same clock source, so don't change clk freq in case of flash0 error
677 #ifdef ROM_BUILD //2003 rom only use one flash
678 return hal_cmu_flash_set_freq(freq);
679 #else
680 return 0;
681 #endif
682 }
683
hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq)684 int hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq)
685 {
686 uint32_t set;
687 uint32_t clr;
688 uint32_t lock;
689 bool clk_en;
690
691 if (freq >= HAL_CMU_FREQ_QTY) {
692 return 1;
693 }
694 if (freq == HAL_CMU_FREQ_32K) {
695 return 2;
696 }
697
698 // 2003 psram ctrl use 400M clk from bbpsram
699 switch (freq) {
700 case HAL_CMU_FREQ_26M:
701 set = 0;
702 clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4 | AON_CMU_SEL_PSR_PLL;
703 break;
704 case HAL_CMU_FREQ_52M:
705 set = AON_CMU_SEL_PSR_OSCX2;
706 clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX4 | AON_CMU_SEL_PSR_PLL;
707 break;
708 case HAL_CMU_FREQ_78M:
709 case HAL_CMU_FREQ_104M:
710 #ifdef OSC_26M_X4_AUD2BB
711 set = AON_CMU_SEL_PSR_OSCX4;
712 clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_PLL;
713 break;
714 #endif
715 case HAL_CMU_FREQ_156M:
716 case HAL_CMU_FREQ_208M:
717 case HAL_CMU_FREQ_260M:
718 set = AON_CMU_RSTN_DIV_PSR | AON_CMU_SEL_PSR_PLL | AON_CMU_SEL_PSR_INT;
719 clr = AON_CMU_CFG_DIV_PSR_MASK | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4;
720 if (0) {
721 #ifndef OSC_26M_X4_AUD2BB
722 } else if (freq <= HAL_CMU_FREQ_78M) {
723 set |= AON_CMU_CFG_DIV_PSR(3);
724 } else if (freq <= HAL_CMU_FREQ_104M) {
725 set |= AON_CMU_CFG_DIV_PSR(2);
726 #endif
727 } else if (freq <= HAL_CMU_FREQ_156M) {
728 set |= AON_CMU_CFG_DIV_PSR(1);
729 } else { // 208M or 260M
730 set |= AON_CMU_CFG_DIV_PSR(0);
731 }
732 break;
733 case HAL_CMU_FREQ_390M:
734 case HAL_CMU_FREQ_780M:
735 default:
736 set = AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_PLL | AON_CMU_SEL_PSR_INT;
737 clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4;
738 break;
739 };
740
741 lock = int_lock();
742 clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_PSRAM200);
743 if (clk_en) {
744 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PHY_PS_DISABLE;
745 cmu->OCLK_DISABLE = SYS_OCLK_PSRAM200;
746 cmu->HCLK_DISABLE = SYS_HCLK_PSRAM200;
747 // Wait at least 2 cycles of psram controller. The min freq is 26M, the same as AON.
748 aocmu_reg_update_wait();
749 aocmu_reg_update_wait();
750 }
751 aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
752 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PHY_PS_ENABLE;
753 if (clk_en) {
754 cmu->HCLK_ENABLE = SYS_HCLK_PSRAM200;
755 cmu->OCLK_ENABLE = SYS_OCLK_PSRAM200;
756 }
757 int_unlock(lock);
758
759 return 0;
760 }
761
hal_cmu_ddr_clock_enable()762 int hal_cmu_ddr_clock_enable()
763 {
764 uint32_t set;
765 uint32_t clr;
766 uint32_t lock;
767 bool clk_en;
768
769 hal_cmu_pll_enable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_PSRAM);
770 #if 1
771 //pxclk use xclk, works in synchronous mode
772 //a7 can change sys freq in this mode
773 cmu->PERIPH_CLK &= ~CMU_SEL_PSRAMX2;
774 *(volatile uint32_t *)(GPV_PSRAM1G_BASE+0x42020) = 0;
775 #else
776 //pxclk use psram2, works in asynchronous mode
777 *(volatile uint32_t *)(GPV_PSRAM1G_BASE+0x42020) = 4;
778 cmu->PERIPH_CLK |= CMU_SEL_PSRAMX2;
779 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_PSRAMX2_ENABLE;
780 #endif
781
782 // PSRAMUHS can't use ddr pll divider
783 set = AON_CMU_BYPASS_DIV_DDR | AON_CMU_SEL_DDR_PLL | AON_CMU_CFG_DIV_PSRAMX2(2);
784 clr = AON_CMU_RSTN_DIV_DDR | AON_CMU_SEL_DDR_OSCX2 | AON_CMU_SEL_DDR_OSCX4 | AON_CMU_CFG_DIV_PSRAMX2_MASK;
785
786 lock = int_lock();
787 clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_PSRAM1G);
788 if (clk_en) {
789 cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G;
790 cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G;
791 // Wait at least 2 cycles of psram controller. The min freq is 26M, the same as AON.
792 aocmu_reg_update_wait();
793 aocmu_reg_update_wait();
794 }
795 aoncmu->DDR_CLK = (aoncmu->DDR_CLK & ~clr) | set;
796
797 cmu->XCLK_ENABLE = SYS_XCLK_PSRAM1G | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_PSRAM1G;
798 cmu->HCLK_ENABLE = SYS_HCLK_PSRAM1G;
799 cmu->OCLK_ENABLE = SYS_OCLK_PSRAM1G;
800
801 int_unlock(lock);
802
803 return 0;
804 }
805
hal_cmu_ddr_clock_disable()806 void hal_cmu_ddr_clock_disable()
807 {
808 cmu->XCLK_DISABLE = SYS_XCLK_PSRAM1G | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_PSRAM1G;
809 cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G;
810 cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G;
811 hal_cmu_pll_disable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_PSRAM);
812 }
813
hal_cmu_ddr_reset_set()814 void hal_cmu_ddr_reset_set()
815 {
816 cmu->XRESET_SET = SYS_XRST_PSRAM1G | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_PSRAM1G;
817 cmu->ORESET_SET = SYS_ORST_PSRAM1G;
818 cmu->HRESET_SET = SYS_HRST_PSRAM1G;
819 }
820
hal_cmu_ddr_reset_clear()821 void hal_cmu_ddr_reset_clear()
822 {
823 cmu->XRESET_CLR = SYS_XRST_PSRAM1G | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_PSRAM1G;
824 cmu->ORESET_CLR = SYS_ORST_PSRAM1G;
825 cmu->HRESET_CLR = SYS_HRST_PSRAM1G;
826 }
827
828 int hal_cmu_dsp_set_freq(enum HAL_CMU_FREQ_T freq);
829
hal_cmu_dsi_clock_enable(void)830 void hal_cmu_dsi_clock_enable(void)
831 {
832 hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
833 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
834 hal_cmu_pll_enable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
835 cmu->APCLK_ENABLE = SYS_APCLK_DISPLAY;
836 aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN |
837 SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_DSI, 0xc);
838 cmu->QCLK_ENABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
839 hal_sys_timer_delay_us(10);
840 }
841
hal_cmu_dsi_clock_enable_v2(uint8_t pixel_div)842 void hal_cmu_dsi_clock_enable_v2(uint8_t pixel_div)
843 {
844 hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
845 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
846 hal_cmu_pll_enable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
847 cmu->APCLK_ENABLE = SYS_APCLK_DISPLAY;
848 aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN |
849 SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_DSI, pixel_div);
850 cmu->QCLK_ENABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
851 hal_sys_timer_delay_us(10);
852 }
853
hal_cmu_dsi_clock_disable(void)854 void hal_cmu_dsi_clock_disable(void)
855 {
856 aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN);
857 cmu->QCLK_DISABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
858 cmu->APCLK_DISABLE = SYS_APCLK_DISPLAY;
859 hal_cmu_pll_disable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
860 }
861
hal_cmu_dsi_reset_set(void)862 void hal_cmu_dsi_reset_set(void)
863 {
864 cmu->QRESET_SET = SYS_QRST_DSI_DSI | SYS_QRST_DSI_PIX;
865 cmu->APRESET_SET = SYS_APRST_DISPLAY;
866 }
867
hal_cmu_dsi_reset_clear(void)868 void hal_cmu_dsi_reset_clear(void)
869 {
870 cmu->APRESET_CLR = SYS_APRST_DISPLAY;
871 cmu->QRESET_CLR = SYS_QRST_DSI_DSI | SYS_QRST_DSI_PIX;
872 hal_sys_timer_delay_us(10);
873 }
874
hal_cmu_lcdc_clock_enable(void)875 void hal_cmu_lcdc_clock_enable(void)
876 {
877 cmu->XCLK_ENABLE = SYS_XCLK_DSI | SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH;
878 cmu->QCLK_ENABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV;
879 }
880
hal_cmu_lcdc_clock_disable(void)881 void hal_cmu_lcdc_clock_disable(void)
882 {
883 cmu->QCLK_DISABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV;
884 cmu->XCLK_DISABLE = SYS_XCLK_DSI | SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH;
885 }
886
hal_cmu_lcdc_reset_set(void)887 void hal_cmu_lcdc_reset_set(void)
888 {
889 cmu->QRESET_SET = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV;
890 cmu->XRESET_SET = SYS_XRST_DSI | SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH;
891 }
892
hal_cmu_lcdc_reset_clear(void)893 void hal_cmu_lcdc_reset_clear(void)
894 {
895 cmu->XRESET_CLR = SYS_XRST_DSI | SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH;
896 cmu->QRESET_CLR = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV;
897 hal_sys_timer_delay_us(10);
898 }
899
hal_cmu_csi_clock_enable(void)900 void hal_cmu_csi_clock_enable(void)
901 {
902 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
903 aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_CSI_IN |
904 SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_CSI, 0x7); //0xa:240M 1lane
905 cmu->APCLK_ENABLE = SYS_APCLK_CSI;
906 cmu->XCLK_ENABLE = SYS_XCLK_CSI;
907 cmu->QCLK_ENABLE = SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG;
908 }
909
hal_cmu_csi_clock_disable(void)910 void hal_cmu_csi_clock_disable(void)
911 {
912 cmu->XCLK_DISABLE = SYS_XCLK_CSI;
913 cmu->QCLK_ENABLE = SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG;
914 cmu->APCLK_DISABLE = SYS_APCLK_CSI;
915 aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_CSI_IN);
916 }
917
hal_cmu_csi_reset_set(void)918 void hal_cmu_csi_reset_set(void)
919 {
920 cmu->XRESET_SET = SYS_XRST_CSI;
921 cmu->QRESET_SET = SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG;
922 cmu->APRESET_SET = SYS_APRST_CSI;
923 }
924
hal_cmu_csi_reset_clear(void)925 void hal_cmu_csi_reset_clear(void)
926 {
927 cmu->APRESET_CLR = SYS_APRST_CSI;
928 cmu->XRESET_CLR = SYS_XRST_CSI;
929 cmu->QRESET_CLR = SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG;
930 hal_sys_timer_delay_us(10);
931 }
932
933 #ifdef LOW_SYS_FREQ
934 #ifdef LOW_SYS_FREQ_6P5M
hal_cmu_fast_timer_offline(void)935 int hal_cmu_fast_timer_offline(void)
936 {
937 return (cmu_sys_freq == HAL_CMU_FREQ_6P5M);
938 }
939 #endif
940 #endif
941
942 #ifdef CHIP_BEST2003_DSP
943
944 int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq) __attribute__((alias("hal_cmu_dsp_set_freq")));
945
946 enum HAL_CMU_FREQ_T hal_cmu_sys_get_freq(void) __attribute__((alias("hal_cmu_dsp_get_freq")));
947
948 #else // !CHIP_BEST2003_DSP
949
hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq)950 int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq)
951 {
952 uint32_t enable;
953 uint32_t disable;
954 int div;
955 uint32_t lock;
956
957 if (freq >= HAL_CMU_FREQ_QTY) {
958 return 1;
959 }
960
961 #ifdef LOW_SYS_FREQ
962 cmu_sys_freq = freq;
963 #endif
964
965 div = -1;
966
967 switch (freq) {
968 case HAL_CMU_FREQ_32K:
969 enable = 0;
970 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_OSC_4_DISABLE | CMU_SEL_MCU_OSC_2_DISABLE |
971 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_SLOW_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
972 break;
973 case HAL_CMU_FREQ_6P5M:
974 #if defined(LOW_SYS_FREQ) && defined(LOW_SYS_FREQ_6P5M)
975 enable = CMU_SEL_MCU_OSC_4_ENABLE;
976 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
977 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_SLOW_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
978 break;
979 #endif
980 case HAL_CMU_FREQ_13M:
981 #ifdef LOW_SYS_FREQ
982 enable = CMU_SEL_MCU_OSC_2_ENABLE | CMU_SEL_MCU_SLOW_ENABLE;
983 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
984 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
985 break;
986 #endif
987 case HAL_CMU_FREQ_26M:
988 enable = CMU_SEL_MCU_SLOW_ENABLE;
989 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_OSC_2_ENABLE |
990 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
991 break;
992 case HAL_CMU_FREQ_52M:
993 enable = CMU_SEL_MCU_FAST_ENABLE;
994 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
995 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
996 break;
997 case HAL_CMU_FREQ_78M:
998 case HAL_CMU_FREQ_104M:
999 #ifdef OSC_26M_X4_AUD2BB
1000 enable = CMU_SEL_MCU_OSCX4_ENABLE | CMU_SEL_MCU_FAST_ENABLE;
1001 disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
1002 break;
1003 #endif
1004 case HAL_CMU_FREQ_156M:
1005 case HAL_CMU_FREQ_208M:
1006 case HAL_CMU_FREQ_260M:
1007 enable = CMU_RSTN_DIV_MCU_ENABLE | CMU_SEL_MCU_PLL_ENABLE;
1008 disable = CMU_BYPASS_DIV_MCU_DISABLE;
1009 if (0) {
1010 #ifndef OSC_26M_X4_AUD2BB
1011 } else if (freq <= HAL_CMU_FREQ_78M) {
1012 div = 3;
1013 } else if (freq <= HAL_CMU_FREQ_104M) {
1014 div = 2;
1015 #endif
1016 } else if (freq <= HAL_CMU_FREQ_156M) {
1017 div = 1;
1018 } else { // 208M or 260M
1019 div = 0;
1020 }
1021 break;
1022 case HAL_CMU_FREQ_390M:
1023 case HAL_CMU_FREQ_780M:
1024 default:
1025 enable = CMU_BYPASS_DIV_MCU_ENABLE | CMU_SEL_MCU_PLL_ENABLE;
1026 disable = CMU_RSTN_DIV_MCU_DISABLE;
1027 break;
1028 };
1029
1030 if (div >= 0) {
1031 lock = int_lock();
1032 cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_MCU, div);
1033 int_unlock(lock);
1034 }
1035
1036 if (enable & CMU_SEL_MCU_PLL_ENABLE) {
1037 cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_MCU_ENABLE;
1038 if (enable & CMU_BYPASS_DIV_MCU_ENABLE) {
1039 cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_MCU_ENABLE;
1040 } else {
1041 cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_MCU_DISABLE;
1042 }
1043 }
1044 cmu->SYS_CLK_ENABLE = enable;
1045 if (enable & CMU_SEL_MCU_PLL_ENABLE) {
1046 cmu->SYS_CLK_DISABLE = disable;
1047 } else {
1048 cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE);
1049 cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_MCU_DISABLE;
1050 cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_MCU_DISABLE;
1051 }
1052
1053 return 0;
1054 }
1055
hal_cmu_sys_get_freq(void)1056 enum HAL_CMU_FREQ_T BOOT_TEXT_SRAM_LOC hal_cmu_sys_get_freq(void)
1057 {
1058 uint32_t sys_clk;
1059 uint32_t div;
1060
1061 sys_clk = cmu->SYS_CLK_ENABLE;
1062
1063 if (sys_clk & CMU_SEL_MCU_PLL_ENABLE) {
1064 if (sys_clk & CMU_BYPASS_DIV_MCU_ENABLE) {
1065 // 384M
1066 return HAL_CMU_FREQ_390M;
1067 } else {
1068 div = GET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_MCU);
1069 if (div == 0) {
1070 // 192M
1071 return HAL_CMU_FREQ_208M;
1072 } else if (div == 1) {
1073 // 128M
1074 return HAL_CMU_FREQ_156M;
1075 } else if (div == 2) {
1076 // 96M
1077 return HAL_CMU_FREQ_104M;
1078 } else { // div == 3
1079 // 76.8M
1080 return HAL_CMU_FREQ_78M;
1081 }
1082 }
1083 } else if (sys_clk & CMU_SEL_MCU_FAST_ENABLE) {
1084 if (sys_clk & CMU_SEL_MCU_OSCX4_ENABLE) {
1085 return HAL_CMU_FREQ_104M;
1086 } else {
1087 return HAL_CMU_FREQ_52M;
1088 }
1089 } else if (sys_clk & CMU_SEL_MCU_SLOW_ENABLE) {
1090 return HAL_CMU_FREQ_26M;
1091 } else {
1092 return HAL_CMU_FREQ_32K;
1093 }
1094 }
1095
1096 #endif // !CHIP_BEST2003_DSP
1097
hal_cmu_dsp_set_freq(enum HAL_CMU_FREQ_T freq)1098 int hal_cmu_dsp_set_freq(enum HAL_CMU_FREQ_T freq)
1099 {
1100 uint32_t enable;
1101 uint32_t disable;
1102 int div;
1103 uint32_t lock;
1104
1105 if (freq >= HAL_CMU_FREQ_QTY) {
1106 return 1;
1107 }
1108
1109 #ifdef CHIP_BEST2003_DSP
1110 #ifdef LOW_SYS_FREQ
1111 cmu_sys_freq = freq;
1112 #endif
1113 #endif
1114
1115 div = -1;
1116
1117 switch (freq) {
1118 case HAL_CMU_FREQ_32K:
1119 enable = 0;
1120 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_OSC_4_DISABLE | CMU_SEL_A7_OSC_2_DISABLE |
1121 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_SLOW_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1122 break;
1123 case HAL_CMU_FREQ_6P5M:
1124 #if defined(LOW_SYS_FREQ) && defined(LOW_SYS_FREQ_6P5M)
1125 enable = CMU_SEL_A7_OSC_4_ENABLE;
1126 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
1127 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_SLOW_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1128 break;
1129 #endif
1130 case HAL_CMU_FREQ_13M:
1131 #ifdef LOW_SYS_FREQ
1132 enable = CMU_SEL_A7_OSC_2_ENABLE | CMU_SEL_A7_SLOW_ENABLE;
1133 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
1134 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1135 break;
1136 #endif
1137 case HAL_CMU_FREQ_26M:
1138 enable = CMU_SEL_A7_SLOW_ENABLE;
1139 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_OSC_2_DISABLE |
1140 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1141 break;
1142 case HAL_CMU_FREQ_52M:
1143 enable = CMU_SEL_A7_FAST_ENABLE;
1144 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
1145 CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1146 break;
1147 case HAL_CMU_FREQ_78M:
1148 case HAL_CMU_FREQ_104M:
1149 #ifdef OSC_26M_X4_AUD2BB
1150 enable = CMU_SEL_A7_OSCX4_ENABLE | CMU_SEL_A7_FAST_ENABLE;
1151 disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_PLL_DISABLE;
1152 break;
1153 #endif
1154 case HAL_CMU_FREQ_156M:
1155 case HAL_CMU_FREQ_208M:
1156 case HAL_CMU_FREQ_260M:
1157 case HAL_CMU_FREQ_390M:
1158 enable = CMU_RSTN_DIV_A7_ENABLE | CMU_SEL_A7_PLL_ENABLE;
1159 disable = CMU_BYPASS_DIV_A7_DISABLE;
1160 if (0) {
1161 } else if (freq <= HAL_CMU_FREQ_156M) {
1162 div = 3;
1163 } else if (freq <= HAL_CMU_FREQ_208M) {
1164 div = 2;
1165 } else if (freq <= HAL_CMU_FREQ_260M) {
1166 div = 1;
1167 } else { // 390M
1168 div = 0;
1169 }
1170 break;
1171 case HAL_CMU_FREQ_780M:
1172 default:
1173 enable = CMU_BYPASS_DIV_A7_ENABLE | CMU_SEL_A7_PLL_ENABLE;
1174 disable = CMU_RSTN_DIV_A7_DISABLE;
1175 break;
1176 };
1177
1178 if (div >= 0) {
1179 lock = int_lock();
1180 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_A7, div);
1181 int_unlock(lock);
1182 }
1183
1184 if (enable & CMU_SEL_A7_PLL_ENABLE) {
1185 cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_A7_ENABLE;
1186 if (enable & CMU_BYPASS_DIV_A7_ENABLE) {
1187 cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_A7_ENABLE;
1188 } else {
1189 cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_A7_DISABLE;
1190 }
1191 }
1192 cmu->SYS_CLK_ENABLE = enable;
1193 if (enable & CMU_SEL_A7_PLL_ENABLE) {
1194 cmu->SYS_CLK_DISABLE = disable;
1195 } else {
1196 cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE);
1197 cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_A7_DISABLE;
1198 cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_A7_DISABLE;
1199 }
1200
1201 return 0;
1202 }
1203
hal_cmu_dsp_get_freq(void)1204 enum HAL_CMU_FREQ_T BOOT_TEXT_SRAM_LOC hal_cmu_dsp_get_freq(void)
1205 {
1206 uint32_t sys_clk;
1207 uint32_t div;
1208
1209 sys_clk = cmu->SYS_CLK_ENABLE;
1210
1211 if (sys_clk & CMU_SEL_A7_PLL_ENABLE) {
1212 if (sys_clk & CMU_BYPASS_DIV_A7_ENABLE) {
1213 return HAL_CMU_FREQ_780M;
1214 } else {
1215 div = GET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_A7);
1216 if (div == 0) {
1217 return HAL_CMU_FREQ_390M;
1218 } else if (div == 1) {
1219 return HAL_CMU_FREQ_260M;
1220 } else if (div == 2) {
1221 return HAL_CMU_FREQ_208M;
1222 } else { // div == 3
1223 return HAL_CMU_FREQ_156M;
1224 }
1225 }
1226 } else if (sys_clk & CMU_SEL_A7_FAST_ENABLE) {
1227 if (sys_clk & CMU_SEL_A7_OSCX4_ENABLE) {
1228 return HAL_CMU_FREQ_104M;
1229 } else {
1230 return HAL_CMU_FREQ_52M;
1231 }
1232 } else if (sys_clk & CMU_SEL_A7_SLOW_ENABLE) {
1233 return HAL_CMU_FREQ_26M;
1234 } else {
1235 return HAL_CMU_FREQ_32K;
1236 }
1237 }
1238
hal_cmu_flash_select_pll(enum HAL_CMU_PLL_T pll)1239 int BOOT_TEXT_SRAM_LOC hal_cmu_flash_select_pll(enum HAL_CMU_PLL_T pll)
1240 {
1241 return 0;
1242 }
1243
hal_cmu_flash1_select_pll(enum HAL_CMU_PLL_T pll)1244 int BOOT_TEXT_SRAM_LOC hal_cmu_flash1_select_pll(enum HAL_CMU_PLL_T pll)
1245 {
1246 return 0;
1247 }
1248
hal_cmu_mem_select_pll(enum HAL_CMU_PLL_T pll)1249 int hal_cmu_mem_select_pll(enum HAL_CMU_PLL_T pll)
1250 {
1251 return 0;
1252 }
1253
hal_cmu_dsp_select_pll(enum HAL_CMU_PLL_T pll)1254 int hal_cmu_dsp_select_pll(enum HAL_CMU_PLL_T pll)
1255 {
1256 uint32_t lock;
1257 uint32_t set;
1258 uint32_t clr;
1259
1260 if (pll == HAL_CMU_PLL_USB) {
1261 set = AON_CMU_SEL_A7_PLLUSB | AON_CMU_SEL_A7_PLLBB;
1262 clr = 0;
1263 } else if (pll == HAL_CMU_PLL_DSP) {
1264 set = 0;
1265 clr = AON_CMU_SEL_A7_PLLUSB | AON_CMU_SEL_A7_PLLBB;
1266 } else if (pll == HAL_CMU_PLL_BB) {
1267 set = AON_CMU_SEL_A7_PLLBB;
1268 clr = AON_CMU_SEL_A7_PLLUSB;
1269 } else {
1270 // == HAL_CMU_PLL_DDR or == HAL_CMU_PLL_BB_PSRAM or >= HAL_CMU_PLL_QTY
1271 return 1;
1272 }
1273
1274 lock = int_lock();
1275 aoncmu->DSP_PLL_SELECT = (aoncmu->DSP_PLL_SELECT & ~clr) | set;
1276 int_unlock(lock);
1277
1278 return 0;
1279 }
1280
hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll)1281 int BOOT_TEXT_FLASH_LOC hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll)
1282 {
1283 uint32_t lock;
1284 uint32_t set;
1285 uint32_t clr;
1286
1287 if (pll == HAL_CMU_PLL_USB) {
1288 set = AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
1289 clr = AON_CMU_SEL_MCU_PLLBB_PS;
1290 } else if (pll == HAL_CMU_PLL_DSP) {
1291 set = AON_CMU_SEL_MCU_PLLA7USB;
1292 clr = AON_CMU_SEL_MCU_PLLBB_PS | AON_CMU_SEL_MCU_PLLUSB;
1293 } else if (pll == HAL_CMU_PLL_BB) {
1294 set = 0;
1295 clr = AON_CMU_SEL_MCU_PLLBB_PS | AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
1296 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1297 set = AON_CMU_SEL_MCU_PLLBB_PS;
1298 clr = AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
1299 } else {
1300 // == HAL_CMU_PLL_DDR or >= HAL_CMU_PLL_QTY
1301 return 1;
1302 }
1303
1304 lock = int_lock();
1305 aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
1306 int_unlock(lock);
1307
1308 return 0;
1309 }
1310
hal_cmu_audio_select_pll(enum HAL_CMU_PLL_T pll)1311 int BOOT_TEXT_FLASH_LOC hal_cmu_audio_select_pll(enum HAL_CMU_PLL_T pll)
1312 {
1313 if (pll == HAL_CMU_PLL_BB) {
1314 aoncmu->PCM_I2S_CLK &= ~AON_CMU_SEL_AUD_PLLUSB;
1315 } else {
1316 aoncmu->PCM_I2S_CLK |= AON_CMU_SEL_AUD_PLLUSB;
1317 }
1318
1319 return 0;
1320 }
1321
hal_cmu_get_pll_status(enum HAL_CMU_PLL_T pll)1322 int hal_cmu_get_pll_status(enum HAL_CMU_PLL_T pll)
1323 {
1324 bool en;
1325
1326 if (pll == HAL_CMU_PLL_USB) {
1327 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE);
1328 } else if (pll == HAL_CMU_PLL_DDR) {
1329 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE);
1330 } else if (pll == HAL_CMU_PLL_DSP) {
1331 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLA7_ENABLE);
1332 } else if (pll == HAL_CMU_PLL_BB) {
1333 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLBB_ENABLE);
1334 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1335 en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE);
1336 } else {
1337 en = false;
1338 }
1339
1340 return en;
1341 }
1342
hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll,enum HAL_CMU_PLL_USER_T user)1343 int BOOT_TEXT_FLASH_LOC hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user)
1344 {
1345 uint32_t pu_val;
1346 uint32_t en_val;
1347 uint32_t lock;
1348
1349 if (pll >= HAL_CMU_PLL_QTY) {
1350 return 1;
1351 }
1352 if (user >= HAL_CMU_PLL_USER_QTY && user != HAL_CMU_PLL_USER_ALL) {
1353 return 2;
1354 }
1355
1356 if (pll == HAL_CMU_PLL_USB) {
1357 pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_PS_ENABLE;
1358 en_val = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
1359 } else if (pll == HAL_CMU_PLL_DDR) {
1360 pu_val = AON_CMU_PU_PLLDDR_ENABLE;
1361 en_val = AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE;
1362 } else if (pll == HAL_CMU_PLL_DSP) {
1363 pu_val = AON_CMU_PU_PLLA7_ENABLE;
1364 en_val = AON_CMU_EN_CLK_TOP_PLLA7_ENABLE;
1365 } else if (pll == HAL_CMU_PLL_BB) {
1366 #ifdef BBPLL_USE_DSI_MCUPLL
1367 pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_MCU_ENABLE;
1368 #else
1369 pu_val = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_MCU_ENABLE;
1370 #endif
1371 en_val = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
1372 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1373 #ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
1374 pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_PS_ENABLE;
1375 #else
1376 pu_val = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_PS_ENABLE;
1377 #endif
1378 en_val = AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE;
1379 } else if (pll == HAL_CMU_PLL_DSI) {
1380 pu_val = AON_CMU_PU_PLLDSI_ENABLE;
1381 en_val = 0;
1382 } else {
1383 pu_val = 0;
1384 en_val = 0;
1385 }
1386
1387 lock = int_lock();
1388
1389 if (pll_user_map[pll] == 0 || user == HAL_CMU_PLL_USER_ALL) {
1390 #ifndef ROM_BUILD
1391 pmu_pll_div_reset_set(pll);
1392 #endif
1393 aoncmu->PLL_ENABLE = pu_val;
1394 #ifndef ROM_BUILD
1395 hal_sys_timer_delay_us(20);
1396 pmu_pll_div_reset_clear(pll);
1397 // Wait at least 10us for clock ready
1398 hal_sys_timer_delay_us(10);
1399 #endif
1400 aoncmu->TOP_CLK_ENABLE = en_val;
1401 }
1402 if (user < HAL_CMU_PLL_USER_QTY) {
1403 pll_user_map[pll] |= (1 << user);
1404 } else if (user == HAL_CMU_PLL_USER_ALL) {
1405 pll_user_map[pll] |= ((1 << user) - 1);
1406 }
1407 int_unlock(lock);
1408
1409 return 0;
1410 }
1411
hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll,enum HAL_CMU_PLL_USER_T user)1412 int BOOT_TEXT_FLASH_LOC hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user)
1413 {
1414 uint32_t pu_val;
1415 uint32_t en_val;
1416 uint32_t lock;
1417
1418 if (pll >= HAL_CMU_PLL_QTY) {
1419 return 1;
1420 }
1421 if (user >= HAL_CMU_PLL_USER_QTY && user != HAL_CMU_PLL_USER_ALL) {
1422 return 2;
1423 }
1424
1425 if (pll == HAL_CMU_PLL_USB) {
1426 pu_val = 0;
1427 en_val = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
1428 } else if (pll == HAL_CMU_PLL_DDR) {
1429 pu_val = AON_CMU_PU_PLLDDR_DISABLE;
1430 en_val = AON_CMU_EN_CLK_TOP_PLLDDR_DISABLE;
1431 } else if (pll == HAL_CMU_PLL_DSP) {
1432 pu_val = AON_CMU_PU_PLLA7_DISABLE;
1433 en_val = AON_CMU_EN_CLK_TOP_PLLA7_DISABLE;
1434 } else if (pll == HAL_CMU_PLL_BB) {
1435 #ifdef BBPLL_USE_DSI_MCUPLL
1436 pu_val = AON_CMU_PU_PLLDSI_DIV_MCU_DISABLE;
1437 #else
1438 pu_val = AON_CMU_PU_PLLBB_DIV_MCU_DISABLE;
1439 #endif
1440 en_val = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
1441 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1442 #ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
1443 pu_val = AON_CMU_PU_PLLDSI_DIV_PS_DISABLE;
1444 #else
1445 pu_val = AON_CMU_PU_PLLBB_DIV_PS_DISABLE;
1446 #endif
1447 en_val = AON_CMU_EN_CLK_TOP_PLLBB_PS_DISABLE;
1448 } else if (pll == HAL_CMU_PLL_DSI) {
1449 pu_val = 0;
1450 en_val = 0;
1451 } else {
1452 pu_val = 0;
1453 en_val = 0;
1454 }
1455
1456 lock = int_lock();
1457 if (user < HAL_CMU_PLL_USER_ALL) {
1458 pll_user_map[pll] &= ~(1 << user);
1459 } else if (user == HAL_CMU_PLL_USER_ALL) {
1460 pll_user_map[pll] = 0;
1461 }
1462 if (pll_user_map[pll] == 0 || user == HAL_CMU_PLL_USER_ALL) {
1463 #if defined(BBPLL_USE_DSI_MCUPLL) && defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
1464 if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0 &&
1465 pll_user_map[HAL_CMU_PLL_USB] == 0 && pll_user_map[HAL_CMU_PLL_DSI] == 0)
1466 pu_val |= AON_CMU_PU_PLLBB_DISABLE;
1467 #elif defined(BBPLL_USE_DSI_MCUPLL) && !defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
1468 if (pll == HAL_CMU_PLL_BB || pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
1469 if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_USB] == 0 &&
1470 pll_user_map[HAL_CMU_PLL_DSI] == 0)
1471 pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
1472 } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
1473 pu_val |= AON_CMU_PU_PLLBB_DISABLE;
1474 }
1475 #elif !defined(BBPLL_USE_DSI_MCUPLL) && defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
1476 if (pll == HAL_CMU_PLL_BB_PSRAM || pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
1477 if (pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0 && pll_user_map[HAL_CMU_PLL_USB] == 0 &&
1478 pll_user_map[HAL_CMU_PLL_DSI] == 0)
1479 pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
1480 } else if (pll == HAL_CMU_PLL_BB) {
1481 pu_val |= AON_CMU_PU_PLLBB_DISABLE;
1482 }
1483 #else
1484 if (pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
1485 if (pll_user_map[HAL_CMU_PLL_USB] == 0 && pll_user_map[HAL_CMU_PLL_DSI] == 0)
1486 pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
1487 } else if (pll == HAL_CMU_PLL_BB || pll == HAL_CMU_PLL_BB_PSRAM) {
1488 if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0)
1489 pu_val |= AON_CMU_PU_PLLBB_DISABLE;
1490 }
1491 #endif
1492 aoncmu->TOP_CLK_DISABLE = en_val;
1493 aoncmu->PLL_DISABLE = pu_val;
1494 }
1495 int_unlock(lock);
1496
1497 return 0;
1498 }
1499
hal_cmu_low_freq_mode_init(void)1500 void BOOT_TEXT_FLASH_LOC hal_cmu_low_freq_mode_init(void)
1501 {
1502 }
1503
hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq,enum HAL_CMU_FREQ_T new_freq)1504 void hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq)
1505 {
1506 enum HAL_CMU_PLL_T pll;
1507 enum HAL_CMU_FREQ_T switch_freq;
1508
1509 // TODO: Select the PLL used by sys
1510 pll = HAL_CMU_PLL_BB;
1511
1512 #ifdef OSC_26M_X4_AUD2BB
1513 switch_freq = HAL_CMU_FREQ_104M;
1514 #else
1515 switch_freq = HAL_CMU_FREQ_52M;
1516 #endif
1517
1518 if (old_freq > switch_freq && new_freq <= switch_freq) {
1519 hal_cmu_pll_disable(pll, HAL_CMU_PLL_USER_SYS);
1520 }
1521 }
1522
hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq,enum HAL_CMU_FREQ_T new_freq)1523 void hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq)
1524 {
1525 enum HAL_CMU_PLL_T pll;
1526 enum HAL_CMU_FREQ_T switch_freq;
1527
1528 // TODO: Select the PLL used by sys
1529 pll = HAL_CMU_PLL_BB;
1530
1531 #ifdef OSC_26M_X4_AUD2BB
1532 switch_freq = HAL_CMU_FREQ_104M;
1533 #else
1534 switch_freq = HAL_CMU_FREQ_52M;
1535 #endif
1536
1537 if (old_freq <= switch_freq && new_freq > switch_freq) {
1538 hal_cmu_pll_enable(pll, HAL_CMU_PLL_USER_SYS);
1539 }
1540 }
1541
hal_cmu_rom_enable_pll(void)1542 void hal_cmu_rom_enable_pll(void)
1543 {
1544 hal_cmu_sys_select_pll(HAL_CMU_PLL_BB);
1545 hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_SYS);
1546
1547 #if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
1548 hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
1549 #endif
1550 }
1551
hal_cmu_sram_init()1552 void BOOT_TEXT_FLASH_LOC hal_cmu_sram_init()
1553 {
1554 uint32_t mcu_ram_size;
1555
1556 #if defined(ARM_CMSE)
1557 mcu_ram_size = RAM5_BASE + RAM5_SIZE - RAM0_BASE;
1558 #elif defined(ARM_CMNS)
1559 mcu_ram_size = RAM_SIZE + RAM_S_SIZE;
1560 #else
1561 mcu_ram_size = RAM_SIZE;
1562 #endif
1563 #if defined(CHIP_HAS_CP) && ((RAMCP_SIZE > 0) || (RAMCPX_SIZE > 0))
1564 mcu_ram_size += (RAMCP_SIZE + RAMCPX_SIZE);
1565 #endif
1566 #ifdef __BT_RAMRUN__
1567 mcu_ram_size += BT_RAMRUN_SIZE;
1568 #endif
1569
1570 switch (mcu_ram_size) {
1571 case RAM1_BASE - RAM0_BASE: //RAM0
1572 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x0);
1573 break;
1574 case RAM2_BASE - RAM0_BASE: //RAM0,1
1575 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x1);
1576 break;
1577 case RAM3_BASE - RAM0_BASE: //RAM0,1,2
1578 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x3);
1579 break;
1580 case RAM4_BASE - RAM0_BASE: //RAM0,1,2,3
1581 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x7);
1582 break;
1583 case RAM5_BASE - RAM0_BASE: //RAM0,1,2,3,4
1584 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0xF);
1585 break;
1586 case (RAM5_BASE + RAM5_SIZE - RAM0_BASE): //RAM0,1,2,3,4,5
1587 default:
1588 cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x1F);
1589 break;
1590 }
1591 }
1592
hal_cmu_programmer_enable_pll(void)1593 void hal_cmu_programmer_enable_pll(void)
1594 {
1595 hal_cmu_sram_init();
1596 hal_cmu_dma_req_init();
1597
1598 hal_cmu_flash_select_pll(HAL_CMU_PLL_BB);
1599 hal_cmu_sys_select_pll(HAL_CMU_PLL_BB);
1600 hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_SYS);
1601
1602 #if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
1603 hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
1604 #endif
1605 }
1606
hal_cmu_init_pll_selection(void)1607 void BOOT_TEXT_FLASH_LOC hal_cmu_init_pll_selection(void)
1608 {
1609 enum HAL_CMU_PLL_T sys;
1610
1611 #if !defined(ARM_CMNS)
1612 // Disable the PLL which might be enabled in ROM
1613 hal_cmu_pll_disable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_ALL);
1614 #endif
1615
1616 #ifdef BBPLL_USE_DSI_MCUPLL
1617 aoncmu->FLS_PSR_CLK |= AON_CMU_SEL_MCU_PLLDSI;
1618 #endif
1619
1620 #ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
1621 aoncmu->FLS_PSR_CLK |= AON_CMU_SEL_PSR_PLLDSI;
1622 #endif
1623
1624 #ifdef SYS_USE_USBPLL
1625 sys = HAL_CMU_PLL_USB;
1626 #elif defined(SYS_USE_BB_PSRAMPLL)
1627 sys = HAL_CMU_PLL_BB_PSRAM;
1628 #elif defined(SYS_USE_DSPPLL)
1629 sys = HAL_CMU_PLL_DSP;
1630 #else
1631 sys = HAL_CMU_PLL_BB;
1632 #endif
1633 hal_cmu_sys_select_pll(sys);
1634
1635 #ifdef AUDIO_USE_BBPLL
1636 hal_cmu_audio_select_pll(HAL_CMU_PLL_BB);
1637 #else
1638 hal_cmu_audio_select_pll(HAL_CMU_PLL_USB);
1639 #endif
1640
1641 #ifndef ULTRA_LOW_POWER
1642 hal_cmu_pll_enable(sys, HAL_CMU_PLL_USER_SYS);
1643 #endif
1644 #if !(defined(FLASH_LOW_SPEED) || defined(OSC_26M_X4_AUD2BB))
1645 hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_FLASH);
1646 #endif
1647 #if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
1648 hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
1649 #endif
1650
1651 hal_cmu_dsp_timer0_select_slow();
1652 #ifdef TIMER1_BASE
1653 hal_cmu_dsp_timer1_select_fast();
1654 #endif
1655 }
1656
1657 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
hal_cmu_audio_26m_x4_enable(enum CMU_AUD_26M_X4_USER_T user)1658 void hal_cmu_audio_26m_x4_enable(enum CMU_AUD_26M_X4_USER_T user)
1659 {
1660 uint32_t lock;
1661
1662 if (user >= CMU_AUD_26M_X4_USER_QTY) {
1663 return;
1664 }
1665
1666 lock = int_lock();
1667
1668 if (aud_26m_x4_map == 0) {
1669 aoncmu->PCM_I2S_CLK |= AON_CMU_SEL_AUD_X4;
1670 }
1671 aud_26m_x4_map |= (1 << user);
1672
1673 int_unlock(lock);
1674 }
1675
hal_cmu_audio_26m_x4_disable(enum CMU_AUD_26M_X4_USER_T user)1676 void hal_cmu_audio_26m_x4_disable(enum CMU_AUD_26M_X4_USER_T user)
1677 {
1678 uint32_t lock;
1679
1680 if (user >= CMU_AUD_26M_X4_USER_QTY) {
1681 return;
1682 }
1683
1684 lock = int_lock();
1685
1686 if (aud_26m_x4_map & (1 << user)) {
1687 aud_26m_x4_map &= ~(1 << user);
1688 if (aud_26m_x4_map == 0) {
1689 aoncmu->PCM_I2S_CLK &= ~AON_CMU_SEL_AUD_X4;
1690 }
1691 }
1692
1693 int_unlock(lock);
1694 }
1695 #endif
1696
hal_cmu_codec_iir_enable(uint32_t speed)1697 void hal_cmu_codec_iir_enable(uint32_t speed)
1698 {
1699 uint32_t lock;
1700 uint32_t mask;
1701 uint32_t val;
1702 uint32_t div;
1703 uint32_t cfg_speed = 0;
1704
1705 mask = AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2 | AON_CMU_BYPASS_DIV_CODECIIR;
1706 val = 0;
1707
1708 if (speed <= 26000000) {
1709 val |= AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2;
1710 cfg_speed = 26000000;
1711 } else if (speed <= 52000000) {
1712 val |= AON_CMU_SEL_CODECIIR_OSCX2;
1713 cfg_speed = 52000000;
1714 } else {
1715 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
1716 if (hal_cmu_get_audio_resample_status()) {
1717 hal_cmu_audio_26m_x4_enable(CMU_AUD_26M_X4_USER_IIR);
1718 val |= AON_CMU_BYPASS_DIV_CODECIIR;
1719 cfg_speed = 104000000;
1720 }
1721 else
1722 #endif
1723 {
1724 // Assume audio stream is one of 48K series
1725 div = HAL_CMU_AUD_PLL_CLOCK / speed;
1726 if (div >= 2) {
1727 hal_cmu_codec_iir_set_div(div);
1728 cfg_speed = HAL_CMU_AUD_PLL_CLOCK / div;
1729 } else {
1730 val |= AON_CMU_BYPASS_DIV_CODECIIR;
1731 cfg_speed = HAL_CMU_AUD_PLL_CLOCK;
1732 }
1733 analog_aud_freq_pll_config(CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV);
1734 analog_aud_pll_open(ANA_AUD_PLL_USER_IIR);
1735 }
1736
1737 //pmu_iir_freq_config(cfg_speed);
1738 }
1739
1740 ASSERT(speed <= cfg_speed, "%s: speed %u should <= cfg_speed %u", __func__, speed, cfg_speed);
1741
1742 lock = int_lock();
1743 aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~mask) | val;
1744 int_unlock(lock);
1745
1746 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECIIR_ENABLE;
1747
1748 aocmu_reg_update_wait();
1749 }
1750
hal_cmu_codec_iir_disable(void)1751 void hal_cmu_codec_iir_disable(void)
1752 {
1753 uint32_t lock;
1754 uint32_t val;
1755 bool high_speed;
1756
1757 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECIIR_DISABLE;
1758
1759 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
1760 hal_cmu_audio_26m_x4_disable(CMU_AUD_26M_X4_USER_IIR);
1761 #endif
1762
1763 high_speed = !(aoncmu->CODEC_IIR & AON_CMU_SEL_CODECIIR_OSC);
1764
1765 val = AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2;
1766
1767 lock = int_lock();
1768 aoncmu->CODEC_IIR |= val;
1769 int_unlock(lock);
1770
1771 if (high_speed) {
1772 //pmu_iir_freq_config(0);
1773 }
1774 analog_aud_pll_close(ANA_AUD_PLL_USER_IIR);
1775 }
1776
hal_cmu_codec_iir_set_div(uint32_t div)1777 int hal_cmu_codec_iir_set_div(uint32_t div)
1778 {
1779 uint32_t lock;
1780
1781 if (div < 2) {
1782 return 1;
1783 }
1784
1785 div -= 2;
1786 lock = int_lock();
1787 aoncmu->CODEC_IIR = SET_BITFIELD(aoncmu->CODEC_IIR, AON_CMU_CFG_DIV_CODECIIR, div);
1788 int_unlock(lock);
1789
1790 return 0;
1791 }
1792
hal_cmu_codec_rs_enable(uint32_t speed)1793 void hal_cmu_codec_rs_enable(uint32_t speed)
1794 {
1795 uint32_t lock;
1796 uint32_t mask;
1797 uint32_t val;
1798 uint32_t div;
1799 uint32_t cfg_speed = 0;
1800
1801 mask = AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2 | AON_CMU_BYPASS_DIV_CODECRS0;
1802 mask |= AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2 | AON_CMU_BYPASS_DIV_CODECRS1;
1803 val = 0;
1804
1805 if (speed <= 26000000) {
1806 val |= AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2;
1807 val |= AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2;
1808 cfg_speed = 26000000;
1809 } else if (speed <= 52000000) {
1810 val |= AON_CMU_SEL_CODECRS0_OSCX2;
1811 val |= AON_CMU_SEL_CODECRS1_OSCX2;
1812 cfg_speed = 52000000;
1813 } else {
1814 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
1815 if (hal_cmu_get_audio_resample_status()) {
1816 hal_cmu_audio_26m_x4_enable(CMU_AUD_26M_X4_USER_RS);
1817 val |= AON_CMU_BYPASS_DIV_CODECRS0;
1818 val |= AON_CMU_BYPASS_DIV_CODECRS1;
1819 cfg_speed = 104000000;
1820 }
1821 else
1822 #endif
1823 {
1824 // Assume audio stream is one of 48K series
1825 div = HAL_CMU_AUD_PLL_CLOCK / speed;
1826 if (div >= 2) {
1827 hal_cmu_codec_rs_set_div(div);
1828 cfg_speed = HAL_CMU_AUD_PLL_CLOCK / div;
1829 } else {
1830 val |= AON_CMU_BYPASS_DIV_CODECRS0;
1831 val |= AON_CMU_BYPASS_DIV_CODECRS1;
1832 cfg_speed = HAL_CMU_AUD_PLL_CLOCK;
1833 }
1834 analog_aud_freq_pll_config(CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV);
1835 analog_aud_pll_open(ANA_AUD_PLL_USER_RS);
1836 }
1837 }
1838
1839 ASSERT(speed <= cfg_speed, "%s: speed %u should <= cfg_speed %u", __func__, speed, cfg_speed);
1840
1841 lock = int_lock();
1842 aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~mask) | val;
1843 int_unlock(lock);
1844
1845 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECRS0_ENABLE | AON_CMU_EN_CLK_CODECRS1_ENABLE;
1846
1847 aocmu_reg_update_wait();
1848 }
1849
hal_cmu_codec_rs_disable(void)1850 void hal_cmu_codec_rs_disable(void)
1851 {
1852 uint32_t lock;
1853 //bool high_speed;
1854
1855 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECRS0_DISABLE | AON_CMU_EN_CLK_CODECRS1_DISABLE;
1856
1857 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
1858 hal_cmu_audio_26m_x4_disable(CMU_AUD_26M_X4_USER_RS);
1859 #endif
1860
1861 lock = int_lock();
1862 aoncmu->CODEC_IIR |= AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2 | AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2;
1863 int_unlock(lock);
1864
1865 analog_aud_pll_close(ANA_AUD_PLL_USER_RS);
1866 }
1867
hal_cmu_codec_rs_set_div(uint32_t div)1868 int hal_cmu_codec_rs_set_div(uint32_t div)
1869 {
1870 uint32_t lock;
1871
1872 if (div < 2) {
1873 return 1;
1874 }
1875
1876 div -= 2;
1877 lock = int_lock();
1878 aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~(AON_CMU_CFG_DIV_CODECRS0_MASK | AON_CMU_CFG_DIV_CODECRS1_MASK)) |
1879 AON_CMU_CFG_DIV_CODECRS0(div) | AON_CMU_CFG_DIV_CODECRS1(div);
1880 int_unlock(lock);
1881
1882 return 0;
1883 }
1884
hal_cmu_codec_clock_enable(void)1885 void hal_cmu_codec_clock_enable(void)
1886 {
1887 uint32_t lock;
1888
1889 lock = int_lock();
1890 aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~(AON_CMU_SEL_CODEC_OSC | AON_CMU_SEL_CODECHCLK_OSCX2 | AON_CMU_SEL_CODEC_ANA_2 | AON_CMU_SEL_CODECHCLK_PLL)) |
1891 AON_CMU_SEL_CODEC_OSC_2;
1892 int_unlock(lock);
1893
1894 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECHCLK_ENABLE | AON_CMU_EN_CLK_CODEC_ENABLE;
1895 hal_cmu_clock_enable(HAL_CMU_MOD_H_CODEC);
1896 }
1897
hal_cmu_codec_clock_disable(void)1898 void hal_cmu_codec_clock_disable(void)
1899 {
1900 hal_cmu_clock_disable(HAL_CMU_MOD_H_CODEC);
1901 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECHCLK_DISABLE | AON_CMU_EN_CLK_CODEC_DISABLE;
1902 }
1903
hal_cmu_codec_vad_clock_enable(int type)1904 void hal_cmu_codec_vad_clock_enable(int type)
1905 {
1906 uint32_t lock;
1907
1908 lock = int_lock();
1909 aoncmu->CODEC_DIV |= (AON_CMU_EN_VAD_IIR | AON_CMU_EN_VAD_RS);
1910 int_unlock(lock);
1911
1912 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSC_ENABLE | AON_CMU_EN_CLK_VAD32K_ENABLE;
1913 if (type == AUD_VAD_TYPE_MIX) {
1914 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_DISABLE;
1915 }
1916 }
1917
hal_cmu_codec_vad_clock_disable(int type)1918 void hal_cmu_codec_vad_clock_disable(int type)
1919 {
1920 uint32_t lock;
1921
1922 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_OSC_DISABLE | AON_CMU_EN_CLK_VAD32K_DISABLE;
1923 if (type == AUD_VAD_TYPE_MIX) {
1924 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODEC_ENABLE;
1925 }
1926
1927 lock = int_lock();
1928 aoncmu->CODEC_DIV &= ~(AON_CMU_EN_VAD_IIR | AON_CMU_EN_VAD_RS);
1929 int_unlock(lock);
1930 }
1931
hal_cmu_codec_reset_set(void)1932 void hal_cmu_codec_reset_set(void)
1933 {
1934 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_CODEC_SET;
1935 }
1936
hal_cmu_codec_reset_clear(void)1937 void hal_cmu_codec_reset_clear(void)
1938 {
1939 hal_cmu_reset_clear(HAL_CMU_MOD_H_CODEC);
1940 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_CODEC_CLR;
1941 aocmu_reg_update_wait();
1942 }
1943
hal_cmu_codec_set_fault_mask(uint32_t msk)1944 void hal_cmu_codec_set_fault_mask(uint32_t msk)
1945 {
1946 uint32_t lock;
1947
1948 lock = int_lock();
1949 // If bit set 1, DAC will be muted when some faults occur
1950 cmu->PERIPH_CLK = SET_BITFIELD(cmu->PERIPH_CLK, CMU_MASK_OBS, msk);
1951 int_unlock(lock);
1952 }
1953
hal_cmu_i2s_clock_out_enable(enum HAL_I2S_ID_T id)1954 void hal_cmu_i2s_clock_out_enable(enum HAL_I2S_ID_T id)
1955 {
1956 uint32_t lock;
1957 uint32_t val;
1958
1959 if (id == HAL_I2S_ID_0) {
1960 val = CMU_EN_CLK_I2S0_OUT;
1961 } else {
1962 val = CMU_EN_CLK_I2S1_OUT;
1963 }
1964
1965 lock = int_lock();
1966 cmu->I2C_CLK |= val;
1967 int_unlock(lock);
1968 }
1969
hal_cmu_i2s_clock_out_disable(enum HAL_I2S_ID_T id)1970 void hal_cmu_i2s_clock_out_disable(enum HAL_I2S_ID_T id)
1971 {
1972 uint32_t lock;
1973 uint32_t val;
1974
1975 if (id == HAL_I2S_ID_0) {
1976 val = CMU_EN_CLK_I2S0_OUT;
1977 } else {
1978 val = CMU_EN_CLK_I2S1_OUT;
1979 }
1980
1981 lock = int_lock();
1982 cmu->I2C_CLK &= ~val;
1983 int_unlock(lock);
1984 }
1985
hal_cmu_i2s_set_slave_mode(enum HAL_I2S_ID_T id)1986 void hal_cmu_i2s_set_slave_mode(enum HAL_I2S_ID_T id)
1987 {
1988 uint32_t lock;
1989 uint32_t val;
1990
1991 if (id == HAL_I2S_ID_0) {
1992 val = CMU_SEL_I2S0_CLKIN;
1993 } else {
1994 val = CMU_SEL_I2S1_CLKIN;
1995 }
1996
1997 lock = int_lock();
1998 cmu->I2C_CLK |= val;
1999 int_unlock(lock);
2000 }
2001
hal_cmu_i2s_set_master_mode(enum HAL_I2S_ID_T id)2002 void hal_cmu_i2s_set_master_mode(enum HAL_I2S_ID_T id)
2003 {
2004 uint32_t lock;
2005 uint32_t val;
2006
2007 if (id == HAL_I2S_ID_0) {
2008 val = CMU_SEL_I2S0_CLKIN;
2009 } else {
2010 val = CMU_SEL_I2S1_CLKIN;
2011 }
2012
2013 lock = int_lock();
2014 cmu->I2C_CLK &= ~val;
2015 int_unlock(lock);
2016 }
2017
hal_cmu_i2s_clock_enable(enum HAL_I2S_ID_T id)2018 void hal_cmu_i2s_clock_enable(enum HAL_I2S_ID_T id)
2019 {
2020 uint32_t lock;
2021 uint32_t val;
2022 volatile uint32_t *reg;
2023
2024 if (id == HAL_I2S_ID_0) {
2025 val = AON_CMU_EN_CLK_PLL_I2S0;
2026 reg = &aoncmu->PCM_I2S_CLK;
2027 } else {
2028 val = AON_CMU_EN_CLK_PLL_I2S1;
2029 reg = &aoncmu->SPDIF_CLK;
2030 }
2031
2032 lock = int_lock();
2033 *reg |= val;
2034 int_unlock(lock);
2035 }
2036
hal_cmu_i2s_clock_disable(enum HAL_I2S_ID_T id)2037 void hal_cmu_i2s_clock_disable(enum HAL_I2S_ID_T id)
2038 {
2039 uint32_t lock;
2040 uint32_t val;
2041 volatile uint32_t *reg;
2042
2043 if (id == HAL_I2S_ID_0) {
2044 val = AON_CMU_EN_CLK_PLL_I2S0;
2045 reg = &aoncmu->PCM_I2S_CLK;
2046 } else {
2047 val = AON_CMU_EN_CLK_PLL_I2S1;
2048 reg = &aoncmu->SPDIF_CLK;
2049 }
2050
2051 lock = int_lock();
2052 *reg &= ~val;
2053 int_unlock(lock);
2054 }
2055
hal_cmu_i2s_set_div(enum HAL_I2S_ID_T id,uint32_t div)2056 int hal_cmu_i2s_set_div(enum HAL_I2S_ID_T id, uint32_t div)
2057 {
2058 uint32_t lock;
2059
2060 if (div < 2) {
2061 return 1;
2062 }
2063
2064 div -= 2;
2065 if ((div & (AON_CMU_CFG_DIV_I2S0_MASK >> AON_CMU_CFG_DIV_I2S0_SHIFT)) != div) {
2066 return 1;
2067 }
2068
2069 lock = int_lock();
2070 if (id == HAL_I2S_ID_0) {
2071 aoncmu->PCM_I2S_CLK = SET_BITFIELD(aoncmu->PCM_I2S_CLK, AON_CMU_CFG_DIV_I2S0, div);
2072 } else {
2073 aoncmu->SPDIF_CLK = SET_BITFIELD(aoncmu->SPDIF_CLK, AON_CMU_CFG_DIV_I2S1, div);
2074 }
2075 int_unlock(lock);
2076
2077 return 0;
2078 }
2079
hal_cmu_pcm_clock_out_enable(void)2080 void hal_cmu_pcm_clock_out_enable(void)
2081 {
2082 uint32_t lock;
2083
2084 lock = int_lock();
2085 cmu->I2C_CLK |= CMU_EN_CLK_PCM_OUT;
2086 int_unlock(lock);
2087 }
2088
hal_cmu_pcm_clock_out_disable(void)2089 void hal_cmu_pcm_clock_out_disable(void)
2090 {
2091 uint32_t lock;
2092
2093 lock = int_lock();
2094 cmu->I2C_CLK &= ~CMU_EN_CLK_PCM_OUT;
2095 int_unlock(lock);
2096 }
2097
hal_cmu_pcm_set_slave_mode(int clk_pol)2098 void hal_cmu_pcm_set_slave_mode(int clk_pol)
2099 {
2100 uint32_t lock;
2101 uint32_t mask;
2102 uint32_t cfg;
2103
2104 mask = CMU_SEL_PCM_CLKIN | CMU_POL_CLK_PCM_IN;
2105
2106 if (clk_pol) {
2107 cfg = CMU_SEL_PCM_CLKIN | CMU_POL_CLK_PCM_IN;
2108 } else {
2109 cfg = CMU_SEL_PCM_CLKIN;
2110 }
2111
2112 lock = int_lock();
2113 cmu->I2C_CLK = (cmu->I2C_CLK & ~mask) | cfg;
2114 int_unlock(lock);
2115 }
2116
hal_cmu_pcm_set_master_mode(void)2117 void hal_cmu_pcm_set_master_mode(void)
2118 {
2119 uint32_t lock;
2120
2121 lock = int_lock();
2122 cmu->I2C_CLK &= ~CMU_SEL_PCM_CLKIN;
2123 int_unlock(lock);
2124 }
2125
hal_cmu_pcm_clock_enable(void)2126 void hal_cmu_pcm_clock_enable(void)
2127 {
2128 uint32_t lock;
2129
2130 lock = int_lock();
2131 aoncmu->PCM_I2S_CLK |= AON_CMU_EN_CLK_PLL_PCM;
2132 int_unlock(lock);
2133 }
2134
hal_cmu_pcm_clock_disable(void)2135 void hal_cmu_pcm_clock_disable(void)
2136 {
2137 uint32_t lock;
2138
2139 lock = int_lock();
2140 aoncmu->PCM_I2S_CLK &= ~AON_CMU_EN_CLK_PLL_PCM;
2141 int_unlock(lock);
2142 }
2143
hal_cmu_pcm_set_div(uint32_t div)2144 int hal_cmu_pcm_set_div(uint32_t div)
2145 {
2146 uint32_t lock;
2147
2148 if (div < 2) {
2149 return 1;
2150 }
2151
2152 div -= 2;
2153 if ((div & (AON_CMU_CFG_DIV_PCM_MASK >> AON_CMU_CFG_DIV_PCM_SHIFT)) != div) {
2154 return 1;
2155 }
2156
2157 lock = int_lock();
2158 aoncmu->PCM_I2S_CLK = SET_BITFIELD(aoncmu->PCM_I2S_CLK, AON_CMU_CFG_DIV_PCM, div);
2159 int_unlock(lock);
2160 return 0;
2161 }
2162
hal_cmu_spdif_clock_enable(enum HAL_SPDIF_ID_T id)2163 int hal_cmu_spdif_clock_enable(enum HAL_SPDIF_ID_T id)
2164 {
2165 uint32_t lock;
2166 uint32_t mask;
2167
2168 if (id >= HAL_SPDIF_ID_QTY) {
2169 return 1;
2170 }
2171
2172 mask = AON_CMU_EN_CLK_PLL_SPDIF0;
2173
2174 lock = int_lock();
2175 aoncmu->SPDIF_CLK |= mask;
2176 int_unlock(lock);
2177 return 0;
2178 }
2179
hal_cmu_spdif_clock_disable(enum HAL_SPDIF_ID_T id)2180 int hal_cmu_spdif_clock_disable(enum HAL_SPDIF_ID_T id)
2181 {
2182 uint32_t lock;
2183 uint32_t mask;
2184
2185 if (id >= HAL_SPDIF_ID_QTY) {
2186 return 1;
2187 }
2188
2189 mask = AON_CMU_EN_CLK_PLL_SPDIF0;
2190
2191 lock = int_lock();
2192 aoncmu->SPDIF_CLK &= ~mask;
2193 int_unlock(lock);
2194
2195 return 0;
2196 }
2197
hal_cmu_spdif_set_div(enum HAL_SPDIF_ID_T id,uint32_t div)2198 int hal_cmu_spdif_set_div(enum HAL_SPDIF_ID_T id, uint32_t div)
2199 {
2200 uint32_t lock;
2201
2202 if (id >= HAL_SPDIF_ID_QTY) {
2203 return 1;
2204 }
2205
2206 if (div < 2) {
2207 return 2;
2208 }
2209
2210 div -= 2;
2211 if ((div & (AON_CMU_CFG_DIV_SPDIF0_MASK >> AON_CMU_CFG_DIV_SPDIF0_SHIFT)) != div) {
2212 return 2;
2213 }
2214
2215 lock = int_lock();
2216 aoncmu->SPDIF_CLK = SET_BITFIELD(aoncmu->SPDIF_CLK, AON_CMU_CFG_DIV_SPDIF0, div);
2217 int_unlock(lock);
2218 return 0;
2219 }
2220
2221 #ifdef CHIP_HAS_USB
hal_cmu_usb_set_device_mode(void)2222 void hal_cmu_usb_set_device_mode(void)
2223 {
2224 uint32_t lock;
2225
2226 lock = int_lock();
2227 cmu->SYS_DIV |= CMU_USB_ID;
2228 int_unlock(lock);
2229 }
2230
hal_cmu_usb_set_host_mode(void)2231 void hal_cmu_usb_set_host_mode(void)
2232 {
2233 uint32_t lock;
2234
2235 lock = int_lock();
2236 cmu->SYS_DIV &= ~CMU_USB_ID;
2237 int_unlock(lock);
2238 }
2239
2240 #ifdef ROM_BUILD
hal_cmu_usb_rom_select_clock_source(int pll_en,unsigned int crystal)2241 enum HAL_CMU_USB_CLOCK_SEL_T hal_cmu_usb_rom_select_clock_source(int pll_en, unsigned int crystal)
2242 {
2243 enum HAL_CMU_USB_CLOCK_SEL_T sel;
2244
2245 if (crystal == 24000000) {
2246 sel = HAL_CMU_USB_CLOCK_SEL_24M_X2;
2247 } else {
2248 sel = HAL_CMU_USB_CLOCK_SEL_PLL;
2249 }
2250
2251 hal_cmu_usb_rom_set_clock_source(sel);
2252
2253 return sel;
2254 }
hal_cmu_usb_rom_set_clock_source(enum HAL_CMU_USB_CLOCK_SEL_T sel)2255 void hal_cmu_usb_rom_set_clock_source(enum HAL_CMU_USB_CLOCK_SEL_T sel)
2256 {
2257 }
2258 #endif
2259
hal_cmu_usb_get_clock_source(void)2260 static uint32_t hal_cmu_usb_get_clock_source(void)
2261 {
2262 uint32_t src;
2263
2264 #ifdef USB_HIGH_SPEED
2265 src = CMU_USB_CLK_SRC_PLL_60M;
2266 #else
2267 #ifndef USB_USE_USBPLL
2268 if (hal_cmu_get_crystal_freq() == 24000000)
2269 src = CMU_USB_CLK_SRC_OSC_24M_X2;
2270 else
2271 #endif
2272 src = CMU_USB_CLK_SRC_PLL_48M;
2273 #endif
2274
2275 return src;
2276 }
2277
hal_cmu_usb_clock_enable(void)2278 void hal_cmu_usb_clock_enable(void)
2279 {
2280 enum HAL_CMU_PLL_T pll;
2281 uint32_t lock;
2282 uint32_t src;
2283 POSSIBLY_UNUSED uint32_t div;
2284
2285 #if !defined(USB_HIGH_SPEED) && defined(USB_USE_USBPLL)
2286 pll = HAL_CMU_PLL_USB;
2287 #else
2288 pll = HAL_CMU_PLL_BB;
2289 #endif
2290 src = hal_cmu_usb_get_clock_source();
2291 if (src != CMU_USB_CLK_SRC_OSC_24M_X2)
2292 hal_cmu_pll_enable(pll, HAL_CMU_PLL_USER_USB);
2293
2294 lock = int_lock();
2295 #ifdef USB_HIGH_SPEED
2296 cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_SEL_USB_SRC, 1);
2297 #else
2298 cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_SEL_USB_SRC, 0);
2299 if (src == CMU_USB_CLK_SRC_OSC_24M_X2) {
2300 aoncmu->CLK_SELECT |= AON_CMU_SEL_USB_OSCX2;
2301 } else {
2302 #ifdef USB_USE_USBPLL
2303 aoncmu->CLK_SELECT |= AON_CMU_SEL_USB_PLLUSB;
2304 // DSI PSRAMPLL to dig: ?
2305 div = 8;///TODO:
2306 #else // USB usb BBPLL
2307 aoncmu->CLK_SELECT &= ~AON_CMU_SEL_USB_PLLUSB;
2308 // BBPLL to dig: 384M
2309 div = 8;
2310 #endif
2311 aoncmu->CLK_SELECT = SET_BITFIELD(aoncmu->CLK_SELECT, AON_CMU_CFG_DIV_USB, div-2);
2312 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_USB_PLL_ENABLE;
2313 }
2314 #endif /*USB_HIGH_SPEED*/
2315 int_unlock(lock);
2316 hal_cmu_clock_enable(HAL_CMU_MOD_H_USBC);
2317 #ifdef USB_HIGH_SPEED
2318 hal_cmu_clock_enable(HAL_CMU_MOD_H_USBH);
2319 #endif
2320 hal_cmu_clock_enable(HAL_CMU_MOD_O_USB32K);
2321 hal_cmu_clock_enable(HAL_CMU_MOD_O_USB);
2322 hal_cmu_reset_set(HAL_CMU_MOD_O_USB);
2323 hal_cmu_reset_set(HAL_CMU_MOD_O_USB32K);
2324 #ifdef USB_HIGH_SPEED
2325 hal_cmu_reset_set(HAL_CMU_MOD_H_USBH);
2326 #endif
2327 hal_cmu_reset_set(HAL_CMU_MOD_H_USBC);
2328 hal_sys_timer_delay(US_TO_TICKS(60));
2329 hal_cmu_reset_clear(HAL_CMU_MOD_H_USBC);
2330 #ifdef USB_HIGH_SPEED
2331 hal_cmu_reset_clear(HAL_CMU_MOD_H_USBH);
2332 #endif
2333 hal_cmu_reset_clear(HAL_CMU_MOD_O_USB32K);
2334 hal_cmu_reset_clear(HAL_CMU_MOD_O_USB);
2335 }
2336
hal_cmu_usb_clock_disable(void)2337 void hal_cmu_usb_clock_disable(void)
2338 {
2339 enum HAL_CMU_PLL_T pll;
2340
2341 #if !defined(USB_HIGH_SPEED) && defined(USB_USE_USBPLL)
2342 pll = HAL_CMU_PLL_USB;
2343 #else
2344 pll = HAL_CMU_PLL_BB;
2345 #endif
2346
2347 hal_cmu_reset_set(HAL_CMU_MOD_O_USB);
2348 hal_cmu_reset_set(HAL_CMU_MOD_O_USB32K);
2349 #ifdef USB_HIGH_SPEED
2350 hal_cmu_reset_set(HAL_CMU_MOD_H_USBH);
2351 #endif
2352 hal_cmu_reset_set(HAL_CMU_MOD_H_USBC);
2353 hal_cmu_clock_disable(HAL_CMU_MOD_O_USB);
2354 hal_cmu_clock_disable(HAL_CMU_MOD_O_USB32K);
2355 #ifdef USB_HIGH_SPEED
2356 hal_cmu_clock_disable(HAL_CMU_MOD_H_USBH);
2357 #endif
2358 hal_cmu_clock_disable(HAL_CMU_MOD_H_USBC);
2359 #ifndef USB_HIGH_SPEED
2360 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_USB_PLL_DISABLE;
2361 #endif
2362
2363 if (hal_cmu_usb_get_clock_source() != CMU_USB_CLK_SRC_OSC_24M_X2)
2364 hal_cmu_pll_disable(pll, HAL_CMU_PLL_USER_USB);
2365 }
2366 #endif
2367
hal_cmu_apb_init_div(void)2368 void BOOT_TEXT_FLASH_LOC hal_cmu_apb_init_div(void)
2369 {
2370 // Divider defaults to 2 (div = reg_val + 2)
2371 //cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_PCLK, 0);
2372 }
2373
hal_cmu_periph_set_div(uint32_t div)2374 int hal_cmu_periph_set_div(uint32_t div)
2375 {
2376 uint32_t lock;
2377 int ret = 0;
2378
2379 if (div == 0 || div > ((AON_CMU_CFG_DIV_PER_MASK >> AON_CMU_CFG_DIV_PER_SHIFT) + 2)) {
2380 ret = 1;
2381 } else {
2382 lock = int_lock();
2383 if (div == 1) {
2384 aoncmu->CLK_SELECT |= AON_CMU_BYPASS_DIV_PER;
2385 } else {
2386 div -= 2;
2387 aoncmu->CLK_SELECT = (aoncmu->CLK_SELECT & ~(AON_CMU_CFG_DIV_PER_MASK | AON_CMU_BYPASS_DIV_PER)) |
2388 AON_CMU_CFG_DIV_PER(div);
2389 }
2390 int_unlock(lock);
2391 }
2392
2393 return ret;
2394 }
2395
2396 #define PERPH_SET_DIV_FUNC(f, F, r) \
2397 int hal_cmu_ ##f## _set_div(uint32_t div) \
2398 { \
2399 uint32_t lock; \
2400 int ret = 0; \
2401 lock = int_lock(); \
2402 if (div < 2 || div > ((CMU_CFG_DIV_ ##F## _MASK >> CMU_CFG_DIV_ ##F## _SHIFT) + 2)) { \
2403 cmu->r &= ~(CMU_SEL_OSCX2_ ##F | CMU_SEL_PLL_ ##F | CMU_EN_PLL_ ##F); \
2404 ret = 1; \
2405 } else { \
2406 div -= 2; \
2407 cmu->r = (cmu->r & ~(CMU_CFG_DIV_ ##F## _MASK)) | CMU_SEL_OSCX2_ ##F | CMU_SEL_PLL_ ##F | \
2408 CMU_CFG_DIV_ ##F(div); \
2409 cmu->r |= CMU_EN_PLL_ ##F; \
2410 } \
2411 int_unlock(lock); \
2412 return ret; \
2413 }
2414
2415 PERPH_SET_DIV_FUNC(uart0, UART0, UART_CLK);
2416 PERPH_SET_DIV_FUNC(uart1, UART1, UART_CLK);
2417 PERPH_SET_DIV_FUNC(uart2, UART2, UART_CLK);
2418 PERPH_SET_DIV_FUNC(uart3, UART3, UART_CLK);
2419 PERPH_SET_DIV_FUNC(spi, SPI0, SYS_DIV);
2420 PERPH_SET_DIV_FUNC(slcd, SPI1, SYS_DIV);
2421 PERPH_SET_DIV_FUNC(sdmmc, SDMMC, PERIPH_CLK);
2422 PERPH_SET_DIV_FUNC(i2c, I2C, I2C_CLK);
2423
2424 #define PERPH_SET_FREQ_FUNC(f, F, r) \
2425 int hal_cmu_ ##f## _set_freq(enum HAL_CMU_PERIPH_FREQ_T freq) \
2426 { \
2427 uint32_t lock; \
2428 int ret = 0; \
2429 lock = int_lock(); \
2430 if (freq == HAL_CMU_PERIPH_FREQ_26M) { \
2431 cmu->r &= ~(CMU_SEL_OSCX2_ ##F | CMU_SEL_PLL_ ##F | CMU_EN_PLL_ ##F); \
2432 } else if (freq == HAL_CMU_PERIPH_FREQ_52M) { \
2433 cmu->r = (cmu->r & ~(CMU_SEL_PLL_ ##F | CMU_EN_PLL_ ##F)) | CMU_SEL_OSCX2_ ##F; \
2434 } else { \
2435 ret = 1; \
2436 } \
2437 int_unlock(lock); \
2438 return ret; \
2439 }
2440
2441 PERPH_SET_FREQ_FUNC(uart0, UART0, UART_CLK);
2442 PERPH_SET_FREQ_FUNC(uart1, UART1, UART_CLK);
2443 PERPH_SET_FREQ_FUNC(uart2, UART2, UART_CLK);
2444 PERPH_SET_FREQ_FUNC(uart3, UART3, UART_CLK);
2445 PERPH_SET_FREQ_FUNC(spi, SPI0, SYS_DIV);
2446 PERPH_SET_FREQ_FUNC(slcd, SPI1, SYS_DIV);
2447 PERPH_SET_FREQ_FUNC(sdmmc, SDMMC, PERIPH_CLK);
2448 PERPH_SET_FREQ_FUNC(i2c, I2C, I2C_CLK);
2449
hal_cmu_ispi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq)2450 int hal_cmu_ispi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq)
2451 {
2452 uint32_t lock;
2453 int ret = 0;
2454
2455 lock = int_lock();
2456 if (freq == HAL_CMU_PERIPH_FREQ_26M) {
2457 cmu->SYS_DIV &= ~CMU_SEL_OSCX2_SPI2;
2458 } else if (freq == HAL_CMU_PERIPH_FREQ_52M) {
2459 cmu->SYS_DIV |= CMU_SEL_OSCX2_SPI2;
2460 } else {
2461 ret = 1;
2462 }
2463 int_unlock(lock);
2464
2465 return ret;
2466 }
2467
hal_cmu_sec_eng_clock_enable(void)2468 void hal_cmu_sec_eng_clock_enable(void)
2469 {
2470 hal_cmu_clock_enable(HAL_CMU_MOD_H_SEC_ENG);
2471 hal_cmu_clock_enable(HAL_CMU_MOD_P_SEC_ENG);
2472 hal_cmu_reset_clear(HAL_CMU_MOD_H_SEC_ENG);
2473 hal_cmu_reset_clear(HAL_CMU_MOD_P_SEC_ENG);
2474 }
2475
hal_cmu_sec_eng_clock_disable(void)2476 void hal_cmu_sec_eng_clock_disable(void)
2477 {
2478 hal_cmu_reset_set(HAL_CMU_MOD_H_SEC_ENG);
2479 hal_cmu_reset_set(HAL_CMU_MOD_P_SEC_ENG);
2480 hal_cmu_clock_disable(HAL_CMU_MOD_H_SEC_ENG);
2481 hal_cmu_clock_disable(HAL_CMU_MOD_P_SEC_ENG);
2482 }
2483
hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id)2484 int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id)
2485 {
2486 uint32_t lock;
2487 uint32_t sel;
2488 uint32_t cfg;
2489
2490 enum CMU_CLK_OUT_SEL_T {
2491 CMU_CLK_OUT_SEL_AON = 0,
2492 CMU_CLK_OUT_SEL_CODEC = 1,
2493 CMU_CLK_OUT_SEL_BT = 2,
2494 CMU_CLK_OUT_SEL_MCU = 3,
2495 CMU_CLK_OUT_SEL_WF = 4,
2496
2497 CMU_CLK_OUT_SEL_QTY
2498 };
2499
2500 sel = CMU_CLK_OUT_SEL_QTY;
2501 cfg = 0;
2502
2503 if (id <= HAL_CMU_CLOCK_OUT_AON_SYS) {
2504 sel = CMU_CLK_OUT_SEL_AON;
2505 cfg = id - HAL_CMU_CLOCK_OUT_AON_32K;
2506 } else if (HAL_CMU_CLOCK_OUT_MCU_32K <= id && id <= HAL_CMU_CLOCK_OUT_MCU_I2S1) {
2507 sel = CMU_CLK_OUT_SEL_MCU;
2508 lock = int_lock();
2509 cmu->PERIPH_CLK = SET_BITFIELD(cmu->PERIPH_CLK, CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_MCU_32K);
2510 int_unlock(lock);
2511 } else if (HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA <= id && id <= HAL_CMU_CLOCK_OUT_CODEC_HCLK) {
2512 sel = CMU_CLK_OUT_SEL_CODEC;
2513 hal_codec_select_clock_out(id - HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA);
2514 } else if (HAL_CMU_CLOCK_OUT_BT_NONE <= id && id <= HAL_CMU_CLOCK_OUT_BT_DACD8) {
2515 sel = CMU_CLK_OUT_SEL_BT;
2516 btcmu->CLK_OUT = SET_BITFIELD(btcmu->CLK_OUT, BT_CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_BT_NONE);
2517 } else if (HAL_CMU_CLOCK_OUT_WF_32K <= id && id <= HAL_CMU_CLOCK_OUT_WF_BBDIGFIFO) {
2518 sel = CMU_CLK_OUT_SEL_WF;
2519 wlancmu->CLK_OUT = SET_BITFIELD(wlancmu->CLK_OUT, WLAN_CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_WF_32K);
2520 }
2521
2522 if (sel < CMU_CLK_OUT_SEL_QTY) {
2523 lock = int_lock();
2524 aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~(AON_CMU_SEL_CLK_OUT_MASK | AON_CMU_CFG_CLK_OUT_MASK)) |
2525 AON_CMU_SEL_CLK_OUT(sel) | AON_CMU_CFG_CLK_OUT(cfg) | AON_CMU_EN_CLK_OUT;
2526 int_unlock(lock);
2527
2528 return 0;
2529 }
2530
2531 return 1;
2532 }
2533
hal_cmu_clock_out_disable(void)2534 void hal_cmu_clock_out_disable(void)
2535 {
2536 uint32_t lock;
2537
2538 lock = int_lock();
2539 aoncmu->CLK_OUT &= ~AON_CMU_EN_CLK_OUT;
2540 int_unlock(lock);
2541 }
2542
hal_cmu_i2s_mclk_enable(enum HAL_CMU_I2S_MCLK_ID_T id)2543 int hal_cmu_i2s_mclk_enable(enum HAL_CMU_I2S_MCLK_ID_T id)
2544 {
2545 uint32_t lock;
2546
2547 lock = int_lock();
2548 aoncmu->CODEC_DIV = SET_BITFIELD(aoncmu->CODEC_DIV, AON_CMU_SEL_I2S_MCLK, id) | AON_CMU_EN_I2S_MCLK;
2549 int_unlock(lock);
2550
2551 return 0;
2552 }
2553
hal_cmu_i2s_mclk_disable(void)2554 void hal_cmu_i2s_mclk_disable(void)
2555 {
2556 uint32_t lock;
2557
2558 lock = int_lock();
2559 aoncmu->CODEC_DIV &= ~AON_CMU_EN_I2S_MCLK;
2560 int_unlock(lock);
2561 }
2562
hal_cmu_pwm_set_freq(enum HAL_PWM_ID_T id,uint32_t freq)2563 int hal_cmu_pwm_set_freq(enum HAL_PWM_ID_T id, uint32_t freq)
2564 {
2565 uint32_t lock;
2566 int clk_32k;
2567 uint32_t div;
2568
2569 if (id >= HAL_PWM_ID_QTY) {
2570 return 1;
2571 }
2572
2573 if (freq == 0) {
2574 clk_32k = 1;
2575 div = 0;
2576 } else {
2577 clk_32k = 0;
2578 div = hal_cmu_get_crystal_freq() / freq;
2579 if (div < 2) {
2580 return -1;
2581 }
2582
2583 div -= 2;
2584 if ((div & (AON_CMU_CFG_DIV_PWM0_MASK >> AON_CMU_CFG_DIV_PWM0_SHIFT)) != div) {
2585 return -2;
2586 }
2587 }
2588
2589 lock = int_lock();
2590 if (id == HAL_PWM_ID_0) {
2591 aoncmu->PWM01_CLK = (aoncmu->PWM01_CLK & ~(AON_CMU_CFG_DIV_PWM0_MASK | AON_CMU_SEL_PWM0_OSC | AON_CMU_EN_CLK_PWM0_OSC)) |
2592 AON_CMU_CFG_DIV_PWM0(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM0_OSC | AON_CMU_EN_CLK_PWM0_OSC));
2593 } else if (id == HAL_PWM_ID_1) {
2594 aoncmu->PWM01_CLK = (aoncmu->PWM01_CLK & ~(AON_CMU_CFG_DIV_PWM1_MASK | AON_CMU_SEL_PWM1_OSC | AON_CMU_EN_CLK_PWM1_OSC)) |
2595 AON_CMU_CFG_DIV_PWM1(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM1_OSC | AON_CMU_EN_CLK_PWM1_OSC));
2596 } else if (id == HAL_PWM_ID_2) {
2597 aoncmu->PWM23_CLK = (aoncmu->PWM23_CLK & ~(AON_CMU_CFG_DIV_PWM2_MASK | AON_CMU_SEL_PWM2_OSC | AON_CMU_EN_CLK_PWM2_OSC)) |
2598 AON_CMU_CFG_DIV_PWM2(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM2_OSC | AON_CMU_EN_CLK_PWM2_OSC));
2599 } else if (id == HAL_PWM_ID_3) {
2600 aoncmu->PWM23_CLK = (aoncmu->PWM23_CLK & ~(AON_CMU_CFG_DIV_PWM3_MASK | AON_CMU_SEL_PWM3_OSC | AON_CMU_EN_CLK_PWM3_OSC)) |
2601 AON_CMU_CFG_DIV_PWM3(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM3_OSC | AON_CMU_EN_CLK_PWM3_OSC));
2602 } else if (id == HAL_PWM1_ID_0) {
2603 aoncmu->PWM45_CLK = (aoncmu->PWM45_CLK & ~(AON_CMU_CFG_DIV_PWM4_MASK | AON_CMU_SEL_PWM4_OSC | AON_CMU_EN_CLK_PWM4_OSC)) |
2604 AON_CMU_CFG_DIV_PWM4(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM4_OSC | AON_CMU_EN_CLK_PWM4_OSC));
2605 } else if (id == HAL_PWM1_ID_1) {
2606 aoncmu->PWM45_CLK = (aoncmu->PWM45_CLK & ~(AON_CMU_CFG_DIV_PWM5_MASK | AON_CMU_SEL_PWM5_OSC | AON_CMU_EN_CLK_PWM5_OSC)) |
2607 AON_CMU_CFG_DIV_PWM5(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM5_OSC | AON_CMU_EN_CLK_PWM5_OSC));
2608 } else if (id == HAL_PWM1_ID_2) {
2609 aoncmu->PWM67_CLK = (aoncmu->PWM67_CLK & ~(AON_CMU_CFG_DIV_PWM6_MASK | AON_CMU_SEL_PWM6_OSC | AON_CMU_EN_CLK_PWM6_OSC)) |
2610 AON_CMU_CFG_DIV_PWM6(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM6_OSC | AON_CMU_EN_CLK_PWM6_OSC));
2611 } else if (id == HAL_PWM1_ID_3) {
2612 aoncmu->PWM67_CLK = (aoncmu->PWM67_CLK & ~(AON_CMU_CFG_DIV_PWM7_MASK | AON_CMU_SEL_PWM7_OSC | AON_CMU_EN_CLK_PWM7_OSC)) |
2613 AON_CMU_CFG_DIV_PWM7(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM7_OSC | AON_CMU_EN_CLK_PWM7_OSC));
2614 } else {
2615 ASSERT(0,"PWM id error!");
2616 }
2617 int_unlock(lock);
2618 return 0;
2619 }
2620
hal_cmu_jtag_enable(void)2621 void hal_cmu_jtag_enable(void)
2622 {
2623 uint32_t lock;
2624
2625 lock = int_lock();
2626 cmu->MCU_TIMER &= ~(CMU_SECURE_BOOT_JTAG | CMU_SECURE_BOOT_I2C);
2627 int_unlock(lock);
2628 }
2629
hal_cmu_jtag_disable(void)2630 void hal_cmu_jtag_disable(void)
2631 {
2632 uint32_t lock;
2633
2634 lock = int_lock();
2635 cmu->MCU_TIMER |= (CMU_SECURE_BOOT_JTAG | CMU_SECURE_BOOT_I2C);
2636 int_unlock(lock);
2637 }
2638
hal_cmu_jtag_clock_enable(void)2639 void hal_cmu_jtag_clock_enable(void)
2640 {
2641 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_JTAG_ENABLE;
2642 }
2643
hal_cmu_jtag_clock_disable(void)2644 void hal_cmu_jtag_clock_disable(void)
2645 {
2646 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_JTAG_DISABLE;
2647 }
2648
hal_cmu_jtag_set_cp(void)2649 void hal_cmu_jtag_set_cp(void)
2650 {
2651 cmu->PERIPH_CLK |= CMU_JTAG_SEL_CP;
2652 }
2653
hal_cmu_jtag_set_a7(void)2654 void hal_cmu_jtag_set_a7(void)
2655 {
2656 cmu->PERIPH_CLK |= CMU_JTAG_SEL_A7;
2657 }
2658
hal_cmu_rom_clock_init(void)2659 void hal_cmu_rom_clock_init(void)
2660 {
2661 aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~AON_CMU_SEL_AON_OSCX2) | AON_CMU_SEL_AON_OSC;
2662 // Enable PMU fast clock
2663 //aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~AON_CMU_SEL_DCDC_PLL) | AON_CMU_SEL_DCDC_OSC | AON_CMU_BYPASS_DIV_DCDC | AON_CMU_EN_CLK_DCDC0;
2664
2665 hal_cmu_dma_req_init();
2666
2667 // Debug Select CMU REG F4
2668 cmu->MCU_TIMER = SET_BITFIELD(cmu->MCU_TIMER, CMU_DEBUG_REG_SEL, CMU_DEBUG_REG_SEL_DEBUG);
2669 }
2670
hal_cmu_init_chip_feature(uint16_t feature)2671 void hal_cmu_init_chip_feature(uint16_t feature)
2672 {
2673 aoncmu->CHIP_FEATURE = feature | AON_CMU_EFUSE_LOCK;
2674 }
2675
hal_cmu_osc_x2_enable(void)2676 void BOOT_TEXT_FLASH_LOC hal_cmu_osc_x2_enable(void)
2677 {
2678 // Debug Select CMU REG F4
2679 cmu->MCU_TIMER = SET_BITFIELD(cmu->MCU_TIMER, CMU_DEBUG_REG_SEL, CMU_DEBUG_REG_SEL_DEBUG);
2680 // Power on OSCX2
2681 aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX2_ENABLE;
2682 // Disable DIG OSCX2
2683 aoncmu->CLK_SELECT &= ~AON_CMU_SEL_OSCX2_DIG;
2684 // Enable OSCX2
2685 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX2_ENABLE | AON_CMU_EN_CLK_MCU_OSCX2_ENABLE;
2686 }
2687
hal_cmu_osc_x4_enable(void)2688 void BOOT_TEXT_FLASH_LOC hal_cmu_osc_x4_enable(void)
2689 {
2690 #ifdef ANA_26M_X4_ENABLE
2691 // Power on OSCX4
2692 aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX4_ENABLE;
2693 // Disable DIG OSCX4
2694 aoncmu->CLK_SELECT &= ~AON_CMU_SEL_OSCX4_DIG;
2695 // Enable OSCX4
2696 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX4_ENABLE;
2697 #endif
2698 }
2699
2700 struct CMU_DMA_PER_2_REQ_T {
2701 enum HAL_DMA_PERIPH_T periph;
2702 enum CMU_DMA_REQ_T req;
2703 };
2704 const static BOOT_RODATA_FLASH_LOC struct CMU_DMA_PER_2_REQ_T periph_map[] = {
2705 {HAL_DMA_PERIPH_NULL, CMU_DMA_REQ_NULL},
2706 {HAL_AUDMA_CODEC_RX, CMU_DMA_REQ_CODEC_RX},
2707 {HAL_AUDMA_CODEC_TX, CMU_DMA_REQ_CODEC_TX},
2708 {HAL_AUDMA_DSD_RX, CMU_DMA_REQ_DSD_RX},
2709 {HAL_AUDMA_DSD_TX, CMU_DMA_REQ_DSD_TX},
2710 {HAL_GPDMA_IR_RX, CMU_DMA_REQ_IR_RX},
2711 {HAL_GPDMA_IR_TX, CMU_DMA_REQ_IR_TX},
2712 {HAL_GPDMA_FLASH1, CMU_DMA_REQ_FLS1},
2713 {HAL_GPDMA_FLASH0, CMU_DMA_REQ_FLS0},
2714 {HAL_AUDMA_BTDUMP, CMU_DMA_REQ_BTDUMP},
2715 {HAL_GPDMA_SDMMC, CMU_DMA_REQ_SDEMMC},
2716 {HAL_GPDMA_I2C0_RX, CMU_DMA_REQ_I2C0_RX},
2717 {HAL_GPDMA_I2C0_TX, CMU_DMA_REQ_I2C0_TX},
2718 {HAL_GPDMA_I2C1_RX, CMU_DMA_REQ_I2C1_RX},
2719 {HAL_GPDMA_I2C1_TX, CMU_DMA_REQ_I2C1_TX},
2720 {HAL_GPDMA_I2C2_RX, CMU_DMA_REQ_I2C2_RX},
2721 {HAL_GPDMA_I2C2_TX, CMU_DMA_REQ_I2C2_TX},
2722 {HAL_GPDMA_SPI_RX, CMU_DMA_REQ_SPILCD0_RX},
2723 {HAL_GPDMA_SPI_TX, CMU_DMA_REQ_SPILCD0_TX},
2724 {HAL_GPDMA_SPILCD_RX, CMU_DMA_REQ_SPILCD1_RX},
2725 {HAL_GPDMA_SPILCD_TX, CMU_DMA_REQ_SPILCD1_TX},
2726 {HAL_GPDMA_ISPI_RX, CMU_DMA_REQ_SPI_ITN_RX},
2727 {HAL_GPDMA_ISPI_TX, CMU_DMA_REQ_SPI_ITN_TX},
2728 {HAL_GPDMA_UART0_RX, CMU_DMA_REQ_UART0_RX},
2729 {HAL_GPDMA_UART0_TX, CMU_DMA_REQ_UART0_TX},
2730 {HAL_GPDMA_UART1_RX, CMU_DMA_REQ_UART1_RX},
2731 {HAL_GPDMA_UART1_TX, CMU_DMA_REQ_UART1_TX},
2732 {HAL_GPDMA_UART2_RX, CMU_DMA_REQ_UART2_RX},
2733 {HAL_GPDMA_UART2_TX, CMU_DMA_REQ_UART2_TX},
2734 {HAL_GPDMA_UART3_RX, CMU_DMA_REQ_UART3_RX},
2735 {HAL_GPDMA_UART3_TX, CMU_DMA_REQ_UART3_TX},
2736 {HAL_AUDMA_BTPCM_RX, CMU_DMA_REQ_PCM_RX},
2737 {HAL_AUDMA_BTPCM_TX, CMU_DMA_REQ_PCM_TX},
2738 {HAL_AUDMA_I2S0_RX, CMU_DMA_REQ_I2S0_RX},
2739 {HAL_AUDMA_I2S0_TX, CMU_DMA_REQ_I2S0_TX},
2740 {HAL_AUDMA_I2S1_RX, CMU_DMA_REQ_I2S1_RX},
2741 {HAL_AUDMA_I2S1_TX, CMU_DMA_REQ_I2S1_TX},
2742 {HAL_AUDMA_SPDIF0_RX, CMU_DMA_REQ_SPDIF0_RX},
2743 {HAL_AUDMA_SPDIF0_TX, CMU_DMA_REQ_SPDIF0_TX},
2744 };
2745
hal_dma_periph_2_idx(enum HAL_DMA_PERIPH_T periph)2746 enum CMU_DMA_REQ_T BOOT_TEXT_FLASH_LOC hal_dma_periph_2_idx(enum HAL_DMA_PERIPH_T periph)
2747 {
2748 uint32_t i;
2749 for (i=0; i<ARRAY_SIZE(periph_map); ++i)
2750 if (periph_map[i].periph == periph)
2751 return periph_map[i].req;
2752 return CMU_DMA_REQ_NULL;
2753 }
2754
hal_cmu_dma_req_init(void)2755 void BOOT_TEXT_FLASH_LOC hal_cmu_dma_req_init(void)
2756 {
2757 // DMA channel config
2758 cmu->ADMA_CH0_4_REQ =
2759 CMU_ADMA_CH0_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[0])) |
2760 CMU_ADMA_CH1_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[1])) |
2761 CMU_ADMA_CH2_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[2])) |
2762 CMU_ADMA_CH3_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[3])) |
2763 CMU_ADMA_CH4_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[4]));
2764 cmu->ADMA_CH5_9_REQ =
2765 CMU_ADMA_CH5_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[5])) |
2766 CMU_ADMA_CH6_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[6])) |
2767 CMU_ADMA_CH7_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[7])) |
2768 CMU_ADMA_CH8_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[8])) |
2769 CMU_ADMA_CH9_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[9]));
2770 cmu->ADMA_CH10_14_REQ =
2771 CMU_ADMA_CH10_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[10])) |
2772 CMU_ADMA_CH11_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[11])) |
2773 CMU_ADMA_CH12_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[12])) |
2774 CMU_ADMA_CH13_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[13])) |
2775 CMU_ADMA_CH14_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[14]));
2776 cmu->ADMA_CH15_REQ =
2777 CMU_ADMA_CH15_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[15]));
2778
2779 cmu->GDMA_CH0_4_REQ =
2780 CMU_GDMA_CH0_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[0])) |
2781 CMU_GDMA_CH1_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[1])) |
2782 CMU_GDMA_CH2_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[2])) |
2783 CMU_GDMA_CH3_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[3])) |
2784 CMU_GDMA_CH4_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[4]));
2785 cmu->GDMA_CH5_9_REQ =
2786 CMU_GDMA_CH5_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[5])) |
2787 CMU_GDMA_CH6_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[6])) |
2788 CMU_GDMA_CH7_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[7])) |
2789 CMU_GDMA_CH8_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[8])) |
2790 CMU_GDMA_CH9_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[9]));
2791 cmu->GDMA_CH10_14_REQ =
2792 CMU_GDMA_CH10_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[10])) |
2793 CMU_GDMA_CH11_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[11])) |
2794 CMU_GDMA_CH12_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[12])) |
2795 CMU_GDMA_CH13_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[13])) |
2796 CMU_GDMA_CH14_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[14]));
2797 cmu->GDMA_CH15_REQ =
2798 CMU_GDMA_CH15_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[15]));
2799 }
2800
hal_cmu_module_init_state(void)2801 void BOOT_TEXT_FLASH_LOC hal_cmu_module_init_state(void)
2802 {
2803 aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~AON_CMU_SEL_AON_OSCX2) | AON_CMU_SEL_AON_OSC;
2804 // Slow down PMU fast clock
2805 //aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~(AON_CMU_BYPASS_DIV_DCDC | AON_CMU_CFG_DIV_DCDC_MASK)) | AON_CMU_CFG_DIV_DCDC(2);
2806
2807 hal_cmu_sram_init();
2808
2809 hal_cmu_dma_req_init();
2810
2811 #ifndef SIMU
2812 cmu->ORESET_SET = SYS_ORST_USB | SYS_ORST_USB32K | SYS_ORST_PSRAM1G | SYS_ORST_PSRAM200 | SYS_ORST_SDMMC |
2813 SYS_ORST_WDT | SYS_ORST_TIMER2 | SYS_ORST_I2C0 | SYS_ORST_I2C1 | SYS_ORST_I2C2 | SYS_ORST_SPI | SYS_ORST_SLCD | SYS_ORST_SPI_PHY |
2814 #ifndef ARM_CMNS
2815 SYS_ORST_UART0 |
2816 #endif
2817 SYS_ORST_UART1 | SYS_ORST_UART2 | SYS_ORST_UART3 | SYS_ORST_PCM | SYS_ORST_I2S0 | SYS_ORST_I2S1 |
2818 SYS_ORST_SPDIF0 | SYS_ORST_A7 | SYS_ORST_TSF | SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP | SYS_ORST_FLASH1;
2819 cmu->PRESET_SET = SYS_PRST_WDT | SYS_PRST_TIMER2 | SYS_PRST_I2C0 | SYS_PRST_I2C1 | SYS_PRST_I2C2 | SYS_PRST_IR |
2820 SYS_PRST_SPI | SYS_PRST_SLCD | SYS_PRST_SPI_PHY |
2821 #ifndef ARM_CMNS
2822 SYS_PRST_UART0 |
2823 #endif
2824 SYS_PRST_UART1 | SYS_PRST_UART2 | SYS_PRST_UART3 |
2825 SYS_PRST_PCM | SYS_PRST_I2S0 | SYS_PRST_I2S1 | SYS_PRST_SPDIF0 | SYS_PRST_TQWF | SYS_PRST_TQA7;
2826 cmu->HRESET_SET = SYS_HRST_CORE1 | SYS_HRST_BCM | SYS_HRST_USBC | SYS_HRST_USBH | SYS_HRST_CODEC |
2827 SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G | SYS_HRST_PSRAM200 | SYS_HRST_BT_DUMP | SYS_HRST_WF_DUMP | SYS_HRST_SDMMC |
2828 SYS_HRST_CHECKSUM | SYS_HRST_CRC | SYS_HRST_FLASH1;
2829 cmu->XRESET_SET = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PSRAM1G | SYS_XRST_PER |
2830 SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
2831 SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH | SYS_XRST_CSI | SYS_XRST_DSI | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_MAIN | SYS_XRST_GPV_PSRAM1G;
2832 cmu->APRESET_SET = SYS_APRST_BOOTREG | SYS_APRST_WDT| SYS_APRST_TIMER0 | SYS_APRST_TIMER1 | SYS_APRST_TQ | SYS_APRST_DAP |
2833 SYS_APRST_DISPLAY | SYS_APRST_CSI;
2834 cmu->QRESET_SET = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV | SYS_QRST_DSI_PIX |
2835 SYS_QRST_DSI_DSI | SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG | SYS_QRST_IR;
2836
2837 cmu->OCLK_DISABLE = SYS_OCLK_USB | SYS_OCLK_USB32K | SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_SDMMC |
2838 SYS_OCLK_WDT | SYS_OCLK_TIMER2 | SYS_OCLK_I2C0 | SYS_OCLK_I2C1 | SYS_OCLK_I2C2 | SYS_OCLK_SPI | SYS_OCLK_SLCD | SYS_OCLK_SPI_PHY |
2839 #ifndef ARM_CMNS
2840 SYS_OCLK_UART0 |
2841 #endif
2842 SYS_OCLK_UART1 | SYS_OCLK_UART2 | SYS_OCLK_UART3 | SYS_OCLK_PCM | SYS_OCLK_I2S0 | SYS_OCLK_I2S1 |
2843 SYS_OCLK_SPDIF0 | SYS_OCLK_A7 | SYS_OCLK_TSF | SYS_OCLK_WDT_AP | SYS_OCLK_TIMER0_AP | SYS_OCLK_TIMER1_AP | SYS_OCLK_FLASH1;
2844 cmu->PCLK_DISABLE = SYS_PCLK_WDT | SYS_PCLK_TIMER2 | SYS_PCLK_I2C0 | SYS_PCLK_I2C1 | SYS_PCLK_I2C2 | SYS_PCLK_IR |
2845 SYS_PCLK_SPI | SYS_PCLK_SLCD | SYS_PCLK_SPI_PHY |
2846 #ifndef ARM_CMNS
2847 SYS_PCLK_UART0 |
2848 #endif
2849 SYS_PCLK_UART1 | SYS_PCLK_UART2 | SYS_PCLK_UART3 |
2850 SYS_PCLK_PCM | SYS_PCLK_I2S0 | SYS_PCLK_I2S1 | SYS_PCLK_SPDIF0 | SYS_PCLK_TQWF | SYS_PCLK_TQA7;
2851 cmu->HCLK_DISABLE = SYS_HCLK_CORE1 | SYS_HCLK_BCM | SYS_HCLK_USBC | SYS_HCLK_USBH | SYS_HCLK_CODEC |
2852 SYS_HCLK_AX2H_A7 | SYS_HCLK_PSRAM1G | SYS_HCLK_PSRAM200 | SYS_HCLK_BT_DUMP | SYS_HCLK_WF_DUMP | SYS_HCLK_SDMMC |
2853 SYS_HCLK_CHECKSUM | SYS_HCLK_CRC | SYS_HCLK_FLASH1;
2854 cmu->XCLK_DISABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PSRAM1G | SYS_XCLK_PER |
2855 SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
2856 SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH | SYS_XCLK_CSI | SYS_XCLK_DSI | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_MAIN | SYS_XCLK_GPV_PSRAM1G;;
2857 cmu->APCLK_DISABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP |
2858 SYS_APCLK_DISPLAY | SYS_APCLK_CSI;
2859 cmu->QCLK_DISABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV | SYS_QCLK_DSI_PIX |
2860 SYS_QCLK_DSI_DSI | SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG | SYS_QCLK_IR;
2861
2862 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_DISABLE | AON_CMU_EN_CLK_CODECIIR_DISABLE | AON_CMU_EN_CLK_CODECRS0_DISABLE |
2863 AON_CMU_EN_CLK_CODECRS1_DISABLE | AON_CMU_EN_CLK_CODECHCLK_DISABLE | AON_CMU_EN_CLK_VAD32K_DISABLE |
2864 AON_CMU_EN_CLK_BT_DISABLE | AON_CMU_EN_CLK_WF_DISABLE;
2865
2866 aoncmu->RESET_SET = AON_CMU_ARESETN_SET(AON_ARST_PWM | AON_ARST_PWM1) |
2867 AON_CMU_ORESETN_SET(AON_ORST_PWM0 | AON_ORST_PWM1 | AON_ORST_PWM2 | AON_ORST_PWM3 |
2868 AON_ORST_PWM4 | AON_ORST_PWM5 | AON_ORST_PWM6 | AON_ORST_PWM7 | AON_ORST_BTAON);
2869
2870 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_CODEC_SET |
2871 AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET |
2872 AON_CMU_SOFT_RSTN_WF_SET | AON_CMU_SOFT_RSTN_WFCPU_SET |
2873 AON_CMU_SOFT_RSTN_BT_SET | AON_CMU_SOFT_RSTN_BTCPU_SET;
2874
2875 aoncmu->MOD_CLK_DISABLE = AON_CMU_MANUAL_ACLK_DISABLE(AON_ACLK_PWM) |
2876 AON_CMU_MANUAL_OCLK_DISABLE(AON_OCLK_PWM0 | AON_OCLK_PWM1 | AON_OCLK_PWM2 | AON_OCLK_PWM3 | AON_OCLK_BTAON);
2877
2878 aoncmu->MOD_CLK_MODE &= ~AON_CMU_MODE_ACLK(AON_ACLK_CMU | AON_ACLK_GPIO_INT | AON_ACLK_WDT | AON_ACLK_PWM |
2879 AON_ACLK_TIMER | AON_ACLK_IOMUX);
2880 cmu->PCLK_MODE &= ~(SYS_PCLK_CMU | SYS_PCLK_WDT | SYS_PCLK_TIMER0 | SYS_PCLK_TIMER1 | SYS_PCLK_TIMER2);
2881
2882 aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_DSI | AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_DSI_IN |
2883 AON_CMU_POL_CLK_CSI_IN);
2884
2885 //cmu->HCLK_MODE = 0;
2886 //cmu->PCLK_MODE = SYS_PCLK_UART0 | SYS_PCLK_UART1 | SYS_PCLK_UART2;
2887 //cmu->OCLK_MODE = 0;
2888 #endif
2889 hal_psc_init();
2890 }
2891
hal_cmu_ema_init(void)2892 void BOOT_TEXT_FLASH_LOC hal_cmu_ema_init(void)
2893 {
2894 // Never change EMA
2895 }
2896
hal_cmu_lpu_wait_26m_ready(void)2897 void hal_cmu_lpu_wait_26m_ready(void)
2898 {
2899 while ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCH26 | CMU_LPU_STATUS_26M)) ==
2900 CMU_LPU_AUTO_SWITCH26);
2901 }
2902
hal_cmu_lpu_busy(void)2903 int hal_cmu_lpu_busy(void)
2904 {
2905 if ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCH26 | CMU_LPU_STATUS_26M)) ==
2906 CMU_LPU_AUTO_SWITCH26) {
2907 return 1;
2908 }
2909 if ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_STATUS_PLL)) ==
2910 CMU_LPU_AUTO_SWITCHPLL) {
2911 return 1;
2912 }
2913 return 0;
2914 }
2915
hal_cmu_lpu_init(enum HAL_CMU_LPU_CLK_CFG_T cfg)2916 int BOOT_TEXT_FLASH_LOC hal_cmu_lpu_init(enum HAL_CMU_LPU_CLK_CFG_T cfg)
2917 {
2918 uint32_t lpu_clk;
2919 uint32_t timer_26m;
2920 uint32_t timer_pll;
2921
2922 timer_26m = LPU_TIMER_US(TICKS_TO_US(HAL_CMU_26M_READY_TIMEOUT));
2923 timer_pll = LPU_TIMER_US(TICKS_TO_US(HAL_CMU_PLL_LOCKED_TIMEOUT));
2924
2925 if (cfg >= HAL_CMU_LPU_CLK_QTY) {
2926 return 1;
2927 }
2928 if ((timer_26m & (CMU_TIMER_WT26_MASK >> CMU_TIMER_WT26_SHIFT)) != timer_26m) {
2929 return 2;
2930 }
2931 if ((timer_pll & (CMU_TIMER_WTPLL_MASK >> CMU_TIMER_WTPLL_SHIFT)) != timer_pll) {
2932 return 3;
2933 }
2934 if (hal_cmu_lpu_busy()) {
2935 return -1;
2936 }
2937 lpu_clk = cmu->WAKEUP_CLK_CFG;
2938 lpu_clk &= ~(CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26);
2939
2940 if (cfg == HAL_CMU_LPU_CLK_26M) {
2941 lpu_clk |= CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCH26;
2942 } else if (cfg == HAL_CMU_LPU_CLK_PLL) {
2943 lpu_clk |= CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26;
2944 } else {
2945 }
2946
2947 if (lpu_clk & CMU_LPU_AUTO_SWITCH26) {
2948 // Disable RAM wakeup early
2949 cmu->MCU_TIMER &= ~CMU_RAM_RETN_UP_EARLY;
2950 // MCU/ROM/RAM auto clock gating (which depends on RAM gating signal)
2951 cmu->HCLK_MODE &= ~(SYS_HCLK_CORE0 | SYS_HCLK_ROM0 | SYS_HCLK_RAM0 | SYS_HCLK_RAM1 |
2952 SYS_HCLK_RAM2 | SYS_HCLK_RAM3 | SYS_HCLK_RAM4 | SYS_HCLK_RAM5);
2953 // AON_CMU enable auto switch 26M (AON_CMU must have selected 26M and disabled 52M/32K already)
2954 aoncmu->CODEC_DIV |= AON_CMU_LPU_AUTO_SWITCH26;
2955 } else {
2956 // AON_CMU disable auto switch 26M
2957 aoncmu->CODEC_DIV &= ~AON_CMU_LPU_AUTO_SWITCH26;
2958 }
2959
2960 lpu_clk |= CMU_TIMER_WT26(timer_26m);
2961 if (timer_pll) {
2962 lpu_clk |= CMU_TIMER_WTPLL(timer_pll);
2963 hal_sys_timer_delay(US_TO_TICKS(60));
2964 cmu->WAKEUP_CLK_CFG = lpu_clk;
2965 } else {
2966 lpu_clk |= CMU_TIMER_WTPLL(0);
2967 cmu->WAKEUP_CLK_CFG = lpu_clk;
2968 }
2969
2970 #ifndef ARM_CMNS
2971 hal_sec_init(); //need metal_id
2972 #endif
2973
2974 if (hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4) {
2975 cmu->CMU_REMAP = CMU_REMAP(0xF); //psram cache and flash cache
2976 } else {
2977 cmu->CMU_REMAP = CMU_REMAP(0xC); //psram cache
2978 }
2979
2980 return 0;
2981 }
2982
cpu_sleep(uint32_t wakeup_cfg)2983 __STATIC_FORCEINLINE void cpu_sleep(uint32_t wakeup_cfg)
2984 {
2985 __DSB();
2986
2987 if (wakeup_cfg & (CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26)) {
2988 // 1) Avoid race condition between LPU state machine entry and IRQ wakeup:
2989 // Wait 4 (at least 2) cycles of 32K clock, or 3248 cycles of 26M clock.
2990 // 2) Avoid race condition between CPU clock gating and RAM access when waiting:
2991 // No consecutive RAM access is allowed.
2992 // This is related to instruction width/alignment, pipeline state, branch prediction state, etc.
2993 // Unfortunately, it is too hard to control all of these, especially on M33.
2994 __WFI();
2995 } else {
2996 __WFI();
2997 }
2998 }
2999
hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)3000 int SRAM_TEXT_LOC hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
3001 {
3002 uint32_t start;
3003 uint32_t timeout;
3004 uint32_t saved_pll_cfg;
3005 uint32_t saved_clk_cfg;
3006 uint32_t saved_codec_div;
3007 uint32_t saved_top_clk;
3008 uint32_t wakeup_cfg;
3009 uint32_t saved_hclk;
3010 uint32_t saved_oclk;
3011
3012 saved_codec_div = aoncmu->CODEC_DIV;
3013 saved_top_clk = aoncmu->TOP_CLK_ENABLE;
3014 saved_pll_cfg = aoncmu->PLL_ENABLE;
3015 saved_clk_cfg = cmu->SYS_CLK_ENABLE;
3016 saved_hclk = cmu->HCLK_ENABLE;
3017 saved_oclk = cmu->OCLK_ENABLE;
3018
3019 // Switch VAD clock to AON and disable codec HCLK
3020 aoncmu->CODEC_DIV |= AON_CMU_SEL_CODECHCLK_MCU;
3021 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3022 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECHCLK_DISABLE;
3023 } else {
3024 // Avoid auto-gating OSC and OSCX2
3025 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX2_ENABLE | AON_CMU_EN_CLK_TOP_OSC_ENABLE;
3026 }
3027
3028 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3029 wakeup_cfg = cmu->WAKEUP_CLK_CFG;
3030 } else {
3031 wakeup_cfg = 0;
3032 }
3033
3034 // Disable memory/flash freq
3035 cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_FLASH;
3036 cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G | SYS_HCLK_PSRAM200 | SYS_HCLK_FLASH;
3037
3038 #ifndef ROM_BUILD
3039 // Reset pll div if pll is enabled
3040 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3041 pmu_pll_div_reset_set(HAL_CMU_PLL_USB);
3042 }
3043 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3044 pmu_pll_div_reset_set(HAL_CMU_PLL_DDR);
3045 }
3046 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3047 pmu_pll_div_reset_set(HAL_CMU_PLL_DSP);
3048 }
3049 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3050 pmu_pll_div_reset_set(HAL_CMU_PLL_BB);
3051 }
3052 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3053 pmu_pll_div_reset_set(HAL_CMU_PLL_BB_PSRAM);
3054 }
3055 #endif
3056
3057 // Setup wakeup mask
3058 #ifdef __ARM_ARCH_ISA_ARM
3059 cmu->WAKEUP_MASK0 = GICDistributor->ISENABLER[0];
3060 cmu->WAKEUP_MASK1 = GICDistributor->ISENABLER[1];
3061 cmu->WAKEUP_MASK2 = GICDistributor->ISENABLER[2];
3062 #else
3063 cmu->WAKEUP_MASK0 = NVIC->ISER[0];
3064 cmu->WAKEUP_MASK1 = NVIC->ISER[1];
3065 cmu->WAKEUP_MASK2 = NVIC->ISER[2];
3066 #endif
3067
3068 // Switch system freq to 26M
3069 cmu->SYS_CLK_ENABLE = CMU_SEL_MCU_SLOW_ENABLE;
3070 cmu->SYS_CLK_DISABLE = CMU_SEL_MCU_OSC_4_DISABLE | CMU_SEL_MCU_OSC_2_DISABLE |
3071 CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
3072 cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_MCU_DISABLE;
3073 // Shutdown PLLs
3074 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3075 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
3076 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLUSB_DISABLE;
3077 }
3078 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3079 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLDDR_DISABLE;
3080 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLDDR_DISABLE;
3081 }
3082 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3083 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLA7_DISABLE;
3084 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLA7_DISABLE;
3085 }
3086 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3087 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
3088 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DIV_MCU_DISABLE;
3089 }
3090 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3091 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_PS_DISABLE;
3092 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DIV_PS_DISABLE;
3093 }
3094 if (saved_pll_cfg & AON_CMU_PU_PLLBB_ENABLE) {
3095 aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DISABLE;
3096 }
3097 if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
3098 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_OSCX4_DISABLE;
3099 aoncmu->PLL_DISABLE = AON_CMU_PU_OSCX4_DISABLE;
3100 }
3101
3102 if (wakeup_cfg & CMU_LPU_AUTO_SWITCHPLL) {
3103 // Do nothing
3104 // Hardware will switch system freq to 32K and shutdown PLLs automatically
3105 } else {
3106 if (wakeup_cfg & CMU_LPU_AUTO_SWITCH26) {
3107 // Do nothing
3108 // Hardware will switch system freq to 32K automatically
3109 } else {
3110 // Manually switch AON_CMU clock to 32K
3111 aoncmu->CODEC_DIV &= ~(AON_CMU_SEL_AON_OSC | AON_CMU_SEL_AON_OSCX2);
3112 // Switch system freq to 32K
3113 cmu->SYS_CLK_DISABLE = CMU_SEL_MCU_SLOW_DISABLE;
3114 }
3115 }
3116
3117 if (wakeup_cfg & CMU_LPU_AUTO_SWITCH26) {
3118 // Enable auto memory retention
3119 cmu->SLEEP = (cmu->SLEEP & ~CMU_MANUAL_RAM_RETN) |
3120 CMU_DEEPSLEEP_EN | CMU_DEEPSLEEP_ROMRAM_EN | CMU_DEEPSLEEP_START;
3121 } else {
3122 // Disable auto memory retention
3123 cmu->SLEEP = (cmu->SLEEP & ~CMU_DEEPSLEEP_ROMRAM_EN) |
3124 CMU_DEEPSLEEP_EN | CMU_MANUAL_RAM_RETN | CMU_DEEPSLEEP_START;
3125 }
3126
3127 #ifndef __ARM_ARCH_ISA_ARM
3128 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3129 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
3130 } else {
3131 SCB->SCR = 0;
3132 }
3133 #endif
3134
3135 cpu_sleep(wakeup_cfg);
3136
3137 if (wakeup_cfg & CMU_LPU_AUTO_SWITCHPLL) {
3138 start = hal_sys_timer_get();
3139 timeout = HAL_CMU_26M_READY_TIMEOUT + HAL_CMU_PLL_LOCKED_TIMEOUT + HAL_CMU_LPU_EXTRA_TIMEOUT;
3140 while ((cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_PLL) == 0 &&
3141 (hal_sys_timer_get() - start) < timeout);
3142 // Hardware will switch system to PLL divider and enable PLLs automatically
3143 } else {
3144 // Wait for 26M ready
3145 if (wakeup_cfg & CMU_LPU_AUTO_SWITCH26) {
3146 start = hal_sys_timer_get();
3147 timeout = HAL_CMU_26M_READY_TIMEOUT + HAL_CMU_LPU_EXTRA_TIMEOUT;
3148 while ((cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_26M) == 0 &&
3149 (hal_sys_timer_get() - start) < timeout);
3150 // Hardware will switch system freq to 26M automatically
3151 } else {
3152 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3153 timeout = HAL_CMU_26M_READY_TIMEOUT;
3154 hal_sys_timer_delay(timeout);
3155 }
3156 // Switch system freq to 26M
3157 cmu->SYS_CLK_ENABLE = CMU_SEL_MCU_SLOW_ENABLE;
3158 // Restore AON_CMU clock
3159 aoncmu->CODEC_DIV = saved_codec_div;
3160 }
3161 }
3162
3163 // System freq is 26M now and will be restored later
3164 // Restore PLLs
3165 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3166 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLUSB_ENABLE;
3167 }
3168 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3169 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLDDR_ENABLE;
3170 }
3171 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3172 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLA7_ENABLE;
3173 }
3174 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3175 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_MCU_ENABLE;
3176 }
3177 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3178 aoncmu->PLL_ENABLE = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_PS_ENABLE;
3179 }
3180 if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
3181 aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX4_ENABLE;
3182 }
3183 #ifndef ROM_BUILD
3184 hal_sys_timer_delay_us(20);
3185 // Clear pll div reset if pll is enabled
3186 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3187 pmu_pll_div_reset_clear(HAL_CMU_PLL_USB);
3188 }
3189 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3190 pmu_pll_div_reset_clear(HAL_CMU_PLL_DDR);
3191 }
3192 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3193 pmu_pll_div_reset_clear(HAL_CMU_PLL_DSP);
3194 }
3195 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3196 pmu_pll_div_reset_clear(HAL_CMU_PLL_BB);
3197 }
3198 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3199 pmu_pll_div_reset_clear(HAL_CMU_PLL_BB_PSRAM);
3200 }
3201 hal_sys_timer_delay_us(10);
3202 #endif
3203 if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
3204 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
3205 }
3206 if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
3207 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE;
3208 }
3209 if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
3210 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLA7_ENABLE;
3211 }
3212 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
3213 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
3214 }
3215 if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
3216 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE;
3217 }
3218 if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
3219 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX4_ENABLE;
3220 }
3221 // Restore system freq
3222 cmu->SYS_CLK_ENABLE = saved_clk_cfg & CMU_RSTN_DIV_MCU_ENABLE;
3223 cmu->SYS_CLK_ENABLE = saved_clk_cfg;
3224 // The original system freq are at least 26M
3225 //cmu->SYS_CLK_DISABLE = ~saved_clk_cfg;
3226
3227 // Switch VAD clock to MCU and enable codec HCLK if it is on before entering sleep
3228 aoncmu->CODEC_DIV &= ~AON_CMU_SEL_CODECHCLK_MCU;
3229 if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
3230 aoncmu->TOP_CLK_ENABLE = saved_top_clk & AON_CMU_EN_CLK_CODECHCLK_ENABLE;
3231 } else {
3232 // Restore the original top clock settings
3233 aoncmu->TOP_CLK_DISABLE = ~saved_top_clk;
3234 }
3235
3236 if (saved_oclk & (SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_FLASH)) {
3237 // Enable memory/flash clock
3238 cmu->HCLK_ENABLE = saved_hclk;
3239 cmu->OCLK_ENABLE = saved_oclk;
3240 // Wait until memory/flash clock ready
3241 hal_sys_timer_delay_us(2);
3242 }
3243
3244 return 0;
3245 }
3246
hal_cmu_get_bootmode_addr(void)3247 volatile uint32_t *hal_cmu_get_bootmode_addr(void)
3248 {
3249 return &aoncmu->BOOTMODE;
3250 }
3251
hal_cmu_bt_clock_enable(void)3252 void hal_cmu_bt_clock_enable(void)
3253 {
3254 aoncmu->MOD_CLK_ENABLE = AON_CMU_MANUAL_OCLK_ENABLE(AON_OCLK_BTAON);
3255 aocmu_reg_update_wait();
3256 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_BT_ENABLE;
3257 aocmu_reg_update_wait();
3258 }
3259
hal_cmu_bt_clock_disable(void)3260 void hal_cmu_bt_clock_disable(void)
3261 {
3262 aoncmu->MOD_CLK_DISABLE = AON_CMU_MANUAL_OCLK_DISABLE(AON_OCLK_BTAON);
3263 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_BT_DISABLE;
3264 }
3265
hal_cmu_bt_reset_set(void)3266 void hal_cmu_bt_reset_set(void)
3267 {
3268 aoncmu->RESET_SET = AON_CMU_ORESETN_SET(AON_ORST_BTAON);
3269 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_BT_SET | AON_CMU_SOFT_RSTN_BTCPU_SET;
3270 }
3271
hal_cmu_bt_reset_clear(void)3272 void hal_cmu_bt_reset_clear(void)
3273 {
3274 aoncmu->RESET_CLR = AON_CMU_ORESETN_CLR(AON_ORST_BTAON);
3275 aocmu_reg_update_wait();
3276 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_BT_CLR | AON_CMU_SOFT_RSTN_BTCPU_CLR;
3277 aocmu_reg_update_wait();
3278 }
3279
hal_cmu_bt_module_init(void)3280 void hal_cmu_bt_module_init(void)
3281 {
3282 //btcmu->CLK_MODE = 0;
3283 }
3284
hal_cmu_wifi_clock_enable(void)3285 void hal_cmu_wifi_clock_enable(void)
3286 {
3287 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_WF_ENABLE;
3288 aocmu_reg_update_wait();
3289 }
3290
hal_cmu_wifi_clock_disable(void)3291 void hal_cmu_wifi_clock_disable(void)
3292 {
3293 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_WF_DISABLE;
3294 }
3295
hal_cmu_wifi_reset_set(void)3296 void hal_cmu_wifi_reset_set(void)
3297 {
3298 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_WF_SET | AON_CMU_SOFT_RSTN_WFCPU_SET;
3299 }
3300
hal_cmu_wifi_reset_clear(void)3301 void hal_cmu_wifi_reset_clear(void)
3302 {
3303 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_WF_CLR | AON_CMU_SOFT_RSTN_WFCPU_CLR;
3304 aocmu_reg_update_wait();
3305 }
3306
hal_cmu_wlan_set_sleep_allow(uint32_t auto_mode)3307 void BOOT_TEXT_FLASH_LOC hal_cmu_wlan_set_sleep_allow(uint32_t auto_mode)
3308 {
3309 if (auto_mode) { //controlled by wifi sleep signal
3310 aoncmu->RESERVED_0E8 = aoncmu->RESERVED_0E8 & (~((1<<4)|(1<<6)));
3311 } else { //force allow cmu sleep
3312 aoncmu->RESERVED_0E8 = (aoncmu->RESERVED_0E8 & (~((1<<5)|(1<<7)))) | ((1<<4)|(1<<6));
3313 }
3314 }
3315
hal_cmu_dsp_clock_enable(void)3316 void hal_cmu_dsp_clock_enable(void)
3317 {
3318 enum HAL_CMU_PLL_T dsp;
3319 #ifdef DSP_ENABLE
3320 hal_psc_a7_enable();
3321 #endif
3322 // DSP AXI clock divider defaults to 4 (div = reg_val + 2)
3323 cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_XCLK, 2);
3324 cmu->XCLK_ENABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PER |
3325 SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
3326 SYS_XCLK_GPV_MAIN;
3327 cmu->APCLK_ENABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
3328 cmu->HCLK_ENABLE = SYS_HCLK_AX2H_A7;
3329
3330 cmu->DSP_CFG0 |= CMU_CA7_DBGEN_MASK | CMU_CA7_SPIDEN_MASK | CMU_CA7_NIDEN_MASK | CMU_CA7_SPNIDEN_MASK;
3331
3332 cmu->PERIPH_CLK |= CMU_A7_ALLIRQ_MASK;
3333 cmu->DSP_CFG0 |= CMU_A7TOM33_IRQS_MASK(8);
3334
3335 #ifdef DSP_USE_BBPLL
3336 dsp = HAL_CMU_PLL_BB;
3337 #elif defined(DSP_USE_USBPLL)
3338 dsp = HAL_CMU_PLL_USB;
3339 #else
3340 dsp = HAL_CMU_PLL_DSP;
3341 #endif
3342 hal_cmu_dsp_select_pll(dsp);
3343 hal_cmu_pll_enable(dsp, HAL_CMU_PLL_USER_DSP);
3344
3345 hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
3346
3347 #ifdef DSP_ENABLE
3348 hal_cmu_clock_enable(HAL_CMU_MOD_O_A7);
3349 hal_cmu_clock_enable(HAL_CMU_MOD_O_WDT_AP);
3350 hal_cmu_clock_enable(HAL_CMU_MOD_O_TIMER0_AP);
3351 hal_cmu_clock_enable(HAL_CMU_MOD_O_TIMER1_AP);
3352 #endif
3353 }
3354
hal_cmu_dsp_clock_disable(void)3355 void hal_cmu_dsp_clock_disable(void)
3356 {
3357 enum HAL_CMU_PLL_T dsp;
3358
3359 hal_cmu_clock_disable(HAL_CMU_MOD_O_A7);
3360
3361 #ifdef DSP_USE_BBPLL
3362 dsp = HAL_CMU_PLL_BB;
3363 #elif defined(DSP_USE_USBPLL)
3364 dsp = HAL_CMU_PLL_USB;
3365 #else
3366 dsp = HAL_CMU_PLL_DSP;
3367 #endif
3368 hal_cmu_pll_disable(dsp, HAL_CMU_PLL_USER_DSP);
3369
3370 cmu->XCLK_DISABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PER |
3371 SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
3372 SYS_XCLK_GPV_MAIN;
3373 cmu->APCLK_DISABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
3374 cmu->OCLK_DISABLE = SYS_OCLK_WDT_AP | SYS_OCLK_TIMER0_AP | SYS_OCLK_TIMER1_AP;
3375 cmu->HCLK_DISABLE = SYS_HCLK_AX2H_A7;
3376
3377 hal_psc_a7_disable();
3378 }
3379
hal_cmu_dsp_reset_set(void)3380 void hal_cmu_dsp_reset_set(void)
3381 {
3382 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET;
3383 cmu->ORESET_SET = SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP;
3384 cmu->XRESET_SET = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PER |
3385 SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
3386 SYS_XRST_GPV_MAIN;
3387 cmu->APRESET_SET = SYS_APRST_BOOTREG | SYS_APRST_WDT | SYS_APRST_TIMER0 | SYS_APRST_TIMER1 | SYS_APRST_TQ | SYS_APRST_DAP;
3388 cmu->HRESET_SET = SYS_HRST_AX2H_A7;
3389 }
3390
hal_cmu_dsp_reset_clear(void)3391 void hal_cmu_dsp_reset_clear(void)
3392 {
3393 cmu->APRESET_CLR = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
3394 cmu->XRESET_CLR = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PER |
3395 SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
3396 SYS_XRST_GPV_MAIN;
3397 cmu->ORESET_CLR = SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP;
3398 cmu->HRESET_CLR = SYS_HRST_AX2H_A7;
3399 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7_CLR;
3400 aocmu_reg_update_wait();
3401 }
3402
hal_cmu_dsp_reset_hold(void)3403 void hal_cmu_dsp_reset_hold(void)
3404 {
3405 aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET;
3406 cmu->HRESET_SET = SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G;
3407 cmu->ORESET_SET = SYS_ORST_PSRAM1G;
3408 cmu->ORESET_SET = SYS_ORST_WDT_AP | SYS_ORST_TIMER1_AP;
3409 }
3410
hal_cmu_dsp_reset_release(void)3411 void hal_cmu_dsp_reset_release(void)
3412 {
3413 cmu->ORESET_CLR = SYS_ORST_WDT_AP | SYS_ORST_TIMER1_AP;
3414 cmu->ORESET_CLR = SYS_ORST_PSRAM1G;
3415 cmu->HRESET_CLR = SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G;
3416 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7_CLR;
3417 aocmu_reg_update_wait();
3418 }
3419
hal_cmu_dsp_init_boot_reg(uint32_t entry)3420 void hal_cmu_dsp_init_boot_reg(uint32_t entry)
3421 {
3422 int i;
3423 volatile uint32_t *boot = (volatile uint32_t *)DSP_BOOT_REG;
3424
3425 // Unlock
3426 boot[32] = 0xCAFE0001;
3427 __DMB();
3428
3429 for (i = 0; i < 8; i++) {
3430 // ldr pc, [pc, #24]
3431 boot[0 + i] = 0xE59FF018;
3432 // Init_Handler
3433 boot[8 + i] = 0x00000040;
3434 }
3435 // b 40
3436 boot[16] = 0xEAFFFFFE;
3437
3438 // Update reset handler
3439 boot[8] = entry;
3440
3441 // Lock
3442 __DMB();
3443 boot[32] = 0xCAFE0000;
3444 __DMB();
3445 }
3446
hal_cmu_dsp_start_cpu(void)3447 void hal_cmu_dsp_start_cpu(void)
3448 {
3449 hal_cmu_dsp_set_freq(HAL_CMU_FREQ_156M);//div 5
3450 aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7CPU_CLR;
3451 }
3452
hal_cmu_dsp_stop_cpu(void)3453 void hal_cmu_dsp_stop_cpu(void)
3454 {
3455 uint32_t lock;
3456 lock = int_lock();
3457 #ifdef PSRAMUHS_ENABLE
3458 hal_psramuhs_hold();
3459 #endif
3460 hal_cmu_dsp_reset_hold();
3461 //hal_cmu_dsp_clock_disable();
3462
3463 #ifdef PSRAMUHS_ENABLE
3464 //hal_cmu_dsp_clock_enable();
3465 hal_cmu_dsp_reset_release();
3466 hal_psramuhs_release();
3467 #endif
3468 int_unlock(lock);
3469 }
3470
hal_cmu_get_aon_chip_id(void)3471 uint32_t hal_cmu_get_aon_chip_id(void)
3472 {
3473 return aoncmu->CHIP_ID;
3474 }
3475
hal_cmu_get_aon_revision_id(void)3476 uint32_t hal_cmu_get_aon_revision_id(void)
3477 {
3478 return GET_BITFIELD(aoncmu->CHIP_ID, AON_CMU_REVISION_ID);
3479 }
3480
hal_cmu_cp_enable(uint32_t sp,uint32_t entry)3481 void hal_cmu_cp_enable(uint32_t sp, uint32_t entry)
3482 {
3483 struct CP_STARTUP_CFG_T * cp_cfg;
3484 uint32_t cfg_addr;
3485
3486 // Use (sp - 128) as the default vector. The Address must aligned to 128-byte boundary.
3487 cfg_addr = (sp - (1 << 7)) & ~((1 << 7) - 1);
3488
3489 cmu->CP_VTOR = cfg_addr;
3490 cp_cfg = (struct CP_STARTUP_CFG_T *)cfg_addr;
3491
3492 cp_cfg->stack = sp;
3493 cp_cfg->reset_hdlr = (uint32_t)system_cp_reset_handler;
3494 cp_entry = entry;
3495
3496 hal_cmu_clock_enable(HAL_CMU_MOD_H_CP);
3497 hal_cmu_reset_clear(HAL_CMU_MOD_H_CP);
3498 }
3499
hal_cmu_cp_disable(void)3500 void hal_cmu_cp_disable(void)
3501 {
3502 hal_cmu_reset_set(HAL_CMU_MOD_H_CP);
3503 hal_cmu_clock_disable(HAL_CMU_MOD_H_CP);
3504 }
3505
hal_cmu_cp_get_entry_addr(void)3506 uint32_t hal_cmu_cp_get_entry_addr(void)
3507 {
3508 return cp_entry;
3509 }
3510
hal_cmu_cp_boot(uint32_t entry)3511 void hal_cmu_cp_boot(uint32_t entry)
3512 {
3513 cmu->CP_VTOR = entry;
3514
3515 hal_cmu_clock_enable(HAL_CMU_MOD_H_CACHE1);
3516 hal_cmu_reset_clear(HAL_CMU_MOD_H_CACHE1);
3517
3518 hal_cmu_clock_enable(HAL_CMU_MOD_H_CP);
3519 hal_cmu_reset_clear(HAL_CMU_MOD_H_CP);
3520 }
3521
hal_cmu_jtag_sel(enum HAL_CMU_JTAG_SEL_T sel)3522 void hal_cmu_jtag_sel(enum HAL_CMU_JTAG_SEL_T sel)
3523 {
3524 uint32_t lock;
3525
3526 lock = int_lock();
3527 cmu->PERIPH_CLK &= ~CMU_JTAG_SEL_MASK;
3528 switch (sel) {
3529 case HAL_CMU_JTAG_SEL_CP:
3530 cmu->PERIPH_CLK |= CMU_JTAG_SEL_CP;
3531 break;
3532 case HAL_CMU_JTAG_SEL_A7:
3533 cmu->PERIPH_CLK |= CMU_JTAG_SEL_A7;
3534 break;
3535 default:
3536 break;
3537 }
3538 int_unlock(lock);
3539 }
3540
hal_cmu_dsp_setup(void)3541 void hal_cmu_dsp_setup(void)
3542 {
3543 hal_sys_timer_open();
3544
3545 hal_sysfreq_req(HAL_SYSFREQ_USER_INIT, HAL_CMU_FREQ_390M);
3546
3547 }
3548
hal_cmu_flash0_dual_die()3549 void hal_cmu_flash0_dual_die()
3550 {
3551 cmu->MCU_TIMER &= ~CMU_FLS1_IO_SEL;
3552 }
3553
hal_cmu_flash1_enable()3554 void hal_cmu_flash1_enable()
3555 {
3556 //aoncmu->FLASH_IOCFG |= AON_CMU_PU_FLASH1_IO;
3557 aoncmu->FLASH_IOCFG = SET_BITFIELD(aoncmu->FLASH_IOCFG, AON_CMU_FLASH1_IODRV, 0x7) | AON_CMU_PU_FLASH1_IO;
3558 }
3559
hal_cmu_set_flash0_x8_mode(uint32_t en)3560 void hal_cmu_set_flash0_x8_mode(uint32_t en)
3561 {
3562 if (en)
3563 cmu->MCU_TIMER |= CMU_FLS0_X8_SEL;
3564 else
3565 cmu->MCU_TIMER &= ~CMU_FLS0_X8_SEL;
3566 }
3567
hal_cmu_set_flash0_size(enum HAL_FLASH0_SIZE_CFG cfg)3568 void hal_cmu_set_flash0_size(enum HAL_FLASH0_SIZE_CFG cfg)
3569 {
3570 *(volatile uint32_t *)(ICACHE_CTRL_BASE + 0x44) = cfg;
3571 }
3572
hal_cmu_get_osc_ready_cycle_cnt(void)3573 uint32_t hal_cmu_get_osc_ready_cycle_cnt(void)
3574 {
3575 uint32_t cnt=10;
3576
3577
3578
3579 return cnt;
3580 }
3581
hal_cmu_get_osc_switch_overhead(void)3582 uint32_t hal_cmu_get_osc_switch_overhead(void)
3583 {
3584 return 6;
3585 }
3586
hal_cmu_bt_sys_set_freq(enum HAL_CMU_FREQ_T freq)3587 void hal_cmu_bt_sys_set_freq(enum HAL_CMU_FREQ_T freq)
3588 {
3589
3590 }
3591
hal_cmu_bt_sys_clock_force_on(void)3592 void hal_cmu_bt_sys_clock_force_on(void)
3593 {
3594 uint32_t lock;
3595
3596 lock = int_lock();
3597 hal_psc_dslp_force_on_bt_enable();
3598 aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_BT_CLK_SYS_ENABLE;
3599 int_unlock(lock);
3600 aocmu_reg_update_wait();
3601 }
3602
hal_cmu_bt_sys_clock_auto(void)3603 void hal_cmu_bt_sys_clock_auto(void)
3604 {
3605 uint32_t lock;
3606
3607 lock = int_lock();
3608 aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_BT_CLK_SYS_DISABLE;
3609 hal_psc_dslp_force_on_bt_disable();
3610 int_unlock(lock);
3611 }
3612
3613 #ifdef REUSE_WIFI_CALI_RESULT
3614 extern void save_wifi_cali_result();
3615 #endif
3616
hal_cmu_shutdown_hook(void)3617 void hal_cmu_shutdown_hook(void)
3618 {
3619 int_lock();
3620 hal_cmu_codec_clock_disable();
3621 hal_cmu_codec_rs_disable();
3622
3623 hal_cmu_dsp_reset_set();
3624 hal_cmu_dsp_clock_disable();
3625
3626 #ifdef REUSE_WIFI_CALI_RESULT
3627 save_wifi_cali_result();
3628 #endif
3629
3630 hal_cmu_wifi_reset_set();
3631 hal_cmu_wifi_clock_disable();
3632 hal_cmu_cp_disable();
3633 hal_cmu_bt_reset_set();
3634 hal_cmu_bt_clock_disable();
3635
3636 // hal_norflash_deinit();
3637
3638 hal_cmu_mem_set_freq(HAL_CMU_FREQ_26M);
3639 hal_cmu_sys_set_freq(HAL_CMU_FREQ_26M);
3640
3641 // psramuhsphy_sleep();
3642 // hal_psram_phy_sleep();
3643 // hal_cmu_pll_disable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_ALL);
3644 // hal_cmu_pll_disable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_ALL);
3645 // hal_cmu_pll_disable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_ALL);
3646 // hal_cmu_pll_disable(HAL_CMU_PLL_DSP, HAL_CMU_PLL_USER_ALL);
3647 // hal_cmu_pll_disable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_ALL);
3648 }
3649
hal_cmu_sys_reboot(void)3650 void hal_cmu_sys_reboot(void)
3651 {
3652 #if defined(FLASH_SUSPEND) && defined(FLASH_API_GUARD_THREAD)
3653 norflash_api_flush_all();
3654 #endif
3655 hal_cmu_shutdown_hook();
3656 hal_cmu_reset_set(HAL_CMU_MOD_GLOBAL);
3657 }