1 /*
2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include "plat_addr_map.h"
16 #include "hal_cmu.h"
17 #ifdef CHIP_SUBSYS_SENS
18 #include CHIP_SPECIFIC_HDR(reg_senscmu)
19 #else
20 #include CHIP_SPECIFIC_HDR(reg_cmu)
21 #endif
22 #ifdef AON_CMU_BASE
23 #include CHIP_SPECIFIC_HDR(reg_aoncmu)
24 #endif
25 #include "cmsis.h"
26 #include "hal_analogif.h"
27 #include "hal_bootmode.h"
28 #include "hal_cache.h"
29 #include "hal_chipid.h"
30 #include "hal_iomux.h"
31 #include "hal_location.h"
32 #include "hal_norflash.h"
33 #include "hal_sleep.h"
34 #include "hal_sysfreq.h"
35 #include "hal_timer.h"
36 #include "hal_trace.h"
37
38 #if defined(CHIP_HAS_USB) && (defined(MCU_HIGH_PERFORMANCE_MODE) && !(defined(ULTRA_LOW_POWER) || defined(OSC_26M_X4_AUD2BB)))
39 #define USB_PLL_INIT_ON
40 #endif
41 #if (!defined(ULTRA_LOW_POWER) && !defined(OSC_26M_X4_AUD2BB)) || \
42 (!defined(FLASH_LOW_SPEED) && !defined(OSC_26M_X4_AUD2BB)) || \
43 (defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED))
44 #define AUD_PLL_INIT_ON
45 #endif
46
47 // SIMU_RES
48 #define CMU_SIMU_RES_PASSED (0x9A55)
49 #define CMU_SIMU_RES_FAILED (0xFA11)
50
51 typedef void (*HAL_POWER_DOWN_WAKEUP_HANDLER)(void);
52
53 #ifdef CHIP_SUBSYS_SENS
54 static struct SENSCMU_T * const cmu = (struct SENSCMU_T *)SENS_CMU_BASE;
55 #else
56 static struct CMU_T * const cmu = (struct CMU_T *)CMU_BASE;
57 #endif
58 #ifdef AON_CMU_BASE
59 static struct AONCMU_T * const POSSIBLY_UNUSED aoncmu = (struct AONCMU_T *)AON_CMU_BASE;
60 #endif
61
62 #ifdef HAL_CMU_VALID_CRYSTAL_FREQ
63 static const uint32_t valid_crystal_freq_list[] = HAL_CMU_VALID_CRYSTAL_FREQ;
64 #define CRYSTAL_FREQ_ATTR BOOT_DATA_LOC
65 #else
66 #define CRYSTAL_FREQ_ATTR const
67 #endif
68
69 static uint32_t CRYSTAL_FREQ_ATTR crystal_freq = HAL_CMU_DEFAULT_CRYSTAL_FREQ;
70
hal_cmu_set_crystal_freq_index(uint32_t index)71 void BOOT_TEXT_FLASH_LOC hal_cmu_set_crystal_freq_index(uint32_t index)
72 {
73 #ifdef HAL_CMU_VALID_CRYSTAL_FREQ
74 if (index >= ARRAY_SIZE(valid_crystal_freq_list)) {
75 index %= ARRAY_SIZE(valid_crystal_freq_list);
76 }
77 crystal_freq = valid_crystal_freq_list[index];
78 #endif
79 }
80
hal_cmu_get_crystal_freq(void)81 uint32_t BOOT_TEXT_SRAM_LOC hal_cmu_get_crystal_freq(void)
82 {
83 return crystal_freq;
84 }
85
hal_cmu_get_default_crystal_freq(void)86 uint32_t BOOT_TEXT_FLASH_LOC hal_cmu_get_default_crystal_freq(void)
87 {
88 return HAL_CMU_DEFAULT_CRYSTAL_FREQ;
89 }
90
91 #ifndef CMU_FAST_TIMER_FREQ
hal_cmu_get_fast_timer_freq(void)92 uint32_t BOOT_TEXT_SRAM_LOC hal_cmu_get_fast_timer_freq(void)
93 {
94 return crystal_freq / 4;
95 }
96 #endif
97
hal_cmu_write_lock(void)98 void hal_cmu_write_lock(void)
99 {
100 cmu->WRITE_UNLOCK = 0xCAFE0000;
101 }
102
hal_cmu_write_unlock(void)103 void hal_cmu_write_unlock(void)
104 {
105 cmu->WRITE_UNLOCK = 0xCAFE0001;
106 }
107
108 #ifndef HAL_CMU_SYS_REBOOT
hal_cmu_sys_reboot(void)109 void hal_cmu_sys_reboot(void)
110 {
111 hal_cmu_reset_set(HAL_CMU_MOD_GLOBAL);
112 }
113 #endif
114
hal_cmu_simu_init(void)115 void hal_cmu_simu_init(void)
116 {
117 #if defined(CHIP_BEST1501SIMU)
118 cmu->MISC_0F8 = 0;
119 #else
120 cmu->SIMU_RES = 0;
121 #endif
122 }
123
hal_cmu_simu_pass(void)124 void hal_cmu_simu_pass(void)
125 {
126 #if defined(CHIP_BEST1501SIMU)
127 cmu->MISC_0F8 = CMU_SIMU_RES_PASSED;
128 #else
129 cmu->SIMU_RES = CMU_SIMU_RES_PASSED;
130 #endif
131 }
132
hal_cmu_simu_fail(void)133 void hal_cmu_simu_fail(void)
134 {
135 #if defined(CHIP_BEST1501SIMU)
136 cmu->MISC_0F8 = CMU_SIMU_RES_FAILED;
137 #else
138 cmu->SIMU_RES = CMU_SIMU_RES_FAILED;
139 #endif
140 }
141
hal_cmu_simu_tag(uint8_t shift)142 void hal_cmu_simu_tag(uint8_t shift)
143 {
144 #if defined(CHIP_BEST1501SIMU)
145 cmu->MISC_0F8 |= (1 << shift);
146 #else
147 cmu->SIMU_RES |= (1 << shift);
148 #endif
149 }
150
hal_cmu_simu_set_val(uint32_t val)151 void hal_cmu_simu_set_val(uint32_t val)
152 {
153 #if defined(CHIP_BEST1501SIMU)
154 cmu->MISC_0F8 = val;
155 #else
156 cmu->SIMU_RES = val;
157 #endif
158 }
159
hal_cmu_simu_get_val(void)160 uint32_t hal_cmu_simu_get_val(void)
161 {
162 #if defined(CHIP_BEST1501SIMU)
163 return cmu->MISC_0F8;
164 #else
165 return cmu->SIMU_RES;
166 #endif
167 }
168
169 #if defined(CP_BOOT) || defined(CP_BUILD)
hal_cmu_dbg_set_val(uint8_t id,uint32_t val)170 void hal_cmu_dbg_set_val(uint8_t id, uint32_t val)
171 {
172 aoncmu->DEBUG_RES[id] = val;
173 }
174
hal_cmu_dbg_get_val(uint8_t id)175 uint32_t hal_cmu_dbg_get_val(uint8_t id)
176 {
177 return aoncmu->DEBUG_RES[id];
178 }
179 #endif
180
hal_cmu_flash_all_select_pll(enum HAL_CMU_PLL_T pll)181 int BOOT_TEXT_FLASH_LOC hal_cmu_flash_all_select_pll(enum HAL_CMU_PLL_T pll)
182 {
183 hal_cmu_flash_select_pll(pll);
184 #ifdef FLASH1_CTRL_BASE
185 hal_cmu_flash1_select_pll(pll);
186 #endif
187 return 0;
188 }
189
190 #if !(defined(CHIP_SUBSYS_SENS) || (defined(CHIP_SUBSYS_BTH) && !defined(BTH_AS_MAIN_MCU)))
191
192 #if defined(CHIP_BEST1501) || defined(CHIP_BEST2000) || \
193 defined(CHIP_BEST2300) || defined(CHIP_BEST2300A) || defined(CHIP_BEST2300P)
hal_cmu_set_wakeup_pc(uint32_t pc)194 void hal_cmu_set_wakeup_pc(uint32_t pc)
195 {
196 uint32_t *wake_pc =
197 #ifdef CHIP_BEST2000
198 (uint32_t *)REGRET_BASE;
199 #else
200 (uint32_t *)&aoncmu->WAKEUP_PC;
201
202 STATIC_ASSERT(sizeof(HAL_POWER_DOWN_WAKEUP_HANDLER) <= sizeof(uint32_t), "Invalid func ptr size");
203 #endif
204
205 *wake_pc = pc;
206 }
207
hal_cmu_rom_wakeup_check(void)208 void hal_cmu_rom_wakeup_check(void)
209 {
210 union HAL_HW_BOOTMODE_T hw;
211 uint32_t sw;
212 HAL_POWER_DOWN_WAKEUP_HANDLER *wake_fn =
213 #ifdef CHIP_BEST2000
214 (HAL_POWER_DOWN_WAKEUP_HANDLER *)REGRET_BASE;
215 #else
216 (HAL_POWER_DOWN_WAKEUP_HANDLER *)&aoncmu->WAKEUP_PC;
217 #endif
218
219 hw = hal_rom_hw_bootmode_get();
220 if (hw.watchdog == 0 && hw.global == 0) {
221 sw = hal_sw_bootmode_get();
222 if ((sw & HAL_SW_BOOTMODE_POWER_DOWN_WAKEUP) && *wake_fn) {
223 (*wake_fn)();
224 }
225 }
226
227 *wake_fn = NULL;
228 }
229 #endif
230
231 #ifndef HAL_CMU_USB_ROM_SELECT_CLOCK_SOURCE
hal_cmu_usb_rom_select_clock_source(int pll_en,unsigned int crystal)232 enum HAL_CMU_USB_CLOCK_SEL_T hal_cmu_usb_rom_select_clock_source(int pll_en, unsigned int crystal)
233 {
234 enum HAL_CMU_USB_CLOCK_SEL_T sel;
235
236 if (pll_en) {
237 sel = HAL_CMU_USB_CLOCK_SEL_PLL;
238 } else {
239 if (crystal == 24000000) {
240 sel = HAL_CMU_USB_CLOCK_SEL_24M_X2;
241 } else if (crystal == 48000000) {
242 sel = HAL_CMU_USB_CLOCK_SEL_48M;
243 } else {
244 sel = HAL_CMU_USB_CLOCK_SEL_26M_X2;
245 }
246 }
247
248 hal_cmu_usb_rom_set_clock_source(sel);
249
250 return sel;
251 }
252 #endif
253
hal_cmu_flash_all_set_freq(enum HAL_CMU_FREQ_T freq)254 __STATIC_FORCEINLINE int hal_cmu_flash_all_set_freq(enum HAL_CMU_FREQ_T freq)
255 {
256 hal_cmu_flash_set_freq(freq);
257 #ifdef FLASH1_CTRL_BASE
258 hal_cmu_flash1_set_freq(freq);
259 #endif
260 return 0;
261 }
262
263 #ifdef ROM_IN_FLASH
264 SRAM_TEXT_LOC
265 #endif
hal_cmu_flash_all_reset_clear(int reset)266 void hal_cmu_flash_all_reset_clear(int reset)
267 {
268 if (reset) {
269 // Reset flash controller (for JTAG reset and run)
270 hal_cmu_reset_set(HAL_CMU_MOD_O_FLASH);
271 hal_cmu_reset_set(HAL_CMU_MOD_H_FLASH);
272 }
273 // Enable flash controller (reset by default in BEST1400)
274 hal_cmu_reset_clear(HAL_CMU_MOD_H_FLASH);
275 hal_cmu_reset_clear(HAL_CMU_MOD_O_FLASH);
276 #ifdef FLASH1_CTRL_BASE
277 if (reset) {
278 hal_cmu_reset_set(HAL_CMU_MOD_O_FLASH1);
279 hal_cmu_reset_set(HAL_CMU_MOD_H_FLASH1);
280 }
281 hal_cmu_reset_clear(HAL_CMU_MOD_H_FLASH1);
282 hal_cmu_reset_clear(HAL_CMU_MOD_O_FLASH1);
283 #endif
284 }
285
286 #ifndef HAL_CMU_PLL_T
hal_cmu_rom_enable_pll(void)287 void hal_cmu_rom_enable_pll(void)
288 {
289 #ifdef CHIP_HAS_USB
290 hal_cmu_pll_enable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_SYS);
291 hal_cmu_sys_select_pll(HAL_CMU_PLL_USB);
292 hal_cmu_flash_all_select_pll(HAL_CMU_PLL_USB);
293 #else
294 hal_cmu_pll_enable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
295 hal_cmu_sys_select_pll(HAL_CMU_PLL_AUD);
296 hal_cmu_flash_all_select_pll(HAL_CMU_PLL_AUD);
297 #endif
298 }
299
hal_cmu_programmer_enable_pll(void)300 void hal_cmu_programmer_enable_pll(void)
301 {
302 hal_cmu_pll_enable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
303 hal_cmu_flash_all_select_pll(HAL_CMU_PLL_AUD);
304 hal_cmu_sys_select_pll(HAL_CMU_PLL_AUD);
305 }
306
hal_cmu_init_pll_selection(void)307 void BOOT_TEXT_FLASH_LOC hal_cmu_init_pll_selection(void)
308 {
309 // !!!!!!
310 // CAUTION:
311 // hal_cmu_pll_enable()/hal_cmu_pll_disable() must be called after hal_chipid_init(),
312 // for the init div values are extracted in hal_chipid_init().
313 // !!!!!!
314
315 #if defined(CHIP_BEST1000) || defined(CHIP_BEST2000)
316 #ifdef CHIP_HAS_USB
317 // Enable USB PLL before switching (clock mux requirement)
318 // -- USB PLL might not be started in ROM
319 hal_cmu_pll_enable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_SYS);
320 #endif
321 hal_cmu_pll_enable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
322 #else // !(best1000 || best2000)
323 // Disable the PLL which might be enabled in ROM
324 #ifdef CHIP_HAS_USB
325 hal_cmu_pll_disable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_ALL);
326 #else
327 hal_cmu_pll_disable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_ALL);
328 #endif
329 #endif // !(best1000 || best2000)
330
331 #ifdef FLASH_LOW_SPEED
332 #ifdef CHIP_HAS_USB
333 // Switch flash clock to USB PLL, and then shutdown USB PLL,
334 // to save power consumed in clock divider
335 hal_cmu_flash_all_select_pll(HAL_CMU_PLL_USB);
336 #endif
337 #else
338 // Switch flash clock to audio PLL
339 hal_cmu_flash_all_select_pll(HAL_CMU_PLL_AUD);
340 #endif
341
342 #ifdef CHIP_HAS_PSRAM
343 #ifdef PSRAM_LOW_SPEED
344 #ifdef CHIP_HAS_USB
345 // Switch psram clock to USB PLL, and then shutdown USB PLL,
346 // to save power consumed in clock divider
347 hal_cmu_mem_select_pll(HAL_CMU_PLL_USB);
348 #endif
349 #else
350 // Switch psram clock to audio PLL
351 hal_cmu_mem_select_pll(HAL_CMU_PLL_AUD);
352 #endif
353 #endif
354
355 // Select system PLL after selecting flash/psram PLLs
356 #ifdef ULTRA_LOW_POWER
357 hal_cmu_low_freq_mode_init();
358 #else
359 #if defined(MCU_HIGH_PERFORMANCE_MODE) && defined(CHIP_HAS_USB)
360 // Switch system clocks to USB PLL
361 hal_cmu_sys_select_pll(HAL_CMU_PLL_USB);
362 #else
363 // Switch system clocks to audio PLL
364 hal_cmu_sys_select_pll(HAL_CMU_PLL_AUD);
365 #endif
366 #endif
367
368 #if defined(CHIP_BEST1000) || defined(CHIP_BEST2000)
369 #ifndef USB_PLL_INIT_ON
370 // Disable USB PLL after switching (clock mux requirement)
371 hal_cmu_pll_disable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_SYS);
372 #endif
373 #ifndef AUD_PLL_INIT_ON
374 hal_cmu_pll_disable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
375 #endif
376 #else // !(best1000 || best2000)
377 #ifdef USB_PLL_INIT_ON
378 hal_cmu_pll_enable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_SYS);
379 #endif
380 #ifdef AUD_PLL_INIT_ON
381 hal_cmu_pll_enable(HAL_CMU_PLL_AUD, HAL_CMU_PLL_USER_SYS);
382 #endif
383 #endif // !(best1000 || best2000)
384
385 #if defined(MCU_HIGH_PERFORMANCE_MODE) && !defined(ULTRA_LOW_POWER) && defined(OSC_26M_X4_AUD2BB)
386 #error "Error configuration: MCU_HIGH_PERFORMANCE_MODE has no effect"
387 #endif
388 }
389 #endif // !HAL_CMU_PLL_T
390
hal_cmu_init_periph_clock(void)391 static void BOOT_TEXT_FLASH_LOC hal_cmu_init_periph_clock(void)
392 {
393 #ifdef PERIPH_PLL_FREQ
394 hal_cmu_periph_set_div(1);
395 #endif
396
397 // TODO: Move the following SDIO freq setting to hal_sdio.c
398 #ifdef CHIP_HAS_SDIO
399 hal_cmu_sdio_set_freq(HAL_CMU_PERIPH_FREQ_26M);
400 #endif
401 }
402
403 #ifdef ROM_IN_FLASH
404 SRAM_TEXT_LOC
405 #endif
hal_cmu_rom_setup(void)406 void hal_cmu_rom_setup(void)
407 {
408 int reset_flash;
409
410 hal_cmu_lpu_wait_26m_ready();
411 hal_cmu_simu_init();
412 hal_cmu_rom_clock_init();
413 hal_sys_timer_open();
414
415 // Init sys clock
416 hal_cmu_sys_set_freq(HAL_CMU_FREQ_26M);
417
418 #ifdef ROM_IN_FLASH
419 // Wait until norflash becomes idle
420 hal_sys_timer_delay(MS_TO_TICKS(3));
421 #endif
422 // Init flash clock (this should be done before load_boot_settings, for security register read)
423 #ifndef CHIP_BEST1501SIMU
424 hal_cmu_flash_all_set_freq(HAL_CMU_FREQ_26M);
425 #endif
426 #ifdef ROM_IN_FLASH
427 reset_flash = false;
428 #else
429 reset_flash = true;
430 #endif
431 hal_cmu_flash_all_reset_clear(reset_flash);
432
433 // TODO: Check why system crashes when ROM_IN_FLASH=1 and INSRAM_RUN=0
434 // Disable cache (for JTAG reset and run)
435 hal_cache_disable(HAL_CACHE_ID_I_CACHE);
436 hal_cache_disable(HAL_CACHE_ID_D_CACHE);
437
438 // Init APB clock
439 hal_cmu_apb_init_div();
440 }
441
hal_cmu_programmer_setup(void)442 void hal_cmu_programmer_setup(void)
443 {
444 #ifdef JTAG_ENABLE
445 hal_iomux_set_jtag();
446 hal_cmu_jtag_clock_enable();
447 #endif
448
449 hal_cmu_ema_init();
450 hal_sys_timer_open();
451
452 // Init system/flash/memory clocks before initializing clock setting
453 // and before switching PLL
454 hal_cmu_flash_all_set_freq(HAL_CMU_FREQ_26M);
455 hal_cmu_mem_set_freq(HAL_CMU_FREQ_26M);
456 hal_cmu_sys_set_freq(HAL_CMU_FREQ_26M);
457
458 #ifndef FPGA
459 int ret;
460 // Open analogif (ISPI)
461 ret = hal_analogif_open();
462 if (ret) {
463 hal_cmu_simu_tag(31);
464 do { volatile int i = 0; i++; } while (1);
465 }
466 // Init chip id
467 // 1) Read id from ana/rf/pmu
468 // 2) Init clock settings in ana/rf/pmu if the default h/w register values are bad
469 hal_chipid_init();
470
471 // Enable OSC X2/X4 in cmu after enabling their source in hal_chipid_init()
472 hal_cmu_osc_x2_enable();
473 hal_cmu_osc_x4_enable();
474
475 // Enable PLL for flash (and system)
476 hal_cmu_programmer_enable_pll();
477 #endif
478 }
479
480 #ifdef FPGA
481
hal_cmu_fpga_setup(void)482 void BOOT_TEXT_FLASH_LOC hal_cmu_fpga_setup(void)
483 {
484 hal_sys_timer_open();
485 hal_sysfreq_req(HAL_SYSFREQ_USER_INIT, HAL_CMU_FREQ_52M);
486
487 hal_cmu_apb_init_div();
488 hal_cmu_ispi_set_freq(HAL_CMU_PERIPH_FREQ_26M);
489
490 // Init peripheral clocks
491 hal_cmu_init_periph_clock();
492 #if !defined(CHIP_BEST1501SIMU)
493 hal_norflash_init();
494 #endif
495 #if defined(CHIP_BEST1501SIMU)
496 hal_cmu_module_init_state();
497 #endif
498 }
499
500 #else // !FPGA
501
hal_cmu_setup(void)502 void BOOT_TEXT_FLASH_LOC hal_cmu_setup(void)
503 {
504 POSSIBLY_UNUSED int ret;
505 enum HAL_CMU_FREQ_T freq;
506
507 #ifndef ARM_CMNS
508 hal_iomux_set_default_config();
509 #endif
510
511 #ifdef JTAG_ENABLE
512 hal_iomux_set_jtag();
513 hal_cmu_jtag_clock_enable();
514 #endif
515 #ifdef CLOCK_OUT_ID
516 hal_iomux_set_clock_out();
517 hal_cmu_clock_out_enable(CLOCK_OUT_ID);
518 #endif
519
520 hal_cmu_ema_init();
521 hal_cmu_module_init_state();
522 hal_sys_timer_open();
523 hal_hw_bootmode_init();
524 #ifndef __MCU_FW_2002__
525 #if !defined(ARM_CMNS)
526 // Init system/flash/memory clocks before initializing clock setting
527 // and before switching PLL
528 hal_norflash_set_boot_freq(HAL_CMU_FREQ_26M);
529 #endif
530 #endif
531 hal_cmu_mem_set_freq(HAL_CMU_FREQ_26M);
532 hal_cmu_sys_set_freq(HAL_CMU_FREQ_26M);
533
534 // Set ISPI module freq
535 hal_cmu_ispi_set_freq(HAL_CMU_PERIPH_FREQ_26M);
536 // Open analogif (ISPI)
537 ret = hal_analogif_open();
538 if (ret) {
539 hal_cmu_simu_tag(31);
540 do { volatile int i = 0; i++; } while (1);
541 }
542 // Init chip id
543 // 1) Read id from ana/rf/pmu
544 // 2) Init clock settings in ana/rf/pmu if the default h/w register values are bad
545 hal_chipid_init();
546
547 #ifdef CALIB_SLOW_TIMER
548 // Calib slow timer after determining the crystal freq
549 hal_sys_timer_calib();
550 #endif
551
552 // Enable OSC X2/X4 in cmu after enabling their source in hal_chipid_init()
553 hal_cmu_osc_x2_enable();
554 hal_cmu_osc_x4_enable();
555
556 // Init PLL selection
557 hal_cmu_init_pll_selection();
558
559 // Init peripheral clocks
560 hal_cmu_init_periph_clock();
561
562 // Sleep setting
563 #ifdef NO_LPU_26M
564 while (hal_cmu_lpu_init(HAL_CMU_LPU_CLK_NONE) == -1);
565 #else
566 while (hal_cmu_lpu_init(HAL_CMU_LPU_CLK_26M) == -1);
567 #endif
568 // Init sys freq after applying the sleep setting (which might change sys freq)
569 #ifdef NO_LPU_26M
570 hal_sys_timer_delay(MS_TO_TICKS(20));
571 #endif
572
573 // Init system clock
574 #ifdef ULTRA_LOW_POWER
575 freq = HAL_CMU_FREQ_52M;
576 #else
577 freq = HAL_CMU_FREQ_104M;
578 #endif
579 hal_sysfreq_req(HAL_SYSFREQ_USER_INIT, freq);
580 #ifndef __MCU_FW_2002__
581 // Init flash
582 #if !defined(ARM_CMNS)
583 hal_norflash_init();
584 #endif
585 #endif
586 }
587
588 #endif // !FPGA
589
590 #endif // !CHIP_SUBSYS_SENS
591
592