1 /*
2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include "plat_addr_map.h"
16 #include CHIP_SPECIFIC_HDR(reg_iomux)
17 #include "hal_iomux.h"
18 #include "hal_chipid.h"
19 #include "hal_gpio.h"
20 #include "hal_location.h"
21 #include "hal_timer.h"
22 #include "hal_trace.h"
23 #include "hal_uart.h"
24 #include "pmu.h"
25 #include "hal_chipid.h"
26
27 #define UART_HALF_DUPLEX
28
29 #ifdef I2S0_VOLTAGE_VMEM
30 #define I2S0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
31 #else
32 #define I2S0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
33 #endif
34
35 #ifdef I2S1_VOLTAGE_VMEM
36 #define I2S1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
37 #else
38 #define I2S1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
39 #endif
40
41 #ifdef SPDIF0_VOLTAGE_VMEM
42 #define SPDIF0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
43 #else
44 #define SPDIF0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
45 #endif
46
47 #ifdef DIGMIC_VOLTAGE_VMEM
48 #define DIGMIC_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
49 #else
50 #define DIGMIC_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
51 #endif
52
53 #ifdef SPI_VOLTAGE_VMEM
54 #define SPI_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
55 #else
56 #define SPI_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
57 #endif
58
59 #ifdef SPILCD_VOLTAGE_VMEM
60 #define SPILCD_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
61 #else
62 #define SPILCD_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
63 #endif
64
65 #ifdef I2C0_VOLTAGE_VMEM
66 #define I2C0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
67 #else
68 #define I2C0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
69 #endif
70
71 #ifdef I2C1_VOLTAGE_VMEM
72 #define I2C1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
73 #else
74 #define I2C1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
75 #endif
76
77 #ifdef I2C2_VOLTAGE_VMEM
78 #define I2C2_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
79 #else
80 #define I2C2_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
81 #endif
82
83 #ifdef CLKOUT_VOLTAGE_VMEM
84 #define CLKOUT_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
85 #else
86 #define CLKOUT_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
87 #endif
88
89 #ifdef PWM0_VOLTAGE_VMEM
90 #define PWM0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
91 #else
92 #define PWM0_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
93 #endif
94
95 #ifdef PWM1_VOLTAGE_VMEM
96 #define PWM1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
97 #else
98 #define PWM1_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
99 #endif
100
101 #ifdef PWM2_VOLTAGE_VMEM
102 #define PWM2_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
103 #else
104 #define PWM2_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
105 #endif
106
107 #ifdef PWM3_VOLTAGE_VMEM
108 #define PWM3_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
109 #else
110 #define PWM3_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
111 #endif
112
113 #ifdef PWM4_VOLTAGE_VMEM
114 #define PWM4_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
115 #else
116 #define PWM4_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
117 #endif
118
119 #ifdef PWM5_VOLTAGE_VMEM
120 #define PWM5_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
121 #else
122 #define PWM5_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
123 #endif
124
125 #ifdef PWM6_VOLTAGE_VMEM
126 #define PWM6_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
127 #else
128 #define PWM6_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
129 #endif
130
131 #ifdef PWM7_VOLTAGE_VMEM
132 #define PWM7_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
133 #else
134 #define PWM7_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
135 #endif
136
137 #ifdef IR_VOLTAGE_VMEM
138 #define IR_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
139 #else
140 #define IR_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
141 #endif
142
143 #ifdef SDMMC_VOLTAGE_VMEM
144 #define SDMMC_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_MEM
145 #else
146 #define SDMMC_VOLTAGE_SEL HAL_IOMUX_PIN_VOLTAGE_VIO
147 #endif
148
149 #ifndef I2S0_I_IOMUX_INDEX
150 //00, 13, 37
151 #define I2S0_I_IOMUX_INDEX 00
152 #endif
153 #ifndef I2S0_I1_IOMUX_INDEX
154 //12, 36
155 //#define I2S0_I1_IOMUX_INDEX 12
156 #endif
157 #ifndef I2S0_I2_IOMUX_INDEX
158 //11, 35
159 //#define I2S0_I2_IOMUX_INDEX 11
160 #endif
161 #ifndef I2S0_I3_IOMUX_INDEX
162 //10, 35
163 //#define I2S0_I3_IOMUX_INDEX 10
164 #endif
165
166 #ifndef I2S0_O_IOMUX_INDEX
167 //01, 07
168 #define I2S0_O_IOMUX_INDEX 01
169 #endif
170 #ifndef I2S0_O1_IOMUX_INDEX
171 //06
172 #define I2S0_O1_IOMUX_INDEX 06
173 #endif
174 #ifndef I2S0_O2_IOMUX_INDEX
175 //05
176 #define I2S0_O2_IOMUX_INDEX 05
177 #endif
178 #ifndef I2S0_O3_IOMUX_INDEX
179 //04
180 #define I2S0_O3_IOMUX_INDEX 04
181 #endif
182
183 #ifndef I2S1_I_IOMUX_INDEX
184 //20, 33
185 #define I2S1_I_IOMUX_INDEX 20
186 #endif
187 #ifndef I2S1_I1_IOMUX_INDEX
188 //32
189 //#define I2S1_I1_IOMUX_INDEX 32
190 #endif
191 #ifndef I2S1_I2_IOMUX_INDEX
192 //31
193 //#define I2S1_I2_IOMUX_INDEX 31
194 #endif
195 #ifndef I2S1_I3_IOMUX_INDEX
196 //30
197 //#define I2S1_I3_IOMUX_INDEX 30
198 #endif
199
200 #ifndef I2S1_O_IOMUX_INDEX
201 //21, 27
202 #define I2S1_O_IOMUX_INDEX 21
203 #endif
204 #ifndef I2S1_O1_IOMUX_INDEX
205 //26
206 #define I2S1_O1_IOMUX_INDEX 26
207 #endif
208 #ifndef I2S1_O2_IOMUX_INDEX
209 //25
210 #define I2S1_O2_IOMUX_INDEX 25
211 #endif
212 #ifndef I2S1_O3_IOMUX_INDEX
213 //24
214 #define I2S1_O3_IOMUX_INDEX 24
215 #endif
216
217 #ifndef I2S_MCLK_IOMUX_INDEX
218 //04, 13, 15, 20, 22, 27, 34
219 #define I2S_MCLK_IOMUX_INDEX 04
220 #endif
221
222 #ifndef SPDIF0_I_IOMUX_INDEX
223 //02, 10, 20, 26, 37, 24
224 #define SPDIF0_I_IOMUX_INDEX 02
225 #endif
226
227 #ifndef SPDIF0_O_IOMUX_INDEX
228 //03, 11, 21, 27, 37, 07
229 #define SPDIF0_O_IOMUX_INDEX 03
230 #endif
231
232 #ifndef DIG_MIC_CK_IOMUX_PIN
233 //HAL_IOMUX_PIN_P0_0, HAL_IOMUX_PIN_P0_4, HAL_IOMUX_PIN_P3_3, HAL_IOMUX_PIN_P3_4
234 #define DIG_MIC_CK_IOMUX_PIN 0
235 #endif
236
237 #ifndef DIG_MIC_D0_IOMUX_PIN
238 //HAL_IOMUX_PIN_P0_1, HAL_IOMUX_PIN_P0_5, HAL_IOMUX_PIN_P3_0, HAL_IOMUX_PIN_P3_5
239 #define DIG_MIC_D0_IOMUX_PIN 1
240 #endif
241
242 #ifndef DIG_MIC_D1_IOMUX_PIN
243 //HAL_IOMUX_PIN_P0_2, HAL_IOMUX_PIN_P0_6, HAL_IOMUX_PIN_P3_1, HAL_IOMUX_PIN_P3_6
244 #define DIG_MIC_D1_IOMUX_PIN 2
245 #endif
246
247 #ifndef DIG_MIC_D2_IOMUX_PIN
248 //HAL_IOMUX_PIN_P0_3, HAL_IOMUX_PIN_P0_7, HAL_IOMUX_PIN_P3_2, HAL_IOMUX_PIN_P3_7
249 #define DIG_MIC_D2_IOMUX_PIN 3
250 #endif
251
252 #ifndef SPI_IOMUX_INDEX
253 //04(05,06,07), 24(25,26,27), 30(31,32,33)
254 #define SPI_IOMUX_INDEX 04
255 #endif
256
257 #ifndef SPI_IOMUX_CS1_INDEX
258 //10, 35
259 //#define SPI_IOMUX_CS1_INDEX 10
260 #endif
261 #ifndef SPI_IOMUX_CS2_INDEX
262 //11, 37
263 //#define SPI_IOMUX_CS2_INDEX 11
264 #endif
265 #ifndef SPI_IOMUX_CS3_INDEX
266 //12, 25
267 //#define SPI_IOMUX_CS3_INDEX 12
268 #endif
269
270 #ifndef SPI_IOMUX_DI1_INDEX
271 //13, 34
272 //#define SPI_IOMUX_DI1_INDEX 13
273 #endif
274 #ifndef SPI_IOMUX_DI2_INDEX
275 //14, 36
276 //#define SPI_IOMUX_DI2_INDEX 14
277 #endif
278 #ifndef SPI_IOMUX_DI3_INDEX
279 //15, 24
280 //#define SPI_IOMUX_DI3_INDEX 15
281 #endif
282
283 #ifndef SPILCD_IOMUX_INDEX
284 //00(01,02,03), 10(11,14,15), 20(21,22,23), 34(35,36,37)
285 #define SPILCD_IOMUX_INDEX 0
286 #endif
287
288 #ifndef SPILCD_IOMUX_CS1_INDEX
289 //05, 12, 27
290 //#define SPILCD_IOMUX_CS1_INDEX 05
291 #endif
292 #ifndef SPILCD_IOMUX_CS2_INDEX
293 //06, 31
294 //#define SPILCD_IOMUX_CS2_INDEX 06
295 #endif
296 #ifndef SPILCD_IOMUX_CS3_INDEX
297 //07, 32
298 //#define SPILCD_IOMUX_CS3_INDEX 07
299 #endif
300
301 #ifndef SPILCD_IOMUX_DI1_INDEX
302 //02, 26
303 //#define SPILCD_IOMUX_DI1_INDEX 02
304 #endif
305 #ifndef SPILCD_IOMUX_DI2_INDEX
306 //03, 30
307 //#define SPILCD_IOMUX_DI2_INDEX 03
308 #endif
309 #ifndef SPILCD_IOMUX_DI3_INDEX
310 //04, 33
311 //#define SPILCD_IOMUX_DI3_INDEX 04
312 #endif
313
314 #ifndef I2C0_IOMUX_INDEX
315 //00(01), 04(05), 16(17), 20(21), 26(27), 34(35)
316 #define I2C0_IOMUX_INDEX 4
317 #endif
318
319 #ifndef I2C1_IOMUX_INDEX
320 //02(03), 06(07), 14(15), 22(23), 30(31)
321 #define I2C1_IOMUX_INDEX 22
322 #endif
323
324 #ifndef I2C2_IOMUX_INDEX
325 //10(11), 12(13), 24(25), 32(33), 36(37)
326 #define I2C2_IOMUX_INDEX 10
327 #endif
328
329 #ifndef CLKOUT_IOMUX_INDEX
330 //04, 13, 15, 20, 21, 22, 23, 27, 34
331 #define CLKOUT_IOMUX_INDEX 20
332 #endif
333
334 #ifndef UART1_IOMUX_INDEX
335 //02, 10, 20, 30, 32
336 #define UART1_IOMUX_INDEX 20
337 #endif
338
339 #ifndef UART2_IOMUX_INDEX
340 //00, 12, 14, 22, 36
341 #define UART2_IOMUX_INDEX 22
342 #endif
343
344 #ifndef UART3_IOMUX_INDEX
345 //04, 06, 24, 26, 34
346 #define UART3_IOMUX_INDEX 04
347 #endif
348
349 #ifndef PWM0_IOMUX_INDEX
350 //00, 10, 20, 30
351 #define PWM0_IOMUX_INDEX 00
352 #endif
353
354 #ifndef PWM1_IOMUX_INDEX
355 //01, 11, 21, 31
356 #define PWM1_IOMUX_INDEX 01
357 #endif
358
359 #ifndef PWM2_IOMUX_INDEX
360 //02, 12, 22, 32
361 #define PWM2_IOMUX_INDEX 02
362 #endif
363
364 #ifndef PWM3_IOMUX_INDEX
365 //03, 13, 23, 33
366 #define PWM3_IOMUX_INDEX 03
367 #endif
368
369 #ifndef PWM4_IOMUX_INDEX
370 //04, 14, 24, 34
371 #define PWM4_IOMUX_INDEX 04
372 #endif
373
374 #ifndef PWM5_IOMUX_INDEX
375 //05, 15, 25, 35
376 #define PWM5_IOMUX_INDEX 05
377 #endif
378
379 #ifndef PWM6_IOMUX_INDEX
380 //06, 16, 26, 36
381 #define PWM6_IOMUX_INDEX 06
382 #endif
383
384 #ifndef PWM7_IOMUX_INDEX
385 //07, 17, 27, 37
386 #define PWM7_IOMUX_INDEX 07
387 #endif
388
389 #ifndef IR_RX_IOMUX_INDEX
390 //00, 02, 06, 10, 12, 14, 22, 26, 31, 33, 36
391 #define IR_RX_IOMUX_INDEX 00
392 #endif
393
394 #ifndef IR_TX_IOMUX_INDEX
395 //01, 03, 07, 11, 13, 15, 21, 27, 32, 34, 37
396 #define IR_TX_IOMUX_INDEX 01
397 #endif
398
399 #define IOMUX_FUNC_VAL_GPIO 15
400
401 #define IOMUX_ALT_FUNC_NUM 11
402
403 // Other func values: 2 -> uart rtx/ctx, 12 -> btdm, 13 -> wf_fem, 14 -> tport, 15 -> gpio
404 static const uint8_t index_to_func_val[IOMUX_ALT_FUNC_NUM] = {
405 0, 1, 3, 4,
406 5, 6, 7, 8,
407 9, 10, 11
408 };
409
410 static const enum HAL_IOMUX_FUNCTION_T pin_func_map[HAL_IOMUX_PIN_NUM][IOMUX_ALT_FUNC_NUM] = {
411 // P0_0
412 { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
413 HAL_IOMUX_FUNC_SPILCD_DCN, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
414 HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM0_CK, HAL_IOMUX_FUNC_I2S0_SDI0, },
415 // P0_1
416 { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
417 HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
418 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDO0, },
419 // P0_2
420 { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
421 HAL_IOMUX_FUNC_SPILCD_DI1, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_BL_EN,
422 HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_WS, },
423 // P0_3
424 { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
425 HAL_IOMUX_FUNC_SPILCD_DI2, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_BL_PWM,
426 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SCK, },
427 // P0_4
428 { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPI_DI0,
429 HAL_IOMUX_FUNC_SPILCD_DI3, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_SPI_DCN,
430 HAL_IOMUX_FUNC_SDMMC_DATA7, HAL_IOMUX_FUNC_PDM1_CK, HAL_IOMUX_FUNC_I2S0_SDO3, },
431 // P0_5
432 { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPI_CLK,
433 HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_CLK, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_TE,
434 HAL_IOMUX_FUNC_SDMMC_DATA6, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDO2, },
435 // P0_6
436 { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPI_CS0,
437 HAL_IOMUX_FUNC_SPILCD_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_CS, HAL_IOMUX_FUNC_WF_WAKE_HOST, HAL_IOMUX_FUNC_IR_RX,
438 HAL_IOMUX_FUNC_SDMMC_DATA5, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_SDO1, },
439 // P0_7
440 { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPI_DIO,
441 HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DIO, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_IR_TX,
442 HAL_IOMUX_FUNC_SDMMC_DATA4, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SDO0, },
443 // P1_0
444 { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CLK,
445 HAL_IOMUX_FUNC_SPI_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_DO1_DCN, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_WF_SDIO_CLK,
446 HAL_IOMUX_FUNC_SDMMC_DATA2, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S0_SDI3, },
447 // P1_1
448 { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_CS0,
449 HAL_IOMUX_FUNC_SPI_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_DO2, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_WF_SDIO_CMD,
450 HAL_IOMUX_FUNC_SDMMC_DATA3, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S0_SDI2, },
451 // P1_2
452 { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CS1,
453 HAL_IOMUX_FUNC_SPI_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO3, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_WF_SDIO_DATA0,
454 HAL_IOMUX_FUNC_SDMMC_CMD, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_I2S0_SDI1, },
455 // P1_3
456 { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_DCN,
457 HAL_IOMUX_FUNC_SPI_DI1, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_SDIO_DATA1,
458 HAL_IOMUX_FUNC_SDMMC_CLK, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_I2S0_SDI0, },
459 // P1_4
460 { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
461 HAL_IOMUX_FUNC_SPI_DI2, HAL_IOMUX_FUNC_DISPLAY_SPI_DI, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_WF_SDIO_DATA2,
462 HAL_IOMUX_FUNC_SDMMC_DATA0, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_DISPLAY_TE, },
463 // P1_5
464 { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
465 HAL_IOMUX_FUNC_SPI_DI3, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_SDIO_DATA3,
466 HAL_IOMUX_FUNC_SDMMC_DATA1, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_DISPLAY_TE, },
467 // P1_6
468 { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART0_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_NONE,
469 HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_WF_WAKE_HOST,
470 HAL_IOMUX_FUNC_BT_UART_RX, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
471 // P1_7
472 { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART0_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_NONE,
473 HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
474 HAL_IOMUX_FUNC_BT_UART_TX, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
475 // P2_0
476 { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
477 HAL_IOMUX_FUNC_SPILCD_DCN, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_RX,
478 HAL_IOMUX_FUNC_BT_UART_RX, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S1_SDI0, },
479 // P2_1
480 { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
481 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_TX,
482 HAL_IOMUX_FUNC_BT_UART_TX, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S1_SDO0, },
483 // P2_2
484 { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
485 HAL_IOMUX_FUNC_DISPLAY_BL_EN, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_CTS,
486 HAL_IOMUX_FUNC_BT_UART_CTS, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_I2S1_WS, },
487 // P2_3
488 { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
489 HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_DISPLAY_BL_PWM, HAL_IOMUX_FUNC_PCM_DI, HAL_IOMUX_FUNC_WF_UART_RTS,
490 HAL_IOMUX_FUNC_BT_UART_RTS, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_I2S1_SCK, },
491 // P2_4
492 { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPI_DI0,
493 HAL_IOMUX_FUNC_SPI_DI3, HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_PCM_DO, HAL_IOMUX_FUNC_SPDIF0_DI,
494 HAL_IOMUX_FUNC_WF_SDIO_CLK, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_I2S1_SDO3, },
495 // P2_5
496 { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPI_DIO,
497 HAL_IOMUX_FUNC_SPI_CS3, HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_PCM_FSYNC, HAL_IOMUX_FUNC_NONE,
498 HAL_IOMUX_FUNC_WF_SDIO_CMD, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_I2S1_SDO2, },
499 // P2_6
500 { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPI_CS0,
501 HAL_IOMUX_FUNC_SPILCD_DI1, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_PCM_CLK, HAL_IOMUX_FUNC_IR_RX,
502 HAL_IOMUX_FUNC_WF_SDIO_DATA0, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S1_SDO1, },
503 // P2_7
504 { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPI_CLK,
505 HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_IR_TX,
506 HAL_IOMUX_FUNC_WF_SDIO_DATA1, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S1_SDO0, },
507 // P3_0
508 { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPI_DI0,
509 HAL_IOMUX_FUNC_SPILCD_DI2, HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_WF_UART_RX, HAL_IOMUX_FUNC_SPILCD_CS1,
510 HAL_IOMUX_FUNC_WF_SDIO_DATA2, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S1_SDI3, },
511 // P3_1
512 { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPI_DIO,
513 HAL_IOMUX_FUNC_WF_SDIO_DATA0, HAL_IOMUX_FUNC_DISPLAY_SPI_DI, HAL_IOMUX_FUNC_WF_UART_TX, HAL_IOMUX_FUNC_IR_RX,
514 HAL_IOMUX_FUNC_WF_SDIO_DATA3, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S1_SDI2, },
515 // P3_2
516 { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPI_CS0,
517 HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO3, HAL_IOMUX_FUNC_WF_UART_CTS, HAL_IOMUX_FUNC_IR_TX,
518 HAL_IOMUX_FUNC_WF_WAKE_HOST, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S1_SDI1, },
519 // P3_3
520 { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPI_CLK,
521 HAL_IOMUX_FUNC_SPILCD_DI3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO2, HAL_IOMUX_FUNC_WF_UART_RTS, HAL_IOMUX_FUNC_SPILCD_DCN,
522 HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM2_CK, HAL_IOMUX_FUNC_I2S1_SDI0, },
523 // P3_4
524 { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
525 HAL_IOMUX_FUNC_SPI_DI1, HAL_IOMUX_FUNC_DISPLAY_SPI_DO1_DCN, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_SPILCD_DCN,
526 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM0_CK, HAL_IOMUX_FUNC_I2S0_SDI3, },
527 // P3_5
528 { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
529 HAL_IOMUX_FUNC_SPI_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_DIO, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_NONE,
530 HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDI2, },
531 // P3_6
532 { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
533 HAL_IOMUX_FUNC_SPI_DI2, HAL_IOMUX_FUNC_DISPLAY_SPI_CS, HAL_IOMUX_FUNC_CLK_REQ_OUT, HAL_IOMUX_FUNC_SPDIF0_DI,
534 HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_SDI1, },
535 // P3_7
536 { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
537 HAL_IOMUX_FUNC_SPI_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_CLK, HAL_IOMUX_FUNC_CLK_REQ_IN, HAL_IOMUX_FUNC_SPDIF0_DO,
538 HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SDI0, },
539 };
540
541 static struct IOMUX_T * const iomux = (struct IOMUX_T *)IOMUX_BASE;
542
543 #ifdef ANC_PROD_TEST
544 #define OPT_TYPE
545 #else
546 #define OPT_TYPE const
547 #endif
548
549 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_ck_pin = DIG_MIC_CK_IOMUX_PIN;
550
551 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d0_pin = DIG_MIC_D0_IOMUX_PIN;
552 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d1_pin = DIG_MIC_D1_IOMUX_PIN;
553 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d2_pin = DIG_MIC_D2_IOMUX_PIN;
554
hal_iomux_set_default_config(void)555 void hal_iomux_set_default_config(void)
556 {
557 uint32_t i;
558 // Set all unused GPIOs to pull-down by default
559 for (i = 0; i < 8; i++) {
560 if (((iomux->REG_004 & (0xF << (i * 4))) >> (i * 4)) == 0xF) {
561 iomux->REG_02C &= ~(1 << i);
562 iomux->REG_030 |= (1 << i);
563 }
564 }
565 for (i = 0; i < 6; i++) {
566 if (((iomux->REG_008 & (0xF << (i * 4))) >> (i * 4)) == 0xF) {
567 iomux->REG_02C &= ~(1 << (i + 8));
568 iomux->REG_030 |= (1 << (i + 8));
569 }
570 }
571 for (i = 0; i < 8; i++) {
572 if (((iomux->REG_00C & (0xF << (i * 4))) >> (i * 4)) == 0xF) {
573 iomux->REG_02C &= ~(1 << (i + 16));
574 iomux->REG_030 |= (1 << (i + 16));
575 }
576 }
577 for (i = 0; i < 8; i++) {
578 if (((iomux->REG_010 & (0xF << (i * 4))) >> (i * 4)) == 0xF) {
579 iomux->REG_02C &= ~(1 << (i + 24));
580 iomux->REG_030 |= (1 << (i + 24));
581 }
582 }
583 }
584
hal_iomux_check(const struct HAL_IOMUX_PIN_FUNCTION_MAP * map,uint32_t count)585 uint32_t hal_iomux_check(const struct HAL_IOMUX_PIN_FUNCTION_MAP *map, uint32_t count)
586 {
587 uint32_t i;
588 for (i = 0; i < count; ++i) {
589 }
590 return 0;
591 }
592
hal_iomux_init(const struct HAL_IOMUX_PIN_FUNCTION_MAP * map,uint32_t count)593 uint32_t hal_iomux_init(const struct HAL_IOMUX_PIN_FUNCTION_MAP *map, uint32_t count)
594 {
595 uint32_t i;
596 uint32_t ret;
597
598 if (map == NULL)
599 return 1;
600
601 for (i = 0; i < count; ++i) {
602 ret = hal_iomux_set_function(map[i].pin, map[i].function, HAL_IOMUX_OP_CLEAN_OTHER_FUNC_BIT);
603 if (ret) {
604 return (i << 8) + 1;
605 }
606 ret = hal_iomux_set_io_voltage_domains(map[i].pin, map[i].volt);
607 if (ret) {
608 return (i << 8) + 2;
609 }
610 ret = hal_iomux_set_io_pull_select(map[i].pin, map[i].pull_sel);
611 if (ret) {
612 return (i << 8) + 3;
613 }
614 }
615
616 return 0;
617 }
618
hal_iomux_set_function(enum HAL_IOMUX_PIN_T pin,enum HAL_IOMUX_FUNCTION_T func,enum HAL_IOMUX_OP_TYPE_T type)619 uint32_t hal_iomux_set_function(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_FUNCTION_T func, enum HAL_IOMUX_OP_TYPE_T type)
620 {
621 int i;
622 uint8_t val;
623 __IO uint32_t *reg;
624 uint32_t shift;
625
626 if (pin >= HAL_IOMUX_PIN_LED_NUM) {
627 return 1;
628 }
629 if (func >= HAL_IOMUX_FUNC_END) {
630 return 2;
631 }
632
633 if (pin == HAL_IOMUX_PIN_P1_6 || pin == HAL_IOMUX_PIN_P1_7) {
634 if (func == HAL_IOMUX_FUNC_I2C_M0_SCL || func == HAL_IOMUX_FUNC_I2C_M0_SDA) {
635 // Enable analog I2C slave
636 #ifndef FPGA
637 iomux->REG_050 &= ~IOMUX_GPIO_I2C_MODE;
638 #endif
639 // Set mcu GPIO func
640 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P16_SEL_MASK | IOMUX_GPIO_P17_SEL_MASK)) |
641 IOMUX_GPIO_P16_SEL(IOMUX_FUNC_VAL_GPIO) | IOMUX_GPIO_P17_SEL(IOMUX_FUNC_VAL_GPIO);
642 return 0;
643 } else {
644 #ifndef FPGA
645 iomux->REG_050 |= IOMUX_GPIO_I2C_MODE;
646 #endif
647 // Continue to set the alt func
648 }
649 } else if (pin == HAL_IOMUX_PIN_P0_2) {
650 if (func == HAL_IOMUX_FUNC_SPDIF0_DI) {
651 iomux->REG_004 = SET_BITFIELD(iomux->REG_004, IOMUX_GPIO_P02_SEL, 6);
652 return 0;
653 }
654 } else if (pin == HAL_IOMUX_PIN_P0_3) {
655 if (func == HAL_IOMUX_FUNC_SPDIF0_DO) {
656 iomux->REG_004 = SET_BITFIELD(iomux->REG_004, IOMUX_GPIO_P03_SEL, 6);
657 return 0;
658 }
659 } else if (pin == HAL_IOMUX_PIN_P2_0) {
660 if (func == HAL_IOMUX_FUNC_CLK_REQ_OUT) {
661 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P20_SEL, 9);
662 return 0;
663 }
664 } else if (pin == HAL_IOMUX_PIN_P2_1) {
665 if (func == HAL_IOMUX_FUNC_CLK_REQ_IN) {
666 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P21_SEL, 9);
667 return 0;
668 }
669 } else if (pin == HAL_IOMUX_PIN_LED1 || pin == HAL_IOMUX_PIN_LED2) {
670 ASSERT(func == HAL_IOMUX_FUNC_GPIO, "Bad func=%d for IOMUX pin=%d", func, pin);
671 return 0;
672 }
673
674 if (func == HAL_IOMUX_FUNC_GPIO) {
675 val = IOMUX_FUNC_VAL_GPIO;
676 } else {
677 for (i = 0; i < IOMUX_ALT_FUNC_NUM; i++) {
678 if (pin_func_map[pin][i] == func) {
679 break;
680 }
681 }
682
683 if (i == IOMUX_ALT_FUNC_NUM) {
684 ASSERT(0, "[Func %d io %d] is unsupported by pin_func_map. Check it or use reg assignment like iomux_set_uart0.", pin, func);
685 return 3;
686 }
687 val = index_to_func_val[i];
688 }
689
690 reg = &iomux->REG_004 + pin / 8;
691 shift = (pin % 8) * 4;
692
693 *reg = (*reg & ~(0xF << shift)) | (val << shift);
694
695 return 0;
696 }
697
hal_iomux_get_function(enum HAL_IOMUX_PIN_T pin)698 enum HAL_IOMUX_FUNCTION_T hal_iomux_get_function(enum HAL_IOMUX_PIN_T pin)
699 {
700 return HAL_IOMUX_FUNC_NONE;
701 }
702
hal_iomux_set_io_voltage_domains(enum HAL_IOMUX_PIN_T pin,enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)703 uint32_t hal_iomux_set_io_voltage_domains(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)
704 {
705 if (pin >= HAL_IOMUX_PIN_LED_NUM) {
706 return 1;
707 }
708 if (pin == HAL_IOMUX_PIN_LED1 || pin == HAL_IOMUX_PIN_LED2) {
709 pmu_led_set_voltage_domains(pin, volt);
710 }
711
712 return 0;
713 }
714
hal_iomux_set_io_pull_select(enum HAL_IOMUX_PIN_T pin,enum HAL_IOMUX_PIN_PULL_SELECT_T pull_sel)715 uint32_t hal_iomux_set_io_pull_select(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_PIN_PULL_SELECT_T pull_sel)
716 {
717 if (pin >= HAL_IOMUX_PIN_LED_NUM) {
718 return 1;
719 }
720
721 if (pin < HAL_IOMUX_PIN_NUM) {
722 iomux->REG_02C &= ~(1 << pin);
723 iomux->REG_030 &= ~(1 << pin);
724 if (pull_sel == HAL_IOMUX_PIN_PULLUP_ENABLE) {
725 iomux->REG_02C |= (1 << pin);
726 } else if (pull_sel == HAL_IOMUX_PIN_PULLDOWN_ENABLE) {
727 iomux->REG_030 |= (1 << pin);
728 }
729 } else if (pin == HAL_IOMUX_PIN_LED1 || pin == HAL_IOMUX_PIN_LED2) {
730 pmu_led_set_pull_select(pin, pull_sel);
731 }
732
733 return 0;
734 }
735
hal_iomux_set_io_drv(enum HAL_IOMUX_PIN_T pin,uint32_t val)736 uint32_t hal_iomux_set_io_drv(enum HAL_IOMUX_PIN_T pin, uint32_t val)
737 {
738 if (pin >= HAL_IOMUX_PIN_NUM) {
739 return 1;
740 }
741 if (val > 3) {
742 return 2;
743 }
744 if (pin < HAL_IOMUX_PIN_P2_0)
745 iomux->REG_074 = (iomux->REG_074 & ~(IOMUX_GPIO_P0_DRV0_SEL_MASK << 2*(pin-HAL_IOMUX_PIN_P0_0))) |
746 (IOMUX_GPIO_P0_DRV0_SEL(val) << 2*(pin-HAL_IOMUX_PIN_P0_0));
747 else
748 iomux->REG_078 = (iomux->REG_078 & ~(IOMUX_GPIO_P0_DRV0_SEL_MASK << 2*(pin-HAL_IOMUX_PIN_P2_0))) |
749 (IOMUX_GPIO_P0_DRV0_SEL(val) << 2*(pin-HAL_IOMUX_PIN_P2_0));
750 return 0;
751 }
752
hal_iomux_set_sdmmc_dt_n_out_group(int enable)753 void hal_iomux_set_sdmmc_dt_n_out_group(int enable)
754 {
755 }
756
hal_iomux_set_uart0_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)757 void hal_iomux_set_uart0_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)
758 {
759 }
760
hal_iomux_set_uart1_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)761 void hal_iomux_set_uart1_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)
762 {
763 }
764
hal_iomux_uart0_connected(void)765 bool hal_iomux_uart0_connected(void)
766 {
767 uint32_t reg_050, reg_008, reg_02c, reg_030;
768 uint32_t mask;
769 int val;
770
771 // Save current iomux settings
772 reg_050 = iomux->REG_050;
773 reg_008 = iomux->REG_008;
774 reg_02c = iomux->REG_02C;
775 reg_030 = iomux->REG_030;
776
777 // Disable analog I2C slave & master
778 #ifndef FPGA
779 iomux->REG_050 |= IOMUX_GPIO_I2C_MODE | IOMUX_I2C0_M_SEL_GPIO;
780 #endif
781 // Set uart0-rx as gpio
782 iomux->REG_008 = SET_BITFIELD(iomux->REG_008, IOMUX_GPIO_P16_SEL, IOMUX_FUNC_VAL_GPIO);
783
784 mask = (1 << HAL_IOMUX_PIN_P1_6);
785 // Clear pullup
786 iomux->REG_02C &= ~mask;
787 // Setup pulldown
788 iomux->REG_030 |= mask;
789
790 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)HAL_IOMUX_PIN_P1_6, HAL_GPIO_DIR_IN, 0);
791
792 hal_sys_timer_delay(MS_TO_TICKS(2));
793
794 val = hal_gpio_pin_get_val((enum HAL_GPIO_PIN_T)HAL_IOMUX_PIN_P1_6);
795
796 // Restore iomux settings
797 iomux->REG_030 = reg_030;
798 iomux->REG_02C = reg_02c;
799 iomux->REG_008 = reg_008;
800 iomux->REG_050 = reg_050;
801
802 hal_sys_timer_delay(MS_TO_TICKS(2));
803
804 return !!val;
805 }
806
hal_iomux_uart1_connected(void)807 bool hal_iomux_uart1_connected(void)
808 {
809 uint32_t reg_00c, reg_02c, reg_030;
810 uint32_t mask;
811 int val;
812
813 // Save current iomux settings
814 reg_00c = iomux->REG_00C;
815 reg_02c = iomux->REG_02C;
816 reg_030 = iomux->REG_030;
817
818 // Set uart1-rx as gpio
819 iomux->REG_00C = SET_BITFIELD(iomux->REG_00C, IOMUX_GPIO_P20_SEL, IOMUX_FUNC_VAL_GPIO);
820
821 mask = (1 << HAL_IOMUX_PIN_P2_0);
822 // Clear pullup
823 iomux->REG_02C &= ~mask;
824 // Setup pulldown
825 iomux->REG_030 |= mask;
826
827 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)HAL_IOMUX_PIN_P2_0, HAL_GPIO_DIR_IN, 0);
828
829 hal_sys_timer_delay(MS_TO_TICKS(2));
830
831 val = hal_gpio_pin_get_val((enum HAL_GPIO_PIN_T)HAL_IOMUX_PIN_P2_0);
832
833 // Restore iomux settings
834 iomux->REG_030 = reg_030;
835 iomux->REG_02C = reg_02c;
836 iomux->REG_00C = reg_00c;
837
838 hal_sys_timer_delay(MS_TO_TICKS(2));
839
840 return !!val;
841 }
842
hal_iomux_set_uart0(void)843 void hal_iomux_set_uart0(void)
844 {
845 uint32_t mask;
846
847 // Disable analog I2C slave & master
848 #ifndef FPGA
849 iomux->REG_050 |= IOMUX_GPIO_I2C_MODE | IOMUX_I2C0_M_SEL_GPIO;
850 #endif
851 // Set uart0 func
852 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P16_SEL_MASK | IOMUX_GPIO_P17_SEL_MASK)) |
853 IOMUX_GPIO_P16_SEL(1) | IOMUX_GPIO_P17_SEL(1);
854
855 mask = (1 << HAL_IOMUX_PIN_P1_6) | (1 << HAL_IOMUX_PIN_P1_7);
856 // Setup pullup
857 iomux->REG_02C |= (1 << HAL_IOMUX_PIN_P1_6);
858 iomux->REG_02C &= ~(1 << HAL_IOMUX_PIN_P1_7);
859 // Clear pulldown
860 iomux->REG_030 &= ~mask;
861 }
862
hal_iomux_set_uart1(void)863 void hal_iomux_set_uart1(void)
864 {
865 uint32_t mask_pd_c, mask_pu, mask_pu_c;
866
867 // Set uart1 func
868 #if (UART1_IOMUX_INDEX == 02)
869 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK)) |
870 IOMUX_GPIO_P02_SEL(1) | IOMUX_GPIO_P03_SEL(1);
871 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_2) | (1 << HAL_IOMUX_PIN_P0_3);
872 mask_pu = (1 << HAL_IOMUX_PIN_P0_2);
873 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_3);
874 #elif (UART1_IOMUX_INDEX == 03) // 32: UART1 RX; 03 UART1 TX
875 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P32_SEL_MASK)) | IOMUX_GPIO_P32_SEL(1);
876 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P03_SEL_MASK)) | IOMUX_GPIO_P03_SEL(1);
877
878 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_3) | (1 << HAL_IOMUX_PIN_P3_2);
879 mask_pu = (1 << HAL_IOMUX_PIN_P3_2);
880 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_3);
881 #elif (UART1_IOMUX_INDEX == 10)
882 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P10_SEL_MASK | IOMUX_GPIO_P11_SEL_MASK)) |
883 IOMUX_GPIO_P10_SEL(1) | IOMUX_GPIO_P11_SEL(1);
884
885 mask_pd_c = (1 << HAL_IOMUX_PIN_P1_0) | (1 << HAL_IOMUX_PIN_P1_1);
886 mask_pu = (1 << HAL_IOMUX_PIN_P1_0);
887 mask_pu_c = (1 << HAL_IOMUX_PIN_P1_1);
888 #elif (UART1_IOMUX_INDEX == 20)
889 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK | IOMUX_GPIO_P21_SEL_MASK)) |
890 IOMUX_GPIO_P20_SEL(1) | IOMUX_GPIO_P21_SEL(1);
891
892 mask_pd_c = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
893 mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
894 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
895 #elif (UART1_IOMUX_INDEX == 30)
896 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P30_SEL_MASK | IOMUX_GPIO_P31_SEL_MASK)) |
897 IOMUX_GPIO_P30_SEL(1) | IOMUX_GPIO_P31_SEL(1);
898
899 mask_pd_c = (1 << HAL_IOMUX_PIN_P3_0) | (1 << HAL_IOMUX_PIN_P3_1);
900 mask_pu = (1 << HAL_IOMUX_PIN_P3_0);
901 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_1);
902 #elif (UART1_IOMUX_INDEX == 32)
903 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P32_SEL_MASK | IOMUX_GPIO_P33_SEL_MASK)) |
904 IOMUX_GPIO_P32_SEL(1) | IOMUX_GPIO_P33_SEL(1);
905
906 mask_pd_c = (1 << HAL_IOMUX_PIN_P3_2) | (1 << HAL_IOMUX_PIN_P3_3);
907 mask_pu = (1 << HAL_IOMUX_PIN_P3_2);
908 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_3);
909 #else
910 #error "Unsupported UART1_IOMUX_INDEX"
911 #endif
912 // Setup pullup
913 iomux->REG_02C |= mask_pu;
914 iomux->REG_02C &= ~(mask_pu_c);
915 // Clear pulldown
916 iomux->REG_030 &= ~mask_pd_c;
917 }
918
hal_iomux_set_uart2(void)919 void hal_iomux_set_uart2(void)
920 {
921 uint32_t mask_pd_c, mask_pu, mask_pu_c;
922
923 // Set uart1 func
924 #if (UART2_IOMUX_INDEX == 00)
925 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P00_SEL_MASK | IOMUX_GPIO_P01_SEL_MASK)) |
926 IOMUX_GPIO_P00_SEL(1) | IOMUX_GPIO_P01_SEL(1);
927 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_0) | (1 << HAL_IOMUX_PIN_P0_1);
928 mask_pu = (1 << HAL_IOMUX_PIN_P0_0);
929 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_1);
930 #elif (UART2_IOMUX_INDEX == 12)
931 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P12_SEL_MASK | IOMUX_GPIO_P13_SEL_MASK)) |
932 IOMUX_GPIO_P12_SEL(1) | IOMUX_GPIO_P13_SEL(1);
933
934 mask_pd_c = (1 << HAL_IOMUX_PIN_P1_2) | (1 << HAL_IOMUX_PIN_P1_3);
935 mask_pu = (1 << HAL_IOMUX_PIN_P1_2);
936 mask_pu_c = (1 << HAL_IOMUX_PIN_P1_3);
937 #elif (UART2_IOMUX_INDEX == 14)
938 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P14_SEL_MASK | IOMUX_GPIO_P15_SEL_MASK)) |
939 IOMUX_GPIO_P14_SEL(1) | IOMUX_GPIO_P15_SEL(1);
940
941 mask_pd_c = (1 << HAL_IOMUX_PIN_P1_4) | (1 << HAL_IOMUX_PIN_P1_5);
942 mask_pu = (1 << HAL_IOMUX_PIN_P1_4);
943 mask_pu_c = (1 << HAL_IOMUX_PIN_P1_5);
944 #elif (UART2_IOMUX_INDEX == 22)
945 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P22_SEL_MASK | IOMUX_GPIO_P23_SEL_MASK)) |
946 IOMUX_GPIO_P22_SEL(1) | IOMUX_GPIO_P23_SEL(1);
947
948 mask_pd_c = (1 << HAL_IOMUX_PIN_P2_2) | (1 << HAL_IOMUX_PIN_P2_3);
949 mask_pu = (1 << HAL_IOMUX_PIN_P2_2);
950 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_3);
951 #elif (UART2_IOMUX_INDEX == 36)
952 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P36_SEL_MASK | IOMUX_GPIO_P37_SEL_MASK)) |
953 IOMUX_GPIO_P36_SEL(1) | IOMUX_GPIO_P37_SEL(1);
954
955 mask_pd_c = (1 << HAL_IOMUX_PIN_P3_6) | (1 << HAL_IOMUX_PIN_P3_7);
956 mask_pu = (1 << HAL_IOMUX_PIN_P3_6);
957 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_7);
958 #else
959 #error "Unsupported UART1_IOMUX_INDEX"
960 #endif
961 // Setup pullup
962 iomux->REG_02C |= mask_pu;
963 iomux->REG_02C &= ~(mask_pu_c);
964 // Clear pulldown
965 iomux->REG_030 &= ~mask_pd_c;
966 }
967
hal_iomux_set_uart3(void)968 void hal_iomux_set_uart3(void)
969 {
970 uint32_t mask_pd_c, mask_pu, mask_pu_c;
971
972 // Set uart1 func
973 #if (UART3_IOMUX_INDEX == 04)
974 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK | IOMUX_GPIO_P05_SEL_MASK)) |
975 IOMUX_GPIO_P04_SEL(1) | IOMUX_GPIO_P05_SEL(1);
976 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_4) | (1 << HAL_IOMUX_PIN_P0_5);
977 mask_pu = (1 << HAL_IOMUX_PIN_P0_4);
978 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_5);
979 #elif (UART3_IOMUX_INDEX == 06)
980 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P06_SEL_MASK | IOMUX_GPIO_P07_SEL_MASK)) |
981 IOMUX_GPIO_P06_SEL(1) | IOMUX_GPIO_P07_SEL(1);
982 mask_pd_c = (1 << HAL_IOMUX_PIN_P0_6) | (1 << HAL_IOMUX_PIN_P0_7);
983 mask_pu = (1 << HAL_IOMUX_PIN_P0_6);
984 mask_pu_c = (1 << HAL_IOMUX_PIN_P0_7);
985 #elif (UART3_IOMUX_INDEX == 24)
986 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P24_SEL_MASK | IOMUX_GPIO_P25_SEL_MASK)) |
987 IOMUX_GPIO_P24_SEL(1) | IOMUX_GPIO_P25_SEL(1);
988
989 mask_pd_c = (1 << HAL_IOMUX_PIN_P2_4) | (1 << HAL_IOMUX_PIN_P2_5);
990 mask_pu = (1 << HAL_IOMUX_PIN_P2_4);
991 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_5);
992 #elif (UART3_IOMUX_INDEX == 26)
993 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P26_SEL_MASK | IOMUX_GPIO_P27_SEL_MASK)) |
994 IOMUX_GPIO_P26_SEL(1) | IOMUX_GPIO_P27_SEL(1);
995
996 mask_pd_c = (1 << HAL_IOMUX_PIN_P2_6) | (1 << HAL_IOMUX_PIN_P2_7);
997 mask_pu = (1 << HAL_IOMUX_PIN_P2_6);
998 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_7);
999 #elif (UART3_IOMUX_INDEX == 34)
1000 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P34_SEL_MASK | IOMUX_GPIO_P35_SEL_MASK)) |
1001 IOMUX_GPIO_P34_SEL(1) | IOMUX_GPIO_P35_SEL(1);
1002
1003 mask_pd_c = (1 << HAL_IOMUX_PIN_P3_4) | (1 << HAL_IOMUX_PIN_P3_5);
1004 mask_pu = (1 << HAL_IOMUX_PIN_P3_4);
1005 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_5);
1006 #else
1007 #error "Unsupported UART1_IOMUX_INDEX"
1008 #endif
1009 // Setup pullup
1010 iomux->REG_02C |= mask_pu;
1011 iomux->REG_02C &= ~(mask_pu_c);
1012 // Clear pulldown
1013 iomux->REG_030 &= ~mask_pd_c;
1014 }
1015
hal_iomux_set_analog_i2c(void)1016 void hal_iomux_set_analog_i2c(void)
1017 {
1018 uint32_t mask;
1019
1020 // Disable analog I2C master
1021 iomux->REG_050 |= IOMUX_I2C0_M_SEL_GPIO;
1022 // Set mcu GPIO func
1023 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P16_SEL_MASK | IOMUX_GPIO_P17_SEL_MASK)) |
1024 IOMUX_GPIO_P16_SEL(0xF) | IOMUX_GPIO_P17_SEL(0xF);
1025 // Enable analog I2C slave
1026 iomux->REG_050 &= ~IOMUX_GPIO_I2C_MODE;
1027
1028 mask = (1 << HAL_IOMUX_PIN_P1_6) | (1 << HAL_IOMUX_PIN_P1_7);
1029 // Setup pullup
1030 iomux->REG_02C |= mask;
1031 // Clear pulldown
1032 iomux->REG_030 &= ~mask;
1033 }
1034
hal_iomux_set_jtag(void)1035 void hal_iomux_set_jtag(void)
1036 {
1037 uint32_t mask;
1038 uint32_t val;
1039
1040 // SWCLK/TCK, SWDIO/TMS
1041 mask = IOMUX_GPIO_P01_SEL_MASK | IOMUX_GPIO_P00_SEL_MASK;
1042 val = IOMUX_GPIO_P01_SEL(7) | IOMUX_GPIO_P00_SEL(7);
1043
1044 // TDI, TDO
1045 #ifdef JTAG_TDI_TDO_PIN
1046 mask |= IOMUX_GPIO_P02_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK;
1047 val |= IOMUX_GPIO_P02_SEL(7) | IOMUX_GPIO_P03_SEL(7);
1048 #endif
1049 iomux->REG_004 = (iomux->REG_004 & ~mask) | val;
1050
1051 // RESET
1052 #if defined(JTAG_RESET_PIN) || defined(JTAG_TDI_TDO_PIN)
1053 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P05_SEL_MASK)) | IOMUX_GPIO_P05_SEL(7);
1054 #endif
1055
1056 mask = (1 << HAL_IOMUX_PIN_P0_1) | (1 << HAL_IOMUX_PIN_P0_0);
1057 #ifdef JTAG_TDI_TDO_PIN
1058 mask |= (1 << HAL_IOMUX_PIN_P0_2) | (1 << HAL_IOMUX_PIN_P0_3);
1059 #endif
1060 #if defined(JTAG_RESET_PIN) || defined(JTAG_TDI_TDO_PIN)
1061 mask |= (1 << HAL_IOMUX_PIN_P0_5);
1062 #endif
1063 // Clear pullup
1064 iomux->REG_02C &= ~mask;
1065 // Clear pulldown
1066 iomux->REG_030 &= ~mask;
1067 }
1068
hal_iomux_ispi_access_enable(enum HAL_IOMUX_ISPI_ACCESS_T access)1069 enum HAL_IOMUX_ISPI_ACCESS_T hal_iomux_ispi_access_enable(enum HAL_IOMUX_ISPI_ACCESS_T access)
1070 {
1071 uint32_t v;
1072
1073 v = iomux->REG_044;
1074 iomux->REG_044 |= access;
1075
1076 return v;
1077 }
1078
hal_iomux_ispi_access_disable(enum HAL_IOMUX_ISPI_ACCESS_T access)1079 enum HAL_IOMUX_ISPI_ACCESS_T hal_iomux_ispi_access_disable(enum HAL_IOMUX_ISPI_ACCESS_T access)
1080 {
1081 uint32_t v;
1082
1083 v = iomux->REG_044;
1084 iomux->REG_044 &= ~access;
1085
1086 return v;
1087 }
1088
hal_iomux_ispi_access_init(void)1089 void hal_iomux_ispi_access_init(void)
1090 {
1091 // Disable bt spi access ana/pmu interface
1092 hal_iomux_ispi_access_disable(HAL_IOMUX_ISPI_BT_ANA | HAL_IOMUX_ISPI_BT_PMU);
1093 }
1094
hal_iomux_set_i2s0(void)1095 void hal_iomux_set_i2s0(void)
1096 {
1097 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2s[] = {
1098 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_I2S0_WS, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1099 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_I2S0_SCK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1100 #if (I2S0_I_IOMUX_INDEX == 00)
1101 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_I2S0_SDI0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1102 #elif (I2S0_I_IOMUX_INDEX == 13)
1103 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_I2S0_SDI0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1104 #elif (I2S0_I_IOMUX_INDEX == 37)
1105 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_I2S0_SDI0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1106 #else
1107 #error "Unsupported I2S0_I_IOMUX_INDEX"
1108 #endif
1109 #if (I2S0_I1_IOMUX_INDEX == 12)
1110 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_I2S0_SDI1, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1111 #elif (I2S0_I1_IOMUX_INDEX == 36)
1112 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_I2S0_SDI1, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1113 #endif
1114 #if (I2S0_I2_IOMUX_INDEX == 11)
1115 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_I2S0_SDI2, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1116 #elif (I2S0_I2_IOMUX_INDEX == 35)
1117 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_I2S0_SDI2, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1118 #endif
1119 #if (I2S0_I3_IOMUX_INDEX == 10)
1120 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_I2S0_SDI3, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1121 #elif (I2S0_I3_IOMUX_INDEX == 34)
1122 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_I2S0_SDI3, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1123 #endif
1124
1125 #if (I2S0_O_IOMUX_INDEX == 01)
1126 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_I2S0_SDO0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1127 #elif (I2S0_O_IOMUX_INDEX == 07)
1128 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_I2S0_SDO0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1129 #else
1130 #error "Unsupported I2S0_O_IOMUX_INDEX"
1131 #endif
1132 #if (I2S0_O1_IOMUX_INDEX == 06)
1133 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_I2S0_SDO1, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1134 #endif
1135 #if (I2S0_O2_IOMUX_INDEX == 05)
1136 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_I2S0_SDO2, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1137 #endif
1138 #if (I2S0_O3_IOMUX_INDEX == 04)
1139 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_I2S0_SDO3, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1140 #endif
1141 };
1142
1143 hal_iomux_init(pinmux_i2s, ARRAY_SIZE(pinmux_i2s));
1144 }
1145
hal_iomux_set_i2s1(void)1146 void hal_iomux_set_i2s1(void)
1147 {
1148 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2s[] = {
1149 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2S1_WS, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1150 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_I2S1_SCK, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1151 #if (I2S1_I_IOMUX_INDEX == 20)
1152 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2S1_SDI0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1153 #elif (I2S1_I_IOMUX_INDEX == 33)
1154 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_I2S1_SDI0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1155 #else
1156 #error "Unsupported I2S1_I_IOMUX_INDEX"
1157 #endif
1158 #if (I2S1_I1_IOMUX_INDEX == 32)
1159 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_I2S1_SDI1, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1160 #endif
1161 #if (I2S1_I2_IOMUX_INDEX == 31)
1162 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_I2S1_SDI2, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1163 #endif
1164 #if (I2S1_I3_IOMUX_INDEX == 30)
1165 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_I2S1_SDI3, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1166 #endif
1167
1168 #if (I2S1_O_IOMUX_INDEX == 21)
1169 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_I2S1_SDO0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1170 #elif (I2S1_O_IOMUX_INDEX == 27)
1171 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_I2S1_SDO0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1172 #else
1173 #error "Unsupported I2S1_O_IOMUX_INDEX"
1174 #endif
1175 #if (I2S1_O1_IOMUX_INDEX == 26)
1176 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_I2S1_SDO1, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1177 #endif
1178 #if (I2S1_O2_IOMUX_INDEX == 25)
1179 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_I2S1_SDO2, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1180 #endif
1181 #if (I2S1_O3_IOMUX_INDEX == 24)
1182 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_I2S1_SDO3, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1183 #endif
1184 };
1185
1186 hal_iomux_init(pinmux_i2s, ARRAY_SIZE(pinmux_i2s));
1187 }
1188
hal_iomux_set_i2s_mclk(void)1189 void hal_iomux_set_i2s_mclk(void)
1190 {
1191 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux[] = {
1192 #if (I2S_MCLK_IOMUX_INDEX == 04)
1193 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1194 #elif (I2S_MCLK_IOMUX_INDEX == 13)
1195 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1196 #elif (I2S_MCLK_IOMUX_INDEX == 15)
1197 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1198 #elif (I2S_MCLK_IOMUX_INDEX == 20)
1199 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1200 #elif (I2S_MCLK_IOMUX_INDEX == 22)
1201 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1202 #elif (I2S_MCLK_IOMUX_INDEX == 27)
1203 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1204 #elif (I2S_MCLK_IOMUX_INDEX == 34)
1205 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1206 #else
1207 #error "Unsupported I2S_MCLK_IOMUX_INDEX"
1208 #endif
1209 };
1210
1211 hal_iomux_init(pinmux, ARRAY_SIZE(pinmux));
1212 }
1213
hal_iomux_set_spdif0(void)1214 void hal_iomux_set_spdif0(void)
1215 {
1216 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spdif[] = {
1217 #if (SPDIF0_I_IOMUX_INDEX == 02)
1218 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1219 #elif (SPDIF0_I_IOMUX_INDEX == 10)
1220 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1221 #elif (SPDIF0_I_IOMUX_INDEX == 20)
1222 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1223 #elif (SPDIF0_I_IOMUX_INDEX == 26)
1224 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1225 #elif (SPDIF0_I_IOMUX_INDEX == 37)
1226 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1227 #elif (SPDIF0_I_IOMUX_INDEX == 24)
1228 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1229 #else
1230 #error "Unsupported SPDIF0_I_IOMUX_INDEX"
1231 #endif
1232
1233 #if (SPDIF0_O_IOMUX_INDEX == 03)
1234 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1235 #elif (SPDIF0_O_IOMUX_INDEX == 11)
1236 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1237 #elif (SPDIF0_O_IOMUX_INDEX == 21)
1238 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1239 #elif (SPDIF0_O_IOMUX_INDEX == 27)
1240 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1241 #elif (SPDIF0_O_IOMUX_INDEX == 37)
1242 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1243 #elif (SPDIF0_O_IOMUX_INDEX == 07)
1244 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1245 #else
1246 #error "Unsupported SPDIF0_O_IOMUX_INDEX"
1247 #endif
1248 };
1249 hal_iomux_init(pinmux_spdif, ARRAY_SIZE(pinmux_spdif));
1250 }
1251
1252
hal_iomux_set_dig_mic(uint32_t map)1253 void hal_iomux_set_dig_mic(uint32_t map)
1254 {
1255 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_digitalmic_clk[] = {
1256 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_PDM0_CK, DIGMIC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1257 };
1258 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_digitalmic0[] = {
1259 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_PDM0_D, DIGMIC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1260 };
1261 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_digitalmic1[] = {
1262 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_PDM1_D, DIGMIC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1263 };
1264 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_digitalmic2[] = {
1265 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_PDM2_D, DIGMIC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1266 };
1267
1268 if (digmic_ck_pin == HAL_IOMUX_PIN_P0_0) {
1269 pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P0_0;
1270 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM0_CK;
1271 } else if (digmic_ck_pin == HAL_IOMUX_PIN_P0_4) {
1272 pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P0_4;
1273 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM1_CK;
1274 } else if (digmic_ck_pin == HAL_IOMUX_PIN_P3_3) {
1275 pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P3_3;
1276 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM2_CK;
1277 } else if (digmic_ck_pin == HAL_IOMUX_PIN_P3_4) {
1278 pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P3_4;
1279 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM0_CK;
1280 }
1281
1282 if (digmic_d0_pin == HAL_IOMUX_PIN_P0_1) {
1283 pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P0_1;
1284 } else if (digmic_d0_pin == HAL_IOMUX_PIN_P0_5) {
1285 pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P0_5;
1286 } else if (digmic_d0_pin == HAL_IOMUX_PIN_P3_0) {
1287 pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P3_0;
1288 } else if (digmic_d0_pin == HAL_IOMUX_PIN_P3_5) {
1289 pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P3_5;
1290 }
1291
1292 if (digmic_d1_pin == HAL_IOMUX_PIN_P0_2) {
1293 pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P0_2;
1294 } else if (digmic_d1_pin == HAL_IOMUX_PIN_P0_6) {
1295 pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P0_6;
1296 } else if (digmic_d1_pin == HAL_IOMUX_PIN_P3_1) {
1297 pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P3_1;
1298 } else if (digmic_d1_pin == HAL_IOMUX_PIN_P3_6) {
1299 pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P3_6;
1300 }
1301
1302 if (digmic_d2_pin == HAL_IOMUX_PIN_P0_3) {
1303 pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P0_3;
1304 } else if (digmic_d2_pin == HAL_IOMUX_PIN_P0_7) {
1305 pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P0_7;
1306 } else if (digmic_d2_pin == HAL_IOMUX_PIN_P3_2) {
1307 pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P3_2;
1308 } else if (digmic_d2_pin == HAL_IOMUX_PIN_P3_7) {
1309 pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P3_7;
1310 }
1311
1312 if ((map & 0xF) == 0) {
1313 pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_GPIO;
1314 }
1315 hal_iomux_init(pinmux_digitalmic_clk, ARRAY_SIZE(pinmux_digitalmic_clk));
1316 if (map & (1 << 0)) {
1317 hal_iomux_init(pinmux_digitalmic0, ARRAY_SIZE(pinmux_digitalmic0));
1318 }
1319 if (map & (1 << 1)) {
1320 hal_iomux_init(pinmux_digitalmic1, ARRAY_SIZE(pinmux_digitalmic1));
1321 }
1322 if (map & (1 << 2)) {
1323 hal_iomux_init(pinmux_digitalmic2, ARRAY_SIZE(pinmux_digitalmic2));
1324 }
1325 }
1326
hal_iomux_set_spi(void)1327 void hal_iomux_set_spi(void)
1328 {
1329 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spi[] = {
1330 #if (SPI_IOMUX_INDEX == 04)
1331 #ifdef SPI_IOMUX_4WIRE
1332 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1333 #endif
1334 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1335 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_SPI_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1336 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1337
1338 #elif (SPI_IOMUX_INDEX == 24)
1339 #ifdef SPI_IOMUX_4WIRE
1340 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1341 #endif
1342 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1343 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPI_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1344 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1345
1346 #elif (SPI_IOMUX_INDEX == 30)
1347 #ifdef SPI_IOMUX_4WIRE
1348 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1349 #endif
1350 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1351 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_SPI_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1352 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1353 #else
1354 #error "Unsupported SPI_IOMUX_INDEX"
1355 #endif
1356
1357 #if (SPI_IOMUX_CS1_INDEX == 10)
1358 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPI_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1359 #elif (SPI_IOMUX_CS1_INDEX == 35)
1360 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_SPI_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1361 #endif
1362 #if (SPI_IOMUX_CS2_INDEX == 11)
1363 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPI_CS2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1364 #elif (SPI_IOMUX_CS2_INDEX == 37)
1365 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPI_CS2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1366 #endif
1367 #if (SPI_IOMUX_CS3_INDEX == 12)
1368 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SPI_CS3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1369 #elif (SPI_IOMUX_CS3_INDEX == 25)
1370 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_SPI_CS3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1371 #endif
1372
1373 #ifdef SPI_IOMUX_4WIRE
1374 #if (SPI_IOMUX_DI1_INDEX == 13)
1375 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_SPI_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1376 #elif (SPI_IOMUX_DI1_INDEX == 34)
1377 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_SPI_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1378 #endif
1379 #if (SPI_IOMUX_DI2_INDEX == 14)
1380 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SPI_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1381 #elif (SPI_IOMUX_DI2_INDEX == 36)
1382 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_SPI_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1383 #endif
1384 #if (SPI_IOMUX_DI3_INDEX == 15)
1385 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SPI_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1386 #elif (SPI_IOMUX_DI3_INDEX == 24)
1387 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPI_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1388 #endif
1389 #endif
1390 };
1391
1392 hal_iomux_init(pinmux_spi, ARRAY_SIZE(pinmux_spi));
1393 }
1394
hal_iomux_set_spilcd_slave(void)1395 void hal_iomux_set_spilcd_slave(void)
1396 {
1397 iomux->REG_050 |= IOMUX_SPILCD1_MASTER_N;
1398 }
1399
hal_iomux_set_spilcd(void)1400 void hal_iomux_set_spilcd(void)
1401 {
1402 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spilcd[] = {
1403 #if (SPILCD_IOMUX_INDEX == 00)
1404 #ifdef SPILCD_IOMUX_4WIRE
1405 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1406 #endif
1407 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1408 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPILCD_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1409 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1410
1411 #elif (SPILCD_IOMUX_INDEX == 10)
1412 #ifdef SPILCD_IOMUX_4WIRE
1413 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1414 #endif
1415 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1416 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPILCD_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1417 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1418
1419 #elif (SPILCD_IOMUX_INDEX == 20)
1420 #ifdef SPILCD_IOMUX_4WIRE
1421 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1422 #endif
1423 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1424 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_SPILCD_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1425 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1426
1427 #elif (SPILCD_IOMUX_INDEX == 34)
1428 #ifdef SPILCD_IOMUX_4WIRE
1429 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1430 #endif
1431 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1432 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_SPILCD_CS0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1433 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1434 #else
1435 #error "Unsupported SPILCD_IOMUX_INDEX"
1436 #endif
1437
1438 #if (SPILCD_IOMUX_CS1_INDEX == 05)
1439 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_SPILCD_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1440 #elif (SPILCD_IOMUX_CS1_INDEX == 12)
1441 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SPILCD_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1442 #elif (SPILCD_IOMUX_CS1_INDEX == 27)
1443 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPILCD_CS1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1444 #endif
1445 #if (SPILCD_IOMUX_CS2_INDEX == 06)
1446 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_SPILCD_CS2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1447 #elif (SPILCD_IOMUX_CS2_INDEX == 31)
1448 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_SPILCD_CS2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1449 #endif
1450 #if (SPILCD_IOMUX_CS3_INDEX == 07)
1451 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPILCD_CS3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1452 #elif (SPILCD_IOMUX_CS3_INDEX == 32)
1453 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_SPILCD_CS3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1454 #endif
1455
1456 #ifdef SPILCD_IOMUX_4WIRE
1457 #if (SPILCD_IOMUX_DI1_INDEX == 02)
1458 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPILCD_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1459 #elif (SPILCD_IOMUX_DI1_INDEX == 26)
1460 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPILCD_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1461 #endif
1462 #if (SPILCD_IOMUX_DI2_INDEX == 03)
1463 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPILCD_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1464 #elif (SPILCD_IOMUX_DI2_INDEX == 30)
1465 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_SPILCD_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1466 #endif
1467 #if (SPILCD_IOMUX_DI3_INDEX == 04)
1468 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_SPILCD_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1469 #elif (SPILCD_IOMUX_DI3_INDEX == 33)
1470 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_SPILCD_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1471 #endif
1472 #endif
1473 };
1474
1475 hal_iomux_init(pinmux_spilcd, ARRAY_SIZE(pinmux_spilcd));
1476 }
1477
hal_iomux_set_i2c0(void)1478 void hal_iomux_set_i2c0(void)
1479 {
1480 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2c[] = {
1481 #if (I2C0_IOMUX_INDEX == 00)
1482 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1483 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1484 #elif (I2C0_IOMUX_INDEX == 04)
1485 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1486 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1487 #elif (I2C0_IOMUX_INDEX == 16)
1488 {HAL_IOMUX_PIN_P1_6, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1489 {HAL_IOMUX_PIN_P1_7, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1490 #elif (I2C0_IOMUX_INDEX == 20)
1491 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1492 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1493 #elif (I2C0_IOMUX_INDEX == 26)
1494 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1495 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1496 #elif (I2C0_IOMUX_INDEX == 34)
1497 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1498 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1499 #else
1500 #error "Unsupported I2C0_IOMUX_INDEX"
1501 #endif
1502 };
1503 hal_iomux_init(pinmux_i2c, ARRAY_SIZE(pinmux_i2c));
1504 iomux->REG_050 |= IOMUX_I2C0_M_SEL_GPIO;
1505 }
1506
hal_iomux_set_i2c1(void)1507 void hal_iomux_set_i2c1(void)
1508 {
1509 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2c[] = {
1510 #if (I2C1_IOMUX_INDEX == 02)
1511 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1512 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1513 #elif (I2C1_IOMUX_INDEX == 06)
1514 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1515 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1516 #elif (I2C1_IOMUX_INDEX == 14)
1517 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1518 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1519 #elif (I2C1_IOMUX_INDEX == 22)
1520 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1521 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1522 #elif (I2C1_IOMUX_INDEX == 30)
1523 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_I2C_M1_SCL, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1524 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_I2C_M1_SDA, I2C1_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1525 #else
1526 #error "Unsupported I2C1_IOMUX_INDEX"
1527 #endif
1528 };
1529 hal_iomux_init(pinmux_i2c, ARRAY_SIZE(pinmux_i2c));
1530 iomux->REG_050 |= IOMUX_I2C1_M_SEL_GPIO;
1531 }
1532
hal_iomux_set_i2c2(void)1533 void hal_iomux_set_i2c2(void)
1534 {
1535 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2c[] = {
1536 #if (I2C2_IOMUX_INDEX == 10)
1537 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1538 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1539 #elif (I2C2_IOMUX_INDEX == 12)
1540 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1541 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1542 #elif (I2C2_IOMUX_INDEX == 24)
1543 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1544 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1545 #elif (I2C2_IOMUX_INDEX == 32)
1546 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1547 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1548 #elif (I2C2_IOMUX_INDEX == 36)
1549 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_I2C_M2_SCL, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1550 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_I2C_M2_SDA, I2C2_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
1551 #else
1552 #error "Unsupported I2C2_IOMUX_INDEX"
1553 #endif
1554 };
1555 hal_iomux_init(pinmux_i2c, ARRAY_SIZE(pinmux_i2c));
1556 iomux->REG_050 |= IOMUX_I2C2_M_SEL_GPIO;
1557 }
1558
hal_iomux_set_pwm0(void)1559 void hal_iomux_set_pwm0(void)
1560 {
1561 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1562 #if (PWM0_IOMUX_INDEX == 00)
1563 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_PWM0, PWM0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1564 #elif (PWM0_IOMUX_INDEX == 10)
1565 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_PWM0, PWM0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1566 #elif (PWM0_IOMUX_INDEX == 20)
1567 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_PWM0, PWM0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1568 #elif (PWM0_IOMUX_INDEX == 30)
1569 {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_PWM0, PWM0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1570 #else
1571 #error "Unsupported PWM0_IOMUX_INDEX"
1572 #endif
1573 };
1574 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1575 }
1576
hal_iomux_set_pwm1(void)1577 void hal_iomux_set_pwm1(void)
1578 {
1579 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1580 #if (PWM1_IOMUX_INDEX == 01)
1581 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_PWM1, PWM1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1582 #elif (PWM1_IOMUX_INDEX == 11)
1583 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_PWM1, PWM1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1584 #elif (PWM1_IOMUX_INDEX == 21)
1585 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_PWM1, PWM1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1586 #elif (PWM1_IOMUX_INDEX == 31)
1587 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_PWM1, PWM1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1588 #else
1589 #error "Unsupported PWM1_IOMUX_INDEX"
1590 #endif
1591 };
1592 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1593 }
1594
hal_iomux_set_pwm2(void)1595 void hal_iomux_set_pwm2(void)
1596 {
1597 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1598 #if (PWM2_IOMUX_INDEX == 02)
1599 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_PWM2, PWM2_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1600 #elif (PWM2_IOMUX_INDEX == 12)
1601 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_PWM2, PWM2_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1602 #elif (PWM2_IOMUX_INDEX == 22)
1603 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_PWM2, PWM2_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1604 #elif (PWM2_IOMUX_INDEX == 32)
1605 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_PWM2, PWM2_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1606 #else
1607 #error "Unsupported PWM2_IOMUX_INDEX"
1608 #endif
1609 };
1610 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1611 }
1612
hal_iomux_set_pwm3(void)1613 void hal_iomux_set_pwm3(void)
1614 {
1615 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1616 #if (PWM3_IOMUX_INDEX == 03)
1617 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_PWM3, PWM3_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1618 #elif (PWM3_IOMUX_INDEX == 13)
1619 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_PWM3, PWM3_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1620 #elif (PWM3_IOMUX_INDEX == 23)
1621 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_PWM3, PWM3_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1622 #elif (PWM3_IOMUX_INDEX == 33)
1623 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_PWM3, PWM3_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1624 #else
1625 #error "Unsupported PWM3_IOMUX_INDEX"
1626 #endif
1627 };
1628 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1629 }
1630
hal_iomux_set_pwm4(void)1631 void hal_iomux_set_pwm4(void)
1632 {
1633 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1634 #if (PWM4_IOMUX_INDEX == 04)
1635 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_PWM4, PWM4_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1636 #elif (PWM4_IOMUX_INDEX == 14)
1637 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_PWM4, PWM4_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1638 #elif (PWM4_IOMUX_INDEX == 24)
1639 {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_PWM4, PWM4_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1640 #elif (PWM4_IOMUX_INDEX == 34)
1641 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_PWM4, PWM4_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1642 #else
1643 #error "Unsupported PWM4_IOMUX_INDEX"
1644 #endif
1645 };
1646 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1647 }
1648
hal_iomux_set_pwm5(void)1649 void hal_iomux_set_pwm5(void)
1650 {
1651 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1652 #if (PWM5_IOMUX_INDEX == 05)
1653 {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_PWM5, PWM5_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1654 #elif (PWM5_IOMUX_INDEX == 15)
1655 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_PWM5, PWM5_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1656 #elif (PWM5_IOMUX_INDEX == 25)
1657 {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_PWM5, PWM5_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1658 #elif (PWM5_IOMUX_INDEX == 35)
1659 {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_PWM5, PWM5_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1660 #else
1661 #error "Unsupported PWM5_IOMUX_INDEX"
1662 #endif
1663 };
1664 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1665 }
1666
hal_iomux_set_pwm6(void)1667 void hal_iomux_set_pwm6(void)
1668 {
1669 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1670 #if (PWM6_IOMUX_INDEX == 06)
1671 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_PWM6, PWM6_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1672 #elif (PWM6_IOMUX_INDEX == 16)
1673 {HAL_IOMUX_PIN_P1_6, HAL_IOMUX_FUNC_PWM6, PWM6_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1674 #elif (PWM6_IOMUX_INDEX == 26)
1675 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_PWM6, PWM6_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1676 #elif (PWM6_IOMUX_INDEX == 36)
1677 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_PWM6, PWM6_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1678 #else
1679 #error "Unsupported PWM6_IOMUX_INDEX"
1680 #endif
1681 };
1682 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1683 }
1684
hal_iomux_set_pwm7(void)1685 void hal_iomux_set_pwm7(void)
1686 {
1687 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_pwm[] = {
1688 #if (PWM7_IOMUX_INDEX == 07)
1689 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_PWM7, PWM7_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1690 #elif (PWM7_IOMUX_INDEX == 17)
1691 {HAL_IOMUX_PIN_P1_7, HAL_IOMUX_FUNC_PWM7, PWM7_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1692 #elif (PWM7_IOMUX_INDEX == 27)
1693 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_PWM7, PWM7_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1694 #elif (PWM7_IOMUX_INDEX == 37)
1695 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_PWM7, PWM7_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1696 #else
1697 #error "Unsupported PWM7_IOMUX_INDEX"
1698 #endif
1699 };
1700 hal_iomux_init(pinmux_pwm, ARRAY_SIZE(pinmux_pwm));
1701 }
1702
hal_iomux_set_ir(void)1703 void hal_iomux_set_ir(void)
1704 {
1705 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_ir[] = {
1706 #if (IR_RX_IOMUX_INDEX == 00)
1707 {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1708 #elif (IR_RX_IOMUX_INDEX == 02)
1709 {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1710 #elif (IR_RX_IOMUX_INDEX == 06)
1711 {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1712 #elif (IR_RX_IOMUX_INDEX == 10)
1713 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1714 #elif (IR_RX_IOMUX_INDEX == 12)
1715 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1716 #elif (IR_RX_IOMUX_INDEX == 14)
1717 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1718 #elif (IR_RX_IOMUX_INDEX == 22)
1719 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1720 #elif (IR_RX_IOMUX_INDEX == 26)
1721 {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1722 #elif (IR_RX_IOMUX_INDEX == 31)
1723 {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1724 #elif (IR_RX_IOMUX_INDEX == 33)
1725 {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1726 #elif (IR_RX_IOMUX_INDEX == 36)
1727 {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_IR_RX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1728 #else
1729 #error "Unsupported IR_RX_IOMUX_INDEX"
1730 #endif
1731
1732 #if (IR_TX_IOMUX_INDEX == 01)
1733 {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1734 #elif (IR_TX_IOMUX_INDEX == 03)
1735 {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1736 #elif (IR_TX_IOMUX_INDEX == 07)
1737 {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1738 #elif (IR_TX_IOMUX_INDEX == 11)
1739 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1740 #elif (IR_TX_IOMUX_INDEX == 13)
1741 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1742 #elif (IR_TX_IOMUX_INDEX == 15)
1743 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1744 #elif (IR_TX_IOMUX_INDEX == 21)
1745 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1746 #elif (IR_TX_IOMUX_INDEX == 27)
1747 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1748 #elif (IR_TX_IOMUX_INDEX == 32)
1749 {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1750 #elif (IR_TX_IOMUX_INDEX == 34)
1751 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1752 #elif (IR_TX_IOMUX_INDEX == 37)
1753 {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_IR_TX, IR_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1754 #else
1755 #error "Unsupported IR_TX_IOMUX_INDEX"
1756 #endif
1757 };
1758
1759 hal_iomux_init(pinmux_ir, ARRAY_SIZE(pinmux_ir));
1760 }
1761
hal_iomux_set_sdmmc(void)1762 void hal_iomux_set_sdmmc(void)
1763 {
1764 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_sdmmc[] = {
1765 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_SDMMC_CLK, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1766 {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SDMMC_CMD, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1767 {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SDMMC_DATA0, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1768 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SDMMC_DATA1, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1769 {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SDMMC_DATA2, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1770 {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SDMMC_DATA3, SDMMC_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1771 };
1772
1773 hal_iomux_init(pinmux_sdmmc, ARRAY_SIZE(pinmux_sdmmc));
1774 }
1775
hal_iomux_set_clock_out(void)1776 void hal_iomux_set_clock_out(void)
1777 {
1778 static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_clkout[] = {
1779 #if (CLKOUT_IOMUX_INDEX == 04)
1780 {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1781 #elif (CLKOUT_IOMUX_INDEX == 13)
1782 {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1783 #elif (CLKOUT_IOMUX_INDEX == 15)
1784 {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1785 #elif (CLKOUT_IOMUX_INDEX == 20)
1786 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1787 #elif (CLKOUT_IOMUX_INDEX == 21)
1788 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1789 #elif (CLKOUT_IOMUX_INDEX == 22)
1790 {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1791 #elif (CLKOUT_IOMUX_INDEX == 23)
1792 {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1793 #elif (CLKOUT_IOMUX_INDEX == 27)
1794 {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1795 #elif (CLKOUT_IOMUX_INDEX == 34)
1796 {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
1797 #else
1798 #error "Unsupported CLKOUT_IOMUX_INDEX"
1799 #endif
1800 };
1801
1802 hal_iomux_init(pinmux_clkout, ARRAY_SIZE(pinmux_clkout));
1803 }
1804
hal_iomux_set_mcu_clock_out(void)1805 void hal_iomux_set_mcu_clock_out(void)
1806 {
1807 }
1808
hal_iomux_set_bt_clock_out(void)1809 void hal_iomux_set_bt_clock_out(void)
1810 {
1811 }
1812
hal_iomux_set_bt_tport(void)1813 void hal_iomux_set_bt_tport(void)
1814 {
1815 ///TODO:
1816 return ;
1817 // P0_0 ~ P0_3,
1818 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P00_SEL_MASK | IOMUX_GPIO_P01_SEL_MASK | IOMUX_GPIO_P02_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK)) |
1819 IOMUX_GPIO_P00_SEL(0xA) | IOMUX_GPIO_P01_SEL(0xA) | IOMUX_GPIO_P02_SEL(0xA) |IOMUX_GPIO_P03_SEL(0xA);
1820 //P1_0 ~ P1_3,
1821 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P10_SEL_MASK | IOMUX_GPIO_P11_SEL_MASK | IOMUX_GPIO_P12_SEL_MASK | IOMUX_GPIO_P13_SEL_MASK )) |
1822 IOMUX_GPIO_P10_SEL(0xA) | IOMUX_GPIO_P11_SEL(0xA) | IOMUX_GPIO_P12_SEL(0xA) | IOMUX_GPIO_P13_SEL(0xA);
1823 // ANA TEST DIR
1824 iomux->REG_014 = 0x0f0f;
1825 // ANA TEST SEL
1826 iomux->REG_018 = IOMUX_ANA_TEST_SEL(5);
1827 }
1828
hal_iomux_set_bt_rf_sw(int rx_on,int tx_on)1829 void hal_iomux_set_bt_rf_sw(int rx_on, int tx_on)
1830 {
1831 ///TODO:
1832 return ;
1833 uint32_t val;
1834 uint32_t dir;
1835
1836 //iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P00_SEL_MASK | IOMUX_GPIO_P01_SEL_MASK)) |
1837 // IOMUX_GPIO_P00_SEL(6) | IOMUX_GPIO_P01_SEL(6);
1838
1839 val = iomux->REG_004;
1840 dir = 0;
1841 if (rx_on) {
1842 val = SET_BITFIELD(val, IOMUX_GPIO_P00_SEL, 0xA);
1843 dir = (1 << HAL_IOMUX_PIN_P0_0);
1844 }
1845 if (tx_on) {
1846 val = SET_BITFIELD(val, IOMUX_GPIO_P01_SEL, 0xA);
1847 dir = (1 << HAL_IOMUX_PIN_P0_1);
1848 }
1849 iomux->REG_004 = val;
1850 // ANA TEST DIR
1851 iomux->REG_014 |= dir;
1852 // ANA TEST SEL
1853 iomux->REG_018 = IOMUX_ANA_TEST_SEL(5);
1854 }
hal_iomux_set_wifi_uart(void)1855 void hal_iomux_set_wifi_uart(void)
1856 {
1857 #ifndef KERNEL_LITEOS_M
1858 uint32_t mask_pd, mask_pu, mask_pu_c;
1859
1860
1861 #if USE_GPIO21_LMAC_LOG
1862
1863 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK | IOMUX_GPIO_P21_SEL_MASK)) |
1864 IOMUX_GPIO_P20_SEL(8) | IOMUX_GPIO_P21_SEL(8);
1865
1866 mask_pd = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
1867 mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
1868 mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
1869
1870 #else
1871
1872 // Set wifi uart func
1873
1874 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P30_SEL_MASK | IOMUX_GPIO_P31_SEL_MASK)) |
1875 IOMUX_GPIO_P30_SEL(7) | IOMUX_GPIO_P31_SEL(7);
1876
1877 mask_pd = (1 << HAL_IOMUX_PIN_P3_0) | (1 << HAL_IOMUX_PIN_P3_1);
1878 mask_pu = (1 << HAL_IOMUX_PIN_P3_0);
1879 mask_pu_c = (1 << HAL_IOMUX_PIN_P3_1);
1880 #endif
1881 // Setup pullup
1882 iomux->REG_02C |= mask_pu;
1883 iomux->REG_02C &= ~(mask_pu_c);
1884 // Clear pulldown
1885 iomux->REG_030 &= ~mask_pd;
1886 #endif
1887 }
1888
hal_pwrkey_set_irq(enum HAL_PWRKEY_IRQ_T type)1889 int WEAK hal_pwrkey_set_irq(enum HAL_PWRKEY_IRQ_T type)
1890 {
1891 uint32_t v;
1892
1893 if (type == HAL_PWRKEY_IRQ_NONE) {
1894 v = IOMUX_POWER_KEY_ON_INT_STATUS | IOMUX_POWER_KEY_OFF_INT_STATUS;
1895 } else if (type == HAL_PWRKEY_IRQ_FALLING_EDGE) {
1896 v = IOMUX_POWER_KEY_ON_INT_EN | IOMUX_POWER_KEY_ON_INT_MSK;
1897 } else if (type == HAL_PWRKEY_IRQ_RISING_EDGE) {
1898 v = IOMUX_POWER_KEY_OFF_INT_EN | IOMUX_POWER_KEY_OFF_INT_MSK;
1899 } else if (type == HAL_PWRKEY_IRQ_BOTH_EDGE) {
1900 v = IOMUX_POWER_KEY_ON_INT_EN | IOMUX_POWER_KEY_ON_INT_MSK |
1901 IOMUX_POWER_KEY_OFF_INT_EN | IOMUX_POWER_KEY_OFF_INT_MSK;
1902 } else {
1903 return 1;
1904 }
1905
1906 iomux->REG_040 = v;
1907
1908 return 0;
1909 }
1910
1911
hal_pwrkey_pressed(void)1912 bool WEAK hal_pwrkey_pressed(void)
1913 {
1914 uint32_t v = iomux->REG_040;
1915 return !!(v & IOMUX_POWER_ON_FEEDOUT);
1916
1917 }
1918
hal_pwrkey_startup_pressed(void)1919 bool hal_pwrkey_startup_pressed(void)
1920 {
1921 return hal_pwrkey_pressed();
1922 }
1923
hal_pwrkey_get_irq_state(void)1924 enum HAL_PWRKEY_IRQ_T WEAK hal_pwrkey_get_irq_state(void)
1925 {
1926 enum HAL_PWRKEY_IRQ_T state = HAL_PWRKEY_IRQ_NONE;
1927 uint32_t v = iomux->REG_040;
1928
1929 if (v & IOMUX_R_POWER_KEY_INTR_U) {
1930 state |= HAL_PWRKEY_IRQ_FALLING_EDGE;
1931 }
1932
1933 if (v & IOMUX_R_POWER_KEY_INTR_D) {
1934 state |= HAL_PWRKEY_IRQ_RISING_EDGE;
1935 }
1936
1937 return state;
1938 }
1939
hal_iomux_set_codec_gpio_trigger(enum HAL_IOMUX_PIN_T pin,bool polarity)1940 void hal_iomux_set_codec_gpio_trigger(enum HAL_IOMUX_PIN_T pin, bool polarity)
1941 {
1942 iomux->REG_064 = SET_BITFIELD(iomux->REG_064, IOMUX_CFG_CODEC_TRIG_SEL, pin);
1943 if (polarity) {
1944 iomux->REG_064 &= ~IOMUX_CFG_CODEC_TRIG_POL;
1945 } else {
1946 iomux->REG_064 |= IOMUX_CFG_CODEC_TRIG_POL;
1947 }
1948 }
1949
hal_iomux_single_wire_uart_rx(uint32_t uart)1950 void hal_iomux_single_wire_uart_rx(uint32_t uart)
1951 {
1952 #ifdef UART_HALF_DUPLEX
1953 #define SUART_TX_PIN_PULL_SEL_IN_RX HAL_IOMUX_PIN_NOPULL
1954 #else
1955 #define SUART_TX_PIN_PULL_SEL_IN_RX HAL_IOMUX_PIN_PULLUP_ENABLE
1956 #endif
1957
1958 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_uart[] =
1959 {
1960 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_PULLUP_ENABLE},
1961 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_GPIO, HAL_IOMUX_PIN_VOLTAGE_VIO, SUART_TX_PIN_PULL_SEL_IN_RX},
1962 };
1963
1964 if (uart == HAL_UART_ID_2) {
1965 pinmux_uart[0].pin = HAL_IOMUX_PIN_P2_2;
1966 pinmux_uart[0].function = HAL_IOMUX_FUNC_UART2_RX;
1967 pinmux_uart[1].pin = HAL_IOMUX_PIN_P2_3;
1968 #ifdef UART_HALF_DUPLEX
1969 iomux->REG_050 &= ~IOMUX_UART2_HALFN;
1970 } else {
1971 iomux->REG_050 &= ~IOMUX_UART1_HALFN;
1972 #endif
1973 }
1974
1975 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)pinmux_uart[0].pin, HAL_GPIO_DIR_IN, 1);
1976 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)pinmux_uart[1].pin, HAL_GPIO_DIR_IN, 1);
1977
1978 hal_iomux_init(pinmux_uart, ARRAY_SIZE(pinmux_uart));
1979
1980 #ifndef UART_HALF_DUPLEX
1981 hal_uart_flush(uart, 0);
1982 #endif
1983 }
1984
hal_iomux_single_wire_uart_tx(uint32_t uart)1985 void hal_iomux_single_wire_uart_tx(uint32_t uart)
1986 {
1987 #ifndef UART_HALF_DUPLEX
1988 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_uart[] =
1989 {
1990 {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_GPIO, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_PULLUP_ENABLE},
1991 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_NOPULL},
1992 };
1993
1994 if (uart == HAL_UART_ID_2) {
1995 pinmux_uart[0].pin = HAL_IOMUX_PIN_P2_2;
1996 pinmux_uart[1].pin = HAL_IOMUX_PIN_P2_3;
1997 pinmux_uart[1].function = HAL_IOMUX_FUNC_UART2_TX;
1998 }
1999
2000 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)pinmux_uart[0].pin, HAL_GPIO_DIR_IN, 1);
2001 hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)pinmux_uart[1].pin, HAL_GPIO_DIR_IN, 1);
2002
2003 hal_iomux_init(pinmux_uart, ARRAY_SIZE(pinmux_uart));
2004 #endif
2005 }
2006
hal_iomux_set_dsi_te(void)2007 void hal_iomux_set_dsi_te(void)
2008 {
2009 struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux[] =
2010 {
2011 {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_NOPULL},
2012 };
2013
2014 hal_iomux_init(pinmux, ARRAY_SIZE(pinmux));
2015 }
2016
hal_iomux_set_wf_fem(int rf_switch)2017 void hal_iomux_set_wf_fem(int rf_switch)
2018 {
2019 uint32_t mask_pd, mask_pu;
2020 #if (1 == WIFI_RF_SWITCH) //bes EVB v2
2021
2022 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK)) | IOMUX_GPIO_P20_SEL(13);
2023
2024 // mask_pd = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
2025 mask_pd = (1 << HAL_IOMUX_PIN_P2_0);
2026 mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
2027 // mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
2028
2029 // Setup voltage as VIO
2030 iomux->REG_090 &= ~(IOMUX_GPIO_P20_SEL_VIO);
2031
2032 // Setup pullup
2033 iomux->REG_02C |= mask_pu;
2034 // iomux->REG_02C &= ~(mask_pu_c);
2035 // Clear pulldown
2036 iomux->REG_030 &= ~mask_pd;
2037
2038 #else
2039 if( (rf_switch == 20) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2040 {
2041 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P24_SEL_MASK)) | IOMUX_GPIO_P24_SEL(13);
2042
2043 mask_pd = (1 << HAL_IOMUX_PIN_P2_4);
2044 mask_pu = (1 << HAL_IOMUX_PIN_P2_4);
2045
2046 // Setup voltage as VIO
2047 iomux->REG_094 &= ~(IOMUX_GPIO_P24_SEL_VIO);
2048
2049 // Setup pullup
2050 iomux->REG_02C |= mask_pu;
2051 // Clear pulldown
2052 iomux->REG_030 &= ~mask_pd;
2053 }
2054
2055 if( (rf_switch == 12) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2056 {
2057 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P14_SEL_MASK)) | IOMUX_GPIO_P14_SEL(13);
2058
2059 mask_pd = (1 << HAL_IOMUX_PIN_P1_4);
2060 mask_pu = (1 << HAL_IOMUX_PIN_P1_4);
2061
2062 // Setup voltage as VIO
2063 iomux->REG_090 &= ~(IOMUX_GPIO_P14_SEL_VIO);
2064
2065 // Setup pullup
2066 iomux->REG_02C |= mask_pu;
2067 // Clear pulldown
2068 iomux->REG_030 &= ~mask_pd;
2069 }
2070
2071 if( (rf_switch == 16) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2072 {
2073 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK)) | IOMUX_GPIO_P20_SEL(13);
2074
2075 // mask_pd = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
2076 mask_pd = (1 << HAL_IOMUX_PIN_P2_0);
2077 mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
2078 // mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
2079
2080 // Setup voltage as VIO
2081 iomux->REG_090 &= ~(IOMUX_GPIO_P20_SEL_VIO);
2082
2083 // Setup pullup
2084 iomux->REG_02C |= mask_pu;
2085 // iomux->REG_02C &= ~(mask_pu_c);
2086 // Clear pulldown
2087 iomux->REG_030 &= ~mask_pd;
2088 }
2089
2090 if( (rf_switch == 2) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2091 {
2092 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK)) | IOMUX_GPIO_P02_SEL(13);
2093
2094 mask_pd = (1 << HAL_IOMUX_PIN_P0_2);
2095 mask_pu = (1 << HAL_IOMUX_PIN_P0_2);
2096
2097 // Setup voltage as VIO
2098 iomux->REG_090 &= ~(IOMUX_GPIO_P02_SEL_VIO);
2099
2100 // Setup pullup
2101 iomux->REG_02C |= mask_pu;
2102 // Clear pulldown
2103 iomux->REG_030 &= ~mask_pd;
2104 }
2105
2106 //hwBoEn V0, gpio12(sw2)5g txon; gpio13(sw3)0:bt, 1:2g4;
2107 if( (rf_switch == 10) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2108 {
2109 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P12_SEL_MASK)) | IOMUX_GPIO_P12_SEL(13);
2110 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P13_SEL_MASK)) | IOMUX_GPIO_P13_SEL(13);
2111 }
2112
2113 //gpio4 no 5G 2.4g/bt --> 1: 2.4, 0:bt;
2114 if( (rf_switch == 4) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2115 {
2116 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2117 }
2118
2119 //5G GPIO-02 -sw1,2.4G GPIO-04-sw4
2120 if( (rf_switch == 6) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2121 {
2122 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK)) | IOMUX_GPIO_P02_SEL(13);
2123
2124 mask_pd = (1 << HAL_IOMUX_PIN_P0_2);
2125 mask_pu = (1 << HAL_IOMUX_PIN_P0_2);
2126
2127 // Setup voltage as VIO
2128 iomux->REG_090 &= ~(IOMUX_GPIO_P02_SEL_VIO);
2129
2130 // Setup pullup
2131 iomux->REG_02C |= mask_pu;
2132 // Clear pulldown
2133 iomux->REG_030 &= ~mask_pd;
2134
2135 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2136
2137 mask_pd = (1 << HAL_IOMUX_PIN_P0_4);
2138 mask_pu = (1 << HAL_IOMUX_PIN_P0_4);
2139
2140 // Setup voltage as VIO
2141 iomux->REG_090 &= ~(IOMUX_GPIO_P04_SEL_VIO);
2142
2143 // Setup pullup
2144 iomux->REG_02C |= mask_pu;
2145 // Clear pulldown
2146 iomux->REG_030 &= ~mask_pd;
2147
2148 }
2149
2150 if( (rf_switch == 25) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2151 {
2152 iomux->REG_010 = (iomux->REG_010 & ~(IOMUX_GPIO_P31_SEL_MASK)) | IOMUX_GPIO_P31_SEL(13);
2153
2154 mask_pd = (1 << HAL_IOMUX_PIN_P3_1);
2155 mask_pu = (1 << HAL_IOMUX_PIN_P3_1);
2156
2157 // Setup voltage as VIO
2158 iomux->REG_094 &= ~(IOMUX_GPIO_P31_SEL_VIO);
2159
2160 // Setup pullup
2161 iomux->REG_02C |= mask_pu;
2162 // Clear pulldown
2163 iomux->REG_030 &= ~mask_pd;
2164 }
2165
2166 //gpio4:epta; gpio20: rxon
2167 if ((rf_switch == 100) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2168 {
2169 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2170 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK)) | IOMUX_GPIO_P20_SEL(13);
2171 }
2172
2173 //fengheyuan(no fem), gpio02 rxon
2174 if ((rf_switch == 102) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2175 {
2176 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK)) | IOMUX_GPIO_P02_SEL(13);
2177 }
2178
2179 /*out fem */
2180 if( (rf_switch == 37) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2181 {
2182 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P13_SEL_MASK)) | IOMUX_GPIO_P13_SEL(13);
2183 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P24_SEL_MASK)) | IOMUX_GPIO_P24_SEL(13);
2184 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P27_SEL_MASK)) | IOMUX_GPIO_P27_SEL(13);
2185 }
2186 if( (rf_switch == 101) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2187 {
2188 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P02_SEL_MASK)) | IOMUX_GPIO_P02_SEL(13);
2189 iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P04_SEL_MASK)) | IOMUX_GPIO_P04_SEL(13);
2190 }
2191 //hwBoEn V1, gpio13(sw2)5g txon; gpio12(sw3)0:bt, 1:2g4;
2192 if((rf_switch == 103) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4)
2193 {
2194 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P12_SEL_MASK)) | IOMUX_GPIO_P12_SEL(13);
2195 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P13_SEL_MASK)) | IOMUX_GPIO_P13_SEL(13);
2196 }
2197 if( (rf_switch == 104) && hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4 )
2198 {
2199 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P12_SEL_MASK)) | IOMUX_GPIO_P12_SEL(13);
2200 iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P13_SEL_MASK)) | IOMUX_GPIO_P13_SEL(13);
2201 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P24_SEL_MASK)) | IOMUX_GPIO_P24_SEL(13);
2202 iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P27_SEL_MASK)) | IOMUX_GPIO_P27_SEL(13);
2203 }
2204 #endif
2205
2206 }
2207