1 /*
2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #include "plat_addr_map.h"
16 #include "cmsis.h"
17 #include "hal_gpio.h"
18 #include "hal_location.h"
19 #include "hal_psc.h"
20 #include "hal_timer.h"
21 #include CHIP_SPECIFIC_HDR(reg_psc)
22
23 #define PSC_WRITE_ENABLE 0xCAFE0000
24
25 enum PSC_INTR_MASK2_T {
26 PSC_INTR_MASK2_GPADC = (1 << 8),
27 PSC_INTR_MASK2_TIMER = (1 << 9),
28 PSC_INTR_MASK2_WDT = (1 << 10),
29 PSC_INTR_MASK2_PMU = (1 << 11),
30 PSC_INTR_MASK2_CHARGE = (1 << 12),
31 PSC_INTR_MASK2_CODEC = (1 << 13),
32 PSC_INTR_MASK2_WAKEUP_BT = (1 << 14),
33 };
34
35 static struct AONPSC_T * const psc = (struct AONPSC_T *)AON_PSC_BASE;
36 BOOT_BSS_LOC static unsigned char g_psc_enable_flags = 0;
37
hal_psc_init(void)38 void BOOT_TEXT_FLASH_LOC hal_psc_init(void)
39 {
40 // Setup MCU wakeup mask
41 psc->REG_080 = 0;
42 psc->REG_084 = 0;
43
44 // Setup BT wakeup mask
45 psc->REG_090 = 0;
46 psc->REG_094 = PSC_INTR_MASK2_WAKEUP_BT;
47
48 // Setup WLAN wakeup mask
49 psc->REG_0A0 = 0;
50 psc->REG_0A4 = 0;
51
52 psc->REG_124 |= PSC_AON_PWR_MEM_SEL_AON_MCU | PSC_AON_PWR_MEM_SEL_AON_BT |
53 PSC_AON_PWR_MEM_SEL_AON_WF | PSC_AON_PWR_MEM_SEL_AON_A7;
54
55 // Power down WLAN
56 hal_psc_wlan_disable();
57 // Power down BT
58 hal_psc_bt_disable();
59 // Power down A7
60 hal_psc_a7_disable();
61 // Power down Codec
62 hal_psc_codec_disable();
63 }
64
hal_psc_codec_enable(void)65 void BOOT_TEXT_FLASH_LOC hal_psc_codec_enable(void)
66 {
67 if(!g_psc_enable_flags)
68 {
69 g_psc_enable_flags = 1;
70 psc->REG_078 = PSC_WRITE_ENABLE |
71 PSC_AON_CODEC_PSW_EN_DR |
72 PSC_AON_CODEC_RESETN_ASSERT_DR | PSC_AON_CODEC_RESETN_ASSERT_REG |
73 PSC_AON_CODEC_ISO_EN_DR | PSC_AON_CODEC_ISO_EN_REG |
74 PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
75 hal_sys_timer_delay(MS_TO_TICKS(1));
76 psc->REG_078 = PSC_WRITE_ENABLE |
77 PSC_AON_CODEC_PSW_EN_DR |
78 PSC_AON_CODEC_RESETN_ASSERT_DR |
79 PSC_AON_CODEC_ISO_EN_DR | PSC_AON_CODEC_ISO_EN_REG |
80 PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
81 psc->REG_078 = PSC_WRITE_ENABLE |
82 PSC_AON_CODEC_PSW_EN_DR |
83 PSC_AON_CODEC_RESETN_ASSERT_DR |
84 PSC_AON_CODEC_ISO_EN_DR |
85 PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
86 psc->REG_078 = PSC_WRITE_ENABLE |
87 PSC_AON_CODEC_PSW_EN_DR |
88 PSC_AON_CODEC_RESETN_ASSERT_DR |
89 PSC_AON_CODEC_ISO_EN_DR |
90 PSC_AON_CODEC_CLK_STOP_DR;
91 }
92
93 }
94
hal_psc_codec_disable(void)95 void BOOT_TEXT_FLASH_LOC hal_psc_codec_disable(void)
96 {
97 if(g_psc_enable_flags)
98 {
99 g_psc_enable_flags = 0;
100 psc->REG_078 = PSC_WRITE_ENABLE |
101 PSC_AON_CODEC_PSW_EN_DR |
102 PSC_AON_CODEC_RESETN_ASSERT_DR |
103 PSC_AON_CODEC_ISO_EN_DR |
104 PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
105 psc->REG_078 = PSC_WRITE_ENABLE |
106 PSC_AON_CODEC_PSW_EN_DR |
107 PSC_AON_CODEC_RESETN_ASSERT_DR |
108 PSC_AON_CODEC_ISO_EN_DR | PSC_AON_CODEC_ISO_EN_REG |
109 PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
110 psc->REG_078 = PSC_WRITE_ENABLE |
111 PSC_AON_CODEC_PSW_EN_DR |
112 PSC_AON_CODEC_RESETN_ASSERT_DR | PSC_AON_CODEC_RESETN_ASSERT_REG |
113 PSC_AON_CODEC_ISO_EN_DR | PSC_AON_CODEC_ISO_EN_REG |
114 PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
115 psc->REG_078 = PSC_WRITE_ENABLE |
116 PSC_AON_CODEC_PSW_EN_DR | PSC_AON_CODEC_PSW_EN_REG |
117 PSC_AON_CODEC_RESETN_ASSERT_DR | PSC_AON_CODEC_RESETN_ASSERT_REG |
118 PSC_AON_CODEC_ISO_EN_DR | PSC_AON_CODEC_ISO_EN_REG |
119 PSC_AON_CODEC_CLK_STOP_DR | PSC_AON_CODEC_CLK_STOP_REG;
120 }
121 }
122
hal_psc_bt_enable(void)123 void BOOT_TEXT_FLASH_LOC hal_psc_bt_enable(void)
124 {
125 psc->REG_038 = PSC_WRITE_ENABLE |
126 PSC_AON_BT_PSW_EN_DR |
127 PSC_AON_BT_RESETN_ASSERT_DR | PSC_AON_BT_RESETN_ASSERT_REG |
128 PSC_AON_BT_ISO_EN_DR | PSC_AON_BT_ISO_EN_REG |
129 PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
130 hal_sys_timer_delay(MS_TO_TICKS(1));
131 psc->REG_038 = PSC_WRITE_ENABLE |
132 PSC_AON_BT_PSW_EN_DR |
133 PSC_AON_BT_RESETN_ASSERT_DR |
134 PSC_AON_BT_ISO_EN_DR | PSC_AON_BT_ISO_EN_REG |
135 PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
136 psc->REG_038 = PSC_WRITE_ENABLE |
137 PSC_AON_BT_PSW_EN_DR |
138 PSC_AON_BT_RESETN_ASSERT_DR |
139 PSC_AON_BT_ISO_EN_DR |
140 PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
141 psc->REG_038 = PSC_WRITE_ENABLE |
142 PSC_AON_BT_PSW_EN_DR |
143 PSC_AON_BT_RESETN_ASSERT_DR |
144 PSC_AON_BT_ISO_EN_DR |
145 PSC_AON_BT_CLK_STOP_DR;
146
147 #ifdef CORE_SLEEP_POWER_DOWN
148 psc->REG_020 = PSC_WRITE_ENABLE | PSC_AON_BT_PG_AUTO_EN | PSC_AON_BT_PG_HW_EN;
149 psc->REG_038 = PSC_WRITE_ENABLE | 0;
150 #endif
151 }
152
hal_psc_bt_disable(void)153 void BOOT_TEXT_FLASH_LOC hal_psc_bt_disable(void)
154 {
155 psc->REG_038 = PSC_WRITE_ENABLE |
156 PSC_AON_BT_PSW_EN_DR |
157 PSC_AON_BT_RESETN_ASSERT_DR |
158 PSC_AON_BT_ISO_EN_DR |
159 PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
160 psc->REG_038 = PSC_WRITE_ENABLE |
161 PSC_AON_BT_PSW_EN_DR |
162 PSC_AON_BT_RESETN_ASSERT_DR |
163 PSC_AON_BT_ISO_EN_DR | PSC_AON_BT_ISO_EN_REG |
164 PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
165 psc->REG_038 = PSC_WRITE_ENABLE |
166 PSC_AON_BT_PSW_EN_DR |
167 PSC_AON_BT_RESETN_ASSERT_DR | PSC_AON_BT_RESETN_ASSERT_REG |
168 PSC_AON_BT_ISO_EN_DR | PSC_AON_BT_ISO_EN_REG |
169 PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
170 psc->REG_038 = PSC_WRITE_ENABLE |
171 PSC_AON_BT_PSW_EN_DR | PSC_AON_BT_PSW_EN_REG |
172 PSC_AON_BT_RESETN_ASSERT_DR | PSC_AON_BT_RESETN_ASSERT_REG |
173 PSC_AON_BT_ISO_EN_DR | PSC_AON_BT_ISO_EN_REG |
174 PSC_AON_BT_CLK_STOP_DR | PSC_AON_BT_CLK_STOP_REG;
175 }
176
hal_psc_bt_enable_auto_power_down(void)177 void hal_psc_bt_enable_auto_power_down(void)
178 {
179 psc->REG_020 = PSC_WRITE_ENABLE | PSC_AON_BT_PG_AUTO_EN | PSC_AON_BT_PG_HW_EN;
180 psc->REG_038 = PSC_WRITE_ENABLE | 0;
181
182 psc->REG_024 |= PSC_AON_BT_SLEEP_NO_WFI;
183 }
184
hal_psc_wlan_enable(void)185 void BOOT_TEXT_FLASH_LOC hal_psc_wlan_enable(void)
186 {
187 hal_cmu_wlan_set_sleep_allow(1);
188 psc->REG_058 = PSC_WRITE_ENABLE |
189 PSC_AON_WLAN_PSW_EN_DR |
190 PSC_AON_WLAN_RESETN_ASSERT_DR | PSC_AON_WLAN_RESETN_ASSERT_REG |
191 PSC_AON_WLAN_ISO_EN_DR | PSC_AON_WLAN_ISO_EN_REG |
192 PSC_AON_WLAN_CLK_STOP_DR | PSC_AON_WLAN_CLK_STOP_REG;
193 hal_sys_timer_delay(MS_TO_TICKS(1));
194 psc->REG_058 = PSC_WRITE_ENABLE |
195 PSC_AON_WLAN_PSW_EN_DR |
196 PSC_AON_WLAN_RESETN_ASSERT_DR |
197 PSC_AON_WLAN_ISO_EN_DR | PSC_AON_WLAN_ISO_EN_REG |
198 PSC_AON_WLAN_CLK_STOP_DR | PSC_AON_WLAN_CLK_STOP_REG;
199 psc->REG_058 = PSC_WRITE_ENABLE |
200 PSC_AON_WLAN_PSW_EN_DR |
201 PSC_AON_WLAN_RESETN_ASSERT_DR |
202 PSC_AON_WLAN_ISO_EN_DR |
203 PSC_AON_WLAN_CLK_STOP_DR | PSC_AON_WLAN_CLK_STOP_REG;
204 psc->REG_058 = PSC_WRITE_ENABLE |
205 PSC_AON_WLAN_PSW_EN_DR |
206 PSC_AON_WLAN_RESETN_ASSERT_DR |
207 PSC_AON_WLAN_ISO_EN_DR |
208 PSC_AON_WLAN_CLK_STOP_DR;
209 #ifdef CORE_SLEEP_POWER_DOWN
210 psc->REG_040 = PSC_WRITE_ENABLE | PSC_AON_WLAN_PG_AUTO_EN | PSC_AON_WLAN_PG_HW_EN;
211 psc->REG_058 = PSC_WRITE_ENABLE | 0;
212 #endif
213 }
214
hal_psc_wlan_disable(void)215 void BOOT_TEXT_FLASH_LOC hal_psc_wlan_disable(void)
216 {
217 psc->REG_058 = PSC_WRITE_ENABLE |
218 PSC_AON_WLAN_PSW_EN_DR |
219 PSC_AON_WLAN_RESETN_ASSERT_DR |
220 PSC_AON_WLAN_ISO_EN_DR |
221 PSC_AON_WLAN_CLK_STOP_DR | PSC_AON_WLAN_CLK_STOP_REG;
222 psc->REG_058 = PSC_WRITE_ENABLE |
223 PSC_AON_WLAN_PSW_EN_DR |
224 PSC_AON_WLAN_RESETN_ASSERT_DR |
225 PSC_AON_WLAN_ISO_EN_DR | PSC_AON_WLAN_ISO_EN_REG |
226 PSC_AON_WLAN_CLK_STOP_DR | PSC_AON_WLAN_CLK_STOP_REG;
227 psc->REG_058 = PSC_WRITE_ENABLE |
228 PSC_AON_WLAN_PSW_EN_DR |
229 PSC_AON_WLAN_RESETN_ASSERT_DR | PSC_AON_WLAN_RESETN_ASSERT_REG |
230 PSC_AON_WLAN_ISO_EN_DR | PSC_AON_WLAN_ISO_EN_REG |
231 PSC_AON_WLAN_CLK_STOP_DR | PSC_AON_WLAN_CLK_STOP_REG;
232 psc->REG_058 = PSC_WRITE_ENABLE |
233 PSC_AON_WLAN_PSW_EN_DR | PSC_AON_WLAN_PSW_EN_REG |
234 PSC_AON_WLAN_RESETN_ASSERT_DR | PSC_AON_WLAN_RESETN_ASSERT_REG |
235 PSC_AON_WLAN_ISO_EN_DR | PSC_AON_WLAN_ISO_EN_REG |
236 PSC_AON_WLAN_CLK_STOP_DR | PSC_AON_WLAN_CLK_STOP_REG;
237 hal_cmu_wlan_set_sleep_allow(0);
238 }
239
hal_psc_a7_enable(void)240 void BOOT_TEXT_FLASH_LOC hal_psc_a7_enable(void)
241 {
242 psc->REG_0D8 = PSC_WRITE_ENABLE |
243 PSC_AON_A7_PSW_EN_DR |
244 PSC_AON_A7_RESETN_ASSERT_DR | PSC_AON_A7_RESETN_ASSERT_REG |
245 PSC_AON_A7_ISO_EN_DR | PSC_AON_A7_ISO_EN_REG |
246 PSC_AON_A7_CLK_STOP_DR | PSC_AON_A7_CLK_STOP_REG;
247 hal_sys_timer_delay(MS_TO_TICKS(1));
248 psc->REG_0D8 = PSC_WRITE_ENABLE |
249 PSC_AON_A7_PSW_EN_DR |
250 PSC_AON_A7_RESETN_ASSERT_DR |
251 PSC_AON_A7_ISO_EN_DR | PSC_AON_A7_ISO_EN_REG |
252 PSC_AON_A7_CLK_STOP_DR | PSC_AON_A7_CLK_STOP_REG;
253 psc->REG_0D8 = PSC_WRITE_ENABLE |
254 PSC_AON_A7_PSW_EN_DR |
255 PSC_AON_A7_RESETN_ASSERT_DR |
256 PSC_AON_A7_ISO_EN_DR |
257 PSC_AON_A7_CLK_STOP_DR | PSC_AON_A7_CLK_STOP_REG;
258 psc->REG_0D8 = PSC_WRITE_ENABLE |
259 PSC_AON_A7_PSW_EN_DR |
260 PSC_AON_A7_RESETN_ASSERT_DR |
261 PSC_AON_A7_ISO_EN_DR |
262 PSC_AON_A7_CLK_STOP_DR;
263 }
264
hal_psc_a7_disable(void)265 void BOOT_TEXT_FLASH_LOC hal_psc_a7_disable(void)
266 {
267 psc->REG_0D8 = PSC_WRITE_ENABLE |
268 PSC_AON_A7_PSW_EN_DR |
269 PSC_AON_A7_RESETN_ASSERT_DR |
270 PSC_AON_A7_ISO_EN_DR |
271 PSC_AON_A7_CLK_STOP_DR | PSC_AON_A7_CLK_STOP_REG;
272 psc->REG_0D8 = PSC_WRITE_ENABLE |
273 PSC_AON_A7_PSW_EN_DR |
274 PSC_AON_A7_RESETN_ASSERT_DR |
275 PSC_AON_A7_ISO_EN_DR | PSC_AON_A7_ISO_EN_REG |
276 PSC_AON_A7_CLK_STOP_DR | PSC_AON_A7_CLK_STOP_REG;
277 psc->REG_0D8 = PSC_WRITE_ENABLE |
278 PSC_AON_A7_PSW_EN_DR |
279 PSC_AON_A7_RESETN_ASSERT_DR | PSC_AON_A7_RESETN_ASSERT_REG |
280 PSC_AON_A7_ISO_EN_DR | PSC_AON_A7_ISO_EN_REG |
281 PSC_AON_A7_CLK_STOP_DR | PSC_AON_A7_CLK_STOP_REG;
282 psc->REG_0D8 = PSC_WRITE_ENABLE |
283 PSC_AON_A7_PSW_EN_DR | PSC_AON_A7_PSW_EN_REG |
284 PSC_AON_A7_RESETN_ASSERT_DR | PSC_AON_A7_RESETN_ASSERT_REG |
285 PSC_AON_A7_ISO_EN_DR | PSC_AON_A7_ISO_EN_REG |
286 PSC_AON_A7_CLK_STOP_DR | PSC_AON_A7_CLK_STOP_REG;
287 }
288
hal_psc_dslp_force_on_bt_enable(void)289 void SRAM_TEXT_LOC hal_psc_dslp_force_on_bt_enable(void)
290 {
291 psc->REG_124 |= PSC_AON_DSLP_FORCE_ON_BT_REG;
292 }
293
hal_psc_dslp_force_on_bt_disable(void)294 void SRAM_TEXT_LOC hal_psc_dslp_force_on_bt_disable(void)
295 {
296 psc->REG_124 &= ~(PSC_AON_DSLP_FORCE_ON_BT_REG);
297 }
298
hal_psc_bt_auto_power_down(void)299 void SRAM_TEXT_LOC hal_psc_bt_auto_power_down(void)
300 {
301 psc->REG_038 = PSC_WRITE_ENABLE | 0;
302 psc->REG_020 = PSC_WRITE_ENABLE | PSC_AON_BT_PG_AUTO_EN | PSC_AON_BT_PG_HW_EN;
303 psc->REG_030 = PSC_WRITE_ENABLE | PSC_AON_BT_POWERDN_START;
304 }
305
hal_psc_wlan_auto_power_down(void)306 void SRAM_TEXT_LOC hal_psc_wlan_auto_power_down(void)
307 {
308 psc->REG_058 = PSC_WRITE_ENABLE | 0;
309 psc->REG_040 = PSC_WRITE_ENABLE | PSC_AON_WLAN_PG_AUTO_EN | PSC_AON_WLAN_PG_HW_EN;
310 psc->REG_050 = PSC_WRITE_ENABLE | PSC_AON_WLAN_POWERDN_START;
311 }
312
hal_psc_core_auto_power_down(void)313 void SRAM_TEXT_LOC hal_psc_core_auto_power_down(void)
314 {
315 // 2003 MCU doesn't support power_down
316 }
317
hal_psc_mcu_gpio_irq_enable(enum HAL_GPIO_PIN_T pin)318 void hal_psc_mcu_gpio_irq_enable(enum HAL_GPIO_PIN_T pin)
319 {
320 if (pin < HAL_GPIO_PIN_NUM) {
321 psc->REG_080 |= (1 << pin);
322 }
323 }
324
hal_psc_mcu_gpio_irq_disable(enum HAL_GPIO_PIN_T pin)325 void hal_psc_mcu_gpio_irq_disable(enum HAL_GPIO_PIN_T pin)
326 {
327 if (pin < HAL_GPIO_PIN_NUM) {
328 psc->REG_080 &= ~(1 << pin);
329 }
330 }
331
hal_psc_mcu_gpio_irq_get_status(uint32_t * status,uint32_t cnt)332 uint32_t hal_psc_mcu_gpio_irq_get_status(uint32_t *status, uint32_t cnt)
333 {
334 volatile uint32_t * const irq_status[] = {
335 &psc->REG_088,
336 };
337 uint32_t i;
338
339 if (cnt > ARRAY_SIZE(irq_status)) {
340 cnt = ARRAY_SIZE(irq_status);
341 }
342 if (status) {
343 for (i = 0; i < cnt; i++) {
344 status[i] = *irq_status[i];
345 }
346 }
347 return cnt;
348 }
349
hal_psc_gpio_irq_enable(enum HAL_GPIO_PIN_T pin)350 void hal_psc_gpio_irq_enable(enum HAL_GPIO_PIN_T pin)
351 {
352 hal_psc_mcu_gpio_irq_enable(pin);
353 }
354
hal_psc_gpio_irq_disable(enum HAL_GPIO_PIN_T pin)355 void hal_psc_gpio_irq_disable(enum HAL_GPIO_PIN_T pin)
356 {
357 hal_psc_mcu_gpio_irq_disable(pin);
358 }
359
hal_psc_gpio_irq_get_status(uint32_t * status,uint32_t cnt)360 uint32_t hal_psc_gpio_irq_get_status(uint32_t *status, uint32_t cnt)
361 {
362 return hal_psc_mcu_gpio_irq_get_status(status, cnt);
363 }
364
hal_psc_get_power_loop_cycle_cnt(void)365 uint32_t hal_psc_get_power_loop_cycle_cnt(void)
366 {
367 return 6 + 14 + 14; // 1.5 + 4.5 + 14 + 14
368 }
369
370