1 /*
2 * hifmc100.c
3 *
4 * The Flash Memory Controller v100 Device Driver for hisilicon
5 *
6 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23 #include "hifmc100.h"
24 #include <common.h>
25 #include <asm/io.h>
26 #include <errno.h>
27 #include <malloc.h>
28 #include <match_table.h>
29 #include <asm/arch/platform.h>
30
31 /*****************************************************************************/
hifmc100_ecc0_switch(struct hifmc_host * host,unsigned char op)32 void hifmc100_ecc0_switch(struct hifmc_host *host, unsigned char op)
33 {
34 unsigned int config;
35 #if EC_DBG
36 unsigned int cmp_cfg;
37
38 config = hifmc_read(host, FMC_CFG);
39 fmc_pr(EC_DBG, "\t *-Get CFG[%#x]%#x\n", FMC_CFG, config);
40
41 if (op)
42 cmp_cfg = host->fmc_cfg;
43 else
44 cmp_cfg = host->fmc_cfg_ecc0;
45
46 if (cmp_cfg != config)
47 db_msg("Warning: FMC config[%#x] is different.\n",
48 cmp_cfg);
49 #endif
50
51 if (op == ENABLE) {
52 config = host->fmc_cfg_ecc0;
53 } else if (op == DISABLE) {
54 config = host->fmc_cfg;
55 } else {
56 db_msg("Error: Invalid opcode: %d\n", op);
57 return;
58 }
59
60 hifmc_write(host, FMC_CFG, config);
61 fmc_pr(EC_DBG, "\t *-Set CFG[%#x]%#x\n", FMC_CFG, config);
62 }
63
64 /*****************************************************************************/
select_addr_of(unsigned char only_oob,struct hifmc_host * host)65 static u32 select_addr_of(unsigned char only_oob, struct hifmc_host *host)
66 {
67 unsigned int addr_of = 0;
68
69 if (only_oob)
70 switch (host->ecctype) {
71 case NAND_ECC_8BIT:
72 addr_of = REG_CNT_ECC_8BIT_OFFSET;
73 break;
74
75 case NAND_ECC_16BIT:
76 addr_of = REG_CNT_ECC_16BIT_OFFSET;
77 break;
78
79 case NAND_ECC_24BIT:
80 addr_of = REG_CNT_ECC_24BIT_OFFSET;
81 break;
82
83 case NAND_ECC_0BIT:
84 default:
85 break;
86 }
87 return addr_of;
88 }
89
set_dma_addr_reg(struct hifmc_host * host)90 static void set_dma_addr_reg(struct hifmc_host *host)
91 {
92 unsigned int reg;
93
94 reg = host->dma_buffer;
95 hifmc_write(host, FMC_DMA_SADDR_D0, reg);
96 fmc_pr(DMA_DB, "\t|-Set DMA_SADDR_D0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg);
97 /* get hight 32 bits */
98 reg = ((unsigned long)host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
99 hifmc_write(host, FMC_DMA_SADDRH_D0, reg);
100 fmc_pr(DMA_DB, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
101 reg = host->dma_oob;
102 hifmc_write(host, FMC_DMA_SADDR_OOB, reg);
103 fmc_pr(DMA_DB, "\t|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB,
104 reg);
105 /* get hight 32 bits */
106 reg = ((unsigned long)host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
107 hifmc_write(host, FMC_DMA_SADDRH_OOB, reg);
108 fmc_pr(DMA_DB, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB,
109 reg);
110 }
111
set_addr_reg(unsigned int addr_of,struct hifmc_host * host)112 static void set_addr_reg(unsigned int addr_of, struct hifmc_host *host)
113 {
114 unsigned int reg;
115 struct nand_chip *chip = host->chip;
116 unsigned char pages_per_block_shift;
117 unsigned int block_num;
118 unsigned int block_num_h;
119 unsigned int page_num;
120
121 pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
122 block_num = host->addr_value[1] >> pages_per_block_shift;
123 block_num_h = block_num >> REG_CNT_HIGH_BLOCK_NUM_SHIFT;
124 reg = fmc_addrh_set(block_num_h);
125 hifmc_write(host, FMC_ADDRH, reg);
126 fmc_pr(REG_DB, "|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
127
128 page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
129 reg = ((block_num & REG_CNT_BLOCK_NUM_MASK) << REG_CNT_BLOCK_NUM_SHIFT) |
130 ((page_num & REG_CNT_PAGE_NUM_MASK) << REG_CNT_PAGE_NUM_SHIFT) |
131 (addr_of & REG_CNT_ECC_OFFSET_MASK);
132 hifmc_write(host, FMC_ADDRL, reg);
133 fmc_pr(REG_DB, "|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
134 }
135
136 /****************************************************************************/
set_cs_addr_reg(enum OP op,unsigned char only_oob,struct hifmc_host * host)137 static void set_cs_addr_reg(enum OP op, unsigned char only_oob,
138 struct hifmc_host *host)
139 {
140 unsigned int reg;
141 struct hifmc_spi *spi = host->spi;
142 unsigned char iftype = 0;
143 unsigned char dummy = 0;
144 unsigned int addr_of = 0;
145
146 reg = FMC_INT_CLR_ALL;
147 hifmc_write(host, FMC_INT_CLR, reg);
148 fmc_pr(WR_DBG, "|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
149
150 if (op == READ) {
151 iftype = spi->read->iftype;
152 dummy = spi->read->dummy;
153 addr_of = select_addr_of(only_oob, host);
154 } else if (op == WRITE) {
155 iftype = spi->write->iftype;
156 } else {
157 iftype = spi->erase->iftype;
158 }
159
160 reg = op_cfg_fm_cs(host->cmd_op.cs) |
161 OP_CFG_OEN_EN |
162 op_cfg_mem_if_type(iftype) |
163 op_cfg_dummy_num(dummy);
164 hifmc_write(host, FMC_OP_CFG, reg);
165 fmc_pr(REG_DB, "|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
166
167 set_addr_reg(addr_of, host);
168 }
169
170 /*****************************************************************************/
hifmc100_send_cmd_pageprog(struct hifmc_host * host)171 static void hifmc100_send_cmd_pageprog(struct hifmc_host *host)
172 {
173 unsigned int reg;
174 struct hifmc_spi *spi = host->spi;
175 unsigned char *hifmc_ip = NULL;
176 #ifndef CONFIG_SYS_DCACHE_OFF
177 unsigned int dma_align_len;
178 #endif
179 fmc_pr(WR_DBG, "\n*-Enter Dma page program!\n");
180
181 hifmc_ip = get_hifmc_ip();
182 if (*hifmc_ip) {
183 printf("Warning: Hifmc IP is busy, Please try again.\n");
184 udelay(1); /* delay 1 us */
185 return;
186 } else {
187 hifmc_dev_type_switch(FLASH_TYPE_SPI_NAND);
188 (*hifmc_ip)++;
189 }
190
191 reg = spi->driver->write_enable(spi);
192 if (reg) {
193 db_msg("Error: Dma program write enable failed! reg: %#x\n", reg);
194 goto end;
195 }
196
197 host->set_system_clock(spi->write, ENABLE);
198
199 if (ecc0_flag == 1) {
200 hifmc100_ecc0_switch(host, ENABLE);
201 hifmc_write(host, FMC_DMA_LEN, oobsize_real);
202 }
203
204 set_cs_addr_reg(WRITE, 0, host);
205
206 if (ecc0_flag != 1)
207 *host->epm = 0x0000;
208
209 #ifndef CONFIG_SYS_DCACHE_OFF
210 dma_align_len = ((host->pagesize + host->oobsize +
211 CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
212 flush_dcache_range(host->dma_buffer, host->dma_buffer + dma_align_len);
213 #endif
214
215 set_dma_addr_reg(host);
216
217 reg = op_ctrl_wr_opcode(spi->write->cmd) | op_ctrl_dma_op(OP_TYPE_DMA) |
218 op_ctrl_rw_op(RW_OP_WRITE) | OP_CTRL_DMA_OP_READY;
219 hifmc_write(host, FMC_OP_CTRL, reg);
220 fmc_pr(WR_DBG, "|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
221 fmc_dma_wait_int_finish(host);
222
223 if (ecc0_flag == 1)
224 hifmc100_ecc0_switch(host, DISABLE);
225
226 reg = spi->driver->wait_ready(spi);
227 if (reg)
228 db_msg("Error: Dma program wait ready failed! status: %#x\n", reg);
229
230 end:
231 (*hifmc_ip)--;
232 fmc_pr(WR_DBG, "*-End Dma page program!\n");
233 }
234 /*****************************************************************************/
hifmc100_send_cmd_readstart(struct hifmc_host * host)235 static void hifmc100_send_cmd_readstart(struct hifmc_host *host)
236 {
237 unsigned char only_oob = 0;
238 unsigned int reg;
239 struct hifmc_spi *spi = host->spi;
240 unsigned char *hifmc_ip = NULL;
241 #ifndef CONFIG_SYS_DCACHE_OFF
242 unsigned int dma_align_len;
243 #endif
244 fmc_pr(RD_DBG, "\n\t*-Start Dma page read\n");
245
246 hifmc_ip = get_hifmc_ip();
247 if (*hifmc_ip) {
248 printf("Warning: Hifmc IP is busy, Please try again.\n");
249 udelay(1); /* delay 1 us */
250 return;
251 } else {
252 hifmc_dev_type_switch(FLASH_TYPE_SPI_NAND);
253 (*hifmc_ip)++;
254 }
255
256 host->set_system_clock(spi->read, ENABLE);
257
258 if (ecc0_flag == 1 && (host->cmd_op.l_cmd != NAND_CMD_READOOB)) {
259 hifmc100_ecc0_switch(host, ENABLE);
260 hifmc_write(host, FMC_DMA_LEN, oobsize_real);
261 }
262
263 if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
264 only_oob = 1;
265 host->cmd_op.op_cfg = op_ctrl_rd_op_sel(RD_OP_READ_OOB);
266 } else {
267 host->cmd_op.op_cfg = op_ctrl_rd_op_sel(RD_OP_READ_ALL_PAGE);
268 }
269
270 set_cs_addr_reg(READ, only_oob, host);
271
272 #ifndef CONFIG_SYS_DCACHE_OFF
273 dma_align_len = ((host->pagesize + host->oobsize +
274 CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
275 invalidate_dcache_range(host->dma_buffer, host->dma_buffer + dma_align_len);
276 #endif
277 set_dma_addr_reg(host);
278
279 reg = op_ctrl_rd_opcode(spi->read->cmd) |
280 host->cmd_op.op_cfg | op_ctrl_dma_op(OP_TYPE_DMA) |
281 op_ctrl_rw_op(RW_OP_READ) | OP_CTRL_DMA_OP_READY;
282 hifmc_write(host, FMC_OP_CTRL, reg);
283 fmc_pr(RD_DBG, "\t|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
284 fmc_dma_wait_int_finish(host);
285
286 if (ecc0_flag == 1 && (host->cmd_op.l_cmd != NAND_CMD_READOOB))
287 hifmc100_ecc0_switch(host, DISABLE);
288
289 #ifndef CONFIG_SYS_DCACHE_OFF
290 invalidate_dcache_range(host->dma_buffer, host->dma_buffer + dma_align_len);
291 #endif
292
293 (*hifmc_ip)--;
294 fmc_pr(RD_DBG, "\t*-End Dma page read\n");
295 }
296
297 /*****************************************************************************/
hifmc100_send_cmd_erase(struct hifmc_host * host)298 static void hifmc100_send_cmd_erase(struct hifmc_host *host)
299 {
300 unsigned int reg;
301 struct hifmc_spi *spi = host->spi;
302 unsigned char *hifmc_ip = NULL;
303
304 if (ER_DBG)
305 printf("\n");
306 fmc_pr(ER_DBG, "\t*-Start send cmd erase!\n");
307
308 hifmc_ip = get_hifmc_ip();
309 if (*hifmc_ip) {
310 printf("Warning: Hifmc IP is busy, Please try again.\n");
311 udelay(1); /* delay 1 us */
312 return;
313 } else {
314 hifmc_dev_type_switch(FLASH_TYPE_SPI_NAND);
315 (*hifmc_ip)++;
316 }
317
318 reg = spi->driver->write_enable(spi);
319 if (reg) {
320 db_msg("Error: Erase write enable failed! reg: %#x\n", reg);
321 goto end;
322 }
323
324 host->set_system_clock(spi->erase, ENABLE);
325
326 reg = FMC_INT_CLR_ALL;
327 hifmc_write(host, FMC_INT_CLR, reg);
328 fmc_pr(ER_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
329
330 reg = spi->erase->cmd;
331 hifmc_write(host, FMC_CMD, fmc_cmd_cmd1(reg));
332 fmc_pr(ER_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
333
334 reg = fmc_addrl_block_h_mask(host->addr_value[1]) |
335 fmc_addrl_block_l_mask(host->addr_value[0]);
336 hifmc_write(host, FMC_ADDRL, reg);
337 fmc_pr(ER_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
338
339 reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN |
340 op_cfg_mem_if_type(spi->erase->iftype) |
341 op_cfg_addr_num(STD_OP_ADDR_NUM) |
342 op_cfg_dummy_num(spi->erase->dummy);
343
344 hifmc_write(host, FMC_OP_CFG, reg);
345 fmc_pr(ER_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
346
347 reg = fmc_op_cmd1_en(ENABLE) | fmc_op_addr_en(ENABLE) |
348 FMC_OP_REG_OP_START;
349 hifmc_write(host, FMC_OP, reg);
350 fmc_pr(ER_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, reg);
351
352 fmc_cmd_wait_cpu_finish(host);
353
354 reg = spi->driver->wait_ready(spi);
355 fmc_pr(ER_DBG, "\t|-Erase wait ready, reg: %#x\n", reg);
356 if (reg)
357 db_msg("Error: Erase wait ready fail! status: %#x\n", reg);
358
359 end:
360 (*hifmc_ip)--;
361
362 fmc_pr(ER_DBG, "\t*-End send cmd erase!\n");
363 }
364
365 /*****************************************************************************/
hifmc100_send_cmd_status(struct hifmc_host * host)366 static void hifmc100_send_cmd_status(struct hifmc_host *host)
367 {
368 unsigned char status;
369 unsigned char addr = STATUS_ADDR;
370 struct hifmc_spi *spi = host->spi;
371 unsigned char *hifmc_ip = get_hifmc_ip();
372
373 if (*hifmc_ip) {
374 printf("Warning: Hifmc IP is busy, Please try again.\n");
375 udelay(1); /* delay 1 us */
376 return;
377 } else {
378 hifmc_dev_type_switch(FLASH_TYPE_SPI_NAND);
379 (*hifmc_ip)++;
380 }
381
382 if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES)
383 addr = PROTECT_ADDR;
384
385 status = spi_nand_feature_op(spi, GET_OP, addr, 0);
386 fmc_pr((ER_DBG || WR_DBG), "\t*-Get status[%#x]: %#x\n", addr, status);
387
388 (*hifmc_ip)--;
389 }
390
391 /*****************************************************************************/
hifmc100_send_cmd_readid(struct hifmc_host * host)392 static void hifmc100_send_cmd_readid(struct hifmc_host *host)
393 {
394 unsigned int reg;
395
396 fmc_pr(BT_DBG, "\t|*-Start send cmd read ID\n");
397
398 hifmc100_ecc0_switch(host, ENABLE);
399
400 reg = fmc_cmd_cmd1(SPI_CMD_RDID);
401 hifmc_write(host, FMC_CMD, reg);
402 fmc_pr(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
403
404 reg = READ_ID_ADDR;
405 hifmc_write(host, FMC_ADDRL, reg);
406 fmc_pr(BT_DBG, "\t||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
407
408 reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN |
409 op_cfg_addr_num(READ_ID_ADDR_NUM);
410 hifmc_write(host, FMC_OP_CFG, reg);
411 fmc_pr(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
412
413 reg = fmc_data_num_cnt(MAX_SPI_NAND_ID_LEN);
414 hifmc_write(host, FMC_DATA_NUM, reg);
415 fmc_pr(BT_DBG, "\t||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
416
417 reg = fmc_op_cmd1_en(ENABLE) | fmc_op_addr_en(ENABLE) |
418 fmc_op_read_data_en(ENABLE) | FMC_OP_REG_OP_START;
419 hifmc_write(host, FMC_OP, reg);
420 fmc_pr(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
421
422 host->addr_cycle = 0x0;
423
424 fmc_cmd_wait_cpu_finish(host);
425
426 hifmc100_ecc0_switch(host, DISABLE);
427
428 fmc_pr(BT_DBG, "\t|*-End read flash ID\n");
429 }
430
431 /*****************************************************************************/
hifmc100_send_cmd_reset(struct hifmc_host * host)432 static void hifmc100_send_cmd_reset(struct hifmc_host *host)
433 {
434 unsigned int reg;
435
436 fmc_pr(BT_DBG, "\t|*-Start send cmd reset\n");
437
438 reg = fmc_cmd_cmd1(SPI_CMD_RESET);
439 hifmc_write(host, FMC_CMD, reg);
440 fmc_pr(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
441
442 reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN;
443 hifmc_write(host, FMC_OP_CFG, reg);
444 fmc_pr(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
445
446 reg = fmc_op_cmd1_en(ENABLE) | FMC_OP_REG_OP_START;
447 hifmc_write(host, FMC_OP, reg);
448 fmc_pr(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
449
450 fmc_cmd_wait_cpu_finish(host);
451
452 fmc_pr(BT_DBG, "\t|*-End send cmd reset\n");
453 }
454
455 /*****************************************************************************/
hifmc100_read_byte(struct mtd_info * mtd)456 static unsigned char hifmc100_read_byte(struct mtd_info *mtd)
457 {
458 struct nand_chip *chip = mtd_to_nand(mtd);
459 struct hifmc_host *host = chip->priv;
460 unsigned char value = 0;
461 unsigned char ret_val = 0;
462
463 if (host->cmd_op.l_cmd == NAND_CMD_READID) {
464 value = readb(host->iobase + host->offset);
465 host->offset++;
466 if (host->cmd_op.data_no == host->offset)
467 host->cmd_op.l_cmd = 0;
468 return value;
469 }
470
471 if (host->cmd_op.cmd == NAND_CMD_STATUS) {
472 value = hifmc_read(host, FMC_STATUS);
473 if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES) {
474 fmc_pr((ER_DBG || WR_DBG), "\t\tRead BP status: %#x\n",
475 value);
476 if (any_bp_enable(value))
477 ret_val |= NAND_STATUS_WP;
478
479 host->cmd_op.l_cmd = NAND_CMD_STATUS;
480 }
481
482 if (!(value & STATUS_OIP_MASK))
483 ret_val |= NAND_STATUS_READY;
484
485 if ((chip->state == FL_ERASING) &&
486 (value & STATUS_E_FAIL_MASK)) {
487 fmc_pr(ER_DBG, "\t\tGet erase status: %#x\n", value);
488 ret_val |= NAND_STATUS_FAIL;
489 }
490
491 if ((chip->state == FL_WRITING) &&
492 (value & STATUS_P_FAIL_MASK)) {
493 fmc_pr(WR_DBG, "\t\tGet write status: %#x\n", value);
494 ret_val |= NAND_STATUS_FAIL;
495 }
496
497 return ret_val;
498 }
499
500 if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
501 value = readb((unsigned char *)
502 ((unsigned char *)(uintptr_t)host->dma_oob + host->offset));
503 host->offset++;
504 return value;
505 }
506
507 host->offset++;
508
509 return readb(host->buffer + host->column + host->offset - 1);
510 }
511
512 /*****************************************************************************/
hifmc100_read_word(struct mtd_info * mtd)513 static unsigned short hifmc100_read_word(struct mtd_info *mtd)
514 {
515 struct nand_chip *chip = mtd_to_nand(mtd);
516 struct hifmc_host *host = chip->priv;
517
518 return readw(host->buffer + host->column + host->offset);
519 }
520
521 /*****************************************************************************/
hifmc100_write_buf(struct mtd_info * mtd,const u_char * buf,int len)522 static void hifmc100_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
523 {
524 struct nand_chip *chip = mtd_to_nand(mtd);
525 struct hifmc_host *host = chip->priv;
526
527 if (buf == chip->oob_poi)
528 memcpy((unsigned char *)(uintptr_t)host->dma_oob, buf, len);
529 else
530 memcpy((unsigned char *)(uintptr_t)host->dma_buffer, buf, len);
531 return;
532 }
533
534 /*****************************************************************************/
hifmc100_read_buf(struct mtd_info * mtd,u_char * buf,int len)535 static void hifmc100_read_buf(struct mtd_info *mtd, u_char *buf, int len)
536 {
537 struct nand_chip *chip = mtd_to_nand(mtd);
538 struct hifmc_host *host = chip->priv;
539
540 if (buf == chip->oob_poi)
541 memcpy(buf, (unsigned char *)(uintptr_t)host->dma_oob, len);
542 else
543 memcpy(buf, (unsigned char *)(uintptr_t)host->dma_buffer, len);
544 return;
545 }
546
547 /*****************************************************************************/
hifmc100_select_chip(struct mtd_info * mtd,int chipselect)548 static void hifmc100_select_chip(struct mtd_info *mtd, int chipselect)
549 {
550 struct nand_chip *chip = mtd_to_nand(mtd);
551 struct hifmc_host *host = chip->priv;
552
553 if (chipselect < 0)
554 return;
555
556 if (chipselect > CONFIG_SPI_NAND_MAX_CHIP_NUM)
557 db_bug("Error: Invalid chipselect: %d\n", chipselect);
558
559 if (host->mtd != mtd)
560 host->mtd = mtd;
561
562 if (!(chip->options & NAND_BROKEN_XD))
563 if ((chip->state == FL_ERASING) || (chip->state == FL_WRITING))
564 host->cmd_op.l_cmd = NAND_CMD_GET_FEATURES;
565 }
566
567 /******************************************************************************/
hifmc100_cmdfunc(struct mtd_info * mtd,unsigned int command,int column,int page_addr)568 static void hifmc100_cmdfunc(struct mtd_info *mtd,
569 unsigned int command,
570 int column, int page_addr)
571 {
572 struct nand_chip *chip = mtd_to_nand(mtd);
573 struct hifmc_host *host = chip->priv;
574
575 switch (command) {
576 case NAND_CMD_RESET:
577 host->send_cmd_reset(host);
578 chip->dev_ready(mtd);
579 break;
580 case NAND_CMD_READID:
581 host->offset = 0;
582 host->cmd_op.l_cmd = command & 0xff;
583 memset((u_char *)(host->iobase), 0, MAX_SPI_NAND_ID_LEN);
584 host->cmd_op.data_no = MAX_SPI_NAND_ID_LEN;
585 host->send_cmd_readid(host);
586 break;
587 case NAND_CMD_GET_FEATURES:
588 case NAND_CMD_STATUS:
589 host->cmd_op.l_cmd = command & 0xff;
590 host->cmd_op.cmd = NAND_CMD_STATUS;
591 host->send_cmd_status(host);
592 break;
593 case NAND_CMD_READOOB:
594 host->offset = 0;
595 host->cmd_op.l_cmd = command & 0xff;
596 /* use same command as normal read */
597 host->cmd_op.cmd = command & 0xff;
598 case NAND_CMD_READ0:
599 if (command == NAND_CMD_READ0)
600 host->cmd_op.l_cmd = command & 0xff;
601 host->addr_value[1] = page_addr;
602 host->send_cmd_readstart(host);
603 break;
604 case NAND_CMD_SEQIN:
605 host->addr_value[1] = page_addr;
606 break;
607 case NAND_CMD_PAGEPROG:
608 host->offset = 0;
609 host->send_cmd_pageprog(host);
610 break;
611 case NAND_CMD_ERASE1:
612 host->cmd_op.l_cmd = command & 0xff;
613 host->addr_value[0] = page_addr;
614 /* page_addr to block_addr, move right 16 bits */
615 host->addr_value[1] = (unsigned int)page_addr >> 16;
616 /* erase operation need a seral of command sequences */
617 host->send_cmd_erase(host);
618 break;
619 case NAND_CMD_ERASE2:
620 case NAND_CMD_READSTART:
621 break;
622 default:
623 printf("%s not support command 0x%08x:\n", mtd->name, command);
624 break;
625 }
626 }
627
628 /*****************************************************************************/
hifmc100_dev_ready(struct mtd_info * mtd)629 static int hifmc100_dev_ready(struct mtd_info *mtd)
630 {
631 unsigned int reg = 0;
632 /* just a big number, so move 12 bits */
633 unsigned long deadline = 1 << 12;
634 struct nand_chip *chip = mtd_to_nand(mtd);
635 struct hifmc_host *host = chip->priv;
636
637 do {
638 reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN;
639 hifmc_write(host, FMC_OP_CFG, reg);
640
641 reg = fmc_op_read_status_en(ENABLE) | FMC_OP_REG_OP_START;
642 hifmc_write(host, FMC_OP, reg);
643
644 fmc_cmd_wait_cpu_finish(host);
645
646 reg = hifmc_read(host, FMC_STATUS);
647 if (!(reg & STATUS_OIP_MASK))
648 return 1;
649
650 udelay(1); /* delay 1 us */
651 } while (deadline--);
652
653 #ifndef CONFIG_SYS_NAND_QUIET_TEST
654 printf("Warning: Wait SPI nand ready timeout, status: %#x\n", reg);
655 #endif
656
657 return 0;
658 }
659
660 /*****************************************************************************/
661 /*
662 * 'host->epm' only use the first oobfree[0] field, it looks very simple, But..
663 */
664 static struct nand_ecclayout nand_ecc_default = {
665 .oobfree = {{2, 30} }
666 };
667
668 #ifdef CONFIG_FS_MAY_NOT_YAFFS2
669 static struct nand_ecclayout nand_ecc_2k16bit = {
670 .oobfree = {{2, 6} }
671 };
672
673 static struct nand_ecclayout nand_ecc_4k16bit = {
674 .oobfree = {{2, 14} }
675 };
676 #endif
677
678 /*****************************************************************************/
679 static struct nand_config_info hifmc_spi_nand_config_table[] = {
680 {NAND_PAGE_4K, NAND_ECC_24BIT, 200, &nand_ecc_default},
681 #ifdef CONFIG_FS_MAY_NOT_YAFFS2
682 {NAND_PAGE_4K, NAND_ECC_16BIT, 128, &nand_ecc_4k16bit},
683 #endif
684 {NAND_PAGE_4K, NAND_ECC_8BIT, 128, &nand_ecc_default},
685 {NAND_PAGE_4K, NAND_ECC_0BIT, 32, &nand_ecc_default},
686
687 {NAND_PAGE_2K, NAND_ECC_24BIT, 128, &nand_ecc_default},
688 #ifdef CONFIG_FS_MAY_NOT_YAFFS2
689 {NAND_PAGE_2K, NAND_ECC_16BIT, 64, &nand_ecc_2k16bit},
690 #endif
691 {NAND_PAGE_2K, NAND_ECC_8BIT, 64, &nand_ecc_default},
692 {NAND_PAGE_2K, NAND_ECC_0BIT, 32, &nand_ecc_default},
693
694 {0, 0, 0, NULL},
695 };
696
697 /*
698 * Auto-sensed the page size and ecc type value. driver will try each of page
699 * size and ecc type one by one till flash can be read and wrote accurately.
700 * so the page size and ecc type is match adaptively without switch on the board
701 */
hifmc100_get_config_type_info(struct mtd_info * mtd)702 static struct nand_config_info *hifmc100_get_config_type_info(struct mtd_info *mtd)
703 {
704 struct nand_config_info *best = NULL;
705 struct nand_config_info *info = hifmc_spi_nand_config_table;
706 struct nand_chip *chip = mtd_to_nand(mtd);
707 for (; info->layout; info++) {
708 if (match_page_type_to_size(info->pagetype) != mtd->writesize)
709 continue;
710
711 if (mtd->oobsize < info->oobsize)
712 continue;
713
714 if (!best || (best->ecctype < info->ecctype))
715 best = info;
716 }
717 /* All SPI NAND are small-page,SLC */
718 chip->bits_per_cell = 1;
719 return best;
720 }
721
722 /*****************************************************************************/
hifmc100_set_oob_info(struct mtd_info * mtd,struct nand_config_info * info)723 static void hifmc100_set_oob_info(struct mtd_info *mtd,
724 struct nand_config_info *info)
725 {
726 struct nand_chip *chip = mtd_to_nand(mtd);
727 struct hifmc_host *host = chip->priv;
728
729 /* oobsize_real for ecc0 read and write */
730 oobsize_real = mtd->oobsize;
731
732 if (info->ecctype != NAND_ECC_0BIT)
733 mtd->oobsize = info->oobsize;
734
735 host->oobsize = mtd->oobsize;
736 host->dma_oob = host->dma_buffer + host->pagesize;
737 host->bbm = (u_char *)(host->buffer + host->pagesize
738 + HIFMC_BAD_BLOCK_POS);
739
740 chip->ecc.layout = info->layout;
741
742 /* EB bytes locate in the bottom two of CTRL(30) */
743 host->epm = (u_short *)(host->buffer + host->pagesize
744 + chip->ecc.layout->oobfree[0].offset + EB_NORMAL);
745
746 #ifdef CONFIG_FS_MAY_NOT_YAFFS2
747
748 if (best->ecctype == NAND_ECC_16BIT)
749 if (host->pagesize == _2K)
750 /* EB bits locate in the bottom two of CTRL(4) */
751 host->epm = (u_short *)(host->buffer + host->pagesize
752 + chip->ecc.layout->oobfree[0].offset + EB_2K_16_BIT);
753 else if (host->pagesize == _4K)
754 /* EB bit locate in the bottom two of CTRL(14) */
755 host->epm = (u_short *)(host->buffer + host->pagesize
756 + chip->ecc.layout->oobfree[0].offset + EB_4K_16_BIT);
757
758 #endif
759 }
760
761 /*****************************************************************************/
hifmc100_get_ecc_reg(struct hifmc_host * host,struct nand_config_info * info)762 static unsigned int hifmc100_get_ecc_reg(struct hifmc_host *host,
763 struct nand_config_info *info)
764 {
765 host->ecctype = info->ecctype;
766
767 return fmc_cfg_ecc_type(match_ecc_type_to_reg(info->ecctype));
768 }
769
770 /*****************************************************************************/
hifmc100_get_page_reg(struct hifmc_host * host,struct nand_config_info * info)771 static unsigned int hifmc100_get_page_reg(struct hifmc_host *host,
772 struct nand_config_info *info)
773 {
774 host->pagesize = match_page_type_to_size(info->pagetype);
775
776 return fmc_cfg_page_size(match_page_type_to_reg(info->pagetype));
777 }
778
779 /*****************************************************************************/
hifmc100_get_block_reg(struct hifmc_host * host,struct nand_config_info * info)780 static unsigned int hifmc100_get_block_reg(struct hifmc_host *host,
781 struct nand_config_info *info)
782 {
783 unsigned int block_reg = 0;
784 unsigned int page_per_block;
785 struct mtd_info *mtd = host->mtd;
786
787 host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
788 page_per_block = mtd->erasesize / match_page_type_to_size(info->pagetype);
789 switch (page_per_block) {
790 case _64_PAGES:
791 block_reg = BLOCK_SIZE_64_PAGE;
792 break;
793 case _128_PAGES:
794 block_reg = BLOCK_SIZE_128_PAGE;
795 break;
796 case _256_PAGES:
797 block_reg = BLOCK_SIZE_256_PAGE;
798 break;
799 case _512_PAGES:
800 block_reg = BLOCK_SIZE_512_PAGE;
801 break;
802 default:
803 db_msg("Can't support block %#x and page %#x size\n",
804 mtd->erasesize, mtd->writesize);
805 }
806
807 return fmc_cfg_block_size(block_reg);
808 }
809
810 /*****************************************************************************/
hifmc100_set_fmc_cfg_reg(struct mtd_info * mtd,struct nand_config_info * type_info)811 static void hifmc100_set_fmc_cfg_reg(struct mtd_info *mtd,
812 struct nand_config_info *type_info)
813 {
814 struct nand_chip *chip = mtd_to_nand(mtd);
815 struct hifmc_host *host = chip->priv;
816 unsigned int page_reg, ecc_reg, block_reg, reg_fmc_cfg;
817
818 ecc_reg = hifmc100_get_ecc_reg(host, type_info);
819 page_reg = hifmc100_get_page_reg(host, type_info);
820 block_reg = hifmc100_get_block_reg(host, type_info);
821
822 reg_fmc_cfg = hifmc_read(host, FMC_CFG);
823 reg_fmc_cfg &= ~(PAGE_SIZE_MASK | ECC_TYPE_MASK | BLOCK_SIZE_MASK);
824 reg_fmc_cfg |= ecc_reg | page_reg | block_reg;
825 hifmc_write(host, FMC_CFG, reg_fmc_cfg);
826
827 /* max number of correctible bit errors per ecc step */
828 mtd->ecc_strength = host->ecctype;
829
830 /* Save value of FMC_CFG and FMC_CFG_ECC0 to turn on/off ECC */
831 host->fmc_cfg = reg_fmc_cfg;
832 host->fmc_cfg_ecc0 = (host->fmc_cfg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
833 fmc_pr(BT_DBG, "\t|-Save FMC_CFG[%#x]: %#x and FMC_CFG_ECC0: %#x\n",
834 FMC_CFG, host->fmc_cfg, host->fmc_cfg_ecc0);
835 }
836
837 /*****************************************************************************/
hifmc100_set_config_info(struct mtd_info * mtd)838 static int hifmc100_set_config_info(struct mtd_info *mtd)
839 {
840 struct nand_config_info *type_info = NULL;
841
842 fmc_pr(BT_DBG, "\t*-Start match PageSize and EccType\n");
843
844 type_info = hifmc100_get_config_type_info(mtd);
845 if (!type_info)
846 db_bug(ERR_STR_DRIVER "pagesize: %d and oobsize: %d.\n",
847 mtd->writesize, mtd->oobsize);
848
849 /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
850 hifmc100_set_fmc_cfg_reg(mtd, type_info);
851
852 fmc_pr(BT_DBG, "\t|- PageSize %s EccType %s OOB Size %d\n",
853 nand_page_name(type_info->pagetype),
854 nand_ecc_name(type_info->ecctype), type_info->oobsize);
855
856 hifmc100_set_oob_info(mtd, type_info);
857
858 fmc_pr(BT_DBG, "\t*-End match PageSize and EccType\n");
859
860 return 0;
861 }
862
863 /*****************************************************************************/
hifmc100_chip_init(struct nand_chip * chip)864 static void hifmc100_chip_init(struct nand_chip *chip)
865 {
866 if (!chip->IO_ADDR_R)
867 chip->IO_ADDR_R = (void __iomem *)CONFIG_HIFMC_BUFFER_BASE;
868 chip->IO_ADDR_W = chip->IO_ADDR_R;
869 memset((char *)chip->IO_ADDR_R, 0xff, HIFMC100_BUFFER_LEN);
870
871 chip->read_byte = hifmc100_read_byte;
872 chip->read_word = hifmc100_read_word;
873 chip->write_buf = hifmc100_write_buf;
874 chip->read_buf = hifmc100_read_buf;
875
876 chip->select_chip = hifmc100_select_chip;
877
878 chip->cmdfunc = hifmc100_cmdfunc;
879 chip->dev_ready = hifmc100_dev_ready;
880
881 chip->chip_delay = FMC_CHIP_DELAY;
882
883 chip->options = NAND_BBT_SCANNED | NAND_BROKEN_XD;
884
885 chip->ecc.layout = NULL;
886 chip->ecc.mode = NAND_ECC_NONE;
887 }
888
889 /*****************************************************************************/
host_data_init(struct hifmc_host * host)890 int host_data_init(struct hifmc_host *host)
891 {
892 unsigned long align_mask;
893
894 host->addr_cycle = 0;
895 host->addr_value[0] = 0;
896 host->addr_value[1] = 0;
897 host->cache_addr_value[0] = ~0;
898 host->cache_addr_value[1] = ~0;
899
900 fmc_pr(BT_DBG, "\t|||-Malloc memory for dma buffer\n");
901 host->buforg = kmalloc((HIFMC100_BUFFER_LEN + FMC_DMA_ALIGN),
902 GFP_KERNEL);
903 if (!host->buforg) {
904 db_msg("Error: Can't malloc memory for SPI Nand driver.\n");
905 return -ENOMEM;
906 }
907 memset(host->buforg, 0xff, HIFMC100_BUFFER_LEN + FMC_DMA_ALIGN);
908
909 /* DMA need 32 bytes alignment */
910 align_mask = FMC_DMA_ALIGN - 1;
911 host->dma_buffer = (uintptr_t)(host->buforg + align_mask) & ~align_mask;
912
913 host->buffer = (char *)(uintptr_t)host->dma_buffer;
914 memset(host->buffer, 0xff, HIFMC100_BUFFER_LEN);
915
916 host->send_cmd_pageprog = hifmc100_send_cmd_pageprog;
917 host->send_cmd_status = hifmc100_send_cmd_status;
918 host->send_cmd_readstart = hifmc100_send_cmd_readstart;
919 host->send_cmd_erase = hifmc100_send_cmd_erase;
920 host->send_cmd_readid = hifmc100_send_cmd_readid;
921 host->send_cmd_reset = hifmc100_send_cmd_reset;
922 host->set_system_clock = hifmc_set_fmc_system_clock;
923
924 return 0;
925 }
926 /*****************************************************************************/
hifmc100_host_init(struct hifmc_host * host)927 int hifmc100_host_init(struct hifmc_host *host)
928 {
929 unsigned int reg;
930 unsigned int flash_type;
931 int ret;
932
933 fmc_pr(BT_DBG, "\t||*-Start SPI Nand host init\n");
934 host->iobase = (void __iomem *)CONFIG_HIFMC_BUFFER_BASE;
935 host->regbase = (void __iomem *)CONFIG_HIFMC_REG_BASE;
936
937 reg = hifmc_read(host, FMC_CFG);
938 flash_type = (reg & FLASH_SEL_MASK) >> FLASH_SEL_SHIFT;
939 if (flash_type != FLASH_TYPE_SPI_NAND) {
940 db_msg("Error: Flash type isn't SPI Nand. reg: %#x\n", reg);
941 return -ENODEV;
942 }
943
944 if ((reg & OP_MODE_MASK) == OP_MODE_BOOT) {
945 reg |= fmc_cfg_op_mode(OP_MODE_NORMAL);
946 hifmc_write(host, FMC_CFG, reg);
947 fmc_pr(BT_DBG, "\t|||-Set CFG[%#x]%#x\n", FMC_CFG, reg);
948 }
949
950 host->fmc_cfg = reg;
951 host->fmc_cfg_ecc0 = (reg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
952
953 reg = hifmc_read(host, FMC_GLOBAL_CFG);
954 if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
955 reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
956 hifmc_write(host, FMC_GLOBAL_CFG, reg);
957 }
958
959 ret = host_data_init(host);
960 if (ret)
961 return ret;
962
963 /* ecc0_flag for ecc0 read/write */
964 ecc0_flag = 0;
965
966 reg = timing_cfg_tcsh(CS_HOLD_TIME) |
967 timing_cfg_tcss(CS_SETUP_TIME) |
968 timing_cfg_tshsl(CS_DESELECT_TIME);
969 hifmc_write(host, FMC_SPI_TIMING_CFG, reg);
970 fmc_pr(BT_DBG, "\t|||-Set TIMING[%#x]%#x\n", FMC_SPI_TIMING_CFG, reg);
971
972 reg = ALL_BURST_ENABLE;
973 hifmc_write(host, FMC_DMA_AHB_CTRL, reg);
974 fmc_pr(BT_DBG, "\t|||-Set DMA_AHB[%#x]%#x\n", FMC_DMA_AHB_CTRL, reg);
975
976 fmc_pr(BT_DBG, "\t|||-Register SPI Nand ID table and ecc probe\n");
977 hifmc_spi_nand_ids_register();
978 nand_oob_resize = hifmc100_set_config_info;
979
980 fmc_pr(BT_DBG, "\t||*-End SPI Nand host init\n");
981
982 return 0;
983 }
984
985 /*****************************************************************************/
hifmc100_spi_nand_init(struct hifmc_host * host)986 void hifmc100_spi_nand_init(struct hifmc_host *host)
987 {
988 struct nand_chip *chip = host->chip;
989
990 fmc_pr(BT_DBG, "\t|*-Start hifmc100 SPI Nand init\n");
991
992 /* Set system clock and enable controller */
993 fmc_pr(BT_DBG, "\t||-Set system clock and Enable Controller\n");
994 if (host->set_system_clock)
995 host->set_system_clock(NULL, ENABLE);
996
997 /* Hifmc nand_chip struct init */
998 fmc_pr(BT_DBG, "\t||-Hifmc100 struct nand_chip init\n");
999 chip->priv = host;
1000 hifmc100_chip_init(chip);
1001
1002 fmc_pr(BT_DBG, "\t|*-End hifmc100 SPI Nand init\n");
1003 }
1004