1 /*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "ena_com.h"
34
35 /*****************************************************************************/
36 /*****************************************************************************/
37
38 /* Timeout in micro-sec */
39 #define ADMIN_CMD_TIMEOUT_US (3000000)
40
41 #define ENA_ASYNC_QUEUE_DEPTH 16
42 #define ENA_ADMIN_QUEUE_DEPTH 32
43
44 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
45 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
46 | (ENA_COMMON_SPEC_VERSION_MINOR))
47
48 #define ENA_CTRL_MAJOR 0
49 #define ENA_CTRL_MINOR 0
50 #define ENA_CTRL_SUB_MINOR 1
51
52 #define MIN_ENA_CTRL_VER \
53 (((ENA_CTRL_MAJOR) << \
54 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
55 ((ENA_CTRL_MINOR) << \
56 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
57 (ENA_CTRL_SUB_MINOR))
58
59 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
60 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
61
62 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
63
64 #define ENA_REGS_ADMIN_INTR_MASK 1
65
66 #define ENA_POLL_MS 5
67
68 /*****************************************************************************/
69 /*****************************************************************************/
70 /*****************************************************************************/
71
72 enum ena_cmd_status {
73 ENA_CMD_SUBMITTED,
74 ENA_CMD_COMPLETED,
75 /* Abort - canceled by the driver */
76 ENA_CMD_ABORTED,
77 };
78
79 struct ena_comp_ctx {
80 struct completion wait_event;
81 struct ena_admin_acq_entry *user_cqe;
82 u32 comp_size;
83 enum ena_cmd_status status;
84 /* status from the device */
85 u8 comp_status;
86 u8 cmd_opcode;
87 bool occupied;
88 };
89
90 struct ena_com_stats_ctx {
91 struct ena_admin_aq_get_stats_cmd get_cmd;
92 struct ena_admin_acq_get_stats_resp get_resp;
93 };
94
ena_com_mem_addr_set(struct ena_com_dev * ena_dev,struct ena_common_mem_addr * ena_addr,dma_addr_t addr)95 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
96 struct ena_common_mem_addr *ena_addr,
97 dma_addr_t addr)
98 {
99 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
100 pr_err("dma address has more bits that the device supports\n");
101 return -EINVAL;
102 }
103
104 ena_addr->mem_addr_low = lower_32_bits(addr);
105 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
106
107 return 0;
108 }
109
ena_com_admin_init_sq(struct ena_com_admin_queue * queue)110 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
111 {
112 struct ena_com_admin_sq *sq = &queue->sq;
113 u16 size = ADMIN_SQ_SIZE(queue->q_depth);
114
115 sq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &sq->dma_addr,
116 GFP_KERNEL);
117
118 if (!sq->entries) {
119 pr_err("memory allocation failed");
120 return -ENOMEM;
121 }
122
123 sq->head = 0;
124 sq->tail = 0;
125 sq->phase = 1;
126
127 sq->db_addr = NULL;
128
129 return 0;
130 }
131
ena_com_admin_init_cq(struct ena_com_admin_queue * queue)132 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
133 {
134 struct ena_com_admin_cq *cq = &queue->cq;
135 u16 size = ADMIN_CQ_SIZE(queue->q_depth);
136
137 cq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &cq->dma_addr,
138 GFP_KERNEL);
139
140 if (!cq->entries) {
141 pr_err("memory allocation failed");
142 return -ENOMEM;
143 }
144
145 cq->head = 0;
146 cq->phase = 1;
147
148 return 0;
149 }
150
ena_com_admin_init_aenq(struct ena_com_dev * dev,struct ena_aenq_handlers * aenq_handlers)151 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
152 struct ena_aenq_handlers *aenq_handlers)
153 {
154 struct ena_com_aenq *aenq = &dev->aenq;
155 u32 addr_low, addr_high, aenq_caps;
156 u16 size;
157
158 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
159 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
160 aenq->entries = dma_zalloc_coherent(dev->dmadev, size, &aenq->dma_addr,
161 GFP_KERNEL);
162
163 if (!aenq->entries) {
164 pr_err("memory allocation failed");
165 return -ENOMEM;
166 }
167
168 aenq->head = aenq->q_depth;
169 aenq->phase = 1;
170
171 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
172 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
173
174 writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
175 writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
176
177 aenq_caps = 0;
178 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
179 aenq_caps |= (sizeof(struct ena_admin_aenq_entry)
180 << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
181 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
182 writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
183
184 if (unlikely(!aenq_handlers)) {
185 pr_err("aenq handlers pointer is NULL\n");
186 return -EINVAL;
187 }
188
189 aenq->aenq_handlers = aenq_handlers;
190
191 return 0;
192 }
193
comp_ctxt_release(struct ena_com_admin_queue * queue,struct ena_comp_ctx * comp_ctx)194 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue,
195 struct ena_comp_ctx *comp_ctx)
196 {
197 comp_ctx->occupied = false;
198 atomic_dec(&queue->outstanding_cmds);
199 }
200
get_comp_ctxt(struct ena_com_admin_queue * queue,u16 command_id,bool capture)201 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
202 u16 command_id, bool capture)
203 {
204 if (unlikely(!queue->comp_ctx)) {
205 pr_err("Completion context is NULL\n");
206 return NULL;
207 }
208
209 if (unlikely(command_id >= queue->q_depth)) {
210 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
211 command_id, queue->q_depth);
212 return NULL;
213 }
214
215 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
216 pr_err("Completion context is occupied\n");
217 return NULL;
218 }
219
220 if (capture) {
221 atomic_inc(&queue->outstanding_cmds);
222 queue->comp_ctx[command_id].occupied = true;
223 }
224
225 return &queue->comp_ctx[command_id];
226 }
227
__ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)228 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
229 struct ena_admin_aq_entry *cmd,
230 size_t cmd_size_in_bytes,
231 struct ena_admin_acq_entry *comp,
232 size_t comp_size_in_bytes)
233 {
234 struct ena_comp_ctx *comp_ctx;
235 u16 tail_masked, cmd_id;
236 u16 queue_size_mask;
237 u16 cnt;
238
239 queue_size_mask = admin_queue->q_depth - 1;
240
241 tail_masked = admin_queue->sq.tail & queue_size_mask;
242
243 /* In case of queue FULL */
244 cnt = atomic_read(&admin_queue->outstanding_cmds);
245 if (cnt >= admin_queue->q_depth) {
246 pr_debug("admin queue is full.\n");
247 admin_queue->stats.out_of_space++;
248 return ERR_PTR(-ENOSPC);
249 }
250
251 cmd_id = admin_queue->curr_cmd_id;
252
253 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
254 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
255
256 cmd->aq_common_descriptor.command_id |= cmd_id &
257 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
258
259 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
260 if (unlikely(!comp_ctx))
261 return ERR_PTR(-EINVAL);
262
263 comp_ctx->status = ENA_CMD_SUBMITTED;
264 comp_ctx->comp_size = (u32)comp_size_in_bytes;
265 comp_ctx->user_cqe = comp;
266 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
267
268 reinit_completion(&comp_ctx->wait_event);
269
270 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
271
272 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
273 queue_size_mask;
274
275 admin_queue->sq.tail++;
276 admin_queue->stats.submitted_cmd++;
277
278 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
279 admin_queue->sq.phase = !admin_queue->sq.phase;
280
281 writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
282
283 return comp_ctx;
284 }
285
ena_com_init_comp_ctxt(struct ena_com_admin_queue * queue)286 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
287 {
288 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
289 struct ena_comp_ctx *comp_ctx;
290 u16 i;
291
292 queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL);
293 if (unlikely(!queue->comp_ctx)) {
294 pr_err("memory allocation failed");
295 return -ENOMEM;
296 }
297
298 for (i = 0; i < queue->q_depth; i++) {
299 comp_ctx = get_comp_ctxt(queue, i, false);
300 if (comp_ctx)
301 init_completion(&comp_ctx->wait_event);
302 }
303
304 return 0;
305 }
306
ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)307 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
308 struct ena_admin_aq_entry *cmd,
309 size_t cmd_size_in_bytes,
310 struct ena_admin_acq_entry *comp,
311 size_t comp_size_in_bytes)
312 {
313 unsigned long flags;
314 struct ena_comp_ctx *comp_ctx;
315
316 spin_lock_irqsave(&admin_queue->q_lock, flags);
317 if (unlikely(!admin_queue->running_state)) {
318 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
319 return ERR_PTR(-ENODEV);
320 }
321 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
322 cmd_size_in_bytes,
323 comp,
324 comp_size_in_bytes);
325 if (IS_ERR(comp_ctx))
326 admin_queue->running_state = false;
327 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
328
329 return comp_ctx;
330 }
331
ena_com_init_io_sq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_sq * io_sq)332 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
333 struct ena_com_create_io_ctx *ctx,
334 struct ena_com_io_sq *io_sq)
335 {
336 size_t size;
337 int dev_node = 0;
338
339 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
340
341 io_sq->dma_addr_bits = ena_dev->dma_addr_bits;
342 io_sq->desc_entry_size =
343 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
344 sizeof(struct ena_eth_io_tx_desc) :
345 sizeof(struct ena_eth_io_rx_desc);
346
347 size = io_sq->desc_entry_size * io_sq->q_depth;
348
349 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
350 dev_node = dev_to_node(ena_dev->dmadev);
351 set_dev_node(ena_dev->dmadev, ctx->numa_node);
352 io_sq->desc_addr.virt_addr =
353 dma_zalloc_coherent(ena_dev->dmadev, size,
354 &io_sq->desc_addr.phys_addr,
355 GFP_KERNEL);
356 set_dev_node(ena_dev->dmadev, dev_node);
357 if (!io_sq->desc_addr.virt_addr) {
358 io_sq->desc_addr.virt_addr =
359 dma_zalloc_coherent(ena_dev->dmadev, size,
360 &io_sq->desc_addr.phys_addr,
361 GFP_KERNEL);
362 }
363 } else {
364 dev_node = dev_to_node(ena_dev->dmadev);
365 set_dev_node(ena_dev->dmadev, ctx->numa_node);
366 io_sq->desc_addr.virt_addr =
367 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
368 set_dev_node(ena_dev->dmadev, dev_node);
369 if (!io_sq->desc_addr.virt_addr) {
370 io_sq->desc_addr.virt_addr =
371 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
372 }
373 }
374
375 if (!io_sq->desc_addr.virt_addr) {
376 pr_err("memory allocation failed");
377 return -ENOMEM;
378 }
379
380 io_sq->tail = 0;
381 io_sq->next_to_comp = 0;
382 io_sq->phase = 1;
383
384 return 0;
385 }
386
ena_com_init_io_cq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_cq * io_cq)387 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
388 struct ena_com_create_io_ctx *ctx,
389 struct ena_com_io_cq *io_cq)
390 {
391 size_t size;
392 int prev_node = 0;
393
394 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
395
396 /* Use the basic completion descriptor for Rx */
397 io_cq->cdesc_entry_size_in_bytes =
398 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
399 sizeof(struct ena_eth_io_tx_cdesc) :
400 sizeof(struct ena_eth_io_rx_cdesc_base);
401
402 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
403
404 prev_node = dev_to_node(ena_dev->dmadev);
405 set_dev_node(ena_dev->dmadev, ctx->numa_node);
406 io_cq->cdesc_addr.virt_addr =
407 dma_zalloc_coherent(ena_dev->dmadev, size,
408 &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
409 set_dev_node(ena_dev->dmadev, prev_node);
410 if (!io_cq->cdesc_addr.virt_addr) {
411 io_cq->cdesc_addr.virt_addr =
412 dma_zalloc_coherent(ena_dev->dmadev, size,
413 &io_cq->cdesc_addr.phys_addr,
414 GFP_KERNEL);
415 }
416
417 if (!io_cq->cdesc_addr.virt_addr) {
418 pr_err("memory allocation failed");
419 return -ENOMEM;
420 }
421
422 io_cq->phase = 1;
423 io_cq->head = 0;
424
425 return 0;
426 }
427
ena_com_handle_single_admin_completion(struct ena_com_admin_queue * admin_queue,struct ena_admin_acq_entry * cqe)428 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
429 struct ena_admin_acq_entry *cqe)
430 {
431 struct ena_comp_ctx *comp_ctx;
432 u16 cmd_id;
433
434 cmd_id = cqe->acq_common_descriptor.command &
435 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
436
437 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
438 if (unlikely(!comp_ctx)) {
439 pr_err("comp_ctx is NULL. Changing the admin queue running state\n");
440 admin_queue->running_state = false;
441 return;
442 }
443
444 comp_ctx->status = ENA_CMD_COMPLETED;
445 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
446
447 if (comp_ctx->user_cqe)
448 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
449
450 if (!admin_queue->polling)
451 complete(&comp_ctx->wait_event);
452 }
453
ena_com_handle_admin_completion(struct ena_com_admin_queue * admin_queue)454 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
455 {
456 struct ena_admin_acq_entry *cqe = NULL;
457 u16 comp_num = 0;
458 u16 head_masked;
459 u8 phase;
460
461 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
462 phase = admin_queue->cq.phase;
463
464 cqe = &admin_queue->cq.entries[head_masked];
465
466 /* Go over all the completions */
467 while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
468 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
469 /* Do not read the rest of the completion entry before the
470 * phase bit was validated
471 */
472 dma_rmb();
473 ena_com_handle_single_admin_completion(admin_queue, cqe);
474
475 head_masked++;
476 comp_num++;
477 if (unlikely(head_masked == admin_queue->q_depth)) {
478 head_masked = 0;
479 phase = !phase;
480 }
481
482 cqe = &admin_queue->cq.entries[head_masked];
483 }
484
485 admin_queue->cq.head += comp_num;
486 admin_queue->cq.phase = phase;
487 admin_queue->sq.head += comp_num;
488 admin_queue->stats.completed_cmd += comp_num;
489 }
490
ena_com_comp_status_to_errno(u8 comp_status)491 static int ena_com_comp_status_to_errno(u8 comp_status)
492 {
493 if (unlikely(comp_status != 0))
494 pr_err("admin command failed[%u]\n", comp_status);
495
496 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))
497 return -EINVAL;
498
499 switch (comp_status) {
500 case ENA_ADMIN_SUCCESS:
501 return 0;
502 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
503 return -ENOMEM;
504 case ENA_ADMIN_UNSUPPORTED_OPCODE:
505 return -EOPNOTSUPP;
506 case ENA_ADMIN_BAD_OPCODE:
507 case ENA_ADMIN_MALFORMED_REQUEST:
508 case ENA_ADMIN_ILLEGAL_PARAMETER:
509 case ENA_ADMIN_UNKNOWN_ERROR:
510 return -EINVAL;
511 }
512
513 return 0;
514 }
515
ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)516 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
517 struct ena_com_admin_queue *admin_queue)
518 {
519 unsigned long flags, timeout;
520 int ret;
521
522 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
523
524 while (1) {
525 spin_lock_irqsave(&admin_queue->q_lock, flags);
526 ena_com_handle_admin_completion(admin_queue);
527 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
528
529 if (comp_ctx->status != ENA_CMD_SUBMITTED)
530 break;
531
532 if (time_is_before_jiffies(timeout)) {
533 pr_err("Wait for completion (polling) timeout\n");
534 /* ENA didn't have any completion */
535 spin_lock_irqsave(&admin_queue->q_lock, flags);
536 admin_queue->stats.no_completion++;
537 admin_queue->running_state = false;
538 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
539
540 ret = -ETIME;
541 goto err;
542 }
543
544 msleep(ENA_POLL_MS);
545 }
546
547 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
548 pr_err("Command was aborted\n");
549 spin_lock_irqsave(&admin_queue->q_lock, flags);
550 admin_queue->stats.aborted_cmd++;
551 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
552 ret = -ENODEV;
553 goto err;
554 }
555
556 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n",
557 comp_ctx->status);
558
559 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
560 err:
561 comp_ctxt_release(admin_queue, comp_ctx);
562 return ret;
563 }
564
ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)565 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
566 struct ena_com_admin_queue *admin_queue)
567 {
568 unsigned long flags;
569 int ret;
570
571 wait_for_completion_timeout(&comp_ctx->wait_event,
572 usecs_to_jiffies(
573 admin_queue->completion_timeout));
574
575 /* In case the command wasn't completed find out the root cause.
576 * There might be 2 kinds of errors
577 * 1) No completion (timeout reached)
578 * 2) There is completion but the device didn't get any msi-x interrupt.
579 */
580 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
581 spin_lock_irqsave(&admin_queue->q_lock, flags);
582 ena_com_handle_admin_completion(admin_queue);
583 admin_queue->stats.no_completion++;
584 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
585
586 if (comp_ctx->status == ENA_CMD_COMPLETED)
587 pr_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n",
588 comp_ctx->cmd_opcode);
589 else
590 pr_err("The ena device doesn't send any completion for the admin cmd %d status %d\n",
591 comp_ctx->cmd_opcode, comp_ctx->status);
592
593 admin_queue->running_state = false;
594 ret = -ETIME;
595 goto err;
596 }
597
598 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
599 err:
600 comp_ctxt_release(admin_queue, comp_ctx);
601 return ret;
602 }
603
604 /* This method read the hardware device register through posting writes
605 * and waiting for response
606 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
607 */
ena_com_reg_bar_read32(struct ena_com_dev * ena_dev,u16 offset)608 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
609 {
610 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
611 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
612 mmio_read->read_resp;
613 u32 mmio_read_reg, ret, i;
614 unsigned long flags;
615 u32 timeout = mmio_read->reg_read_to;
616
617 might_sleep();
618
619 if (timeout == 0)
620 timeout = ENA_REG_READ_TIMEOUT;
621
622 /* If readless is disabled, perform regular read */
623 if (!mmio_read->readless_supported)
624 return readl(ena_dev->reg_bar + offset);
625
626 spin_lock_irqsave(&mmio_read->lock, flags);
627 mmio_read->seq_num++;
628
629 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
630 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
631 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
632 mmio_read_reg |= mmio_read->seq_num &
633 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
634
635 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
636
637 for (i = 0; i < timeout; i++) {
638 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
639 break;
640
641 udelay(1);
642 }
643
644 if (unlikely(i == timeout)) {
645 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
646 mmio_read->seq_num, offset, read_resp->req_id,
647 read_resp->reg_off);
648 ret = ENA_MMIO_READ_TIMEOUT;
649 goto err;
650 }
651
652 if (read_resp->reg_off != offset) {
653 pr_err("Read failure: wrong offset provided");
654 ret = ENA_MMIO_READ_TIMEOUT;
655 } else {
656 ret = read_resp->reg_val;
657 }
658 err:
659 spin_unlock_irqrestore(&mmio_read->lock, flags);
660
661 return ret;
662 }
663
664 /* There are two types to wait for completion.
665 * Polling mode - wait until the completion is available.
666 * Async mode - wait on wait queue until the completion is ready
667 * (or the timeout expired).
668 * It is expected that the IRQ called ena_com_handle_admin_completion
669 * to mark the completions.
670 */
ena_com_wait_and_process_admin_cq(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)671 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
672 struct ena_com_admin_queue *admin_queue)
673 {
674 if (admin_queue->polling)
675 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
676 admin_queue);
677
678 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
679 admin_queue);
680 }
681
ena_com_destroy_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq)682 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
683 struct ena_com_io_sq *io_sq)
684 {
685 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
686 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
687 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
688 u8 direction;
689 int ret;
690
691 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
692
693 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
694 direction = ENA_ADMIN_SQ_DIRECTION_TX;
695 else
696 direction = ENA_ADMIN_SQ_DIRECTION_RX;
697
698 destroy_cmd.sq.sq_identity |= (direction <<
699 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
700 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
701
702 destroy_cmd.sq.sq_idx = io_sq->idx;
703 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
704
705 ret = ena_com_execute_admin_command(admin_queue,
706 (struct ena_admin_aq_entry *)&destroy_cmd,
707 sizeof(destroy_cmd),
708 (struct ena_admin_acq_entry *)&destroy_resp,
709 sizeof(destroy_resp));
710
711 if (unlikely(ret && (ret != -ENODEV)))
712 pr_err("failed to destroy io sq error: %d\n", ret);
713
714 return ret;
715 }
716
ena_com_io_queue_free(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,struct ena_com_io_cq * io_cq)717 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
718 struct ena_com_io_sq *io_sq,
719 struct ena_com_io_cq *io_cq)
720 {
721 size_t size;
722
723 if (io_cq->cdesc_addr.virt_addr) {
724 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
725
726 dma_free_coherent(ena_dev->dmadev, size,
727 io_cq->cdesc_addr.virt_addr,
728 io_cq->cdesc_addr.phys_addr);
729
730 io_cq->cdesc_addr.virt_addr = NULL;
731 }
732
733 if (io_sq->desc_addr.virt_addr) {
734 size = io_sq->desc_entry_size * io_sq->q_depth;
735
736 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
737 dma_free_coherent(ena_dev->dmadev, size,
738 io_sq->desc_addr.virt_addr,
739 io_sq->desc_addr.phys_addr);
740 else
741 devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr);
742
743 io_sq->desc_addr.virt_addr = NULL;
744 }
745 }
746
wait_for_reset_state(struct ena_com_dev * ena_dev,u32 timeout,u16 exp_state)747 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
748 u16 exp_state)
749 {
750 u32 val, i;
751
752 /* Convert timeout from resolution of 100ms to ENA_POLL_MS */
753 timeout = (timeout * 100) / ENA_POLL_MS;
754
755 for (i = 0; i < timeout; i++) {
756 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
757
758 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
759 pr_err("Reg read timeout occurred\n");
760 return -ETIME;
761 }
762
763 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
764 exp_state)
765 return 0;
766
767 msleep(ENA_POLL_MS);
768 }
769
770 return -ETIME;
771 }
772
ena_com_check_supported_feature_id(struct ena_com_dev * ena_dev,enum ena_admin_aq_feature_id feature_id)773 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
774 enum ena_admin_aq_feature_id feature_id)
775 {
776 u32 feature_mask = 1 << feature_id;
777
778 /* Device attributes is always supported */
779 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
780 !(ena_dev->supported_features & feature_mask))
781 return false;
782
783 return true;
784 }
785
ena_com_get_feature_ex(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,dma_addr_t control_buf_dma_addr,u32 control_buff_size)786 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
787 struct ena_admin_get_feat_resp *get_resp,
788 enum ena_admin_aq_feature_id feature_id,
789 dma_addr_t control_buf_dma_addr,
790 u32 control_buff_size)
791 {
792 struct ena_com_admin_queue *admin_queue;
793 struct ena_admin_get_feat_cmd get_cmd;
794 int ret;
795
796 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
797 pr_debug("Feature %d isn't supported\n", feature_id);
798 return -EOPNOTSUPP;
799 }
800
801 memset(&get_cmd, 0x0, sizeof(get_cmd));
802 admin_queue = &ena_dev->admin_queue;
803
804 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
805
806 if (control_buff_size)
807 get_cmd.aq_common_descriptor.flags =
808 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
809 else
810 get_cmd.aq_common_descriptor.flags = 0;
811
812 ret = ena_com_mem_addr_set(ena_dev,
813 &get_cmd.control_buffer.address,
814 control_buf_dma_addr);
815 if (unlikely(ret)) {
816 pr_err("memory address set failed\n");
817 return ret;
818 }
819
820 get_cmd.control_buffer.length = control_buff_size;
821
822 get_cmd.feat_common.feature_id = feature_id;
823
824 ret = ena_com_execute_admin_command(admin_queue,
825 (struct ena_admin_aq_entry *)
826 &get_cmd,
827 sizeof(get_cmd),
828 (struct ena_admin_acq_entry *)
829 get_resp,
830 sizeof(*get_resp));
831
832 if (unlikely(ret))
833 pr_err("Failed to submit get_feature command %d error: %d\n",
834 feature_id, ret);
835
836 return ret;
837 }
838
ena_com_get_feature(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id)839 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
840 struct ena_admin_get_feat_resp *get_resp,
841 enum ena_admin_aq_feature_id feature_id)
842 {
843 return ena_com_get_feature_ex(ena_dev,
844 get_resp,
845 feature_id,
846 0,
847 0);
848 }
849
ena_com_hash_key_fill_default_key(struct ena_com_dev * ena_dev)850 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
851 {
852 struct ena_admin_feature_rss_flow_hash_control *hash_key =
853 (ena_dev->rss).hash_key;
854
855 netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key));
856 /* The key is stored in the device in u32 array
857 * as well as the API requires the key to be passed in this
858 * format. Thus the size of our array should be divided by 4
859 */
860 hash_key->keys_num = sizeof(hash_key->key) / sizeof(u32);
861 }
862
ena_com_get_current_hash_function(struct ena_com_dev * ena_dev)863 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
864 {
865 return ena_dev->rss.hash_func;
866 }
867
ena_com_hash_key_allocate(struct ena_com_dev * ena_dev)868 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
869 {
870 struct ena_rss *rss = &ena_dev->rss;
871
872 rss->hash_key =
873 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
874 &rss->hash_key_dma_addr, GFP_KERNEL);
875
876 if (unlikely(!rss->hash_key))
877 return -ENOMEM;
878
879 return 0;
880 }
881
ena_com_hash_key_destroy(struct ena_com_dev * ena_dev)882 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
883 {
884 struct ena_rss *rss = &ena_dev->rss;
885
886 if (rss->hash_key)
887 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
888 rss->hash_key, rss->hash_key_dma_addr);
889 rss->hash_key = NULL;
890 }
891
ena_com_hash_ctrl_init(struct ena_com_dev * ena_dev)892 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
893 {
894 struct ena_rss *rss = &ena_dev->rss;
895
896 rss->hash_ctrl =
897 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
898 &rss->hash_ctrl_dma_addr, GFP_KERNEL);
899
900 if (unlikely(!rss->hash_ctrl))
901 return -ENOMEM;
902
903 return 0;
904 }
905
ena_com_hash_ctrl_destroy(struct ena_com_dev * ena_dev)906 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
907 {
908 struct ena_rss *rss = &ena_dev->rss;
909
910 if (rss->hash_ctrl)
911 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
912 rss->hash_ctrl, rss->hash_ctrl_dma_addr);
913 rss->hash_ctrl = NULL;
914 }
915
ena_com_indirect_table_allocate(struct ena_com_dev * ena_dev,u16 log_size)916 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
917 u16 log_size)
918 {
919 struct ena_rss *rss = &ena_dev->rss;
920 struct ena_admin_get_feat_resp get_resp;
921 size_t tbl_size;
922 int ret;
923
924 ret = ena_com_get_feature(ena_dev, &get_resp,
925 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
926 if (unlikely(ret))
927 return ret;
928
929 if ((get_resp.u.ind_table.min_size > log_size) ||
930 (get_resp.u.ind_table.max_size < log_size)) {
931 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
932 1 << log_size, 1 << get_resp.u.ind_table.min_size,
933 1 << get_resp.u.ind_table.max_size);
934 return -EINVAL;
935 }
936
937 tbl_size = (1ULL << log_size) *
938 sizeof(struct ena_admin_rss_ind_table_entry);
939
940 rss->rss_ind_tbl =
941 dma_zalloc_coherent(ena_dev->dmadev, tbl_size,
942 &rss->rss_ind_tbl_dma_addr, GFP_KERNEL);
943 if (unlikely(!rss->rss_ind_tbl))
944 goto mem_err1;
945
946 tbl_size = (1ULL << log_size) * sizeof(u16);
947 rss->host_rss_ind_tbl =
948 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
949 if (unlikely(!rss->host_rss_ind_tbl))
950 goto mem_err2;
951
952 rss->tbl_log_size = log_size;
953
954 return 0;
955
956 mem_err2:
957 tbl_size = (1ULL << log_size) *
958 sizeof(struct ena_admin_rss_ind_table_entry);
959
960 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
961 rss->rss_ind_tbl_dma_addr);
962 rss->rss_ind_tbl = NULL;
963 mem_err1:
964 rss->tbl_log_size = 0;
965 return -ENOMEM;
966 }
967
ena_com_indirect_table_destroy(struct ena_com_dev * ena_dev)968 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
969 {
970 struct ena_rss *rss = &ena_dev->rss;
971 size_t tbl_size = (1ULL << rss->tbl_log_size) *
972 sizeof(struct ena_admin_rss_ind_table_entry);
973
974 if (rss->rss_ind_tbl)
975 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
976 rss->rss_ind_tbl_dma_addr);
977 rss->rss_ind_tbl = NULL;
978
979 if (rss->host_rss_ind_tbl)
980 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
981 rss->host_rss_ind_tbl = NULL;
982 }
983
ena_com_create_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,u16 cq_idx)984 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
985 struct ena_com_io_sq *io_sq, u16 cq_idx)
986 {
987 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
988 struct ena_admin_aq_create_sq_cmd create_cmd;
989 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
990 u8 direction;
991 int ret;
992
993 memset(&create_cmd, 0x0, sizeof(create_cmd));
994
995 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
996
997 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
998 direction = ENA_ADMIN_SQ_DIRECTION_TX;
999 else
1000 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1001
1002 create_cmd.sq_identity |= (direction <<
1003 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1004 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1005
1006 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1007 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1008
1009 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1010 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1011 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1012
1013 create_cmd.sq_caps_3 |=
1014 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1015
1016 create_cmd.cq_idx = cq_idx;
1017 create_cmd.sq_depth = io_sq->q_depth;
1018
1019 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1020 ret = ena_com_mem_addr_set(ena_dev,
1021 &create_cmd.sq_ba,
1022 io_sq->desc_addr.phys_addr);
1023 if (unlikely(ret)) {
1024 pr_err("memory address set failed\n");
1025 return ret;
1026 }
1027 }
1028
1029 ret = ena_com_execute_admin_command(admin_queue,
1030 (struct ena_admin_aq_entry *)&create_cmd,
1031 sizeof(create_cmd),
1032 (struct ena_admin_acq_entry *)&cmd_completion,
1033 sizeof(cmd_completion));
1034 if (unlikely(ret)) {
1035 pr_err("Failed to create IO SQ. error: %d\n", ret);
1036 return ret;
1037 }
1038
1039 io_sq->idx = cmd_completion.sq_idx;
1040
1041 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1042 (uintptr_t)cmd_completion.sq_doorbell_offset);
1043
1044 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1045 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1046 + cmd_completion.llq_headers_offset);
1047
1048 io_sq->desc_addr.pbuf_dev_addr =
1049 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1050 cmd_completion.llq_descriptors_offset);
1051 }
1052
1053 pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1054
1055 return ret;
1056 }
1057
ena_com_ind_tbl_convert_to_device(struct ena_com_dev * ena_dev)1058 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1059 {
1060 struct ena_rss *rss = &ena_dev->rss;
1061 struct ena_com_io_sq *io_sq;
1062 u16 qid;
1063 int i;
1064
1065 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1066 qid = rss->host_rss_ind_tbl[i];
1067 if (qid >= ENA_TOTAL_NUM_QUEUES)
1068 return -EINVAL;
1069
1070 io_sq = &ena_dev->io_sq_queues[qid];
1071
1072 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1073 return -EINVAL;
1074
1075 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1076 }
1077
1078 return 0;
1079 }
1080
ena_com_ind_tbl_convert_from_device(struct ena_com_dev * ena_dev)1081 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
1082 {
1083 u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
1084 struct ena_rss *rss = &ena_dev->rss;
1085 u8 idx;
1086 u16 i;
1087
1088 for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
1089 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
1090
1091 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1092 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
1093 return -EINVAL;
1094 idx = (u8)rss->rss_ind_tbl[i].cq_idx;
1095
1096 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
1097 return -EINVAL;
1098
1099 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx];
1100 }
1101
1102 return 0;
1103 }
1104
ena_com_init_interrupt_moderation_table(struct ena_com_dev * ena_dev)1105 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
1106 {
1107 size_t size;
1108
1109 size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS;
1110
1111 ena_dev->intr_moder_tbl =
1112 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
1113 if (!ena_dev->intr_moder_tbl)
1114 return -ENOMEM;
1115
1116 ena_com_config_default_interrupt_moderation_table(ena_dev);
1117
1118 return 0;
1119 }
1120
ena_com_update_intr_delay_resolution(struct ena_com_dev * ena_dev,u16 intr_delay_resolution)1121 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1122 u16 intr_delay_resolution)
1123 {
1124 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1125 unsigned int i;
1126
1127 if (!intr_delay_resolution) {
1128 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1129 intr_delay_resolution = 1;
1130 }
1131 ena_dev->intr_delay_resolution = intr_delay_resolution;
1132
1133 /* update Rx */
1134 for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++)
1135 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution;
1136
1137 /* update Tx */
1138 ena_dev->intr_moder_tx_interval /= intr_delay_resolution;
1139 }
1140
1141 /*****************************************************************************/
1142 /******************************* API ******************************/
1143 /*****************************************************************************/
1144
ena_com_execute_admin_command(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size,struct ena_admin_acq_entry * comp,size_t comp_size)1145 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1146 struct ena_admin_aq_entry *cmd,
1147 size_t cmd_size,
1148 struct ena_admin_acq_entry *comp,
1149 size_t comp_size)
1150 {
1151 struct ena_comp_ctx *comp_ctx;
1152 int ret;
1153
1154 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1155 comp, comp_size);
1156 if (IS_ERR(comp_ctx)) {
1157 if (comp_ctx == ERR_PTR(-ENODEV))
1158 pr_debug("Failed to submit command [%ld]\n",
1159 PTR_ERR(comp_ctx));
1160 else
1161 pr_err("Failed to submit command [%ld]\n",
1162 PTR_ERR(comp_ctx));
1163
1164 return PTR_ERR(comp_ctx);
1165 }
1166
1167 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1168 if (unlikely(ret)) {
1169 if (admin_queue->running_state)
1170 pr_err("Failed to process command. ret = %d\n", ret);
1171 else
1172 pr_debug("Failed to process command. ret = %d\n", ret);
1173 }
1174 return ret;
1175 }
1176
ena_com_create_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1177 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1178 struct ena_com_io_cq *io_cq)
1179 {
1180 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1181 struct ena_admin_aq_create_cq_cmd create_cmd;
1182 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1183 int ret;
1184
1185 memset(&create_cmd, 0x0, sizeof(create_cmd));
1186
1187 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1188
1189 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1190 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1191 create_cmd.cq_caps_1 |=
1192 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1193
1194 create_cmd.msix_vector = io_cq->msix_vector;
1195 create_cmd.cq_depth = io_cq->q_depth;
1196
1197 ret = ena_com_mem_addr_set(ena_dev,
1198 &create_cmd.cq_ba,
1199 io_cq->cdesc_addr.phys_addr);
1200 if (unlikely(ret)) {
1201 pr_err("memory address set failed\n");
1202 return ret;
1203 }
1204
1205 ret = ena_com_execute_admin_command(admin_queue,
1206 (struct ena_admin_aq_entry *)&create_cmd,
1207 sizeof(create_cmd),
1208 (struct ena_admin_acq_entry *)&cmd_completion,
1209 sizeof(cmd_completion));
1210 if (unlikely(ret)) {
1211 pr_err("Failed to create IO CQ. error: %d\n", ret);
1212 return ret;
1213 }
1214
1215 io_cq->idx = cmd_completion.cq_idx;
1216
1217 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1218 cmd_completion.cq_interrupt_unmask_register_offset);
1219
1220 if (cmd_completion.cq_head_db_register_offset)
1221 io_cq->cq_head_db_reg =
1222 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1223 cmd_completion.cq_head_db_register_offset);
1224
1225 if (cmd_completion.numa_node_register_offset)
1226 io_cq->numa_node_cfg_reg =
1227 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1228 cmd_completion.numa_node_register_offset);
1229
1230 pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1231
1232 return ret;
1233 }
1234
ena_com_get_io_handlers(struct ena_com_dev * ena_dev,u16 qid,struct ena_com_io_sq ** io_sq,struct ena_com_io_cq ** io_cq)1235 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1236 struct ena_com_io_sq **io_sq,
1237 struct ena_com_io_cq **io_cq)
1238 {
1239 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1240 pr_err("Invalid queue number %d but the max is %d\n", qid,
1241 ENA_TOTAL_NUM_QUEUES);
1242 return -EINVAL;
1243 }
1244
1245 *io_sq = &ena_dev->io_sq_queues[qid];
1246 *io_cq = &ena_dev->io_cq_queues[qid];
1247
1248 return 0;
1249 }
1250
ena_com_abort_admin_commands(struct ena_com_dev * ena_dev)1251 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1252 {
1253 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1254 struct ena_comp_ctx *comp_ctx;
1255 u16 i;
1256
1257 if (!admin_queue->comp_ctx)
1258 return;
1259
1260 for (i = 0; i < admin_queue->q_depth; i++) {
1261 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1262 if (unlikely(!comp_ctx))
1263 break;
1264
1265 comp_ctx->status = ENA_CMD_ABORTED;
1266
1267 complete(&comp_ctx->wait_event);
1268 }
1269 }
1270
ena_com_wait_for_abort_completion(struct ena_com_dev * ena_dev)1271 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1272 {
1273 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1274 unsigned long flags;
1275
1276 spin_lock_irqsave(&admin_queue->q_lock, flags);
1277 while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1278 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1279 msleep(ENA_POLL_MS);
1280 spin_lock_irqsave(&admin_queue->q_lock, flags);
1281 }
1282 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1283 }
1284
ena_com_destroy_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1285 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1286 struct ena_com_io_cq *io_cq)
1287 {
1288 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1289 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1290 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1291 int ret;
1292
1293 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1294
1295 destroy_cmd.cq_idx = io_cq->idx;
1296 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1297
1298 ret = ena_com_execute_admin_command(admin_queue,
1299 (struct ena_admin_aq_entry *)&destroy_cmd,
1300 sizeof(destroy_cmd),
1301 (struct ena_admin_acq_entry *)&destroy_resp,
1302 sizeof(destroy_resp));
1303
1304 if (unlikely(ret && (ret != -ENODEV)))
1305 pr_err("Failed to destroy IO CQ. error: %d\n", ret);
1306
1307 return ret;
1308 }
1309
ena_com_get_admin_running_state(struct ena_com_dev * ena_dev)1310 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1311 {
1312 return ena_dev->admin_queue.running_state;
1313 }
1314
ena_com_set_admin_running_state(struct ena_com_dev * ena_dev,bool state)1315 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1316 {
1317 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1318 unsigned long flags;
1319
1320 spin_lock_irqsave(&admin_queue->q_lock, flags);
1321 ena_dev->admin_queue.running_state = state;
1322 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1323 }
1324
ena_com_admin_aenq_enable(struct ena_com_dev * ena_dev)1325 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1326 {
1327 u16 depth = ena_dev->aenq.q_depth;
1328
1329 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1330
1331 /* Init head_db to mark that all entries in the queue
1332 * are initially available
1333 */
1334 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1335 }
1336
ena_com_set_aenq_config(struct ena_com_dev * ena_dev,u32 groups_flag)1337 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1338 {
1339 struct ena_com_admin_queue *admin_queue;
1340 struct ena_admin_set_feat_cmd cmd;
1341 struct ena_admin_set_feat_resp resp;
1342 struct ena_admin_get_feat_resp get_resp;
1343 int ret;
1344
1345 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);
1346 if (ret) {
1347 pr_info("Can't get aenq configuration\n");
1348 return ret;
1349 }
1350
1351 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1352 pr_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
1353 get_resp.u.aenq.supported_groups, groups_flag);
1354 return -EOPNOTSUPP;
1355 }
1356
1357 memset(&cmd, 0x0, sizeof(cmd));
1358 admin_queue = &ena_dev->admin_queue;
1359
1360 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1361 cmd.aq_common_descriptor.flags = 0;
1362 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1363 cmd.u.aenq.enabled_groups = groups_flag;
1364
1365 ret = ena_com_execute_admin_command(admin_queue,
1366 (struct ena_admin_aq_entry *)&cmd,
1367 sizeof(cmd),
1368 (struct ena_admin_acq_entry *)&resp,
1369 sizeof(resp));
1370
1371 if (unlikely(ret))
1372 pr_err("Failed to config AENQ ret: %d\n", ret);
1373
1374 return ret;
1375 }
1376
ena_com_get_dma_width(struct ena_com_dev * ena_dev)1377 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1378 {
1379 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1380 int width;
1381
1382 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1383 pr_err("Reg read timeout occurred\n");
1384 return -ETIME;
1385 }
1386
1387 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1388 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1389
1390 pr_debug("ENA dma width: %d\n", width);
1391
1392 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1393 pr_err("DMA width illegal value: %d\n", width);
1394 return -EINVAL;
1395 }
1396
1397 ena_dev->dma_addr_bits = width;
1398
1399 return width;
1400 }
1401
ena_com_validate_version(struct ena_com_dev * ena_dev)1402 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1403 {
1404 u32 ver;
1405 u32 ctrl_ver;
1406 u32 ctrl_ver_masked;
1407
1408 /* Make sure the ENA version and the controller version are at least
1409 * as the driver expects
1410 */
1411 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1412 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1413 ENA_REGS_CONTROLLER_VERSION_OFF);
1414
1415 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1416 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1417 pr_err("Reg read timeout occurred\n");
1418 return -ETIME;
1419 }
1420
1421 pr_info("ena device version: %d.%d\n",
1422 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1423 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1424 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1425
1426 if (ver < MIN_ENA_VER) {
1427 pr_err("ENA version is lower than the minimal version the driver supports\n");
1428 return -1;
1429 }
1430
1431 pr_info("ena controller version: %d.%d.%d implementation version %d\n",
1432 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1433 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1434 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1435 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1436 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1437 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1438 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1439
1440 ctrl_ver_masked =
1441 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1442 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1443 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1444
1445 /* Validate the ctrl version without the implementation ID */
1446 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1447 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1448 return -1;
1449 }
1450
1451 return 0;
1452 }
1453
ena_com_admin_destroy(struct ena_com_dev * ena_dev)1454 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1455 {
1456 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1457 struct ena_com_admin_cq *cq = &admin_queue->cq;
1458 struct ena_com_admin_sq *sq = &admin_queue->sq;
1459 struct ena_com_aenq *aenq = &ena_dev->aenq;
1460 u16 size;
1461
1462 if (admin_queue->comp_ctx)
1463 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1464 admin_queue->comp_ctx = NULL;
1465 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1466 if (sq->entries)
1467 dma_free_coherent(ena_dev->dmadev, size, sq->entries,
1468 sq->dma_addr);
1469 sq->entries = NULL;
1470
1471 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1472 if (cq->entries)
1473 dma_free_coherent(ena_dev->dmadev, size, cq->entries,
1474 cq->dma_addr);
1475 cq->entries = NULL;
1476
1477 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1478 if (ena_dev->aenq.entries)
1479 dma_free_coherent(ena_dev->dmadev, size, aenq->entries,
1480 aenq->dma_addr);
1481 aenq->entries = NULL;
1482 }
1483
ena_com_set_admin_polling_mode(struct ena_com_dev * ena_dev,bool polling)1484 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1485 {
1486 u32 mask_value = 0;
1487
1488 if (polling)
1489 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1490
1491 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1492 ena_dev->admin_queue.polling = polling;
1493 }
1494
ena_com_mmio_reg_read_request_init(struct ena_com_dev * ena_dev)1495 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1496 {
1497 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1498
1499 spin_lock_init(&mmio_read->lock);
1500 mmio_read->read_resp =
1501 dma_zalloc_coherent(ena_dev->dmadev,
1502 sizeof(*mmio_read->read_resp),
1503 &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1504 if (unlikely(!mmio_read->read_resp))
1505 return -ENOMEM;
1506
1507 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1508
1509 mmio_read->read_resp->req_id = 0x0;
1510 mmio_read->seq_num = 0x0;
1511 mmio_read->readless_supported = true;
1512
1513 return 0;
1514 }
1515
ena_com_set_mmio_read_mode(struct ena_com_dev * ena_dev,bool readless_supported)1516 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1517 {
1518 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1519
1520 mmio_read->readless_supported = readless_supported;
1521 }
1522
ena_com_mmio_reg_read_request_destroy(struct ena_com_dev * ena_dev)1523 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1524 {
1525 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1526
1527 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1528 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1529
1530 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1531 mmio_read->read_resp, mmio_read->read_resp_dma_addr);
1532
1533 mmio_read->read_resp = NULL;
1534 }
1535
ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev * ena_dev)1536 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1537 {
1538 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1539 u32 addr_low, addr_high;
1540
1541 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1542 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1543
1544 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1545 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1546 }
1547
ena_com_admin_init(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers,bool init_spinlock)1548 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1549 struct ena_aenq_handlers *aenq_handlers,
1550 bool init_spinlock)
1551 {
1552 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1553 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1554 int ret;
1555
1556 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1557
1558 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1559 pr_err("Reg read timeout occurred\n");
1560 return -ETIME;
1561 }
1562
1563 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1564 pr_err("Device isn't ready, abort com init\n");
1565 return -ENODEV;
1566 }
1567
1568 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1569
1570 admin_queue->q_dmadev = ena_dev->dmadev;
1571 admin_queue->polling = false;
1572 admin_queue->curr_cmd_id = 0;
1573
1574 atomic_set(&admin_queue->outstanding_cmds, 0);
1575
1576 if (init_spinlock)
1577 spin_lock_init(&admin_queue->q_lock);
1578
1579 ret = ena_com_init_comp_ctxt(admin_queue);
1580 if (ret)
1581 goto error;
1582
1583 ret = ena_com_admin_init_sq(admin_queue);
1584 if (ret)
1585 goto error;
1586
1587 ret = ena_com_admin_init_cq(admin_queue);
1588 if (ret)
1589 goto error;
1590
1591 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1592 ENA_REGS_AQ_DB_OFF);
1593
1594 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1595 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1596
1597 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1598 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1599
1600 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1601 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1602
1603 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1604 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1605
1606 aq_caps = 0;
1607 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1608 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1609 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1610 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1611
1612 acq_caps = 0;
1613 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1614 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1615 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1616 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1617
1618 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1619 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1620 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1621 if (ret)
1622 goto error;
1623
1624 admin_queue->running_state = true;
1625
1626 return 0;
1627 error:
1628 ena_com_admin_destroy(ena_dev);
1629
1630 return ret;
1631 }
1632
ena_com_create_io_queue(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx)1633 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1634 struct ena_com_create_io_ctx *ctx)
1635 {
1636 struct ena_com_io_sq *io_sq;
1637 struct ena_com_io_cq *io_cq;
1638 int ret;
1639
1640 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1641 pr_err("Qid (%d) is bigger than max num of queues (%d)\n",
1642 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1643 return -EINVAL;
1644 }
1645
1646 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1647 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1648
1649 memset(io_sq, 0x0, sizeof(*io_sq));
1650 memset(io_cq, 0x0, sizeof(*io_cq));
1651
1652 /* Init CQ */
1653 io_cq->q_depth = ctx->queue_size;
1654 io_cq->direction = ctx->direction;
1655 io_cq->qid = ctx->qid;
1656
1657 io_cq->msix_vector = ctx->msix_vector;
1658
1659 io_sq->q_depth = ctx->queue_size;
1660 io_sq->direction = ctx->direction;
1661 io_sq->qid = ctx->qid;
1662
1663 io_sq->mem_queue_type = ctx->mem_queue_type;
1664
1665 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1666 /* header length is limited to 8 bits */
1667 io_sq->tx_max_header_size =
1668 min_t(u32, ena_dev->tx_max_header_size, SZ_256);
1669
1670 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1671 if (ret)
1672 goto error;
1673 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1674 if (ret)
1675 goto error;
1676
1677 ret = ena_com_create_io_cq(ena_dev, io_cq);
1678 if (ret)
1679 goto error;
1680
1681 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1682 if (ret)
1683 goto destroy_io_cq;
1684
1685 return 0;
1686
1687 destroy_io_cq:
1688 ena_com_destroy_io_cq(ena_dev, io_cq);
1689 error:
1690 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1691 return ret;
1692 }
1693
ena_com_destroy_io_queue(struct ena_com_dev * ena_dev,u16 qid)1694 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1695 {
1696 struct ena_com_io_sq *io_sq;
1697 struct ena_com_io_cq *io_cq;
1698
1699 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1700 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid,
1701 ENA_TOTAL_NUM_QUEUES);
1702 return;
1703 }
1704
1705 io_sq = &ena_dev->io_sq_queues[qid];
1706 io_cq = &ena_dev->io_cq_queues[qid];
1707
1708 ena_com_destroy_io_sq(ena_dev, io_sq);
1709 ena_com_destroy_io_cq(ena_dev, io_cq);
1710
1711 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1712 }
1713
ena_com_get_link_params(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * resp)1714 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1715 struct ena_admin_get_feat_resp *resp)
1716 {
1717 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG);
1718 }
1719
ena_com_get_dev_attr_feat(struct ena_com_dev * ena_dev,struct ena_com_dev_get_features_ctx * get_feat_ctx)1720 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1721 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1722 {
1723 struct ena_admin_get_feat_resp get_resp;
1724 int rc;
1725
1726 rc = ena_com_get_feature(ena_dev, &get_resp,
1727 ENA_ADMIN_DEVICE_ATTRIBUTES);
1728 if (rc)
1729 return rc;
1730
1731 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1732 sizeof(get_resp.u.dev_attr));
1733 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1734
1735 rc = ena_com_get_feature(ena_dev, &get_resp,
1736 ENA_ADMIN_MAX_QUEUES_NUM);
1737 if (rc)
1738 return rc;
1739
1740 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1741 sizeof(get_resp.u.max_queue));
1742 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size;
1743
1744 rc = ena_com_get_feature(ena_dev, &get_resp,
1745 ENA_ADMIN_AENQ_CONFIG);
1746 if (rc)
1747 return rc;
1748
1749 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1750 sizeof(get_resp.u.aenq));
1751
1752 rc = ena_com_get_feature(ena_dev, &get_resp,
1753 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1754 if (rc)
1755 return rc;
1756
1757 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1758 sizeof(get_resp.u.offload));
1759
1760 /* Driver hints isn't mandatory admin command. So in case the
1761 * command isn't supported set driver hints to 0
1762 */
1763 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS);
1764
1765 if (!rc)
1766 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
1767 sizeof(get_resp.u.hw_hints));
1768 else if (rc == -EOPNOTSUPP)
1769 memset(&get_feat_ctx->hw_hints, 0x0,
1770 sizeof(get_feat_ctx->hw_hints));
1771 else
1772 return rc;
1773
1774 return 0;
1775 }
1776
ena_com_admin_q_comp_intr_handler(struct ena_com_dev * ena_dev)1777 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1778 {
1779 ena_com_handle_admin_completion(&ena_dev->admin_queue);
1780 }
1781
1782 /* ena_handle_specific_aenq_event:
1783 * return the handler that is relevant to the specific event group
1784 */
ena_com_get_specific_aenq_cb(struct ena_com_dev * dev,u16 group)1785 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
1786 u16 group)
1787 {
1788 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1789
1790 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
1791 return aenq_handlers->handlers[group];
1792
1793 return aenq_handlers->unimplemented_handler;
1794 }
1795
1796 /* ena_aenq_intr_handler:
1797 * handles the aenq incoming events.
1798 * pop events from the queue and apply the specific handler
1799 */
ena_com_aenq_intr_handler(struct ena_com_dev * dev,void * data)1800 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
1801 {
1802 struct ena_admin_aenq_entry *aenq_e;
1803 struct ena_admin_aenq_common_desc *aenq_common;
1804 struct ena_com_aenq *aenq = &dev->aenq;
1805 ena_aenq_handler handler_cb;
1806 u16 masked_head, processed = 0;
1807 u8 phase;
1808
1809 masked_head = aenq->head & (aenq->q_depth - 1);
1810 phase = aenq->phase;
1811 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
1812 aenq_common = &aenq_e->aenq_common_desc;
1813
1814 /* Go over all the events */
1815 while ((READ_ONCE(aenq_common->flags) &
1816 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
1817 /* Make sure the phase bit (ownership) is as expected before
1818 * reading the rest of the descriptor.
1819 */
1820 dma_rmb();
1821
1822 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
1823 aenq_common->group, aenq_common->syndrom,
1824 (u64)aenq_common->timestamp_low +
1825 ((u64)aenq_common->timestamp_high << 32));
1826
1827 /* Handle specific event*/
1828 handler_cb = ena_com_get_specific_aenq_cb(dev,
1829 aenq_common->group);
1830 handler_cb(data, aenq_e); /* call the actual event handler*/
1831
1832 /* Get next event entry */
1833 masked_head++;
1834 processed++;
1835
1836 if (unlikely(masked_head == aenq->q_depth)) {
1837 masked_head = 0;
1838 phase = !phase;
1839 }
1840 aenq_e = &aenq->entries[masked_head];
1841 aenq_common = &aenq_e->aenq_common_desc;
1842 }
1843
1844 aenq->head += processed;
1845 aenq->phase = phase;
1846
1847 /* Don't update aenq doorbell if there weren't any processed events */
1848 if (!processed)
1849 return;
1850
1851 /* write the aenq doorbell after all AENQ descriptors were read */
1852 mb();
1853 writel_relaxed((u32)aenq->head,
1854 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1855 mmiowb();
1856 }
1857
ena_com_dev_reset(struct ena_com_dev * ena_dev,enum ena_regs_reset_reason_types reset_reason)1858 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
1859 enum ena_regs_reset_reason_types reset_reason)
1860 {
1861 u32 stat, timeout, cap, reset_val;
1862 int rc;
1863
1864 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1865 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1866
1867 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
1868 (cap == ENA_MMIO_READ_TIMEOUT))) {
1869 pr_err("Reg read32 timeout occurred\n");
1870 return -ETIME;
1871 }
1872
1873 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
1874 pr_err("Device isn't ready, can't reset device\n");
1875 return -EINVAL;
1876 }
1877
1878 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
1879 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
1880 if (timeout == 0) {
1881 pr_err("Invalid timeout value\n");
1882 return -EINVAL;
1883 }
1884
1885 /* start reset */
1886 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
1887 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
1888 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
1889 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
1890
1891 /* Write again the MMIO read request address */
1892 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1893
1894 rc = wait_for_reset_state(ena_dev, timeout,
1895 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
1896 if (rc != 0) {
1897 pr_err("Reset indication didn't turn on\n");
1898 return rc;
1899 }
1900
1901 /* reset done */
1902 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
1903 rc = wait_for_reset_state(ena_dev, timeout, 0);
1904 if (rc != 0) {
1905 pr_err("Reset indication didn't turn off\n");
1906 return rc;
1907 }
1908
1909 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
1910 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
1911 if (timeout)
1912 /* the resolution of timeout reg is 100ms */
1913 ena_dev->admin_queue.completion_timeout = timeout * 100000;
1914 else
1915 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
1916
1917 return 0;
1918 }
1919
ena_get_dev_stats(struct ena_com_dev * ena_dev,struct ena_com_stats_ctx * ctx,enum ena_admin_get_stats_type type)1920 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
1921 struct ena_com_stats_ctx *ctx,
1922 enum ena_admin_get_stats_type type)
1923 {
1924 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
1925 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
1926 struct ena_com_admin_queue *admin_queue;
1927 int ret;
1928
1929 admin_queue = &ena_dev->admin_queue;
1930
1931 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
1932 get_cmd->aq_common_descriptor.flags = 0;
1933 get_cmd->type = type;
1934
1935 ret = ena_com_execute_admin_command(admin_queue,
1936 (struct ena_admin_aq_entry *)get_cmd,
1937 sizeof(*get_cmd),
1938 (struct ena_admin_acq_entry *)get_resp,
1939 sizeof(*get_resp));
1940
1941 if (unlikely(ret))
1942 pr_err("Failed to get stats. error: %d\n", ret);
1943
1944 return ret;
1945 }
1946
ena_com_get_dev_basic_stats(struct ena_com_dev * ena_dev,struct ena_admin_basic_stats * stats)1947 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
1948 struct ena_admin_basic_stats *stats)
1949 {
1950 struct ena_com_stats_ctx ctx;
1951 int ret;
1952
1953 memset(&ctx, 0x0, sizeof(ctx));
1954 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
1955 if (likely(ret == 0))
1956 memcpy(stats, &ctx.get_resp.basic_stats,
1957 sizeof(ctx.get_resp.basic_stats));
1958
1959 return ret;
1960 }
1961
ena_com_set_dev_mtu(struct ena_com_dev * ena_dev,int mtu)1962 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
1963 {
1964 struct ena_com_admin_queue *admin_queue;
1965 struct ena_admin_set_feat_cmd cmd;
1966 struct ena_admin_set_feat_resp resp;
1967 int ret;
1968
1969 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
1970 pr_debug("Feature %d isn't supported\n", ENA_ADMIN_MTU);
1971 return -EOPNOTSUPP;
1972 }
1973
1974 memset(&cmd, 0x0, sizeof(cmd));
1975 admin_queue = &ena_dev->admin_queue;
1976
1977 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1978 cmd.aq_common_descriptor.flags = 0;
1979 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
1980 cmd.u.mtu.mtu = mtu;
1981
1982 ret = ena_com_execute_admin_command(admin_queue,
1983 (struct ena_admin_aq_entry *)&cmd,
1984 sizeof(cmd),
1985 (struct ena_admin_acq_entry *)&resp,
1986 sizeof(resp));
1987
1988 if (unlikely(ret))
1989 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret);
1990
1991 return ret;
1992 }
1993
ena_com_get_offload_settings(struct ena_com_dev * ena_dev,struct ena_admin_feature_offload_desc * offload)1994 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
1995 struct ena_admin_feature_offload_desc *offload)
1996 {
1997 int ret;
1998 struct ena_admin_get_feat_resp resp;
1999
2000 ret = ena_com_get_feature(ena_dev, &resp,
2001 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
2002 if (unlikely(ret)) {
2003 pr_err("Failed to get offload capabilities %d\n", ret);
2004 return ret;
2005 }
2006
2007 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2008
2009 return 0;
2010 }
2011
ena_com_set_hash_function(struct ena_com_dev * ena_dev)2012 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2013 {
2014 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2015 struct ena_rss *rss = &ena_dev->rss;
2016 struct ena_admin_set_feat_cmd cmd;
2017 struct ena_admin_set_feat_resp resp;
2018 struct ena_admin_get_feat_resp get_resp;
2019 int ret;
2020
2021 if (!ena_com_check_supported_feature_id(ena_dev,
2022 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2023 pr_debug("Feature %d isn't supported\n",
2024 ENA_ADMIN_RSS_HASH_FUNCTION);
2025 return -EOPNOTSUPP;
2026 }
2027
2028 /* Validate hash function is supported */
2029 ret = ena_com_get_feature(ena_dev, &get_resp,
2030 ENA_ADMIN_RSS_HASH_FUNCTION);
2031 if (unlikely(ret))
2032 return ret;
2033
2034 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2035 pr_err("Func hash %d isn't supported by device, abort\n",
2036 rss->hash_func);
2037 return -EOPNOTSUPP;
2038 }
2039
2040 memset(&cmd, 0x0, sizeof(cmd));
2041
2042 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2043 cmd.aq_common_descriptor.flags =
2044 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2045 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2046 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2047 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2048
2049 ret = ena_com_mem_addr_set(ena_dev,
2050 &cmd.control_buffer.address,
2051 rss->hash_key_dma_addr);
2052 if (unlikely(ret)) {
2053 pr_err("memory address set failed\n");
2054 return ret;
2055 }
2056
2057 cmd.control_buffer.length = sizeof(*rss->hash_key);
2058
2059 ret = ena_com_execute_admin_command(admin_queue,
2060 (struct ena_admin_aq_entry *)&cmd,
2061 sizeof(cmd),
2062 (struct ena_admin_acq_entry *)&resp,
2063 sizeof(resp));
2064 if (unlikely(ret)) {
2065 pr_err("Failed to set hash function %d. error: %d\n",
2066 rss->hash_func, ret);
2067 return -EINVAL;
2068 }
2069
2070 return 0;
2071 }
2072
ena_com_fill_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions func,const u8 * key,u16 key_len,u32 init_val)2073 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2074 enum ena_admin_hash_functions func,
2075 const u8 *key, u16 key_len, u32 init_val)
2076 {
2077 struct ena_rss *rss = &ena_dev->rss;
2078 struct ena_admin_get_feat_resp get_resp;
2079 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2080 rss->hash_key;
2081 int rc;
2082
2083 /* Make sure size is a mult of DWs */
2084 if (unlikely(key_len & 0x3))
2085 return -EINVAL;
2086
2087 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2088 ENA_ADMIN_RSS_HASH_FUNCTION,
2089 rss->hash_key_dma_addr,
2090 sizeof(*rss->hash_key));
2091 if (unlikely(rc))
2092 return rc;
2093
2094 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
2095 pr_err("Flow hash function %d isn't supported\n", func);
2096 return -EOPNOTSUPP;
2097 }
2098
2099 switch (func) {
2100 case ENA_ADMIN_TOEPLITZ:
2101 if (key) {
2102 if (key_len != sizeof(hash_key->key)) {
2103 pr_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2104 key_len, sizeof(hash_key->key));
2105 return -EINVAL;
2106 }
2107 memcpy(hash_key->key, key, key_len);
2108 rss->hash_init_val = init_val;
2109 hash_key->keys_num = key_len >> 2;
2110 }
2111 break;
2112 case ENA_ADMIN_CRC32:
2113 rss->hash_init_val = init_val;
2114 break;
2115 default:
2116 pr_err("Invalid hash function (%d)\n", func);
2117 return -EINVAL;
2118 }
2119
2120 rss->hash_func = func;
2121 rc = ena_com_set_hash_function(ena_dev);
2122
2123 /* Restore the old function */
2124 if (unlikely(rc))
2125 ena_com_get_hash_function(ena_dev, NULL, NULL);
2126
2127 return rc;
2128 }
2129
ena_com_get_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions * func,u8 * key)2130 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2131 enum ena_admin_hash_functions *func,
2132 u8 *key)
2133 {
2134 struct ena_rss *rss = &ena_dev->rss;
2135 struct ena_admin_get_feat_resp get_resp;
2136 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2137 rss->hash_key;
2138 int rc;
2139
2140 if (unlikely(!func))
2141 return -EINVAL;
2142
2143 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2144 ENA_ADMIN_RSS_HASH_FUNCTION,
2145 rss->hash_key_dma_addr,
2146 sizeof(*rss->hash_key));
2147 if (unlikely(rc))
2148 return rc;
2149
2150 /* ffs() returns 1 in case the lsb is set */
2151 rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func);
2152 if (rss->hash_func)
2153 rss->hash_func--;
2154
2155 *func = rss->hash_func;
2156
2157 if (key)
2158 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2159
2160 return 0;
2161 }
2162
ena_com_get_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 * fields)2163 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2164 enum ena_admin_flow_hash_proto proto,
2165 u16 *fields)
2166 {
2167 struct ena_rss *rss = &ena_dev->rss;
2168 struct ena_admin_get_feat_resp get_resp;
2169 int rc;
2170
2171 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2172 ENA_ADMIN_RSS_HASH_INPUT,
2173 rss->hash_ctrl_dma_addr,
2174 sizeof(*rss->hash_ctrl));
2175 if (unlikely(rc))
2176 return rc;
2177
2178 if (fields)
2179 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2180
2181 return 0;
2182 }
2183
ena_com_set_hash_ctrl(struct ena_com_dev * ena_dev)2184 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2185 {
2186 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2187 struct ena_rss *rss = &ena_dev->rss;
2188 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2189 struct ena_admin_set_feat_cmd cmd;
2190 struct ena_admin_set_feat_resp resp;
2191 int ret;
2192
2193 if (!ena_com_check_supported_feature_id(ena_dev,
2194 ENA_ADMIN_RSS_HASH_INPUT)) {
2195 pr_debug("Feature %d isn't supported\n",
2196 ENA_ADMIN_RSS_HASH_INPUT);
2197 return -EOPNOTSUPP;
2198 }
2199
2200 memset(&cmd, 0x0, sizeof(cmd));
2201
2202 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2203 cmd.aq_common_descriptor.flags =
2204 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2205 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2206 cmd.u.flow_hash_input.enabled_input_sort =
2207 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2208 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2209
2210 ret = ena_com_mem_addr_set(ena_dev,
2211 &cmd.control_buffer.address,
2212 rss->hash_ctrl_dma_addr);
2213 if (unlikely(ret)) {
2214 pr_err("memory address set failed\n");
2215 return ret;
2216 }
2217 cmd.control_buffer.length = sizeof(*hash_ctrl);
2218
2219 ret = ena_com_execute_admin_command(admin_queue,
2220 (struct ena_admin_aq_entry *)&cmd,
2221 sizeof(cmd),
2222 (struct ena_admin_acq_entry *)&resp,
2223 sizeof(resp));
2224 if (unlikely(ret))
2225 pr_err("Failed to set hash input. error: %d\n", ret);
2226
2227 return ret;
2228 }
2229
ena_com_set_default_hash_ctrl(struct ena_com_dev * ena_dev)2230 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2231 {
2232 struct ena_rss *rss = &ena_dev->rss;
2233 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2234 rss->hash_ctrl;
2235 u16 available_fields = 0;
2236 int rc, i;
2237
2238 /* Get the supported hash input */
2239 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2240 if (unlikely(rc))
2241 return rc;
2242
2243 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2244 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2245 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2246
2247 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2248 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2249 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2250
2251 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2252 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2253 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2254
2255 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2256 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2257 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2258
2259 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2260 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2261
2262 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2263 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2264
2265 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2266 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2267
2268 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2269 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2270
2271 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2272 available_fields = hash_ctrl->selected_fields[i].fields &
2273 hash_ctrl->supported_fields[i].fields;
2274 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2275 pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2276 i, hash_ctrl->supported_fields[i].fields,
2277 hash_ctrl->selected_fields[i].fields);
2278 return -EOPNOTSUPP;
2279 }
2280 }
2281
2282 rc = ena_com_set_hash_ctrl(ena_dev);
2283
2284 /* In case of failure, restore the old hash ctrl */
2285 if (unlikely(rc))
2286 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2287
2288 return rc;
2289 }
2290
ena_com_fill_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 hash_fields)2291 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2292 enum ena_admin_flow_hash_proto proto,
2293 u16 hash_fields)
2294 {
2295 struct ena_rss *rss = &ena_dev->rss;
2296 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2297 u16 supported_fields;
2298 int rc;
2299
2300 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2301 pr_err("Invalid proto num (%u)\n", proto);
2302 return -EINVAL;
2303 }
2304
2305 /* Get the ctrl table */
2306 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2307 if (unlikely(rc))
2308 return rc;
2309
2310 /* Make sure all the fields are supported */
2311 supported_fields = hash_ctrl->supported_fields[proto].fields;
2312 if ((hash_fields & supported_fields) != hash_fields) {
2313 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2314 proto, hash_fields, supported_fields);
2315 }
2316
2317 hash_ctrl->selected_fields[proto].fields = hash_fields;
2318
2319 rc = ena_com_set_hash_ctrl(ena_dev);
2320
2321 /* In case of failure, restore the old hash ctrl */
2322 if (unlikely(rc))
2323 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2324
2325 return 0;
2326 }
2327
ena_com_indirect_table_fill_entry(struct ena_com_dev * ena_dev,u16 entry_idx,u16 entry_value)2328 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2329 u16 entry_idx, u16 entry_value)
2330 {
2331 struct ena_rss *rss = &ena_dev->rss;
2332
2333 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2334 return -EINVAL;
2335
2336 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2337 return -EINVAL;
2338
2339 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2340
2341 return 0;
2342 }
2343
ena_com_indirect_table_set(struct ena_com_dev * ena_dev)2344 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2345 {
2346 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2347 struct ena_rss *rss = &ena_dev->rss;
2348 struct ena_admin_set_feat_cmd cmd;
2349 struct ena_admin_set_feat_resp resp;
2350 int ret;
2351
2352 if (!ena_com_check_supported_feature_id(
2353 ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2354 pr_debug("Feature %d isn't supported\n",
2355 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2356 return -EOPNOTSUPP;
2357 }
2358
2359 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2360 if (ret) {
2361 pr_err("Failed to convert host indirection table to device table\n");
2362 return ret;
2363 }
2364
2365 memset(&cmd, 0x0, sizeof(cmd));
2366
2367 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2368 cmd.aq_common_descriptor.flags =
2369 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2370 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2371 cmd.u.ind_table.size = rss->tbl_log_size;
2372 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2373
2374 ret = ena_com_mem_addr_set(ena_dev,
2375 &cmd.control_buffer.address,
2376 rss->rss_ind_tbl_dma_addr);
2377 if (unlikely(ret)) {
2378 pr_err("memory address set failed\n");
2379 return ret;
2380 }
2381
2382 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2383 sizeof(struct ena_admin_rss_ind_table_entry);
2384
2385 ret = ena_com_execute_admin_command(admin_queue,
2386 (struct ena_admin_aq_entry *)&cmd,
2387 sizeof(cmd),
2388 (struct ena_admin_acq_entry *)&resp,
2389 sizeof(resp));
2390
2391 if (unlikely(ret))
2392 pr_err("Failed to set indirect table. error: %d\n", ret);
2393
2394 return ret;
2395 }
2396
ena_com_indirect_table_get(struct ena_com_dev * ena_dev,u32 * ind_tbl)2397 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2398 {
2399 struct ena_rss *rss = &ena_dev->rss;
2400 struct ena_admin_get_feat_resp get_resp;
2401 u32 tbl_size;
2402 int i, rc;
2403
2404 tbl_size = (1ULL << rss->tbl_log_size) *
2405 sizeof(struct ena_admin_rss_ind_table_entry);
2406
2407 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2408 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2409 rss->rss_ind_tbl_dma_addr,
2410 tbl_size);
2411 if (unlikely(rc))
2412 return rc;
2413
2414 if (!ind_tbl)
2415 return 0;
2416
2417 rc = ena_com_ind_tbl_convert_from_device(ena_dev);
2418 if (unlikely(rc))
2419 return rc;
2420
2421 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2422 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2423
2424 return 0;
2425 }
2426
ena_com_rss_init(struct ena_com_dev * ena_dev,u16 indr_tbl_log_size)2427 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2428 {
2429 int rc;
2430
2431 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2432
2433 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2434 if (unlikely(rc))
2435 goto err_indr_tbl;
2436
2437 rc = ena_com_hash_key_allocate(ena_dev);
2438 if (unlikely(rc))
2439 goto err_hash_key;
2440
2441 ena_com_hash_key_fill_default_key(ena_dev);
2442
2443 rc = ena_com_hash_ctrl_init(ena_dev);
2444 if (unlikely(rc))
2445 goto err_hash_ctrl;
2446
2447 return 0;
2448
2449 err_hash_ctrl:
2450 ena_com_hash_key_destroy(ena_dev);
2451 err_hash_key:
2452 ena_com_indirect_table_destroy(ena_dev);
2453 err_indr_tbl:
2454
2455 return rc;
2456 }
2457
ena_com_rss_destroy(struct ena_com_dev * ena_dev)2458 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2459 {
2460 ena_com_indirect_table_destroy(ena_dev);
2461 ena_com_hash_key_destroy(ena_dev);
2462 ena_com_hash_ctrl_destroy(ena_dev);
2463
2464 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2465 }
2466
ena_com_allocate_host_info(struct ena_com_dev * ena_dev)2467 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2468 {
2469 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2470
2471 host_attr->host_info =
2472 dma_zalloc_coherent(ena_dev->dmadev, SZ_4K,
2473 &host_attr->host_info_dma_addr, GFP_KERNEL);
2474 if (unlikely(!host_attr->host_info))
2475 return -ENOMEM;
2476
2477 return 0;
2478 }
2479
ena_com_allocate_debug_area(struct ena_com_dev * ena_dev,u32 debug_area_size)2480 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2481 u32 debug_area_size)
2482 {
2483 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2484
2485 host_attr->debug_area_virt_addr =
2486 dma_zalloc_coherent(ena_dev->dmadev, debug_area_size,
2487 &host_attr->debug_area_dma_addr, GFP_KERNEL);
2488 if (unlikely(!host_attr->debug_area_virt_addr)) {
2489 host_attr->debug_area_size = 0;
2490 return -ENOMEM;
2491 }
2492
2493 host_attr->debug_area_size = debug_area_size;
2494
2495 return 0;
2496 }
2497
ena_com_delete_host_info(struct ena_com_dev * ena_dev)2498 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2499 {
2500 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2501
2502 if (host_attr->host_info) {
2503 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
2504 host_attr->host_info_dma_addr);
2505 host_attr->host_info = NULL;
2506 }
2507 }
2508
ena_com_delete_debug_area(struct ena_com_dev * ena_dev)2509 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2510 {
2511 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2512
2513 if (host_attr->debug_area_virt_addr) {
2514 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
2515 host_attr->debug_area_virt_addr,
2516 host_attr->debug_area_dma_addr);
2517 host_attr->debug_area_virt_addr = NULL;
2518 }
2519 }
2520
ena_com_set_host_attributes(struct ena_com_dev * ena_dev)2521 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2522 {
2523 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2524 struct ena_com_admin_queue *admin_queue;
2525 struct ena_admin_set_feat_cmd cmd;
2526 struct ena_admin_set_feat_resp resp;
2527
2528 int ret;
2529
2530 /* Host attribute config is called before ena_com_get_dev_attr_feat
2531 * so ena_com can't check if the feature is supported.
2532 */
2533
2534 memset(&cmd, 0x0, sizeof(cmd));
2535 admin_queue = &ena_dev->admin_queue;
2536
2537 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2538 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2539
2540 ret = ena_com_mem_addr_set(ena_dev,
2541 &cmd.u.host_attr.debug_ba,
2542 host_attr->debug_area_dma_addr);
2543 if (unlikely(ret)) {
2544 pr_err("memory address set failed\n");
2545 return ret;
2546 }
2547
2548 ret = ena_com_mem_addr_set(ena_dev,
2549 &cmd.u.host_attr.os_info_ba,
2550 host_attr->host_info_dma_addr);
2551 if (unlikely(ret)) {
2552 pr_err("memory address set failed\n");
2553 return ret;
2554 }
2555
2556 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2557
2558 ret = ena_com_execute_admin_command(admin_queue,
2559 (struct ena_admin_aq_entry *)&cmd,
2560 sizeof(cmd),
2561 (struct ena_admin_acq_entry *)&resp,
2562 sizeof(resp));
2563
2564 if (unlikely(ret))
2565 pr_err("Failed to set host attributes: %d\n", ret);
2566
2567 return ret;
2568 }
2569
2570 /* Interrupt moderation */
ena_com_interrupt_moderation_supported(struct ena_com_dev * ena_dev)2571 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2572 {
2573 return ena_com_check_supported_feature_id(ena_dev,
2574 ENA_ADMIN_INTERRUPT_MODERATION);
2575 }
2576
ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev,u32 tx_coalesce_usecs)2577 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2578 u32 tx_coalesce_usecs)
2579 {
2580 if (!ena_dev->intr_delay_resolution) {
2581 pr_err("Illegal interrupt delay granularity value\n");
2582 return -EFAULT;
2583 }
2584
2585 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs /
2586 ena_dev->intr_delay_resolution;
2587
2588 return 0;
2589 }
2590
ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev,u32 rx_coalesce_usecs)2591 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2592 u32 rx_coalesce_usecs)
2593 {
2594 if (!ena_dev->intr_delay_resolution) {
2595 pr_err("Illegal interrupt delay granularity value\n");
2596 return -EFAULT;
2597 }
2598
2599 /* We use LOWEST entry of moderation table for storing
2600 * nonadaptive interrupt coalescing values
2601 */
2602 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2603 rx_coalesce_usecs / ena_dev->intr_delay_resolution;
2604
2605 return 0;
2606 }
2607
ena_com_destroy_interrupt_moderation(struct ena_com_dev * ena_dev)2608 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
2609 {
2610 if (ena_dev->intr_moder_tbl)
2611 devm_kfree(ena_dev->dmadev, ena_dev->intr_moder_tbl);
2612 ena_dev->intr_moder_tbl = NULL;
2613 }
2614
ena_com_init_interrupt_moderation(struct ena_com_dev * ena_dev)2615 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2616 {
2617 struct ena_admin_get_feat_resp get_resp;
2618 u16 delay_resolution;
2619 int rc;
2620
2621 rc = ena_com_get_feature(ena_dev, &get_resp,
2622 ENA_ADMIN_INTERRUPT_MODERATION);
2623
2624 if (rc) {
2625 if (rc == -EOPNOTSUPP) {
2626 pr_debug("Feature %d isn't supported\n",
2627 ENA_ADMIN_INTERRUPT_MODERATION);
2628 rc = 0;
2629 } else {
2630 pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2631 rc);
2632 }
2633
2634 /* no moderation supported, disable adaptive support */
2635 ena_com_disable_adaptive_moderation(ena_dev);
2636 return rc;
2637 }
2638
2639 rc = ena_com_init_interrupt_moderation_table(ena_dev);
2640 if (rc)
2641 goto err;
2642
2643 /* if moderation is supported by device we set adaptive moderation */
2644 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2645 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2646 ena_com_enable_adaptive_moderation(ena_dev);
2647
2648 return 0;
2649 err:
2650 ena_com_destroy_interrupt_moderation(ena_dev);
2651 return rc;
2652 }
2653
ena_com_config_default_interrupt_moderation_table(struct ena_com_dev * ena_dev)2654 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)
2655 {
2656 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2657
2658 if (!intr_moder_tbl)
2659 return;
2660
2661 intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2662 ENA_INTR_LOWEST_USECS;
2663 intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval =
2664 ENA_INTR_LOWEST_PKTS;
2665 intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval =
2666 ENA_INTR_LOWEST_BYTES;
2667
2668 intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval =
2669 ENA_INTR_LOW_USECS;
2670 intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval =
2671 ENA_INTR_LOW_PKTS;
2672 intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval =
2673 ENA_INTR_LOW_BYTES;
2674
2675 intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval =
2676 ENA_INTR_MID_USECS;
2677 intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval =
2678 ENA_INTR_MID_PKTS;
2679 intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval =
2680 ENA_INTR_MID_BYTES;
2681
2682 intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval =
2683 ENA_INTR_HIGH_USECS;
2684 intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval =
2685 ENA_INTR_HIGH_PKTS;
2686 intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval =
2687 ENA_INTR_HIGH_BYTES;
2688
2689 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval =
2690 ENA_INTR_HIGHEST_USECS;
2691 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval =
2692 ENA_INTR_HIGHEST_PKTS;
2693 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval =
2694 ENA_INTR_HIGHEST_BYTES;
2695 }
2696
ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev)2697 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2698 {
2699 return ena_dev->intr_moder_tx_interval;
2700 }
2701
ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev)2702 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2703 {
2704 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2705
2706 if (intr_moder_tbl)
2707 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval;
2708
2709 return 0;
2710 }
2711
ena_com_init_intr_moderation_entry(struct ena_com_dev * ena_dev,enum ena_intr_moder_level level,struct ena_intr_moder_entry * entry)2712 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
2713 enum ena_intr_moder_level level,
2714 struct ena_intr_moder_entry *entry)
2715 {
2716 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2717
2718 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2719 return;
2720
2721 intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval;
2722 if (ena_dev->intr_delay_resolution)
2723 intr_moder_tbl[level].intr_moder_interval /=
2724 ena_dev->intr_delay_resolution;
2725 intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;
2726
2727 /* use hardcoded value until ethtool supports bytecount parameter */
2728 if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED)
2729 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;
2730 }
2731
ena_com_get_intr_moderation_entry(struct ena_com_dev * ena_dev,enum ena_intr_moder_level level,struct ena_intr_moder_entry * entry)2732 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
2733 enum ena_intr_moder_level level,
2734 struct ena_intr_moder_entry *entry)
2735 {
2736 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2737
2738 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2739 return;
2740
2741 entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval;
2742 if (ena_dev->intr_delay_resolution)
2743 entry->intr_moder_interval *= ena_dev->intr_delay_resolution;
2744 entry->pkts_per_interval =
2745 intr_moder_tbl[level].pkts_per_interval;
2746 entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
2747 }
2748