1 /*
2 * arch/xtensa/kernel/setup.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Kevin Chea
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
16 */
17
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/cpu.h>
26 #include <linux/of.h>
27 #include <linux/of_fdt.h>
28
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
31 #endif
32
33 #ifdef CONFIG_PROC_FS
34 # include <linux/seq_file.h>
35 #endif
36
37 #include <asm/bootparam.h>
38 #include <asm/kasan.h>
39 #include <asm/mmu_context.h>
40 #include <asm/pgtable.h>
41 #include <asm/processor.h>
42 #include <asm/timex.h>
43 #include <asm/platform.h>
44 #include <asm/page.h>
45 #include <asm/setup.h>
46 #include <asm/param.h>
47 #include <asm/smp.h>
48 #include <asm/sysmem.h>
49
50 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
51 struct screen_info screen_info = {
52 .orig_x = 0,
53 .orig_y = 24,
54 .orig_video_cols = 80,
55 .orig_video_lines = 24,
56 .orig_video_isVGA = 1,
57 .orig_video_points = 16,
58 };
59 #endif
60
61 #ifdef CONFIG_BLK_DEV_INITRD
62 extern unsigned long initrd_start;
63 extern unsigned long initrd_end;
64 int initrd_is_mapped = 0;
65 extern int initrd_below_start_ok;
66 #endif
67
68 #ifdef CONFIG_OF
69 void *dtb_start = __dtb_start;
70 #endif
71
72 extern unsigned long loops_per_jiffy;
73
74 /* Command line specified as configuration option. */
75
76 static char __initdata command_line[COMMAND_LINE_SIZE];
77
78 #ifdef CONFIG_CMDLINE_BOOL
79 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
80 #endif
81
82 #ifdef CONFIG_PARSE_BOOTPARAM
83 /*
84 * Boot parameter parsing.
85 *
86 * The Xtensa port uses a list of variable-sized tags to pass data to
87 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
88 * to be recognised. The list is terminated with a zero-sized
89 * BP_TAG_LAST tag.
90 */
91
92 typedef struct tagtable {
93 u32 tag;
94 int (*parse)(const bp_tag_t*);
95 } tagtable_t;
96
97 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
98 __attribute__((used, section(".taglist"))) = { tag, fn }
99
100 /* parse current tag */
101
parse_tag_mem(const bp_tag_t * tag)102 static int __init parse_tag_mem(const bp_tag_t *tag)
103 {
104 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
105
106 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
107 return -1;
108
109 return memblock_add(mi->start, mi->end - mi->start);
110 }
111
112 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
113
114 #ifdef CONFIG_BLK_DEV_INITRD
115
parse_tag_initrd(const bp_tag_t * tag)116 static int __init parse_tag_initrd(const bp_tag_t* tag)
117 {
118 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
119
120 initrd_start = (unsigned long)__va(mi->start);
121 initrd_end = (unsigned long)__va(mi->end);
122
123 return 0;
124 }
125
126 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
127
128 #endif /* CONFIG_BLK_DEV_INITRD */
129
130 #ifdef CONFIG_OF
131
parse_tag_fdt(const bp_tag_t * tag)132 static int __init parse_tag_fdt(const bp_tag_t *tag)
133 {
134 dtb_start = __va(tag->data[0]);
135 return 0;
136 }
137
138 __tagtable(BP_TAG_FDT, parse_tag_fdt);
139
140 #endif /* CONFIG_OF */
141
parse_tag_cmdline(const bp_tag_t * tag)142 static int __init parse_tag_cmdline(const bp_tag_t* tag)
143 {
144 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
145 return 0;
146 }
147
148 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
149
parse_bootparam(const bp_tag_t * tag)150 static int __init parse_bootparam(const bp_tag_t* tag)
151 {
152 extern tagtable_t __tagtable_begin, __tagtable_end;
153 tagtable_t *t;
154
155 /* Boot parameters must start with a BP_TAG_FIRST tag. */
156
157 if (tag->id != BP_TAG_FIRST) {
158 pr_warn("Invalid boot parameters!\n");
159 return 0;
160 }
161
162 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
163
164 /* Parse all tags. */
165
166 while (tag != NULL && tag->id != BP_TAG_LAST) {
167 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
168 if (tag->id == t->tag) {
169 t->parse(tag);
170 break;
171 }
172 }
173 if (t == &__tagtable_end)
174 pr_warn("Ignoring tag 0x%08x\n", tag->id);
175 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
176 }
177
178 return 0;
179 }
180 #else
parse_bootparam(const bp_tag_t * tag)181 static int __init parse_bootparam(const bp_tag_t *tag)
182 {
183 pr_info("Ignoring boot parameters at %p\n", tag);
184 return 0;
185 }
186 #endif
187
188 #ifdef CONFIG_OF
189
190 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
191 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
192 EXPORT_SYMBOL(xtensa_kio_paddr);
193
xtensa_dt_io_area(unsigned long node,const char * uname,int depth,void * data)194 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
195 int depth, void *data)
196 {
197 const __be32 *ranges;
198 int len;
199
200 if (depth > 1)
201 return 0;
202
203 if (!of_flat_dt_is_compatible(node, "simple-bus"))
204 return 0;
205
206 ranges = of_get_flat_dt_prop(node, "ranges", &len);
207 if (!ranges)
208 return 1;
209 if (len == 0)
210 return 1;
211
212 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
213 /* round down to nearest 256MB boundary */
214 xtensa_kio_paddr &= 0xf0000000;
215
216 init_kio();
217
218 return 1;
219 }
220 #else
xtensa_dt_io_area(unsigned long node,const char * uname,int depth,void * data)221 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
222 int depth, void *data)
223 {
224 return 1;
225 }
226 #endif
227
early_init_devtree(void * params)228 void __init early_init_devtree(void *params)
229 {
230 early_init_dt_scan(params);
231 of_scan_flat_dt(xtensa_dt_io_area, NULL);
232
233 if (!command_line[0])
234 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
235 }
236
237 #endif /* CONFIG_OF */
238
239 /*
240 * Initialize architecture. (Early stage)
241 */
242
init_arch(bp_tag_t * bp_start)243 void __init init_arch(bp_tag_t *bp_start)
244 {
245 /* Initialize MMU. */
246
247 init_mmu();
248
249 /* Initialize initial KASAN shadow map */
250
251 kasan_early_init();
252
253 /* Parse boot parameters */
254
255 if (bp_start)
256 parse_bootparam(bp_start);
257
258 #ifdef CONFIG_OF
259 early_init_devtree(dtb_start);
260 #endif
261
262 #ifdef CONFIG_CMDLINE_BOOL
263 if (!command_line[0])
264 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
265 #endif
266
267 /* Early hook for platforms */
268
269 platform_init(bp_start);
270 }
271
272 /*
273 * Initialize system. Setup memory and reserve regions.
274 */
275
276 extern char _end[];
277 extern char _stext[];
278 extern char _WindowVectors_text_start;
279 extern char _WindowVectors_text_end;
280 extern char _DebugInterruptVector_text_start;
281 extern char _DebugInterruptVector_text_end;
282 extern char _KernelExceptionVector_text_start;
283 extern char _KernelExceptionVector_text_end;
284 extern char _UserExceptionVector_text_start;
285 extern char _UserExceptionVector_text_end;
286 extern char _DoubleExceptionVector_text_start;
287 extern char _DoubleExceptionVector_text_end;
288 #if XCHAL_EXCM_LEVEL >= 2
289 extern char _Level2InterruptVector_text_start;
290 extern char _Level2InterruptVector_text_end;
291 #endif
292 #if XCHAL_EXCM_LEVEL >= 3
293 extern char _Level3InterruptVector_text_start;
294 extern char _Level3InterruptVector_text_end;
295 #endif
296 #if XCHAL_EXCM_LEVEL >= 4
297 extern char _Level4InterruptVector_text_start;
298 extern char _Level4InterruptVector_text_end;
299 #endif
300 #if XCHAL_EXCM_LEVEL >= 5
301 extern char _Level5InterruptVector_text_start;
302 extern char _Level5InterruptVector_text_end;
303 #endif
304 #if XCHAL_EXCM_LEVEL >= 6
305 extern char _Level6InterruptVector_text_start;
306 extern char _Level6InterruptVector_text_end;
307 #endif
308 #ifdef CONFIG_SMP
309 extern char _SecondaryResetVector_text_start;
310 extern char _SecondaryResetVector_text_end;
311 #endif
312
mem_reserve(unsigned long start,unsigned long end)313 static inline int __init_memblock mem_reserve(unsigned long start,
314 unsigned long end)
315 {
316 return memblock_reserve(start, end - start);
317 }
318
setup_arch(char ** cmdline_p)319 void __init setup_arch(char **cmdline_p)
320 {
321 pr_info("config ID: %08x:%08x\n",
322 get_sr(SREG_EPC), get_sr(SREG_EXCSAVE));
323 if (get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
324 get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
325 pr_info("built for config ID: %08x:%08x\n",
326 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
327
328 *cmdline_p = command_line;
329 platform_setup(cmdline_p);
330 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
331
332 /* Reserve some memory regions */
333
334 #ifdef CONFIG_BLK_DEV_INITRD
335 if (initrd_start < initrd_end) {
336 initrd_is_mapped = mem_reserve(__pa(initrd_start),
337 __pa(initrd_end)) == 0;
338 initrd_below_start_ok = 1;
339 } else {
340 initrd_start = 0;
341 }
342 #endif
343
344 mem_reserve(__pa(_stext), __pa(_end));
345
346 #ifdef CONFIG_VECTORS_OFFSET
347 mem_reserve(__pa(&_WindowVectors_text_start),
348 __pa(&_WindowVectors_text_end));
349
350 mem_reserve(__pa(&_DebugInterruptVector_text_start),
351 __pa(&_DebugInterruptVector_text_end));
352
353 mem_reserve(__pa(&_KernelExceptionVector_text_start),
354 __pa(&_KernelExceptionVector_text_end));
355
356 mem_reserve(__pa(&_UserExceptionVector_text_start),
357 __pa(&_UserExceptionVector_text_end));
358
359 mem_reserve(__pa(&_DoubleExceptionVector_text_start),
360 __pa(&_DoubleExceptionVector_text_end));
361
362 #if XCHAL_EXCM_LEVEL >= 2
363 mem_reserve(__pa(&_Level2InterruptVector_text_start),
364 __pa(&_Level2InterruptVector_text_end));
365 #endif
366 #if XCHAL_EXCM_LEVEL >= 3
367 mem_reserve(__pa(&_Level3InterruptVector_text_start),
368 __pa(&_Level3InterruptVector_text_end));
369 #endif
370 #if XCHAL_EXCM_LEVEL >= 4
371 mem_reserve(__pa(&_Level4InterruptVector_text_start),
372 __pa(&_Level4InterruptVector_text_end));
373 #endif
374 #if XCHAL_EXCM_LEVEL >= 5
375 mem_reserve(__pa(&_Level5InterruptVector_text_start),
376 __pa(&_Level5InterruptVector_text_end));
377 #endif
378 #if XCHAL_EXCM_LEVEL >= 6
379 mem_reserve(__pa(&_Level6InterruptVector_text_start),
380 __pa(&_Level6InterruptVector_text_end));
381 #endif
382
383 #endif /* CONFIG_VECTORS_OFFSET */
384
385 #ifdef CONFIG_SMP
386 mem_reserve(__pa(&_SecondaryResetVector_text_start),
387 __pa(&_SecondaryResetVector_text_end));
388 #endif
389 parse_early_param();
390 bootmem_init();
391 kasan_init();
392 unflatten_and_copy_device_tree();
393
394 #ifdef CONFIG_SMP
395 smp_init_cpus();
396 #endif
397
398 paging_init();
399 zones_init();
400
401 #ifdef CONFIG_VT
402 # if defined(CONFIG_VGA_CONSOLE)
403 conswitchp = &vga_con;
404 # elif defined(CONFIG_DUMMY_CONSOLE)
405 conswitchp = &dummy_con;
406 # endif
407 #endif
408
409 #ifdef CONFIG_PCI
410 platform_pcibios_init();
411 #endif
412 }
413
414 static DEFINE_PER_CPU(struct cpu, cpu_data);
415
topology_init(void)416 static int __init topology_init(void)
417 {
418 int i;
419
420 for_each_possible_cpu(i) {
421 struct cpu *cpu = &per_cpu(cpu_data, i);
422 cpu->hotpluggable = !!i;
423 register_cpu(cpu, i);
424 }
425
426 return 0;
427 }
428 subsys_initcall(topology_init);
429
cpu_reset(void)430 void cpu_reset(void)
431 {
432 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
433 local_irq_disable();
434 /*
435 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
436 * be flushed.
437 * Way 4 is not currently used by linux.
438 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
439 * Way 5 shall be flushed and way 6 shall be set to identity mapping
440 * on MMUv3.
441 */
442 local_flush_tlb_all();
443 invalidate_page_directory();
444 #if XCHAL_HAVE_SPANNING_WAY
445 /* MMU v3 */
446 {
447 unsigned long vaddr = (unsigned long)cpu_reset;
448 unsigned long paddr = __pa(vaddr);
449 unsigned long tmpaddr = vaddr + SZ_512M;
450 unsigned long tmp0, tmp1, tmp2, tmp3;
451
452 /*
453 * Find a place for the temporary mapping. It must not be
454 * in the same 512MB region with vaddr or paddr, otherwise
455 * there may be multihit exception either on entry to the
456 * temporary mapping, or on entry to the identity mapping.
457 * (512MB is the biggest page size supported by TLB.)
458 */
459 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
460 tmpaddr += SZ_512M;
461
462 /* Invalidate mapping in the selected temporary area */
463 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
464 invalidate_itlb_entry(itlb_probe(tmpaddr));
465 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
466 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
467
468 /*
469 * Map two consecutive pages starting at the physical address
470 * of this function to the temporary mapping area.
471 */
472 write_itlb_entry(__pte((paddr & PAGE_MASK) |
473 _PAGE_HW_VALID |
474 _PAGE_HW_EXEC |
475 _PAGE_CA_BYPASS),
476 tmpaddr & PAGE_MASK);
477 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
478 _PAGE_HW_VALID |
479 _PAGE_HW_EXEC |
480 _PAGE_CA_BYPASS),
481 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
482
483 /* Reinitialize TLB */
484 __asm__ __volatile__ ("movi %0, 1f\n\t"
485 "movi %3, 2f\n\t"
486 "add %0, %0, %4\n\t"
487 "add %3, %3, %5\n\t"
488 "jx %0\n"
489 /*
490 * No literal, data or stack access
491 * below this point
492 */
493 "1:\n\t"
494 /* Initialize *tlbcfg */
495 "movi %0, 0\n\t"
496 "wsr %0, itlbcfg\n\t"
497 "wsr %0, dtlbcfg\n\t"
498 /* Invalidate TLB way 5 */
499 "movi %0, 4\n\t"
500 "movi %1, 5\n"
501 "1:\n\t"
502 "iitlb %1\n\t"
503 "idtlb %1\n\t"
504 "add %1, %1, %6\n\t"
505 "addi %0, %0, -1\n\t"
506 "bnez %0, 1b\n\t"
507 /* Initialize TLB way 6 */
508 "movi %0, 7\n\t"
509 "addi %1, %9, 3\n\t"
510 "addi %2, %9, 6\n"
511 "1:\n\t"
512 "witlb %1, %2\n\t"
513 "wdtlb %1, %2\n\t"
514 "add %1, %1, %7\n\t"
515 "add %2, %2, %7\n\t"
516 "addi %0, %0, -1\n\t"
517 "bnez %0, 1b\n\t"
518 "isync\n\t"
519 /* Jump to identity mapping */
520 "jx %3\n"
521 "2:\n\t"
522 /* Complete way 6 initialization */
523 "witlb %1, %2\n\t"
524 "wdtlb %1, %2\n\t"
525 /* Invalidate temporary mapping */
526 "sub %0, %9, %7\n\t"
527 "iitlb %0\n\t"
528 "add %0, %0, %8\n\t"
529 "iitlb %0"
530 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
531 "=&a"(tmp3)
532 : "a"(tmpaddr - vaddr),
533 "a"(paddr - vaddr),
534 "a"(SZ_128M), "a"(SZ_512M),
535 "a"(PAGE_SIZE),
536 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
537 : "memory");
538 }
539 #endif
540 #endif
541 __asm__ __volatile__ ("movi a2, 0\n\t"
542 "wsr a2, icountlevel\n\t"
543 "movi a2, 0\n\t"
544 "wsr a2, icount\n\t"
545 #if XCHAL_NUM_IBREAK > 0
546 "wsr a2, ibreakenable\n\t"
547 #endif
548 #if XCHAL_HAVE_LOOPS
549 "wsr a2, lcount\n\t"
550 #endif
551 "movi a2, 0x1f\n\t"
552 "wsr a2, ps\n\t"
553 "isync\n\t"
554 "jx %0\n\t"
555 :
556 : "a" (XCHAL_RESET_VECTOR_VADDR)
557 : "a2");
558 for (;;)
559 ;
560 }
561
machine_restart(char * cmd)562 void machine_restart(char * cmd)
563 {
564 platform_restart();
565 }
566
machine_halt(void)567 void machine_halt(void)
568 {
569 platform_halt();
570 while (1);
571 }
572
machine_power_off(void)573 void machine_power_off(void)
574 {
575 platform_power_off();
576 while (1);
577 }
578 #ifdef CONFIG_PROC_FS
579
580 /*
581 * Display some core information through /proc/cpuinfo.
582 */
583
584 static int
c_show(struct seq_file * f,void * slot)585 c_show(struct seq_file *f, void *slot)
586 {
587 /* high-level stuff */
588 seq_printf(f, "CPU count\t: %u\n"
589 "CPU list\t: %*pbl\n"
590 "vendor_id\t: Tensilica\n"
591 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
592 "core ID\t\t: " XCHAL_CORE_ID "\n"
593 "build ID\t: 0x%x\n"
594 "config ID\t: %08x:%08x\n"
595 "byte order\t: %s\n"
596 "cpu MHz\t\t: %lu.%02lu\n"
597 "bogomips\t: %lu.%02lu\n",
598 num_online_cpus(),
599 cpumask_pr_args(cpu_online_mask),
600 XCHAL_BUILD_UNIQUE_ID,
601 get_sr(SREG_EPC), get_sr(SREG_EXCSAVE),
602 XCHAL_HAVE_BE ? "big" : "little",
603 ccount_freq/1000000,
604 (ccount_freq/10000) % 100,
605 loops_per_jiffy/(500000/HZ),
606 (loops_per_jiffy/(5000/HZ)) % 100);
607 seq_puts(f, "flags\t\t: "
608 #if XCHAL_HAVE_NMI
609 "nmi "
610 #endif
611 #if XCHAL_HAVE_DEBUG
612 "debug "
613 # if XCHAL_HAVE_OCD
614 "ocd "
615 # endif
616 #endif
617 #if XCHAL_HAVE_DENSITY
618 "density "
619 #endif
620 #if XCHAL_HAVE_BOOLEANS
621 "boolean "
622 #endif
623 #if XCHAL_HAVE_LOOPS
624 "loop "
625 #endif
626 #if XCHAL_HAVE_NSA
627 "nsa "
628 #endif
629 #if XCHAL_HAVE_MINMAX
630 "minmax "
631 #endif
632 #if XCHAL_HAVE_SEXT
633 "sext "
634 #endif
635 #if XCHAL_HAVE_CLAMPS
636 "clamps "
637 #endif
638 #if XCHAL_HAVE_MAC16
639 "mac16 "
640 #endif
641 #if XCHAL_HAVE_MUL16
642 "mul16 "
643 #endif
644 #if XCHAL_HAVE_MUL32
645 "mul32 "
646 #endif
647 #if XCHAL_HAVE_MUL32_HIGH
648 "mul32h "
649 #endif
650 #if XCHAL_HAVE_FP
651 "fpu "
652 #endif
653 #if XCHAL_HAVE_S32C1I
654 "s32c1i "
655 #endif
656 "\n");
657
658 /* Registers. */
659 seq_printf(f,"physical aregs\t: %d\n"
660 "misc regs\t: %d\n"
661 "ibreak\t\t: %d\n"
662 "dbreak\t\t: %d\n",
663 XCHAL_NUM_AREGS,
664 XCHAL_NUM_MISC_REGS,
665 XCHAL_NUM_IBREAK,
666 XCHAL_NUM_DBREAK);
667
668
669 /* Interrupt. */
670 seq_printf(f,"num ints\t: %d\n"
671 "ext ints\t: %d\n"
672 "int levels\t: %d\n"
673 "timers\t\t: %d\n"
674 "debug level\t: %d\n",
675 XCHAL_NUM_INTERRUPTS,
676 XCHAL_NUM_EXTINTERRUPTS,
677 XCHAL_NUM_INTLEVELS,
678 XCHAL_NUM_TIMERS,
679 XCHAL_DEBUGLEVEL);
680
681 /* Cache */
682 seq_printf(f,"icache line size: %d\n"
683 "icache ways\t: %d\n"
684 "icache size\t: %d\n"
685 "icache flags\t: "
686 #if XCHAL_ICACHE_LINE_LOCKABLE
687 "lock "
688 #endif
689 "\n"
690 "dcache line size: %d\n"
691 "dcache ways\t: %d\n"
692 "dcache size\t: %d\n"
693 "dcache flags\t: "
694 #if XCHAL_DCACHE_IS_WRITEBACK
695 "writeback "
696 #endif
697 #if XCHAL_DCACHE_LINE_LOCKABLE
698 "lock "
699 #endif
700 "\n",
701 XCHAL_ICACHE_LINESIZE,
702 XCHAL_ICACHE_WAYS,
703 XCHAL_ICACHE_SIZE,
704 XCHAL_DCACHE_LINESIZE,
705 XCHAL_DCACHE_WAYS,
706 XCHAL_DCACHE_SIZE);
707
708 return 0;
709 }
710
711 /*
712 * We show only CPU #0 info.
713 */
714 static void *
c_start(struct seq_file * f,loff_t * pos)715 c_start(struct seq_file *f, loff_t *pos)
716 {
717 return (*pos == 0) ? (void *)1 : NULL;
718 }
719
720 static void *
c_next(struct seq_file * f,void * v,loff_t * pos)721 c_next(struct seq_file *f, void *v, loff_t *pos)
722 {
723 ++*pos;
724 return c_start(f, pos);
725 }
726
727 static void
c_stop(struct seq_file * f,void * v)728 c_stop(struct seq_file *f, void *v)
729 {
730 }
731
732 const struct seq_operations cpuinfo_op =
733 {
734 .start = c_start,
735 .next = c_next,
736 .stop = c_stop,
737 .show = c_show,
738 };
739
740 #endif /* CONFIG_PROC_FS */
741