1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_i2s.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of I2S LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_I2S I2S
47 * @brief I2S LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_I2S_H__
53 #define __GR55xx_LL_I2S_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined (I2S_M) || defined (I2S_S)
63
64 /** @defgroup LL_I2S_DRIVER_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup I2S_LL_ES_INIT I2S Exported init structure
70 * @{
71 */
72
73 /**
74 * @brief LL I2S init structures definition
75 */
76 typedef struct _ll_i2s_init_t {
77 uint32_t rxdata_size; /**< Specifies the I2S receive data size.
78 This parameter can be a value of @ref I2S_LL_EC_DATASIZE.
79 This feature can be modified afterwards using unitary function
80 @ref ll_i2s_set_rxsize(). */
81
82 uint32_t txdata_size; /**< Specifies the I2S transmit data size.
83 This parameter can be a value of @ref I2S_LL_EC_DATASIZE.
84 This feature can be modified afterwards using unitary function
85 @ref ll_i2s_set_txsize(). */
86
87 uint32_t rx_threshold; /**< Specifies the I2S receive FIFO threshold.
88 This parameter can be a value of @ref I2S_LL_EC_FIFO_THRESHOLD.
89 This feature can be modified afterwards using unitary function
90 @ref ll_i2s_set_rx_fifo_threshold(). */
91
92 uint32_t tx_threshold; /**< Specifies the I2S transmit FIFO threshold.
93 This parameter can be a value of @ref I2S_LL_EC_FIFO_THRESHOLD.
94 This feature can be modified afterwards using unitary function
95 @ref ll_i2s_set_tx_fifo_threshold(). */
96
97 uint32_t clock_source; /**< Specifies the source of the I2S clock.
98 This parameter can be a value of @ref I2S_LL_EC_CLOCK_SOURCE.
99 This feature can be modified afterwards using unitary function
100 @ref ll_i2s_set_clock_src(). */
101
102 uint32_t audio_freq; /**< Specifies the frequency selected for the I2S communication.
103 This feature can be modified afterwards using unitary function
104 @ref ll_i2s_set_clock_div(). */
105 } ll_i2s_init_t;
106
107 /** @} */
108
109 /** @} */
110
111 /**
112 * @defgroup I2S_LL_MACRO Defines
113 * @{
114 */
115
116 /* Exported constants --------------------------------------------------------*/
117 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
118 * @{
119 */
120
121 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
122 * @brief Flags definitions which can be used with LL_I2S_ReadReg function
123 * @{
124 */
125 #define LL_I2S_STATUS_TXFO I2S_INTSTAT_TXFO /**< TX FIFO write overflow flag */
126 #define LL_I2S_STATUS_TXFE I2S_INTSTAT_TXFE /**< TX FIFO threshold level is not reached flag */
127 #define LL_I2S_STATUS_RXFO I2S_INTSTAT_RXFO /**< RX FIFO receive overflow flag */
128 #define LL_I2S_STATUS_RXDA I2S_INTSTAT_RXDA /**< RX FIFO threshold level is reached flag */
129 /** @} */
130
131 /** @defgroup I2S_LL_EC_INTERRUPT Interrupt Defines
132 * @brief Interrupt definitions which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
133 * @{
134 */
135 #define LL_I2S_INT_TXFO I2S_INTMASK_TXFO /**< TX FIFO write overflow interrupt */
136 #define LL_I2S_INT_TXFE I2S_INTMASK_TXFE /**< TX FIFO threshold level is not reached interrupt */
137 #define LL_I2S_INT_RXFO I2S_INTMASK_RXFO /**< RX FIFO receive overflow interrupt */
138 #define LL_I2S_INT_RXDA I2S_INTMASK_RXDA /**< RX FIFO threshold level is reached interrupt */
139 /** @} */
140
141 /** @defgroup I2S_LL_EC_CLOCK_SOURCE I2S Clock Source
142 * @{
143 */
144 #define LL_I2S_CLOCK_SRC_96M (0x00000000UL) /**< I2S clock source select: 96M */
145 #define LL_I2S_CLOCK_SRC_32M (1UL << 18) /**< I2S clock source select: 32M */
146 /** @} */
147
148 /** @defgroup I2S_LL_EC_DATASIZE Transfer Data width
149 * @{
150 */
151 #define LL_I2S_DATASIZE_IGNORE (0x00000000UL) /**< Data size for I2S transfer: 32 bits */
152 #define LL_I2S_DATASIZE_12BIT (1UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 12 bits */
153 #define LL_I2S_DATASIZE_16BIT (2UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 16 bits */
154 #define LL_I2S_DATASIZE_20BIT (3UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 20 bits */
155 #define LL_I2S_DATASIZE_24BIT (4UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 24 bits */
156 #define LL_I2S_DATASIZE_32BIT (5UL << I2S_RXSIZE_WLEN_Pos) /**< Data size for I2S transfer: 32 bits */
157 /** @} */
158
159 /** @defgroup I2S_LL_EC_TRANSFER_MODE Transfer Mode
160 * @{
161 */
162 #define LL_I2S_SIMPLEX_TX (1UL) /**< Simplex TX mode. */
163 #define LL_I2S_SIMPLEX_RX (2UL) /**< Simplex RX mode. */
164 #define LL_I2S_FULL_DUPLEX (3UL) /**< Full-Duplex mode. */
165 /** @} */
166
167 /** @defgroup I2S_LL_EC_FIFO_THRESHOLD FIFO Threshold
168 * @{
169 */
170 #define LL_I2S_THRESHOLD_1FIFO (0x00000000UL) /**< Trigger level for FIFO: 1 depth. */
171 #define LL_I2S_THRESHOLD_2FIFO (1UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 2 depth. */
172 #define LL_I2S_THRESHOLD_3FIFO (2UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 3 depth. */
173 #define LL_I2S_THRESHOLD_4FIFO (3UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 4 depth. */
174 #define LL_I2S_THRESHOLD_5FIFO (4UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 5 depth. */
175 #define LL_I2S_THRESHOLD_6FIFO (5UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 6 depth. */
176 #define LL_I2S_THRESHOLD_7FIFO (6UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 7 depth. */
177 #define LL_I2S_THRESHOLD_8FIFO (7UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 8 depth. */
178 #define LL_I2S_THRESHOLD_9FIFO (8UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 9 depth. */
179 #define LL_I2S_THRESHOLD_10FIFO (9UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 10 depth. */
180 #define LL_I2S_THRESHOLD_11FIFO (10UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 11 depth. */
181 #define LL_I2S_THRESHOLD_12FIFO (11UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 12 depth. */
182 #define LL_I2S_THRESHOLD_13FIFO (12UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 13 depth. */
183 #define LL_I2S_THRESHOLD_14FIFO (13UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 14 depth. */
184 #define LL_I2S_THRESHOLD_15FIFO (14UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 15 depth. */
185 #define LL_I2S_THRESHOLD_16FIFO (15UL << I2S_RXFIFO_TL_Pos) /**< Trigger level for FIFO: 16 depth. */
186 /** @} */
187
188 /** @defgroup I2S_LL_EC_WS_CYCLES Word Select Line Cycles
189 * @{
190 */
191 #define LL_I2S_WS_CYCLES_16 (0x00000000UL) /**< 16 SCLK cycles in word select line. */
192 #define LL_I2S_WS_CYCLES_24 (0x1UL << I2S_CLKCONFIG_WSS_Pos) /**< 24 SCLK cycles in word select line. */
193 #define LL_I2S_WS_CYCLES_32 (0x2UL << I2S_CLKCONFIG_WSS_Pos) /**< 32 SCLK cycles in word select line. */
194 /** @} */
195
196 /** @defgroup I2S_LL_EC_SCLK_GATE SCLK Gate
197 * @{
198 */
199 #define LL_I2S_SCLKG_NONE (0x00000000UL) /**< Clock gating is disabled. */
200 #define LL_I2S_SCLKG_CYCLES_12 (0x1UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 12 sclk cycles. */
201 #define LL_I2S_SCLKG_CYCLES_16 (0x2UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 16 sclk cycles. */
202 #define LL_I2S_SCLKG_CYCLES_20 (0x3UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 20 sclk cycles. */
203 #define LL_I2S_SCLKG_CYCLES_24 (0x4UL << I2S_CLKCONFIG_SCLKG_Pos) /**< Gating after 24 sclk cycles. */
204 /** @} */
205
206 /** @defgroup I2S_LL_EC_RESOLUTION RX/TX resolution of one channel
207 * @{
208 */
209 #define LL_I2S_RESOLUTION_12BIT (0UL) /**< 12 bits resolution. */
210 #define LL_I2S_RESOLUTION_16BIT (1UL) /**< 16 bits resolution. */
211 #define LL_I2S_RESOLUTION_20BIT (2UL) /**< 20 bits resolution. */
212 #define LL_I2S_RESOLUTION_24BIT (3UL) /**< 24 bits resolution. */
213 #define LL_I2S_RESOLUTION_32BIT (4UL) /**< 32 bits resolution. */
214 /** @} */
215
216 /** @defgroup I2S_LL_EC_CHANNELS the number of RX/TX channels
217 * @{
218 */
219 #define LL_I2S_CHANNEL_NUM_1 (0UL) /**< 1 channel. */
220 #define LL_I2S_CHANNEL_NUM_2 (1UL) /**< 2 channels. */
221 #define LL_I2S_CHANNEL_NUM_3 (2UL) /**< 3 channels. */
222 #define LL_I2S_CHANNEL_NUM_4 (3UL) /**< 4 channels. */
223 /** @} */
224
225 /** @defgroup I2S_LL_EC_FIFO_DEPTH RX/TX FIFO depth
226 * @{
227 */
228 #define LL_I2S_FIFO_DEPTH_2 (0UL) /**< FIFO depth is 2 . */
229 #define LL_I2S_FIFO_DEPTH_4 (1UL) /**< FIFO depth is 4 . */
230 #define LL_I2S_FIFO_DEPTH_8 (2UL) /**< FIFO depth is 8 . */
231 #define LL_I2S_FIFO_DEPTH_16 (3UL) /**< FIFO depth is 16. */
232 /** @} */
233
234 /** @defgroup I2S_LL_EC_APB_WIDTH APB data width
235 * @{
236 */
237 #define LL_I2S_APB_WIDTH_8BIT (0UL) /**< 8 bits APB data width. */
238 #define LL_I2S_APB_WIDTH_16BIT (1UL) /**< 16 bits APB data width. */
239 #define LL_I2S_APB_WIDTH_32BIT (2UL) /**< 32 bits APB data width. */
240 /** @} */
241
242 /** @} */
243
244 /** @defgroup I2S_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
245 * @{
246 */
247
248 /**
249 * @brief LL I2S InitStrcut default configuartion
250 */
251 #define LL_I2S_DEFAULT_CONFIG \
252 { \
253 .rxdata_size = LL_I2S_DATASIZE_16BIT, \
254 .txdata_size = LL_I2S_DATASIZE_16BIT, \
255 .rx_threshold = LL_I2S_THRESHOLD_1FIFO, \
256 .tx_threshold = LL_I2S_THRESHOLD_9FIFO, \
257 .clock_source = LL_I2S_CLOCK_SRC_32M, \
258 .audio_freq = 48000 \
259 }
260
261 /** @} */
262
263 /* Exported macro ------------------------------------------------------------*/
264 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
265 * @{
266 */
267
268 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
269 * @{
270 */
271
272 /**
273 * @brief Write a value in I2S register
274 * @param __instance__ I2S instance
275 * @param __REG__ Register to be written
276 * @param __VALUE__ Value to be written in the register
277 * @retval None
278 */
279 #define LL_I2S_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
280
281 /**
282 * @brief Read a value in I2S register
283 * @param __instance__ I2S instance
284 * @param __REG__ Register to be read
285 * @retval Register value
286 */
287 #define LL_I2S_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
288
289 /** @} */
290
291 /** @} */
292 /** @} */
293
294 /* Exported functions --------------------------------------------------------*/
295 /** @defgroup I2S_LL_DRIVER_FUNCTIONS Functions
296 * @{
297 */
298
299 /** @defgroup I2S_LL_EF_Configuration Configuration functions
300 * @{
301 */
302
303 /**
304 * @brief Enable I2S
305 *
306 * Register|BitsName
307 * --------|--------
308 * ENABLE | EN
309 *
310 * @param I2Sx I2S instance
311 * @retval None
312 */
ll_i2s_enable(i2s_regs_t * I2Sx)313 __STATIC_INLINE void ll_i2s_enable(i2s_regs_t *I2Sx)
314 {
315 SET_BITS(I2Sx->ENABLE, I2S_ENABLE_EN);
316 }
317
318 /**
319 * @brief Disable I2S
320 *
321 * Register|BitsName
322 * --------|--------
323 * ENABLE | EN
324 *
325 * @param I2Sx I2S instance
326 * @retval None
327 */
ll_i2s_disable(i2s_regs_t * I2Sx)328 __STATIC_INLINE void ll_i2s_disable(i2s_regs_t *I2Sx)
329 {
330 CLEAR_BITS(I2Sx->ENABLE, I2S_ENABLE_EN);
331 }
332
333 /**
334 * @brief Check if I2S is enabled
335 *
336 * Register|BitsName
337 * --------|--------
338 * ENABLE | EN
339 *
340 * @param I2Sx I2S instance
341 * @retval State of bit (1 or 0).
342 */
ll_i2s_is_enabled(i2s_regs_t * I2Sx)343 __STATIC_INLINE uint32_t ll_i2s_is_enabled(i2s_regs_t *I2Sx)
344 {
345 return (READ_BITS(I2Sx->ENABLE, I2S_ENABLE_EN) == (I2S_ENABLE_EN));
346 }
347
348 /**
349 * @brief Enable I2S RX block
350 *
351 * Register|BitsName
352 * --------|--------
353 * RBEN | EN
354 *
355 * @param I2Sx I2S instance
356 * @retval None
357 */
ll_i2s_enable_rxblock(i2s_regs_t * I2Sx)358 __STATIC_INLINE void ll_i2s_enable_rxblock(i2s_regs_t *I2Sx)
359 {
360 SET_BITS(I2Sx->RBEN, I2S_RBEN_EN);
361 }
362
363 /**
364 * @brief Disable I2S RX block
365 *
366 * Register|BitsName
367 * --------|--------
368 * RBEN | EN
369 *
370 * @param I2Sx I2S instance
371 * @retval None
372 */
ll_i2s_disable_rxblock(i2s_regs_t * I2Sx)373 __STATIC_INLINE void ll_i2s_disable_rxblock(i2s_regs_t *I2Sx)
374 {
375 CLEAR_BITS(I2Sx->RBEN, I2S_RBEN_EN);
376 }
377
378 /**
379 * @brief Check if I2S RX block is enabled
380 *
381 * Register|BitsName
382 * --------|--------
383 * RBEN | EN
384 *
385 * @param I2Sx I2S instance
386 * @retval State of bit (1 or 0).
387 */
ll_i2s_is_enabled_rxblock(i2s_regs_t * I2Sx)388 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rxblock(i2s_regs_t *I2Sx)
389 {
390 return (READ_BITS(I2Sx->RBEN, I2S_RBEN_EN) == (I2S_RBEN_EN));
391 }
392
393 /**
394 * @brief Enable I2S TX block
395 *
396 * Register|BitsName
397 * --------|--------
398 * TBEN | EN
399 *
400 * @param I2Sx I2S instance
401 * @retval None
402 */
ll_i2s_enable_txblock(i2s_regs_t * I2Sx)403 __STATIC_INLINE void ll_i2s_enable_txblock(i2s_regs_t *I2Sx)
404 {
405 SET_BITS(I2Sx->TBEN, I2S_TBEN_EN);
406 }
407
408 /**
409 * @brief Disable I2S TX block
410 *
411 * Register|BitsName
412 * --------|--------
413 * TBEN | EN
414 *
415 * @param I2Sx I2S instance
416 * @retval None
417 */
ll_i2s_disable_txblock(i2s_regs_t * I2Sx)418 __STATIC_INLINE void ll_i2s_disable_txblock(i2s_regs_t *I2Sx)
419 {
420 CLEAR_BITS(I2Sx->TBEN, I2S_TBEN_EN);
421 }
422
423 /**
424 * @brief Check if I2S TX block is enabled
425 *
426 * Register|BitsName
427 * --------|--------
428 * TBEN | EN
429 *
430 * @param I2Sx I2S instance
431 * @retval State of bit (1 or 0).
432 */
ll_i2s_is_enabled_txblock(i2s_regs_t * I2Sx)433 __STATIC_INLINE uint32_t ll_i2s_is_enabled_txblock(i2s_regs_t *I2Sx)
434 {
435 return (READ_BITS(I2Sx->TBEN, I2S_TBEN_EN) == (I2S_TBEN_EN));
436 }
437
438 /**
439 * @brief Enable I2S clock
440 *
441 * Register|BitsName
442 * --------|--------
443 * CLKEN | EN
444 *
445 * @param I2Sx I2S instance
446 * @retval None
447 */
ll_i2s_enable_clock(i2s_regs_t * I2Sx)448 __STATIC_INLINE void ll_i2s_enable_clock(i2s_regs_t *I2Sx)
449 {
450 SET_BITS(I2Sx->CLKEN, I2S_CLKEN_EN);
451 }
452
453 /**
454 * @brief Disable I2S clock
455 *
456 * Register|BitsName
457 * --------|--------
458 * CLKEN | EN
459 *
460 * @param I2Sx I2S instance
461 * @retval None
462 */
ll_i2s_disable_clock(i2s_regs_t * I2Sx)463 __STATIC_INLINE void ll_i2s_disable_clock(i2s_regs_t *I2Sx)
464 {
465 CLEAR_BITS(I2Sx->CLKEN, I2S_CLKEN_EN);
466 }
467
468 /**
469 * @brief Check if I2S clock is enabled
470 *
471 * Register|BitsName
472 * --------|--------
473 * CLKEN | EN
474 *
475 * @param I2Sx I2S instance
476 * @retval State of bit (1 or 0).
477 */
ll_i2s_is_enabled_clock(i2s_regs_t * I2Sx)478 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock(i2s_regs_t *I2Sx)
479 {
480 return (READ_BITS(I2Sx->CLKEN, I2S_CLKEN_EN) == (I2S_CLKEN_EN));
481 }
482
483 /**
484 * @brief Set word select line cycles for left or right sample
485 * @note This bit should be written only when I2S is disabled (I2S_EN = 0) for correct operation.
486 *
487 * Register|BitsName
488 * --------|--------
489 * CLKCONFIG | WSS
490 *
491 * @param I2Sx I2S instance
492 * @param cycles This parameter can be one of the following values:
493 * @arg @ref LL_I2S_WS_CYCLES_16
494 * @arg @ref LL_I2S_WS_CYCLES_24
495 * @arg @ref LL_I2S_WS_CYCLES_32
496 * @retval None
497 */
ll_i2s_set_wss(i2s_regs_t * I2Sx,uint32_t cycles)498 __STATIC_INLINE void ll_i2s_set_wss(i2s_regs_t *I2Sx, uint32_t cycles)
499 {
500 MODIFY_REG(I2Sx->CLKCONFIG, I2S_CLKCONFIG_WSS, cycles);
501 }
502
503 /**
504 * @brief Get word select line cycles for left or right sample
505 *
506 * Register|BitsName
507 * --------|--------
508 * CLKCONFIG | WSS
509 *
510 * @param I2Sx I2S instance
511 * @retval Returned Value can be one of the following values:
512 * @arg @ref LL_I2S_WS_CYCLES_16
513 * @arg @ref LL_I2S_WS_CYCLES_24
514 * @arg @ref LL_I2S_WS_CYCLES_32
515 */
ll_i2s_get_wss(i2s_regs_t * I2Sx)516 __STATIC_INLINE uint32_t ll_i2s_get_wss(i2s_regs_t *I2Sx)
517 {
518 return (uint32_t)(READ_BITS(I2Sx->CLKCONFIG, I2S_CLKCONFIG_WSS));
519 }
520
521 /**
522 * @brief Set the gating of sclk
523 *
524 * Register|BitsName
525 * --------|--------
526 * CLKCONFIG | SCLKG
527 *
528 * @param I2Sx I2S instance
529 * @param cycles This parameter can be one of the following values:
530 * @arg @ref LL_I2S_SCLKG_NONE
531 * @arg @ref LL_I2S_SCLKG_CYCLES_12
532 * @arg @ref LL_I2S_SCLKG_CYCLES_16
533 * @arg @ref LL_I2S_SCLKG_CYCLES_20
534 * @arg @ref LL_I2S_SCLKG_CYCLES_24
535 * @retval None
536 */
ll_i2s_set_sclkg(i2s_regs_t * I2Sx,uint32_t cycles)537 __STATIC_INLINE void ll_i2s_set_sclkg(i2s_regs_t *I2Sx, uint32_t cycles)
538 {
539 MODIFY_REG(I2Sx->CLKCONFIG, I2S_CLKCONFIG_SCLKG, cycles);
540 }
541
542 /**
543 * @brief Get the gating of sclk
544 *
545 * Register|BitsName
546 * --------|--------
547 * CLKCONFIG | SCLKG
548 *
549 * @param I2Sx I2S instance
550 * @retval Returned Value can be one of the following values:
551 * @arg @ref LL_I2S_SCLKG_NONE
552 * @arg @ref LL_I2S_SCLKG_CYCLES_12
553 * @arg @ref LL_I2S_SCLKG_CYCLES_16
554 * @arg @ref LL_I2S_SCLKG_CYCLES_20
555 * @arg @ref LL_I2S_SCLKG_CYCLES_24
556 */
ll_i2s_get_sclkg(i2s_regs_t * I2Sx)557 __STATIC_INLINE uint32_t ll_i2s_get_sclkg(i2s_regs_t *I2Sx)
558 {
559 return (uint32_t)(READ_BITS(I2Sx->CLKCONFIG, I2S_CLKCONFIG_SCLKG));
560 }
561
562 /**
563 * @brief Clear I2S RX FIFO in all channels
564 *
565 * Register|BitsName
566 * --------|--------
567 * RXFIFO_RST | RST
568 *
569 * @param I2Sx I2S instance
570 * @retval None
571 */
ll_i2s_clr_rxfifo_all(i2s_regs_t * I2Sx)572 __STATIC_INLINE void ll_i2s_clr_rxfifo_all(i2s_regs_t *I2Sx)
573 {
574 WRITE_REG(I2Sx->RXFIFO_RST, I2S_RXFIFO_RST);
575 }
576
577 /**
578 * @brief Clear I2S TX FIFO in all channels
579 *
580 * Register|BitsName
581 * --------|--------
582 * TXFIFO_RST | RST
583 *
584 * @param I2Sx I2S instance
585 * @retval None
586 */
ll_i2s_clr_txfifo_all(i2s_regs_t * I2Sx)587 __STATIC_INLINE void ll_i2s_clr_txfifo_all(i2s_regs_t *I2Sx)
588 {
589 WRITE_REG(I2Sx->TXFIFO_RST, I2S_TXFIFO_RST);
590 }
591
592 /**
593 * @brief Set I2S clock divider
594 *
595 * Register|BitsName
596 * --------|--------
597 * I2S_CLK_CFG | DIV
598 *
599 * @param div This parameter can between: 0 ~ 0xFFF
600 * @retval None
601 */
ll_i2s_set_clock_div(uint32_t div)602 __STATIC_INLINE void ll_i2s_set_clock_div(uint32_t div)
603 {
604 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT, div);
605 }
606
607 /**
608 * @brief Get I2S clock divider
609 *
610 * Register|BitsName
611 * --------|--------
612 * I2S_CLK_CFG | DIV
613 *
614 * @retval Returned Value can between: 0 ~ 0xFFF
615 */
ll_i2s_get_clock_div(void)616 __STATIC_INLINE uint32_t ll_i2s_get_clock_div(void)
617 {
618 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_DIV_CNT));
619 }
620
621 /**
622 * @brief Enable I2S clock divider
623 *
624 * Register|BitsName
625 * --------|--------
626 * I2S_CLK_CFG | DIV_EN
627 *
628 * @retval None
629 */
ll_i2s_enable_clock_div(void)630 __STATIC_INLINE void ll_i2s_enable_clock_div(void)
631 {
632 SET_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
633 }
634
635 /**
636 * @brief Disable I2S clock divider
637 *
638 * Register|BitsName
639 * --------|--------
640 * I2S_CLK_CFG | DIV_EN
641 *
642 * @retval None
643 */
ll_i2s_disable_clock_div(void)644 __STATIC_INLINE void ll_i2s_disable_clock_div(void)
645 {
646 CLEAR_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN);
647 }
648
649 /**
650 * @brief Check if I2S clock divider is enabled
651 *
652 * Register|BitsName
653 * --------|--------
654 * I2S_CLK_CFG | DIV_EN
655 *
656 * @retval State of bit (1 or 0).
657 */
ll_i2s_is_enabled_clock_div(void)658 __STATIC_INLINE uint32_t ll_i2s_is_enabled_clock_div(void)
659 {
660 return (READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN) == (MCU_SUB_I2S_CLK_CFG_CLK_DIV_EN));
661 }
662
663 /**
664 * @brief Set I2S clock source
665 *
666 * Register|BitsName
667 * --------|--------
668 * I2S_CLK_CFG | SRC
669 *
670 * @param src This parameter can be one of the following values:
671 * @arg @ref LL_I2S_CLOCK_SRC_96M
672 * @arg @ref LL_I2S_CLOCK_SRC_32M
673 * @retval None
674 */
ll_i2s_set_clock_src(uint32_t src)675 __STATIC_INLINE void ll_i2s_set_clock_src(uint32_t src)
676 {
677 MODIFY_REG(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL, src);
678 }
679
680 /**
681 * @brief Get I2S clock source
682 *
683 * Register|BitsName
684 * --------|--------
685 * I2S_CLK_CFG | SRC
686 *
687 * @retval Returned Value can be one of the following values:
688 * @arg @ref LL_I2S_CLOCK_SRC_96M
689 * @arg @ref LL_I2S_CLOCK_SRC_32M
690 */
ll_i2s_get_clock_src(void)691 __STATIC_INLINE uint32_t ll_i2s_get_clock_src(void)
692 {
693 return (uint32_t)(READ_BITS(MCU_SUB->I2S_CLK_CFG, MCU_SUB_I2S_CLK_CFG_SRC_CLK_SEL));
694 }
695
696 /** @} */
697
698 /** @defgroup I2S_LL_EF_Channel Channel Configuration functions
699 * @{
700 */
701
702 /**
703 * @brief Read one data from left RX FIFO in a channel
704 *
705 * Register|BitsName
706 * --------|--------
707 * DATA_L | DATA
708 *
709 * @param I2Sx I2S instance
710 * @param channel The special channel: 0 ~ 3
711 * @retval None
712 */
ll_i2s_receive_ldata(i2s_regs_t * I2Sx,uint8_t channel)713 __STATIC_INLINE uint32_t ll_i2s_receive_ldata(i2s_regs_t *I2Sx, uint8_t channel)
714 {
715 return (uint32_t)(READ_REG(I2Sx->I2S_CHANNEL[channel].DATA_L));
716 }
717
718 /**
719 * @brief Read one data from right RX FIFO in a channel
720 *
721 * Register|BitsName
722 * --------|--------
723 * DATA_R | DATA
724 *
725 * @param I2Sx I2S instance
726 * @param channel The special channel: 0 ~ 3
727 * @retval None
728 */
ll_i2s_receive_rdata(i2s_regs_t * I2Sx,uint8_t channel)729 __STATIC_INLINE uint32_t ll_i2s_receive_rdata(i2s_regs_t *I2Sx, uint8_t channel)
730 {
731 return (uint32_t)(READ_REG(I2Sx->I2S_CHANNEL[channel].DATA_R));
732 }
733
734 /**
735 * @brief Write one data to left TX FIFO in a channel
736 *
737 * Register|BitsName
738 * --------|--------
739 * DATA_L | DATA
740 *
741 * @param I2Sx I2S instance
742 * @param channel The special channel: 0 ~ 3
743 * @param data The data to send
744 * @retval None
745 */
ll_i2s_transmit_ldata(i2s_regs_t * I2Sx,uint8_t channel,uint32_t data)746 __STATIC_INLINE void ll_i2s_transmit_ldata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
747 {
748 WRITE_REG(I2Sx->I2S_CHANNEL[channel].DATA_L, data);
749 }
750
751 /**
752 * @brief Write one data to right TX FIFO in a channel
753 *
754 * Register|BitsName
755 * --------|--------
756 * DATA_R | DATA
757 *
758 * @param I2Sx I2S instance
759 * @param channel The special channel: 0 ~ 3
760 * @param data The data to send
761 * @retval None
762 */
ll_i2s_transmit_rdata(i2s_regs_t * I2Sx,uint8_t channel,uint32_t data)763 __STATIC_INLINE void ll_i2s_transmit_rdata(i2s_regs_t *I2Sx, uint8_t channel, uint32_t data)
764 {
765 WRITE_REG(I2Sx->I2S_CHANNEL[channel].DATA_R, data);
766 }
767
768 /**
769 * @brief Enable RX in a channel
770 *
771 * Register|BitsName
772 * --------|--------
773 * RXEN | EN
774 *
775 * @param I2Sx I2S instance
776 * @param channel The special channel: 0 ~ 3
777 * @retval None
778 */
ll_i2s_enable_rx(i2s_regs_t * I2Sx,uint8_t channel)779 __STATIC_INLINE void ll_i2s_enable_rx(i2s_regs_t *I2Sx, uint8_t channel)
780 {
781 SET_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN);
782 }
783
784 /**
785 * @brief Disable RX in a channel
786 *
787 * Register|BitsName
788 * --------|--------
789 * RXEN | EN
790 *
791 * @param I2Sx I2S instance
792 * @param channel The special channel: 0 ~ 3
793 * @retval None
794 */
ll_i2s_disable_rx(i2s_regs_t * I2Sx,uint8_t channel)795 __STATIC_INLINE void ll_i2s_disable_rx(i2s_regs_t *I2Sx, uint8_t channel)
796 {
797 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN);
798 }
799
800 /**
801 * @brief Check if RX in a channel is enabled
802 *
803 * Register|BitsName
804 * --------|--------
805 * RXEN | EN
806 *
807 * @param I2Sx I2S instance
808 * @param channel The special channel: 0 ~ 3
809 * @retval State of bit (1 or 0).
810 */
ll_i2s_is_enabled_rx(i2s_regs_t * I2Sx,uint8_t channel)811 __STATIC_INLINE uint32_t ll_i2s_is_enabled_rx(i2s_regs_t *I2Sx, uint8_t channel)
812 {
813 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].RXEN, I2S_RXEN_EN) != (I2S_RXEN_EN));
814 }
815
816 /**
817 * @brief Enable TX in a channel
818 *
819 * Register|BitsName
820 * --------|--------
821 * TXEN | EN
822 *
823 * @param I2Sx I2S instance
824 * @param channel The special channel: 0 ~ 3
825 * @retval None
826 */
ll_i2s_enable_tx(i2s_regs_t * I2Sx,uint8_t channel)827 __STATIC_INLINE void ll_i2s_enable_tx(i2s_regs_t *I2Sx, uint8_t channel)
828 {
829 SET_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN);
830 }
831
832 /**
833 * @brief Disable TX in a channel
834 *
835 * Register|BitsName
836 * --------|--------
837 * TXEN | EN
838 *
839 * @param I2Sx I2S instance
840 * @param channel The special channel: 0 ~ 3
841 * @retval None
842 */
ll_i2s_disable_tx(i2s_regs_t * I2Sx,uint8_t channel)843 __STATIC_INLINE void ll_i2s_disable_tx(i2s_regs_t *I2Sx, uint8_t channel)
844 {
845 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN);
846 }
847
848 /**
849 * @brief Check if TX in a channel is enabled
850 *
851 * Register|BitsName
852 * --------|--------
853 * TXEN | EN
854 *
855 * @param I2Sx I2S instance
856 * @param channel The special channel: 0 ~ 3
857 * @retval State of bit (1 or 0).
858 */
ll_i2s_is_enabled_tx(i2s_regs_t * I2Sx,uint8_t channel)859 __STATIC_INLINE uint32_t ll_i2s_is_enabled_tx(i2s_regs_t *I2Sx, uint8_t channel)
860 {
861 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].TXEN, I2S_TXEN_EN) != (I2S_TXEN_EN));
862 }
863
864 /**
865 * @brief Set receive data width in a channel
866 * @note These bits should not be changed when channel is enabled.
867 *
868 * Register|BitsName
869 * --------|--------
870 * RXSIZE | WLEN
871 *
872 * @param I2Sx I2S instance
873 * @param channel The special channel: 0 ~ 3
874 * @param size This parameter can be one of the following values:
875 * @arg @ref LL_I2S_DATASIZE_IGNORE
876 * @arg @ref LL_I2S_DATASIZE_12BIT
877 * @arg @ref LL_I2S_DATASIZE_16BIT
878 * @arg @ref LL_I2S_DATASIZE_20BIT
879 * @arg @ref LL_I2S_DATASIZE_24BIT
880 * @arg @ref LL_I2S_DATASIZE_32BIT
881 * @retval None
882 */
ll_i2s_set_rxsize(i2s_regs_t * I2Sx,uint8_t channel,uint32_t size)883 __STATIC_INLINE void ll_i2s_set_rxsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
884 {
885 MODIFY_REG(I2Sx->I2S_CHANNEL[channel].RXSIZE, I2S_RXSIZE_WLEN, size);
886 }
887
888 /**
889 * @brief Get receive data width in a channel
890 *
891 * Register|BitsName
892 * --------|--------
893 * RXSIZE | WLEN
894 *
895 * @param I2Sx I2S instance
896 * @param channel The special channel: 0 ~ 3
897 * @retval Returned Value can be one of the following values:
898 * @arg @ref LL_I2S_DATASIZE_IGNORE
899 * @arg @ref LL_I2S_DATASIZE_12BIT
900 * @arg @ref LL_I2S_DATASIZE_16BIT
901 * @arg @ref LL_I2S_DATASIZE_20BIT
902 * @arg @ref LL_I2S_DATASIZE_24BIT
903 * @arg @ref LL_I2S_DATASIZE_32BIT
904 */
ll_i2s_get_rxsize(i2s_regs_t * I2Sx,uint8_t channel)905 __STATIC_INLINE uint32_t ll_i2s_get_rxsize(i2s_regs_t *I2Sx, uint8_t channel)
906 {
907 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].RXSIZE, I2S_RXSIZE_WLEN));
908 }
909
910 /**
911 * @brief Set transmit data width in a channel
912 * @note These bits should not be changed when channel is enabled.
913 *
914 * Register|BitsName
915 * --------|--------
916 * TXSIZE | WLEN
917 *
918 * @param I2Sx I2S instance
919 * @param channel The special channel: 0 ~ 3
920 * @param size This parameter can be one of the following values:
921 * @arg @ref LL_I2S_DATASIZE_IGNORE
922 * @arg @ref LL_I2S_DATASIZE_12BIT
923 * @arg @ref LL_I2S_DATASIZE_16BIT
924 * @arg @ref LL_I2S_DATASIZE_20BIT
925 * @arg @ref LL_I2S_DATASIZE_24BIT
926 * @arg @ref LL_I2S_DATASIZE_32BIT
927 * @retval None
928 */
ll_i2s_set_txsize(i2s_regs_t * I2Sx,uint8_t channel,uint32_t size)929 __STATIC_INLINE void ll_i2s_set_txsize(i2s_regs_t *I2Sx, uint8_t channel, uint32_t size)
930 {
931 MODIFY_REG(I2Sx->I2S_CHANNEL[channel].TXSIZE, I2S_TXSIZE_WLEN, size);
932 }
933
934 /**
935 * @brief Get transmit data width in a channel
936 *
937 * Register|BitsName
938 * --------|--------
939 * TXSIZE | WLEN
940 *
941 * @param I2Sx I2S instance
942 * @param channel The special channel: 0 ~ 3
943 * @retval Returned Value can be one of the following values:
944 * @arg @ref LL_I2S_DATASIZE_IGNORE
945 * @arg @ref LL_I2S_DATASIZE_12BIT
946 * @arg @ref LL_I2S_DATASIZE_16BIT
947 * @arg @ref LL_I2S_DATASIZE_20BIT
948 * @arg @ref LL_I2S_DATASIZE_24BIT
949 * @arg @ref LL_I2S_DATASIZE_32BIT
950 */
ll_i2s_get_txsize(i2s_regs_t * I2Sx,uint8_t channel)951 __STATIC_INLINE uint32_t ll_i2s_get_txsize(i2s_regs_t *I2Sx, uint8_t channel)
952 {
953 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].TXSIZE, I2S_TXSIZE_WLEN));
954 }
955
956 /**
957 * @brief Get interrupt flag in a channel
958 *
959 * Register|BitsName
960 * --------|--------
961 * INTSTAT | TXFO
962 * INTSTAT | TXFE
963 * INTSTAT | RXFO
964 * INTSTAT | RXDA
965 *
966 * @param I2Sx I2S instance
967 * @param channel The special channel: 0 ~ 3
968 * @retval Returned Value can be one or more of the following values:
969 * @arg @ref LL_I2S_STATUS_TXFO
970 * @arg @ref LL_I2S_STATUS_TXFE
971 * @arg @ref LL_I2S_STATUS_RXFO
972 * @arg @ref LL_I2S_STATUS_RXDA
973 */
ll_i2s_get_it_flag(i2s_regs_t * I2Sx,uint8_t channel)974 __STATIC_INLINE uint32_t ll_i2s_get_it_flag(i2s_regs_t *I2Sx, uint8_t channel)
975 {
976 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].INTSTAT, I2S_INTSTAT_TXFO | I2S_INTSTAT_TXFE | \
977 I2S_INTSTAT_RXFO | I2S_INTSTAT_RXDA));
978 }
979
980 /**
981 * @brief Check interrupt flag in a channel
982 *
983 * Register|BitsName
984 * --------|--------
985 * INTSTAT | TXFO
986 * INTSTAT | TXFE
987 * INTSTAT | RXFO
988 * INTSTAT | RXDA
989 *
990 * @param I2Sx I2S instance
991 * @param channel The special channel: 0 ~ 3
992 * @retval flag This parameter can be one or more of the following values:
993 * @arg @ref LL_I2S_STATUS_TXFO
994 * @arg @ref LL_I2S_STATUS_TXFE
995 * @arg @ref LL_I2S_STATUS_RXFO
996 * @arg @ref LL_I2S_STATUS_RXDA
997 * @retval State of bit (1 or 0).
998 */
ll_i2s_is_active_it_flag(i2s_regs_t * I2Sx,uint8_t channel,uint32_t flag)999 __STATIC_INLINE uint32_t ll_i2s_is_active_it_flag(i2s_regs_t *I2Sx, uint8_t channel, uint32_t flag)
1000 {
1001 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].INTSTAT, flag) == flag);
1002 }
1003
1004 /**
1005 * @brief Enable interrupt in a channel
1006 *
1007 * Register|BitsName
1008 * --------|--------
1009 * INTMASK | TXFO
1010 * INTMASK | TXFE
1011 * INTMASK | RXFO
1012 * INTMASK | RXDA
1013 *
1014 * @param I2Sx I2S instance
1015 * @param channel The special channel: 0 ~ 3
1016 * @param mask This parameter can be one or more of the following values:
1017 * @arg @ref LL_I2S_INT_TXFO
1018 * @arg @ref LL_I2S_INT_TXFE
1019 * @arg @ref LL_I2S_INT_RXFO
1020 * @arg @ref LL_I2S_INT_RXDA
1021 * @retval None
1022 */
ll_i2s_enable_it(i2s_regs_t * I2Sx,uint8_t channel,uint32_t mask)1023 __STATIC_INLINE void ll_i2s_enable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1024 {
1025 CLEAR_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask);
1026 }
1027
1028 /**
1029 * @brief Disable interrupt in a channel
1030 *
1031 * Register|BitsName
1032 * --------|--------
1033 * INTMASK | TXFO
1034 * INTMASK | TXFE
1035 * INTMASK | RXFO
1036 * INTMASK | RXDA
1037 *
1038 * @param I2Sx I2S instance
1039 * @param channel The special channel: 0 ~ 3
1040 * @param mask This parameter can be one or more of the following values:
1041 * @arg @ref LL_I2S_INT_TXFO
1042 * @arg @ref LL_I2S_INT_TXFE
1043 * @arg @ref LL_I2S_INT_RXFO
1044 * @arg @ref LL_I2S_INT_RXDA
1045 * @retval None
1046 */
ll_i2s_disable_it(i2s_regs_t * I2Sx,uint8_t channel,uint32_t mask)1047 __STATIC_INLINE void ll_i2s_disable_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1048 {
1049 SET_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask);
1050 }
1051
1052 /**
1053 * @brief Check if interrupt in a channel is enabled
1054 *
1055 * Register|BitsName
1056 * --------|--------
1057 * INTMASK | TXFO
1058 * INTMASK | TXFE
1059 * INTMASK | RXFO
1060 * INTMASK | RXDA
1061 *
1062 * @param I2Sx I2S instance
1063 * @param channel The special channel: 0 ~ 3
1064 * @param mask This parameter can be one or more of the following values:
1065 * @arg @ref LL_I2S_INT_TXFO
1066 * @arg @ref LL_I2S_INT_TXFE
1067 * @arg @ref LL_I2S_INT_RXFO
1068 * @arg @ref LL_I2S_INT_RXDA
1069 * @retval State of bit (1 or 0).
1070 */
ll_i2s_is_enabled_it(i2s_regs_t * I2Sx,uint8_t channel,uint32_t mask)1071 __STATIC_INLINE uint32_t ll_i2s_is_enabled_it(i2s_regs_t *I2Sx, uint8_t channel, uint32_t mask)
1072 {
1073 return ((READ_BITS(I2Sx->I2S_CHANNEL[channel].INTMASK, mask) ^ (mask)) == (mask));
1074 }
1075
1076 /**
1077 * @brief Clear RX FIFO data overrun interrupt flag in a channel
1078 *
1079 * Register|BitsName
1080 * --------|--------
1081 * RXOVR | RXCHO
1082 *
1083 * @param I2Sx I2S instance
1084 * @param channel The special channel: 0 ~ 3
1085 * @retval State of bit (1 or 0).
1086 */
ll_i2s_clear_it_rxovr(i2s_regs_t * I2Sx,uint8_t channel)1087 __STATIC_INLINE uint32_t ll_i2s_clear_it_rxovr(i2s_regs_t *I2Sx, uint8_t channel)
1088 {
1089 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].RXOVR, I2S_RXOVR_RXCHO));
1090 }
1091
1092 /**
1093 * @brief Clear TX FIFO data overrun interrupt flag in a channel
1094 *
1095 * Register|BitsName
1096 * --------|--------
1097 * TXOVR | TXCHO
1098 *
1099 * @param I2Sx I2S instance
1100 * @param channel The special channel: 0 ~ 3
1101 * @retval State of bit (1 or 0).
1102 */
ll_i2s_clear_it_txovr(i2s_regs_t * I2Sx,uint8_t channel)1103 __STATIC_INLINE uint32_t ll_i2s_clear_it_txovr(i2s_regs_t *I2Sx, uint8_t channel)
1104 {
1105 return (READ_BITS(I2Sx->I2S_CHANNEL[channel].TXOVR, I2S_TXOVR_TXCHO));
1106 }
1107
1108 /**
1109 * @brief Set threshold of RXFIFO in a channel that triggers an RXDA event
1110 *
1111 * Register|BitsName
1112 * --------|--------
1113 * RXFIFO_TL | TL
1114 *
1115 * @param I2Sx I2S instance
1116 * @param channel The special channel: 0 ~ 3
1117 * @param threshold This parameter can be one of the following values:
1118 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1119 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1120 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1121 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1122 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1123 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1124 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1125 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1126 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1127 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1128 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1129 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1130 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1131 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1132 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1133 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1134 * @retval None
1135 */
ll_i2s_set_rx_fifo_threshold(i2s_regs_t * I2Sx,uint8_t channel,uint32_t threshold)1136 __STATIC_INLINE void ll_i2s_set_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
1137 {
1138 WRITE_REG(I2Sx->I2S_CHANNEL[channel].RXFIFO_TL, threshold);
1139 }
1140
1141 /**
1142 * @brief Get threshold of RXFIFO in a channel that triggers an RXDA event
1143 *
1144 * Register|BitsName
1145 * --------|--------
1146 * RXFIFO_TL | TL
1147 *
1148 * @param I2Sx I2S instance
1149 * @param channel The special channel: 0 ~ 3
1150 * @retval Returned Value can be one of the following values:
1151 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1152 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1153 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1154 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1155 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1156 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1157 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1158 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1159 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1160 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1161 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1162 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1163 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1164 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1165 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1166 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1167 */
ll_i2s_get_rx_fifo_threshold(i2s_regs_t * I2Sx,uint8_t channel)1168 __STATIC_INLINE uint32_t ll_i2s_get_rx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
1169 {
1170 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].RXFIFO_TL, I2S_RXFIFO_TL));
1171 }
1172
1173 /**
1174 * @brief Set threshold of TXFIFO in a channel that triggers an TXFE event
1175 *
1176 * Register|BitsName
1177 * --------|--------
1178 * TXFIFO_TL | TL
1179 *
1180 * @param I2Sx I2S instance
1181 * @param channel The special channel: 0 ~ 3
1182 * @param threshold This parameter can be one of the following values:
1183 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1184 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1185 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1186 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1187 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1188 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1189 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1190 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1191 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1192 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1193 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1194 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1195 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1196 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1197 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1198 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1199 * @retval None
1200 */
ll_i2s_set_tx_fifo_threshold(i2s_regs_t * I2Sx,uint8_t channel,uint32_t threshold)1201 __STATIC_INLINE void ll_i2s_set_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel, uint32_t threshold)
1202 {
1203 WRITE_REG(I2Sx->I2S_CHANNEL[channel].TXFIFO_TL, threshold);
1204 }
1205
1206 /**
1207 * @brief Get threshold of TXFIFO in a channel that triggers an TXFE event
1208 *
1209 * Register|BitsName
1210 * --------|--------
1211 * TXFIFO_TL | TL
1212 *
1213 * @param I2Sx I2S instance
1214 * @param channel The special channel: 0 ~ 3
1215 * @retval Returned Value can be one of the following values:
1216 * @arg @ref LL_I2S_THRESHOLD_1FIFO
1217 * @arg @ref LL_I2S_THRESHOLD_2FIFO
1218 * @arg @ref LL_I2S_THRESHOLD_3FIFO
1219 * @arg @ref LL_I2S_THRESHOLD_4FIFO
1220 * @arg @ref LL_I2S_THRESHOLD_5FIFO
1221 * @arg @ref LL_I2S_THRESHOLD_6FIFO
1222 * @arg @ref LL_I2S_THRESHOLD_7FIFO
1223 * @arg @ref LL_I2S_THRESHOLD_8FIFO
1224 * @arg @ref LL_I2S_THRESHOLD_9FIFO
1225 * @arg @ref LL_I2S_THRESHOLD_10FIFO
1226 * @arg @ref LL_I2S_THRESHOLD_11FIFO
1227 * @arg @ref LL_I2S_THRESHOLD_12FIFO
1228 * @arg @ref LL_I2S_THRESHOLD_13FIFO
1229 * @arg @ref LL_I2S_THRESHOLD_14FIFO
1230 * @arg @ref LL_I2S_THRESHOLD_15FIFO
1231 * @arg @ref LL_I2S_THRESHOLD_16FIFO
1232 */
ll_i2s_get_tx_fifo_threshold(i2s_regs_t * I2Sx,uint8_t channel)1233 __STATIC_INLINE uint32_t ll_i2s_get_tx_fifo_threshold(i2s_regs_t *I2Sx, uint8_t channel)
1234 {
1235 return (uint32_t)(READ_BITS(I2Sx->I2S_CHANNEL[channel].TXFIFO_TL, I2S_TXFIFO_TL));
1236 }
1237
1238 /**
1239 * @brief Clear RX FIFO data in a channel
1240 *
1241 * Register|BitsName
1242 * --------|--------
1243 * RXFIFO_FLUSH | FLUSH
1244 *
1245 * @param I2Sx I2S instance
1246 * @param channel The special channel: 0 ~ 3
1247 * @retval None
1248 */
ll_i2s_clr_rxfifo_channel(i2s_regs_t * I2Sx,uint8_t channel)1249 __STATIC_INLINE void ll_i2s_clr_rxfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
1250 {
1251 WRITE_REG(I2Sx->I2S_CHANNEL[channel].RXFIFO_FLUSH, I2S_RXFIFO_FLUSH);
1252 }
1253
1254 /**
1255 * @brief Clear TX FIFO data in a channel
1256 *
1257 * Register|BitsName
1258 * --------|--------
1259 * TXFIFO_FLUSH | FLUSH
1260 *
1261 * @param I2Sx I2S instance
1262 * @param channel The special channel: 0 ~ 3
1263 * @retval None
1264 */
ll_i2s_clr_txfifo_channel(i2s_regs_t * I2Sx,uint8_t channel)1265 __STATIC_INLINE void ll_i2s_clr_txfifo_channel(i2s_regs_t *I2Sx, uint8_t channel)
1266 {
1267 WRITE_REG(I2Sx->I2S_CHANNEL[channel].TXFIFO_FLUSH, I2S_TXFIFO_FLUSH);
1268 }
1269
1270 /** @} */
1271
1272 /** @defgroup I2S_LL_EF_DMA_Management DMA Management Functions
1273 * @{
1274 */
1275
1276 /**
1277 * @brief Reset RX block DMA
1278 * @note The RX DMA can be reset to the lowest channel via this register.
1279 *
1280 * Register|BitsName
1281 * --------|--------
1282 * RXDMA_RST | RST
1283 *
1284 * @param I2Sx I2S instance
1285 * @retval None
1286 */
ll_i2s_rst_rxdma(i2s_regs_t * I2Sx)1287 __STATIC_INLINE void ll_i2s_rst_rxdma(i2s_regs_t *I2Sx)
1288 {
1289 WRITE_REG(I2Sx->RXDMA_RST, I2S_RXDMA_RST);
1290 }
1291
1292 /**
1293 * @brief Reset TX block DMA
1294 * @note The TX DMA can be reset to the lowest channel via this register.
1295 *
1296 * Register|BitsName
1297 * --------|--------
1298 * TXDMA_RST | RST
1299 *
1300 * @param I2Sx I2S instance
1301 * @retval None
1302 */
ll_i2s_rst_txdma(i2s_regs_t * I2Sx)1303 __STATIC_INLINE void ll_i2s_rst_txdma(i2s_regs_t *I2Sx)
1304 {
1305 WRITE_REG(I2Sx->TXDMA_RST, I2S_TXDMA_RST);
1306 }
1307
1308
1309 /**
1310 * @brief Enable I2S DMA
1311 *
1312 * Register|BitsName
1313 * --------|--------
1314 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1315 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1316 *
1317 * @param I2Sx I2S instance
1318 * @retval None
1319 */
ll_i2s_enable_dma(i2s_regs_t * I2Sx)1320 __STATIC_INLINE void ll_i2s_enable_dma(i2s_regs_t *I2Sx)
1321 {
1322 if (I2S_M == I2Sx)
1323 SET_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1324 else
1325 SET_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1326 }
1327
1328 /**
1329 * @brief Disable I2S DMA
1330 *
1331 * Register|BitsName
1332 * --------|--------
1333 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1334 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1335 *
1336 * @param I2Sx I2S instance
1337 * @retval None
1338 */
ll_i2s_disable_dma(i2s_regs_t * I2Sx)1339 __STATIC_INLINE void ll_i2s_disable_dma(i2s_regs_t *I2Sx)
1340 {
1341 if (I2S_M == I2Sx)
1342 CLEAR_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1343 else
1344 CLEAR_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1345 }
1346
1347 /**
1348 * @brief Check if I2S DMA is enabled
1349 *
1350 * Register|BitsName
1351 * --------|--------
1352 * DMA_ACC_SEL | QSPI1_I2S_M_SEL
1353 * DMA_ACC_SEL | I2C1_I2S_S_SEL
1354 *
1355 * @param I2Sx I2S instance
1356 * @retval State of bit (1 or 0).
1357 */
ll_i2s_is_enabled_dma(i2s_regs_t * I2Sx)1358 __STATIC_INLINE uint32_t ll_i2s_is_enabled_dma(i2s_regs_t *I2Sx)
1359 {
1360 if (I2S_M == I2Sx)
1361 return (READ_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM) == MCU_SUB_DMA_ACC_SEL_QSPI1_I2SM);
1362 else
1363 return (READ_BITS(MCU_SUB->DMA_ACC_SEL, MCU_SUB_DMA_ACC_SEL_I2C1_I2SS) == MCU_SUB_DMA_ACC_SEL_I2C1_I2SS);
1364 }
1365
1366
1367 /** @} */
1368
1369 /** @defgroup I2S_LL_EF_Component Component Paraments Functions
1370 * @{
1371 */
1372
1373 /**
1374 * @brief Get I2S component paramenters: rx resolution
1375 *
1376 * Register|BitsName
1377 * --------|--------
1378 * I2S_PARAM2 | RXSIZE_3
1379 * I2S_PARAM2 | RXSIZE_2
1380 * I2S_PARAM2 | RXSIZE_1
1381 * I2S_PARAM2 | RXSIZE_0
1382 *
1383 * @param I2Sx I2S instance
1384 * @param channel The special channel: 0 ~ 3
1385 * @retval Returned Value can be one of the following values:
1386 * @arg @ref LL_I2S_RESOLUTION_12BIT
1387 * @arg @ref LL_I2S_RESOLUTION_16BIT
1388 * @arg @ref LL_I2S_RESOLUTION_20BIT
1389 * @arg @ref LL_I2S_RESOLUTION_24BIT
1390 * @arg @ref LL_I2S_RESOLUTION_32BIT
1391 */
ll_i2s_get_rx_resolution(i2s_regs_t * I2Sx,uint8_t channel)1392 __STATIC_INLINE uint32_t ll_i2s_get_rx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
1393 {
1394 uint32_t pos[4] = {I2S_PARAM2_RXSIZE_0_Pos, I2S_PARAM2_RXSIZE_1_Pos, \
1395 I2S_PARAM2_RXSIZE_2_Pos, I2S_PARAM2_RXSIZE_3_Pos
1396 };
1397 uint32_t mask[4] = {I2S_PARAM2_RXSIZE_0, I2S_PARAM2_RXSIZE_1, I2S_PARAM2_RXSIZE_2, I2S_PARAM2_RXSIZE_3};
1398
1399 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM2, mask[channel]) >> pos[channel]);
1400 }
1401
1402 /**
1403 * @brief Get I2S component paramenters: tx resolution
1404 *
1405 * Register|BitsName
1406 * --------|--------
1407 * I2S_PARAM1 | TXSIZE_3
1408 * I2S_PARAM1 | TXSIZE_2
1409 * I2S_PARAM1 | TXSIZE_1
1410 * I2S_PARAM1 | TXSIZE_0
1411 *
1412 * @param I2Sx I2S instance
1413 * @param channel The special channel: 0 ~ 3
1414 * @retval Returned Value can be one of the following values:
1415 * @arg @ref LL_I2S_RESOLUTION_12BIT
1416 * @arg @ref LL_I2S_RESOLUTION_16BIT
1417 * @arg @ref LL_I2S_RESOLUTION_20BIT
1418 * @arg @ref LL_I2S_RESOLUTION_24BIT
1419 * @arg @ref LL_I2S_RESOLUTION_32BIT
1420 */
ll_i2s_get_tx_resolution(i2s_regs_t * I2Sx,uint8_t channel)1421 __STATIC_INLINE uint32_t ll_i2s_get_tx_resolution(i2s_regs_t *I2Sx, uint8_t channel)
1422 {
1423 uint32_t pos[4] = {I2S_PARAM1_TXSIZE_0_Pos, I2S_PARAM1_TXSIZE_1_Pos, \
1424 I2S_PARAM1_TXSIZE_2_Pos, I2S_PARAM1_TXSIZE_3_Pos
1425 };
1426 uint32_t mask[4] = {I2S_PARAM1_TXSIZE_0, I2S_PARAM1_TXSIZE_1, I2S_PARAM1_TXSIZE_2, I2S_PARAM1_TXSIZE_3};
1427
1428 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, mask[channel]) >> pos[channel]);
1429 }
1430
1431 /**
1432 * @brief Get I2S component paramenters: the number of tx channels
1433 *
1434 * Register|BitsName
1435 * --------|--------
1436 * I2S_PARAM1 | TXCHN
1437 *
1438 * @param I2Sx I2S instance
1439 * @retval Returned Value can be one of the following values:
1440 * @arg @ref LL_I2S_CHANNEL_NUM_1
1441 * @arg @ref LL_I2S_CHANNEL_NUM_2
1442 * @arg @ref LL_I2S_CHANNEL_NUM_3
1443 * @arg @ref LL_I2S_CHANNEL_NUM_4
1444 */
ll_i2s_get_tx_channels(i2s_regs_t * I2Sx)1445 __STATIC_INLINE uint32_t ll_i2s_get_tx_channels(i2s_regs_t *I2Sx)
1446 {
1447 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_TXCHN) >> I2S_PARAM1_TXCHN_Pos);
1448 }
1449
1450 /**
1451 * @brief Get I2S component paramenters: the number of rx channels
1452 *
1453 * Register|BitsName
1454 * --------|--------
1455 * I2S_PARAM1 | RXCHN
1456 *
1457 * @param I2Sx I2S instance
1458 * @retval Returned Value can be one of the following values:
1459 * @arg @ref LL_I2S_CHANNEL_NUM_1
1460 * @arg @ref LL_I2S_CHANNEL_NUM_2
1461 * @arg @ref LL_I2S_CHANNEL_NUM_3
1462 * @arg @ref LL_I2S_CHANNEL_NUM_4
1463 */
ll_i2s_get_rx_channels(i2s_regs_t * I2Sx)1464 __STATIC_INLINE uint32_t ll_i2s_get_rx_channels(i2s_regs_t *I2Sx)
1465 {
1466 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_RXCHN) >> I2S_PARAM1_RXCHN_Pos);
1467 }
1468
1469 /**
1470 * @brief Get I2S component paramenters: whether the receiver block is enabled or not
1471 *
1472 * Register|BitsName
1473 * --------|--------
1474 * I2S_PARAM1 | RXBLOCK
1475 *
1476 * @param I2Sx I2S instance
1477 * @retval State of bit (1 or 0).
1478 */
ll_i2s_get_rx_block(i2s_regs_t * I2Sx)1479 __STATIC_INLINE uint32_t ll_i2s_get_rx_block(i2s_regs_t *I2Sx)
1480 {
1481 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_RXBLOCK) == I2S_PARAM1_RXBLOCK);
1482 }
1483
1484 /**
1485 * @brief Get I2S component paramenters: whether the transmitter block is enabled or not
1486 *
1487 * Register|BitsName
1488 * --------|--------
1489 * I2S_PARAM1 | TXBLOCK
1490 *
1491 * @param I2Sx I2S instance
1492 * @retval State of bit (1 or 0).
1493 */
ll_i2s_get_tx_block(i2s_regs_t * I2Sx)1494 __STATIC_INLINE uint32_t ll_i2s_get_tx_block(i2s_regs_t *I2Sx)
1495 {
1496 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_TXBLOCK) == I2S_PARAM1_TXBLOCK);
1497 }
1498
1499 /**
1500 * @brief Get I2S component paramenters: whether the master mode is enabled or not
1501 *
1502 * Register|BitsName
1503 * --------|--------
1504 * I2S_PARAM1 | MODE
1505 *
1506 * @param I2Sx I2S instance
1507 * @retval State of bit (1 or 0).
1508 */
ll_i2s_get_master_mode(i2s_regs_t * I2Sx)1509 __STATIC_INLINE uint32_t ll_i2s_get_master_mode(i2s_regs_t *I2Sx)
1510 {
1511 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_MODE) == I2S_PARAM1_MODE);
1512 }
1513
1514 /**
1515 * @brief Get I2S component paramenters: FIOF depth
1516 *
1517 * Register|BitsName
1518 * --------|--------
1519 * I2S_PARAM1 | FIFO_DEPTH
1520 *
1521 * @param I2Sx I2S instance
1522 * @retval Returned Value can be one of the following values:
1523 * @arg @ref LL_I2S_FIFO_DEPTH_2
1524 * @arg @ref LL_I2S_FIFO_DEPTH_4
1525 * @arg @ref LL_I2S_FIFO_DEPTH_8
1526 * @arg @ref LL_I2S_FIFO_DEPTH_16
1527 */
ll_i2s_get_fifo_depth(i2s_regs_t * I2Sx)1528 __STATIC_INLINE uint32_t ll_i2s_get_fifo_depth(i2s_regs_t *I2Sx)
1529 {
1530 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_FIFO_DEPTH) >> I2S_PARAM1_FIFO_DEPTH_Pos);
1531 }
1532
1533 /**
1534 * @brief Get I2S component paramenters: APB data width
1535 *
1536 * Register|BitsName
1537 * --------|--------
1538 * I2S_PARAM1 | APB_DATA_WIDTH
1539 *
1540 * @param I2Sx I2S instance
1541 * @retval Returned Value can be one of the following values:
1542 * @arg @ref LL_I2S_APB_WIDTH_8BIT
1543 * @arg @ref LL_I2S_APB_WIDTH_16BIT
1544 * @arg @ref LL_I2S_APB_WIDTH_32BIT
1545 */
ll_i2s_get_apb_width(i2s_regs_t * I2Sx)1546 __STATIC_INLINE uint32_t ll_i2s_get_apb_width(i2s_regs_t *I2Sx)
1547 {
1548 return (uint32_t)(READ_BITS(I2Sx->I2S_PARAM1, I2S_PARAM1_APB_DATA_WIDTH) >> I2S_PARAM1_APB_DATA_WIDTH_Pos);
1549 }
1550
1551 /**
1552 * @brief Get I2S component version
1553 *
1554 * Register|BitsName
1555 * --------|--------
1556 * I2S_VERSION | VERSION
1557 *
1558 * @param I2Sx I2S instance
1559 * @retval Returned Value is const.
1560 */
ll_i2s_get_version(i2s_regs_t * I2Sx)1561 __STATIC_INLINE uint32_t ll_i2s_get_version(i2s_regs_t *I2Sx)
1562 {
1563 return (uint32_t)(READ_REG(I2Sx->I2S_VERSION));
1564 }
1565
1566 /**
1567 * @brief Get I2S component type
1568 *
1569 * Register|BitsName
1570 * --------|--------
1571 * I2S_TYPE | TYPE
1572 *
1573 * @param I2Sx I2S instance
1574 * @retval Returned Value is const.
1575 */
ll_i2s_get_type(i2s_regs_t * I2Sx)1576 __STATIC_INLINE uint32_t ll_i2s_get_type(i2s_regs_t *I2Sx)
1577 {
1578 return (uint32_t)(READ_REG(I2Sx->I2S_TYPE));
1579 }
1580
1581 /** @} */
1582
1583 /** @defgroup I2S_LL_EF_Init I2S_M Initialization and de-initialization functions
1584 * @{
1585 */
1586
1587 /**
1588 * @brief De-initialize I2S registers (Registers restored to their default values).
1589 * @param I2Sx I2S instance
1590 * @retval An error_status_t enumeration value:
1591 * - SUCCESS: I2S registers are de-initialized
1592 * - ERROR: I2S registers are not de-initialized
1593 */
1594 error_status_t ll_i2s_deinit(i2s_regs_t *I2Sx);
1595
1596 /**
1597 * @brief Initialize I2S_M registers according to the specified
1598 * parameters in p_i2s_init.
1599 * @param I2Sx I2S instance
1600 * @param p_i2s_init Pointer to a ll_i2s_init_t structure that contains the configuration
1601 * information for the specified I2S_M peripheral.
1602 * @retval An error_status_t enumeration value:
1603 * - SUCCESS: I2S registers are initialized according to p_i2s_init content
1604 * - ERROR: Problem occurred during I2S Registers initialization
1605 */
1606 error_status_t ll_i2s_init(i2s_regs_t *I2Sx, ll_i2s_init_t *p_i2s_init);
1607
1608 /**
1609 * @brief Set each field of a @ref ll_i2s_init_t type structure to default value.
1610 * @param p_i2s_init Pointer to a @ref ll_i2s_init_t structure
1611 * whose fields will be set to default values.
1612 * @retval None
1613 */
1614 void ll_i2s_struct_init(ll_i2s_init_t *p_i2s_init);
1615
1616 /** @} */
1617
1618 /** @} */
1619
1620 #endif /* I2S_M || I2S_S */
1621
1622 #ifdef __cplusplus
1623 }
1624 #endif
1625
1626 #endif /* __GR55xx_LL_I2S_H__ */
1627
1628 /** @} */
1629
1630 /** @} */
1631
1632 /** @} */
1633