1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_ll_uart.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of UART LL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup LL_DRIVER LL Driver
43 * @{
44 */
45
46 /** @defgroup LL_UART UART
47 * @brief UART LL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_LL_UART_H__
53 #define __GR55xx_LL_UART_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include "gr55xx.h"
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62 #if defined (UART0) || defined (UART1)
63
64 /** @defgroup UART_LL_STRUCTURES Structures
65 * @{
66 */
67
68 /* Exported types ------------------------------------------------------------*/
69 /** @defgroup UART_LL_ES_INIT UART Exported init structures
70 * @{
71 */
72
73 /**
74 * @brief LL UART init Structure definition
75 */
76 typedef struct _ll_uart_init_t {
77 uint32_t baud_rate; /**< This field defines expected Usart communication baud rate.
78 This feature can be modified afterwards using unitary function
79 @ref ll_uart_set_baud_rate(). */
80
81 uint32_t data_bits; /**< Specifies the number of
82 data bits transmitted or
83 received in a frame.
84 This parameter can be a value of @ref UART_LL_EC_DATABITS.
85 This feature can be modified afterwards using unitary function
86 @ref ll_uart_set_data_bits_length(). */
87
88 uint32_t stop_bits; /**< Specifies the number of stop bits transmitted.
89 This parameter can be a value of @ref UART_LL_EC_STOPBITS.
90 This feature can be modified afterwards using unitary function
91 @ref ll_uart_set_stop_bits_length(). */
92
93 uint32_t parity; /**< Specifies the parity mode.
94 This parameter can be a value of @ref UART_LL_EC_PARITY.
95 This feature can be modified afterwards using unitary function
96 @ref ll_uart_set_parity(). */
97
98 uint32_t hw_flow_ctrl; /**< Specifies whether the
99 hardware flow control mode
100 is enabled or disabled.
101 This parameter can be a value of @ref UART_LL_EC_HWCONTROL.
102 This feature can be modified afterwards using unitary function
103 @ref ll_uart_set_hw_flow_ctrl(). */
104 } ll_uart_init_t;
105
106 /** @} */
107
108 /** @} */
109
110 /**
111 * @defgroup UART_LL_MACRO Defines
112 * @{
113 */
114
115 /* Exported constants --------------------------------------------------------*/
116 /** @defgroup UART_LL_Exported_Constants UART Exported Constants
117 * @{
118 */
119
120 /** @defgroup UART_LL_EC_GET_FLAG Get Flags Defines
121 * @brief Flags definitions which can be used with LL_UART_ReadReg function
122 * @{
123 */
124 #define LL_UART_LSR_OE UART_LSR_OE /**< Overrun error flag */
125 #define LL_UART_LSR_PE UART_LSR_PE /**< Parity error flag */
126 #define LL_UART_LSR_FE UART_LSR_FE /**< Framing error flag */
127 #define LL_UART_LSR_BI UART_LSR_BI /**< Break detection flag */
128 #define LL_UART_LSR_THRE UART_LSR_THRE /**< Transmit holding register
129 empty flag */
130 #define LL_UART_LSR_TEMT UART_LSR_TEMT /**< Transmitter empty flag */
131 #define LL_UART_LSR_RFE UART_LSR_RFE /**< Rx FIFO error flag */
132
133 #define LL_UART_IIR_MS UART_IIR_IID_MS /**< Modem Status flag */
134 #define LL_UART_IIR_NIP UART_IIR_IID_NIP /**< No Interrupt Pending flag */
135 #define LL_UART_IIR_THRE UART_IIR_IID_THRE /**< THR Empty flag */
136 #define LL_UART_IIR_RDA UART_IIR_IID_RDA /**< Received Data Available flag */
137 #define LL_UART_IIR_RLS UART_IIR_IID_RLS /**< Receiver Line Status flag */
138 #define LL_UART_IIR_CTO UART_IIR_IID_CTO /**< Character Timeout flag */
139
140 #define LL_UART_USR_RFF UART_USR_RFF /**< Rx FIFO Full flag */
141 #define LL_UART_USR_RFNE UART_USR_RFNE /**< Rx FIFO Not Empty flag */
142 #define LL_UART_USR_TFE UART_USR_TFE /**< Tx FIFO Empty flag */
143 #define LL_UART_USR_TFNF UART_USR_TFNF /**< Tx FIFO Not Full flag */
144 /** @} */
145
146 /** @defgroup UART_LL_EC_IT IT Defines
147 * @brief Interrupt definitions which can be used with LL_UART_ReadReg and LL_UART_WriteReg functions
148 * @{
149 */
150 #define LL_UART_IER_MS UART_IER_EDSSI /**< Enable Modem Status
151 Interrupt */
152 #define LL_UART_IER_RLS UART_IER_ERLS /**< Enable Receiver Line
153 Status
154 Interrupt */
155 #define LL_UART_IER_THRE (UART_IER_ETBEI | UART_IER_PTIME) /**< Enable Transmit Holding
156 Register
157 Empty Interrupt */
158 #define LL_UART_IER_RDA UART_IER_ERBFI /**< Enable Received Data Available
159 Interrupt and Character
160 Timeout
161 Interrupt */
162 /** @} */
163
164 /** @defgroup UART_LL_EC_PARITY Parity Control
165 * @{
166 */
167 #define LL_UART_PARITY_NONE UART_LCR_PARITY_NONE /**< Parity control disabled */
168 #define LL_UART_PARITY_ODD UART_LCR_PARITY_ODD /**< Parity control enabled and
169 Odd Parity is selected */
170 #define LL_UART_PARITY_EVEN UART_LCR_PARITY_EVEN /**< Parity control enabled and
171 Even Parity is selected */
172 #define LL_UART_PARITY_SP0 UART_LCR_PARITY_SP0 /**< Parity control enabled and
173 Stick Parity 0 is selected */
174 #define LL_UART_PARITY_SP1 UART_LCR_PARITY_SP1 /**< Parity control enabled and
175 Stick Parity 1 is selected */
176 /** @} */
177
178 /** @defgroup UART_LL_EC_DATABITS Data Bits
179 * @{
180 */
181 #define LL_UART_DATABITS_5B UART_LCR_DLS_5 /**< 5 bits word length : Start bit,
182 5 data bits, n stop bits */
183 #define LL_UART_DATABITS_6B UART_LCR_DLS_6 /**< 6 bits word length : Start bit,
184 6 data bits, n stop bits */
185 #define LL_UART_DATABITS_7B UART_LCR_DLS_7 /**< 7 bits word length : Start bit,
186 7 data bits, n stop bits */
187 #define LL_UART_DATABITS_8B UART_LCR_DLS_8 /**< 8 bits word length : Start bit,
188 8 data bits, n stop bits */
189 /** @} */
190
191 /** @defgroup UART_LL_EC_STOPBITS Stop Bits
192 * @{
193 */
194 #define LL_UART_STOPBITS_1 UART_LCR_STOP_1 /**< 1 stop bit */
195 #define LL_UART_STOPBITS_1_5 UART_LCR_STOP_1_5 /**< 1.5 stop bits */
196 #define LL_UART_STOPBITS_2 UART_LCR_STOP_2 /**< 2 stop bits */
197 /** @} */
198
199 /** @defgroup UART_LL_EC_HWCONTROL Hardware Flow Control
200 * @{
201 */
202 #define LL_UART_HWCONTROL_NONE 0x00000000U /**< CTS and RTS hardware flow
203 control disabled */
204 #define LL_UART_HWCONTROL_RTS_CTS (UART_MCR_AFCE | UART_MCR_RTS) /**< CTS and RTS hardware flow
205 control enabled */
206 /** @} */
207
208 /** @defgroup UART_LL_EC_TX_FIFO_TH TX FIFO Threshold
209 * @{
210 */
211 #define LL_UART_TX_FIFO_TH_EMPTY 0x00000000U /**< TX FIFO empty */
212 #define LL_UART_TX_FIFO_TH_CHAR_2 0x00000001U /**< 2 characters in TX FIFO */
213 #define LL_UART_TX_FIFO_TH_QUARTER_FULL 0x00000002U /**< TX FIFO 1/4 full */
214 #define LL_UART_TX_FIFO_TH_HALF_FULL 0x00000003U /**< TX FIFO 1/2 full */
215 /** @} */
216
217 /** @defgroup UART_LL_EC_RX_FIFO_TH RX FIFO Threshold
218 * @{
219 */
220 #define LL_UART_RX_FIFO_TH_CHAR_1 0x00000000U /**< 1 character in RX FIFO */
221 #define LL_UART_RX_FIFO_TH_QUARTER_FULL 0x00000001U /**< RX FIFO 1/4 full */
222 #define LL_UART_RX_FIFO_TH_HALF_FULL 0x00000002U /**< RX FIFO 1/2 full */
223 #define LL_UART_RX_FIFO_TH_FULL_2 0x00000003U /**< RX FIFO 2 less than full */
224 /** @} */
225
226 /** @defgroup UART_LL_EC_RTSPIN_STATE RTS Pin State
227 * @{
228 */
229 #define LL_UART_RTSPIN_STATE_ACTIVE 0x00000001U /**< RTS pin active(Logic 1) */
230 #define LL_UART_RTSPIN_STATE_INACTIVE 0x00000000U /**< RTS pin inactive(Logic 0) */
231 /** @} */
232
233 /** @defgroup UART_LL_EC_CTSPIN_STATE CTS Pin State
234 * @{
235 */
236 #define LL_UART_CTSPIN_STATE_ACTIVE 0x00000001U /**< CTS pin active(Logic 1) */
237 #define LL_UART_CTSPIN_STATE_INACTIVE 0x00000000U /**< CTS pin pin inactive(Logic 0) */
238 /** @} */
239
240 /** @defgroup UART_LL_EC_DEFAULT_CONFIG InitStrcut default configuartion
241 * @{
242 */
243
244 /**
245 * @brief LL UART InitStrcut default configuartion
246 */
247 #define LL_UART_DEFAULT_CONFIG \
248 { \
249 .baud_rate = 9600U, \
250 .data_bits = LL_UART_DATABITS_8B, \
251 .stop_bits = LL_UART_STOPBITS_1, \
252 .parity = LL_UART_PARITY_NONE, \
253 .hw_flow_ctrl = LL_UART_HWCONTROL_NONE, \
254 }
255 /** @} */
256
257 /** @} */
258
259 /* Exported macro ------------------------------------------------------------*/
260 /** @defgroup UART_LL_Exported_Macros UART Exported Macros
261 * @{
262 */
263
264 /** @defgroup UART_LL_EM_WRITE_READ Common Write and read registers Macros
265 * @{
266 */
267
268 /**
269 * @brief Write a value in UART register
270 * @param __instance__ UART instance
271 * @param __REG__ Register to be written
272 * @param __VALUE__ Value to be written in the register
273 * @retval None
274 */
275 #define LL_UART_WriteReg(__instance__, __REG__, __VALUE__) WRITE_REG(__instance__->__REG__, (__VALUE__))
276
277 /**
278 * @brief Read a value in UART register
279 * @param __instance__ UART instance
280 * @param __REG__ Register to be read
281 * @retval Register value
282 */
283 #define LL_UART_ReadReg(__instance__, __REG__) READ_REG(__instance__->__REG__)
284
285 /** @} */
286
287 /** @defgroup UART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
288 * @{
289 */
290
291 /**
292 * @brief Compute UARTDIV value according to Peripheral Clock and
293 * expected Baud Rate (32 bits value of UARTDIV is returned)
294 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
295 * @param __BAUDRATE__ Baud rate value to achieve
296 * @retval UARTDIV value to be used for DLL,DLH registers
297 */
298 #define __LL_UART_DIV(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) / 16)
299
300 /**
301 * @brief Compute UARTDLF value according to Peripheral Clock and
302 * expected Baud Rate (32 bits value of UARTDLF is returned)
303 * @param __PERIPHCLK__ Peripheral Clock frequency used for UART instance
304 * @param __BAUDRATE__ Baud rate value to achieve
305 * @retval UARTDLF value to be used for DLL,DLH registers
306 */
307 #define __LL_UART_DLF(__PERIPHCLK__, __BAUDRATE__) ((__PERIPHCLK__) / (__BAUDRATE__) % 16)
308
309 /** @} */
310
311 /** @} */
312
313 /** @} */
314
315 /* Exported functions --------------------------------------------------------*/
316 /** @defgroup UART_LL_DRIVER_FUNCTIONS Functions
317 * @{
318 */
319
320 /** @defgroup UART_LL_EF_Configuration Configuration functions
321 * @{
322 */
323
324 /**
325 * @brief Configure UART DLF and DLH register for achieving expected Baud Rate value.
326 * @note Peripheral clock and Baud rate values provided as function parameters should be valid
327 * (Baud rate value != 0)
328 *
329 * Register|BitsName
330 * --------|--------
331 * DLL | DLL
332 * DLH | DLH
333 *
334 * @param UARTx UART instance
335 * @param peripheral_clock Peripheral Clock
336 * @param baud_rate Baud Rate
337 * @retval None
338 */
ll_uart_set_baud_rate(uart_regs_t * UARTx,uint32_t peripheral_clock,uint32_t baud_rate)339 __STATIC_INLINE void ll_uart_set_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock, uint32_t baud_rate)
340 {
341 register uint32_t uartdiv = __LL_UART_DIV(peripheral_clock, baud_rate);
342
343 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
344 WRITE_REG(UARTx->RBR_DLL_THR.DLL, uartdiv & UART_DLL_DLL);
345 WRITE_REG(UARTx->DLH_IER.DLH, (uartdiv >> ITEM_8) & UART_DLH_DLH);
346 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
347 WRITE_REG(UARTx->DLF, __LL_UART_DLF(peripheral_clock, baud_rate));
348 }
349
350 /**
351 * @brief Return current Baud Rate value
352 * @note In case of non-initialized or invalid value stored in DLL, DLH and DLF register,
353 * the value 0 will be returned.
354 *
355 * Register|BitsName
356 * --------|--------
357 * DLL | DLL
358 * DLH | DLH
359 *
360 * @param UARTx UART instance
361 * @param peripheral_clock Peripheral Clock
362 * @retval Baud Rate
363 */
ll_uart_get_baud_rate(uart_regs_t * UARTx,uint32_t peripheral_clock)364 __STATIC_INLINE uint32_t ll_uart_get_baud_rate(uart_regs_t *UARTx, uint32_t peripheral_clock)
365 {
366 register uint32_t uartdiv = 0x0U;
367 register uint32_t baud = 0x0U;
368
369 SET_BITS(UARTx->LCR, UART_LCR_DLAB);
370 uartdiv = UARTx->RBR_DLL_THR.DLL | (UARTx->DLH_IER.DLH << ITEM_8);
371 CLEAR_BITS(UARTx->LCR, UART_LCR_DLAB);
372
373 if ((uartdiv != 0) && (UARTx->DLF != 0x0U)) {
374 baud = peripheral_clock / (ITEM_16 * uartdiv + UARTx->DLF);
375 }
376
377 return baud;
378 }
379
380 /**
381 * @brief Set the length of the data bits
382 *
383 * Register|BitsName
384 * --------|--------
385 * LCR | DLS
386 *
387 * @param UARTx UART instance
388 * @param data_bits This parameter can be one of the following values:
389 * @arg @ref LL_UART_DATABITS_5B
390 * @arg @ref LL_UART_DATABITS_6B
391 * @arg @ref LL_UART_DATABITS_7B
392 * @arg @ref LL_UART_DATABITS_8B
393 *
394 * @retval None
395 */
ll_uart_set_data_bits_length(uart_regs_t * UARTx,uint32_t data_bits)396 __STATIC_INLINE void ll_uart_set_data_bits_length(uart_regs_t *UARTx, uint32_t data_bits)
397 {
398 MODIFY_REG(UARTx->LCR, UART_LCR_DLS, data_bits);
399 }
400
401 /**
402 * @brief Return the length of the data bits
403 *
404 * Register|BitsName
405 * --------|--------
406 * LCR | DLS
407 *
408 * @param UARTx UART instance
409 * @retval Returned value can be one of the following values:
410 * @arg @ref LL_UART_DATABITS_5B
411 * @arg @ref LL_UART_DATABITS_6B
412 * @arg @ref LL_UART_DATABITS_7B
413 * @arg @ref LL_UART_DATABITS_8B
414 */
ll_uart_get_data_bits_length(uart_regs_t * UARTx)415 __STATIC_INLINE uint32_t ll_uart_get_data_bits_length(uart_regs_t *UARTx)
416 {
417 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_DLS));
418 }
419
420 /**
421 * @brief Set the length of the stop bits
422 *
423 * Register|BitsName
424 * --------|--------
425 * LCR | STOP
426 *
427 * @param UARTx UART instance
428 * @param stop_bits This parameter can be one of the following values:
429 * @arg @ref LL_UART_STOPBITS_1
430 * @arg @ref LL_UART_STOPBITS_1_5 (*)
431 * @arg @ref LL_UART_STOPBITS_2 (*)
432 *
433 * (*) STOPBITS_1_5 only valid when DataBits = 5
434 * (*) STOPBITS_2 is invalid when DataBits = 5
435 * @retval None
436 */
ll_uart_set_stop_bits_length(uart_regs_t * UARTx,uint32_t stop_bits)437 __STATIC_INLINE void ll_uart_set_stop_bits_length(uart_regs_t *UARTx, uint32_t stop_bits)
438 {
439 MODIFY_REG(UARTx->LCR, UART_LCR_STOP, stop_bits);
440 }
441
442 /**
443 * @brief Retrieve the length of the stop bits
444 *
445 * Register|BitsName
446 * --------|--------
447 * LCR | STOP
448 *
449 * @param UARTx UART instance
450 * @retval Returned value can be one of the following values:
451 * @arg @ref LL_UART_STOPBITS_1
452 * @arg @ref LL_UART_STOPBITS_1_5
453 * @arg @ref LL_UART_STOPBITS_2
454 */
ll_uart_get_stop_bits_length(uart_regs_t * UARTx)455 __STATIC_INLINE uint32_t ll_uart_get_stop_bits_length(uart_regs_t *UARTx)
456 {
457 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_STOP));
458 }
459
460 /**
461 * @brief Configure Parity.
462 * @note This function selects if hardware parity control
463 * (generation and detection) is enabled or disabled.
464 * When the parity control is enabled (Odd,Even,0,1),
465 * computed parity bit is inserted at the MSB position
466 * and parity is checked on the received data.
467 *
468 * Register|BitsName
469 * --------|--------
470 * LCR | SP
471 * LCR | EPS
472 * LCR | PEN
473 *
474 * @param UARTx UART instance
475 * @param parity This parameter can be one of the following values:
476 * @arg @ref LL_UART_PARITY_NONE
477 * @arg @ref LL_UART_PARITY_EVEN
478 * @arg @ref LL_UART_PARITY_ODD
479 * @arg @ref LL_UART_PARITY_SP0
480 * @arg @ref LL_UART_PARITY_SP1
481 * @retval None
482 */
ll_uart_set_parity(uart_regs_t * UARTx,uint32_t parity)483 __STATIC_INLINE void ll_uart_set_parity(uart_regs_t *UARTx, uint32_t parity)
484 {
485 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY, parity);
486 }
487
488 /**
489 * @brief Return Parity configuration
490 *
491 * Register|BitsName
492 * --------|--------
493 * LCR | SP
494 * LCR | EPS
495 * LCR | PEN
496 *
497 * @param UARTx UART instance
498 * @retval Returned value can be one of the following values:
499 * @arg @ref LL_UART_PARITY_NONE
500 * @arg @ref LL_UART_PARITY_EVEN
501 * @arg @ref LL_UART_PARITY_ODD
502 * @arg @ref LL_UART_PARITY_SP0
503 * @arg @ref LL_UART_PARITY_SP1
504 */
ll_uart_get_parity(uart_regs_t * UARTx)505 __STATIC_INLINE uint32_t ll_uart_get_parity(uart_regs_t *UARTx)
506 {
507 return (uint32_t)(READ_BITS(UARTx->LCR, UART_LCR_PARITY));
508 }
509
510 /**
511 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
512 * @note This function call is equivalent to the following function call sequence :
513 * - Data Width configuration using @ref ll_uart_set_data_bits_length() function
514 * - Parity Control and mode configuration using @ref ll_uart_set_parity() function
515 * - Stop bits configuration using @ref ll_uart_set_stop_bits_length() function
516 *
517 * Register|BitsName
518 * --------|--------
519 * LCR | PS
520 * LCR | EPS
521 * LCR | PEN
522 * LCR | STOP
523 * LCR | DLS
524 *
525 * @param UARTx UART instance
526 * @param data_bits This parameter can be one of the following values:
527 * @arg @ref LL_UART_DATABITS_5B
528 * @arg @ref LL_UART_DATABITS_6B
529 * @arg @ref LL_UART_DATABITS_7B
530 * @arg @ref LL_UART_DATABITS_8B
531 * @param parity This parameter can be one of the following values:
532 * @arg @ref LL_UART_PARITY_NONE
533 * @arg @ref LL_UART_PARITY_EVEN
534 * @arg @ref LL_UART_PARITY_ODD
535 * @arg @ref LL_UART_PARITY_SP0
536 * @arg @ref LL_UART_PARITY_SP1
537 * @param stop_bits This parameter can be one of the following values:
538 * @arg @ref LL_UART_STOPBITS_1
539 * @arg @ref LL_UART_STOPBITS_1_5 (*)
540 * @arg @ref LL_UART_STOPBITS_2 (*)
541 *
542 * (*) STOPBITS_1_5 only valid when DataBits = 5
543 * (*) STOPBITS_2 is invalid when DataBits = 5
544 * @retval None
545 */
ll_uart_config_character(uart_regs_t * UARTx,uint32_t data_bits,uint32_t parity,uint32_t stop_bits)546 __STATIC_INLINE void ll_uart_config_character(uart_regs_t *UARTx, uint32_t data_bits,
547 uint32_t parity, uint32_t stop_bits)
548 {
549 MODIFY_REG(UARTx->LCR, UART_LCR_PARITY | UART_LCR_STOP | UART_LCR_DLS, parity | stop_bits | data_bits);
550 }
551
552 /**
553 * @brief Set UART RTS pin state to Active/Inactive
554 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
555 *
556 * Register|BitsName
557 * --------|--------
558 * SRTS | SRTS
559 * MCR | RTS
560 *
561 * @param UARTx UART instance
562 * @param pin_state This parameter can be one of the following values:
563 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
564 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
565 * @retval None
566 */
ll_uart_set_rts_pin_state(uart_regs_t * UARTx,uint32_t pin_state)567 __STATIC_INLINE void ll_uart_set_rts_pin_state(uart_regs_t *UARTx, uint32_t pin_state)
568 {
569 WRITE_REG(UARTx->SRTS, pin_state);
570 }
571
572 /**
573 * @brief Get UART RTS pin state
574 * @note The RTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
575 *
576 * Register|BitsName
577 * --------|--------
578 * SRTS | SRTS
579 * MCR | RTS
580 *
581 * @param UARTx UART instance
582 * @retval Returned value can be one of the following values:
583 * @arg @ref LL_UART_RTSPIN_STATE_ACTIVE
584 * @arg @ref LL_UART_RTSPIN_STATE_INACTIVE
585 */
ll_uart_get_rts_pin_state(uart_regs_t * UARTx)586 __STATIC_INLINE uint32_t ll_uart_get_rts_pin_state(uart_regs_t *UARTx)
587 {
588 return (uint32_t)(READ_REG(UARTx->SRTS));
589 }
590
591 /**
592 * @brief Get UART CTS pin state
593 * @note The CTS pin is ACTIVE when logic level is low, and INACTIVE when logic level is high.
594 *
595 * Register|BitsName
596 * --------|--------
597 * MSR | CTS
598 *
599 * @param UARTx UART instance
600 * @retval Returned value can be one of the following values:
601 * @arg @ref LL_UART_CTSPIN_STATE_ACTIVE
602 * @arg @ref LL_UART_CTSPIN_STATE_INACTIVE
603 */
ll_uart_get_cts_pin_state(uart_regs_t * UARTx)604 __STATIC_INLINE uint32_t ll_uart_get_cts_pin_state(uart_regs_t *UARTx)
605 {
606 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_CTS) >> UART_MSR_CTS_Pos);
607 }
608
609 /**
610 * @brief Indicate if CTS is changed since the last time the MSR was read
611 *
612 * Register|BitsName
613 * --------|--------
614 * MSR | DCTS
615 *
616 * @param UARTx UART instance
617 * @retval State of bit (1 or 0).
618 */
ll_uart_is_changed_cts(uart_regs_t * UARTx)619 __STATIC_INLINE uint32_t ll_uart_is_changed_cts(uart_regs_t *UARTx)
620 {
621 return (uint32_t)(READ_BITS(UARTx->MSR, UART_MSR_DCTS) >> UART_MSR_DCTS_Pos);
622 }
623
624 /**
625 * @brief Configure HW Flow Control mode (None or Both CTS and RTS)
626 * @note This function is used to Enable/Disable UART Auto Flow Control.
627 *
628 * Register|BitsName
629 * --------|--------
630 * MCR | AFCE
631 * MCR | RTS
632 *
633 * @param UARTx UART instance
634 * @param hw_flow_ctrl This parameter can be one of the following values:
635 * @arg @ref LL_UART_HWCONTROL_NONE
636 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
637 * @retval None
638 */
ll_uart_set_hw_flow_ctrl(uart_regs_t * UARTx,uint32_t hw_flow_ctrl)639 __STATIC_INLINE void ll_uart_set_hw_flow_ctrl(uart_regs_t *UARTx, uint32_t hw_flow_ctrl)
640 {
641 MODIFY_REG(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS, hw_flow_ctrl);
642 }
643
644 /**
645 * @brief Return HW Flow Control configuration (None or Both CTS and RTS)
646 *
647 * Register|BitsName
648 * --------|--------
649 * MCR | AFCE
650 * MCR | RTS
651 *
652 * @param UARTx UART instance
653 * @retval Returned value can be one of the following values:
654 * @arg @ref LL_UART_HWCONTROL_NONE
655 * @arg @ref LL_UART_HWCONTROL_RTS_CTS
656 */
ll_uart_get_hw_flow_ctrl(uart_regs_t * UARTx)657 __STATIC_INLINE uint32_t ll_uart_get_hw_flow_ctrl(uart_regs_t *UARTx)
658 {
659 return (uint32_t)(READ_BITS(UARTx->MCR, UART_MCR_AFCE | UART_MCR_RTS));
660 }
661
662 /**
663 * @brief Enable Break sending
664 *
665 * Register|BitsName
666 * --------|--------
667 * LCR | BC
668 *
669 * @param UARTx UART instance
670 * @retval None
671 */
ll_uart_enable_break_sending(uart_regs_t * UARTx)672 __STATIC_INLINE void ll_uart_enable_break_sending(uart_regs_t *UARTx)
673 {
674 WRITE_REG(UARTx->SBCR, 0x1U);
675 }
676
677 /**
678 * @brief Disable Break sending
679 *
680 * Register|BitsName
681 * --------|--------
682 * LCR | BC
683 *
684 * @param UARTx UART instance
685 * @retval None
686 */
ll_uart_disable_break_sending(uart_regs_t * UARTx)687 __STATIC_INLINE void ll_uart_disable_break_sending(uart_regs_t *UARTx)
688 {
689 WRITE_REG(UARTx->SBCR, 0x0U);
690 }
691
692 /**
693 * @brief Indicate if Break sending is enabled
694 *
695 * Register|BitsName
696 * --------|--------
697 * LCR | BC
698 *
699 * @param UARTx UART instance
700 * @retval State of bit (1 or 0).
701 */
ll_uart_is_enabled_break_sending(uart_regs_t * UARTx)702 __STATIC_INLINE uint32_t ll_uart_is_enabled_break_sending(uart_regs_t *UARTx)
703 {
704 return READ_REG(UARTx->SBCR);
705 }
706
707 /**
708 * @brief Enable TX FIFO and RX FIFO
709 *
710 * Register|BitsName
711 * --------|--------
712 * SFE | SFE
713 *
714 * @param UARTx UART instance
715 * @retval None
716 */
ll_uart_enable_fifo(uart_regs_t * UARTx)717 __STATIC_INLINE void ll_uart_enable_fifo(uart_regs_t *UARTx)
718 {
719 WRITE_REG(UARTx->SFE, 0x1U);
720 }
721
722 /**
723 * @brief Disable TX FIFO and RX FIFO
724 *
725 * Register|BitsName
726 * --------|--------
727 * SFE | SFE
728 *
729 * @param UARTx UART instance
730 * @retval None
731 */
ll_uart_disable_fifo(uart_regs_t * UARTx)732 __STATIC_INLINE void ll_uart_disable_fifo(uart_regs_t *UARTx)
733 {
734 WRITE_REG(UARTx->SFE, 0x0U);
735 }
736
737 /**
738 * @brief Indicate if TX FIFO and RX FIFO is enabled
739 *
740 * Register|BitsName
741 * --------|--------
742 * SFE | SFE
743 *
744 * @param UARTx UART instance
745 * @retval State of bit (1 or 0).
746 */
ll_uart_is_enabled_fifo(uart_regs_t * UARTx)747 __STATIC_INLINE uint32_t ll_uart_is_enabled_fifo(uart_regs_t *UARTx)
748 {
749 return READ_REG(UARTx->SFE);
750 }
751
752 /**
753 * @brief Set threshold of TX FIFO that triggers an THRE interrupt
754 *
755 * Register|BitsName
756 * --------|--------
757 * STET | STET
758 *
759 * @param UARTx UART instance
760 * @param threshold This parameter can be one of the following values:
761 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
762 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
763 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
764 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
765 * @retval None
766 */
ll_uart_set_tx_fifo_threshold(uart_regs_t * UARTx,uint32_t threshold)767 __STATIC_INLINE void ll_uart_set_tx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
768 {
769 WRITE_REG(UARTx->STET, threshold);
770 }
771
772 /**
773 * @brief Get threshold of TX FIFO that triggers an THRE interrupt
774 *
775 * Register|BitsName
776 * --------|--------
777 * STET | STET
778 *
779 * @param UARTx UART instance
780 * @retval Returned value can be one of the following values:
781 * @arg @ref LL_UART_TX_FIFO_TH_EMPTY
782 * @arg @ref LL_UART_TX_FIFO_TH_CHAR_2
783 * @arg @ref LL_UART_TX_FIFO_TH_QUARTER_FULL
784 * @arg @ref LL_UART_TX_FIFO_TH_HALF_FULL
785 */
ll_uart_get_tx_fifo_threshold(uart_regs_t * UARTx)786 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_threshold(uart_regs_t *UARTx)
787 {
788 return (uint32_t)(READ_REG(UARTx->STET));
789 }
790
791 /**
792 * @brief Set threshold of RX FIFO that triggers an RDA interrupt
793 *
794 * Register|BitsName
795 * --------|--------
796 * SRT | SRT
797 *
798 * @param UARTx UART instance
799 * @param threshold This parameter can be one of the following values:
800 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
801 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
802 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
803 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
804 * @retval None
805 */
ll_uart_set_rx_fifo_threshold(uart_regs_t * UARTx,uint32_t threshold)806 __STATIC_INLINE void ll_uart_set_rx_fifo_threshold(uart_regs_t *UARTx, uint32_t threshold)
807 {
808 WRITE_REG(UARTx->SRT, threshold);
809 }
810
811 /**
812 * @brief Get threshold of RX FIFO that triggers an RDA interrupt
813 *
814 * Register|BitsName
815 * --------|--------
816 * SRT | SRT
817 *
818 * @param UARTx UART instance
819 * @retval Returned value can be one of the following values:
820 * @arg @ref LL_UART_RX_FIFO_TH_CHAR_1
821 * @arg @ref LL_UART_RX_FIFO_TH_QUARTER_FULL
822 * @arg @ref LL_UART_RX_FIFO_TH_HALF_FULL
823 * @arg @ref LL_UART_RX_FIFO_TH_FULL_2
824 */
ll_uart_get_rx_fifo_threshold(uart_regs_t * UARTx)825 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_threshold(uart_regs_t *UARTx)
826 {
827 return (uint32_t)(READ_REG(UARTx->SRT));
828 }
829
830 /**
831 * @brief Get FIFO Transmission Level
832 *
833 * Register|BitsName
834 * --------|--------
835 * TFL | TFL
836 *
837 * @param UARTx UART instance
838 * @retval Returned value can be one of the following values:
839 */
ll_uart_get_tx_fifo_level(uart_regs_t * UARTx)840 __STATIC_INLINE uint32_t ll_uart_get_tx_fifo_level(uart_regs_t *UARTx)
841 {
842 return (uint32_t)(READ_REG(UARTx->TFL));
843 }
844
845 /**
846 * @brief Get FIFO reception Level
847 *
848 * Register|BitsName
849 * --------|--------
850 * RFL | RFL
851 *
852 * @param UARTx UART instance
853 * @retval Returned value can be one of the following values:
854 */
ll_uart_get_rx_fifo_level(uart_regs_t * UARTx)855 __STATIC_INLINE uint32_t ll_uart_get_rx_fifo_level(uart_regs_t *UARTx)
856 {
857 return (uint32_t)(READ_REG(UARTx->RFL));
858 }
859
860 /**
861 * @brief Flush Receive FIFO
862 *
863 * Register|BitsName
864 * --------|--------
865 * SRR | RFR
866 *
867 * @param UARTx UART instance
868 * @retval None
869 */
ll_uart_flush_rx_fifo(uart_regs_t * UARTx)870 __STATIC_INLINE void ll_uart_flush_rx_fifo(uart_regs_t *UARTx)
871 {
872 WRITE_REG(UARTx->SRR, UART_SRR_RFR);
873 }
874
875 /**
876 * @brief Flush Transmit FIFO
877 *
878 * Register|BitsName
879 * --------|--------
880 * SRR | XFR
881 *
882 * @param UARTx UART instance
883 * @retval None
884 */
ll_uart_flush_tx_fifo(uart_regs_t * UARTx)885 __STATIC_INLINE void ll_uart_flush_tx_fifo(uart_regs_t *UARTx)
886 {
887 WRITE_REG(UARTx->SRR, UART_SRR_XFR);
888 }
889
890 /**
891 * @brief Reset UART
892 * @note This function asynchronously resets the DW_apb_uart and synchronously
893 * removes the reset assertion. For a two clock implementation, both pclk
894 * and sclk domains will be reset.
895 *
896 * Register|BitsName
897 * --------|--------
898 * SRR | UR
899 *
900 * @param UARTx UART instance
901 * @retval None
902 */
ll_uart_reset(uart_regs_t * UARTx)903 __STATIC_INLINE void ll_uart_reset(uart_regs_t *UARTx)
904 {
905 WRITE_REG(UARTx->SRR, UART_SRR_UR);
906 }
907
908 /** @} */
909
910 /** @defgroup UART_LL_EF_IT_Management IT_Management
911 * @{
912 */
913
914 /**
915 * @brief Enable Modem Status Interrupt
916 *
917 * Register|BitsName
918 * --------|--------
919 * IER | EDSSI
920 *
921 * @param UARTx UART instance
922 * @retval None
923 */
ll_uart_enabled_it_ms(uart_regs_t * UARTx)924 __STATIC_INLINE void ll_uart_enabled_it_ms(uart_regs_t *UARTx)
925 {
926 SET_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
927 }
928
929 /**
930 * @brief Enable Receiver Line Status Interrupt
931 *
932 * Register|BitsName
933 * --------|--------
934 * IER | RLS
935 *
936 * @param UARTx UART instance
937 * @retval None
938 */
ll_uart_enable_it_rls(uart_regs_t * UARTx)939 __STATIC_INLINE void ll_uart_enable_it_rls(uart_regs_t *UARTx)
940 {
941 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
942 }
943
944 /**
945 * @brief Enable Transmit Holding Register Empty Interrupt
946 *
947 * Register|BitsName
948 * --------|--------
949 * IER | PTIME
950 * IER | ETBEI
951 *
952 * @param UARTx UART instance
953 * @retval None
954 */
ll_uart_enable_it_thre(uart_regs_t * UARTx)955 __STATIC_INLINE void ll_uart_enable_it_thre(uart_regs_t *UARTx)
956 {
957 SET_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
958 }
959
960 /**
961 * @brief Enable Received Data Available Interrupt and Character Timeout Interrupt
962 *
963 * Register|BitsName
964 * --------|--------
965 * IER | ERBFI
966 *
967 * @param UARTx UART instance
968 * @retval None
969 */
ll_uart_enable_it_rda(uart_regs_t * UARTx)970 __STATIC_INLINE void ll_uart_enable_it_rda(uart_regs_t *UARTx)
971 {
972 SET_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
973 }
974
975 /**
976 * @brief Disable Modem Status Interrupt
977 *
978 * Register|BitsName
979 * --------|--------
980 * IER | EDSSI
981 *
982 * @param UARTx UART instance
983 * @retval None
984 */
ll_uart_disable_it_ms(uart_regs_t * UARTx)985 __STATIC_INLINE void ll_uart_disable_it_ms(uart_regs_t *UARTx)
986 {
987 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI);
988 }
989
990 /**
991 * @brief Disable Receiver Line Status Interrupt
992 *
993 * Register|BitsName
994 * --------|--------
995 * IER | RLS
996 *
997 * @param UARTx UART instance
998 * @retval None
999 */
ll_uart_disable_it_rls(uart_regs_t * UARTx)1000 __STATIC_INLINE void ll_uart_disable_it_rls(uart_regs_t *UARTx)
1001 {
1002 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS);
1003 }
1004
1005 /**
1006 * @brief Disable Transmit Holding Register Empty Interrupt
1007 *
1008 * Register|BitsName
1009 * --------|--------
1010 * IER | PTIME
1011 * IER | ETBEI
1012 *
1013 * @param UARTx UART instance
1014 * @retval None
1015 */
ll_uart_disable_it_thre(uart_regs_t * UARTx)1016 __STATIC_INLINE void ll_uart_disable_it_thre(uart_regs_t *UARTx)
1017 {
1018 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI);
1019 }
1020
1021 /**
1022 * @brief Disable Received Data Available Interrupt and Character Timeout Interrupt
1023 *
1024 * Register|BitsName
1025 * --------|--------
1026 * IER | ERBFI
1027 *
1028 * @param UARTx UART instance
1029 * @retval None
1030 */
ll_uart_disable_it_rda(uart_regs_t * UARTx)1031 __STATIC_INLINE void ll_uart_disable_it_rda(uart_regs_t *UARTx)
1032 {
1033 CLEAR_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI);
1034 }
1035
1036 /**
1037 * @brief Check if the UART Modem Status Interrupt is enabled or disabled.
1038 *
1039 * Register|BitsName
1040 * --------|--------
1041 * IER | EDSSI
1042 *
1043 * @param UARTx UART instance
1044 * @retval State of bit (1 or 0).
1045 */
ll_uart_is_enabled_it_ms(uart_regs_t * UARTx)1046 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_ms(uart_regs_t *UARTx)
1047 {
1048 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_EDSSI) == (UART_IER_EDSSI));
1049 }
1050
1051 /**
1052 * @brief Check if the UART Receiver Line Status Interrupt is enabled or disabled.
1053 *
1054 * Register|BitsName
1055 * --------|--------
1056 * IER | RLS
1057 *
1058 * @param UARTx UART instance
1059 * @retval State of bit (1 or 0).
1060 */
ll_uart_is_enabled_it_rls(uart_regs_t * UARTx)1061 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rls(uart_regs_t *UARTx)
1062 {
1063 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERLS) == (UART_IER_ERLS));
1064 }
1065
1066 /**
1067 * @brief Check if the UART Transmit Holding Register Empty Interrupt is enabled or disabled.
1068 *
1069 * Register|BitsName
1070 * --------|--------
1071 * IER | PTIME
1072 * IER | ETBEI
1073 *
1074 * @param UARTx UART instance
1075 * @retval State of bit (1 or 0).
1076 */
ll_uart_is_enabled_it_thre(uart_regs_t * UARTx)1077 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_thre(uart_regs_t *UARTx)
1078 {
1079 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_PTIME | UART_IER_ETBEI) == \
1080 (UART_IER_PTIME | UART_IER_ETBEI));
1081 }
1082
1083 /**
1084 * @brief Check if the UART Received Data Available Interrupt and Character Timeout Interrupt
1085 * is enabled or disabled.
1086 *
1087 * Register|BitsName
1088 * --------|--------
1089 * IER | ERBFI
1090 *
1091 * @param UARTx UART instance
1092 * @retval State of bit (1 or 0).
1093 */
ll_uart_is_enabled_it_rda(uart_regs_t * UARTx)1094 __STATIC_INLINE uint32_t ll_uart_is_enabled_it_rda(uart_regs_t *UARTx)
1095 {
1096 return (READ_BITS(UARTx->DLH_IER.IER, UART_IER_ERBFI) == (UART_IER_ERBFI));
1097 }
1098
1099 /**
1100 * @brief Enable the specified UART Interrupt.
1101 *
1102 * Register|BitsName
1103 * --------|--------
1104 * IER | EDSSI
1105 * IER | ERLS
1106 * IER | PTIME
1107 * IER | ETBEI
1108 * IER | ERBFI
1109 *
1110 * @param UARTx UART instance
1111 * @param mask This parameter can be a combination of the following values:
1112 * @arg @ref LL_UART_IER_MS
1113 * @arg @ref LL_UART_IER_RLS
1114 * @arg @ref LL_UART_IER_THRE
1115 * @arg @ref LL_UART_IER_RDA
1116 * @retval None
1117 */
ll_uart_enable_it(uart_regs_t * UARTx,uint32_t mask)1118 __STATIC_INLINE void ll_uart_enable_it(uart_regs_t *UARTx, uint32_t mask)
1119 {
1120 SET_BITS(UARTx->DLH_IER.IER, mask);
1121 }
1122
1123 /**
1124 * @brief Disable the specified UART Interrupt.
1125 *
1126 * Register|BitsName
1127 * --------|--------
1128 * IER | EDSSI
1129 * IER | ERLS
1130 * IER | PTIME
1131 * IER | ETBEI
1132 * IER | ERBFI
1133 *
1134 * @param UARTx UART instance
1135 * @param mask This parameter can be a combination of the following values:
1136 * @arg @ref LL_UART_IER_MS
1137 * @arg @ref LL_UART_IER_RLS
1138 * @arg @ref LL_UART_IER_THRE
1139 * @arg @ref LL_UART_IER_RDA
1140 * @retval None
1141 */
ll_uart_disable_it(uart_regs_t * UARTx,uint32_t mask)1142 __STATIC_INLINE void ll_uart_disable_it(uart_regs_t *UARTx, uint32_t mask)
1143 {
1144 CLEAR_BITS(UARTx->DLH_IER.IER, mask);
1145 }
1146
1147 /**
1148 * @brief Check if the specified UART Interrupt is enabled or disabled.
1149 *
1150 * Register|BitsName
1151 * --------|--------
1152 * IER | EDSSI
1153 * IER | ERLS
1154 * IER | PTIME
1155 * IER | ETBEI
1156 * IER | ERBFI
1157 *
1158 * @param UARTx UART instance
1159 * @param mask This parameter can be a combination of the following values:
1160 * @arg @ref LL_UART_IER_MS
1161 * @arg @ref LL_UART_IER_RLS
1162 * @arg @ref LL_UART_IER_THRE
1163 * @arg @ref LL_UART_IER_RDA
1164 * @retval State of bit (1 or 0).
1165 */
ll_uart_is_enabled_it(uart_regs_t * UARTx,uint32_t mask)1166 __STATIC_INLINE uint32_t ll_uart_is_enabled_it(uart_regs_t *UARTx, uint32_t mask)
1167 {
1168 return (READ_BITS(UARTx->DLH_IER.IER, mask) == (mask));
1169 }
1170
1171 /** @} */
1172
1173 /** @defgroup UART_LL_EF_FLAG_Management FLAG_Management
1174 * @{
1175 */
1176
1177 /**
1178 * @brief Get UART Receive Line Status Flag
1179 * @note This function is used to get OE/PE/FE/BI/THRE/TEMT/RFE flags in LSR register.
1180 * After LSR register was read, OE/PE/FE/BI/RFE flags will be cleared.
1181 *
1182 * Register|BitsName
1183 * --------|--------
1184 * LSR | OE
1185 * LSR | PE
1186 * LSR | FE
1187 * LSR | BI
1188 * LSR | THRE
1189 * LSR | TEMT
1190 * LSR | RFE
1191 *
1192 * @param UARTx UART instance
1193 * @retval Returned value can be a combination of the following values:
1194 * @arg @ref LL_UART_LSR_OE
1195 * @arg @ref LL_UART_LSR_PE
1196 * @arg @ref LL_UART_LSR_FE
1197 * @arg @ref LL_UART_LSR_BI
1198 * @arg @ref LL_UART_LSR_THRE
1199 * @arg @ref LL_UART_LSR_TEMT
1200 * @arg @ref LL_UART_LSR_RFE
1201 */
ll_uart_get_line_status_flag(uart_regs_t * UARTx)1202 __STATIC_INLINE uint32_t ll_uart_get_line_status_flag(uart_regs_t *UARTx)
1203 {
1204 return ((uint32_t)READ_REG(UARTx->LSR));
1205 }
1206
1207 /**
1208 * @brief Clear UART Receive Line Status Flag
1209 * @note OE/PE/FE/BI/RFE flags can be cleared by reading LSR register.
1210 *
1211 * Register|BitsName
1212 * --------|--------
1213 * LSR | OE
1214 * LSR | PE
1215 * LSR | FE
1216 * LSR | BI
1217 * LSR | RFE
1218 *
1219 * @param UARTx UART instance
1220 * @retval None
1221 */
ll_uart_clear_line_status_flag(uart_regs_t * UARTx)1222 __STATIC_INLINE void ll_uart_clear_line_status_flag(uart_regs_t *UARTx)
1223 {
1224 __IO uint32_t tmpreg;
1225 tmpreg = READ_REG(UARTx->LSR);
1226 (void) tmpreg;
1227 }
1228
1229 /**
1230 * @brief Check if the UART Receive FIFO Full Flag is set or not
1231 *
1232 * Register|BitsName
1233 * --------|--------
1234 * USR | RFF
1235 *
1236 * @param UARTx UART instance
1237 * @retval State of bit (1 or 0).
1238 */
ll_uart_is_active_flag_rff(uart_regs_t * UARTx)1239 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rff(uart_regs_t *UARTx)
1240 {
1241 return (READ_BITS(UARTx->USR, UART_USR_RFF) == UART_USR_RFF);
1242 }
1243
1244 /**
1245 * @brief Check if the UART Receive FIFO Not Empty Flag is set or not
1246 *
1247 * Register|BitsName
1248 * --------|--------
1249 * USR | RFNE
1250 *
1251 * @param UARTx UART instance
1252 * @retval State of bit (1 or 0).
1253 */
ll_uart_is_active_flag_rfne(uart_regs_t * UARTx)1254 __STATIC_INLINE uint32_t ll_uart_is_active_flag_rfne(uart_regs_t *UARTx)
1255 {
1256 return (READ_BITS(UARTx->USR, UART_USR_RFNE) == UART_USR_RFNE);
1257 }
1258
1259 /**
1260 * @brief Check if the UART Transmit FIFO Empty Flag is set or not
1261 *
1262 * Register|BitsName
1263 * --------|--------
1264 * USR | TFE
1265 *
1266 * @param UARTx UART instance
1267 * @retval State of bit (1 or 0).
1268 */
ll_uart_is_active_flag_tfe(uart_regs_t * UARTx)1269 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfe(uart_regs_t *UARTx)
1270 {
1271 return (READ_BITS(UARTx->USR, UART_USR_TFE) == UART_USR_TFE);
1272 }
1273
1274 /**
1275 * @brief Check if the UART Transmit FIFO Not Full Flag is set or not
1276 *
1277 * Register|BitsName
1278 * --------|--------
1279 * USR | TFNF
1280 *
1281 * @param UARTx UART instance
1282 * @retval State of bit (1 or 0).
1283 */
ll_uart_is_active_flag_tfnf(uart_regs_t * UARTx)1284 __STATIC_INLINE uint32_t ll_uart_is_active_flag_tfnf(uart_regs_t *UARTx)
1285 {
1286 return (READ_BITS(UARTx->USR, UART_USR_TFNF) == UART_USR_TFNF);
1287 }
1288
1289 /**
1290 * @brief Get UART interrupt flags
1291 * @note The interrupt flags will be cleared after reading IIR.
1292 * If interrupt was triggered when reading IIR register, the interrupt will be pended,
1293 * and No Interrupt Pending Flag will be RESET, read IIR
1294 * again can get the pended interrupt
1295 *
1296 * Register|BitsName
1297 * --------|--------
1298 * IIR | IID
1299 *
1300 * @param UARTx UART instance
1301 * @retval Returned value can be one or combination of the following values:
1302 * @arg @ref LL_UART_IIR_MS
1303 * @arg @ref LL_UART_IIR_NIP
1304 * @arg @ref LL_UART_IIR_THRE
1305 * @arg @ref LL_UART_IIR_RDA
1306 * @arg @ref LL_UART_IIR_RLS
1307 * @arg @ref LL_UART_IIR_CTO
1308 */
ll_uart_get_it_flag(uart_regs_t * UARTx)1309 __STATIC_INLINE uint32_t ll_uart_get_it_flag(uart_regs_t *UARTx)
1310 {
1311 return (uint32_t)(READ_BITS(UARTx->FCR_IIR.IIR, UART_IIR_IID));
1312 }
1313
1314 /** @} */
1315
1316 /** @defgroup UART_LL_EF_DMA_Management DMA_Management
1317 * @{
1318 */
1319
1320 /**
1321 * @brief Get the data register address used for DMA transfer
1322 * @note The address of data register RBR is the same as the address of THR.
1323 *
1324 * Register|BitsName
1325 * --------|--------
1326 * RBR | RBR
1327 * THR | THR
1328 *
1329 * @param UARTx UART instance
1330 * @retval Address of data register
1331 */
ll_uart_dma_get_register_address(uart_regs_t * UARTx)1332 __STATIC_INLINE uint32_t ll_uart_dma_get_register_address(uart_regs_t *UARTx)
1333 {
1334 return ((uint32_t) &(UARTx->RBR_DLL_THR));
1335 }
1336
1337 /** @} */
1338
1339 /** @defgroup UART_LL_EF_Data_Management Data_Management
1340 * @{
1341 */
1342
1343 /**
1344 * @brief Read Receiver Data register (Receive Data value, 8 bits)
1345 *
1346 * Register|BitsName
1347 * --------|--------
1348 * RBR | RBR
1349 *
1350 * @param UARTx UART instance
1351 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1352 */
ll_uart_receive_data8(uart_regs_t * UARTx)1353 __STATIC_INLINE uint8_t ll_uart_receive_data8(uart_regs_t *UARTx)
1354 {
1355 return (uint8_t)(READ_REG(UARTx->RBR_DLL_THR.RBR));
1356 }
1357
1358 /**
1359 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
1360 *
1361 * Register|BitsName
1362 * --------|--------
1363 * THR | THR
1364 *
1365 * @param UARTx UART instance
1366 * @param value between Min_Data=0x00 and Max_Data=0xFF
1367 * @retval None
1368 */
ll_uart_transmit_data8(uart_regs_t * UARTx,uint8_t value)1369 __STATIC_INLINE void ll_uart_transmit_data8(uart_regs_t *UARTx, uint8_t value)
1370 {
1371 WRITE_REG(UARTx->RBR_DLL_THR.THR, value);
1372 }
1373
1374 /** @} */
1375
1376 /** @defgroup UART_LL_EF_Init Initialization and de-initialization functions
1377 * @{
1378 */
1379
1380 /**
1381 * @brief De-initialize UART registers (Registers restored to their default values).
1382 * @param UARTx UART instance
1383 * @retval An error_status_t enumeration value:
1384 * - SUCCESS: UART registers are de-initialized
1385 * - ERROR: UART registers are not de-initialized
1386 */
1387 error_status_t ll_uart_deinit(uart_regs_t *UARTx);
1388
1389 /**
1390 * @brief Initialize UART registers according to the specified
1391 * parameters in p_uart_init.
1392 * @param UARTx UART instance
1393 * @param p_uart_init Pointer to a ll_uart_init_t structure that contains the configuration
1394 * information for the specified UART peripheral.
1395 * @retval An error_status_t enumeration value:
1396 * - SUCCESS: UART registers are initialized according to p_uart_init content
1397 * - ERROR: Problem occurred during UART Registers initialization
1398 */
1399 error_status_t ll_uart_init(uart_regs_t *UARTx, ll_uart_init_t *p_uart_init);
1400
1401 /**
1402 * @brief Set each field of a @ref ll_uart_init_t type structure to default value.
1403 * @param p_uart_init Pointer to a @ref ll_uart_init_t structure
1404 * whose fields will be set to default values.
1405 * @retval None
1406 */
1407 void ll_uart_struct_init(ll_uart_init_t *p_uart_init);
1408
1409 /** @} */
1410
1411 /** @} */
1412
1413 #endif /* UART0 || UART1 */
1414
1415 #ifdef __cplusplus
1416 }
1417 #endif
1418
1419 #endif /* __GR55xx_LL_UART_H__ */
1420
1421 /** @} */
1422
1423 /** @} */
1424
1425 /** @} */
1426