1 /*
2 * Copyright (c) 2021 Bestechnic (Shanghai) Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15 #ifndef __HAL_UART_H__
16 #define __HAL_UART_H__
17
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21
22 #ifdef CHIP_HAS_UART
23
24 #include "plat_types.h"
25 #include "stdbool.h"
26 #include "stdint.h"
27 #include "hal_dma.h"
28
29 //#define BT_UART
30
31 #define HAL_UART_DMA_TRANSFER_STEP 0xFFF
32 #ifdef __KNOWLES
33 #define HAL_UART_DMA_TRANSFER_STEP_PINGPANG 640
34 #else
35 #define HAL_UART_DMA_TRANSFER_STEP_PINGPANG 4
36 #endif
37
38 enum HAL_UART_ID_T {
39 HAL_UART_ID_0 = 0,
40 #if (CHIP_HAS_UART >= 2)
41 HAL_UART_ID_1,
42 #endif
43 #if (CHIP_HAS_UART >= 3)
44 HAL_UART_ID_2,
45 #endif
46 #if (CHIP_HAS_UART >= 4)
47 HAL_UART_ID_3,
48 #endif
49 #ifdef BT_UART
50 HAL_UART_ID_BT,
51 #endif
52
53 HAL_UART_ID_QTY
54 };
55
56 enum HAL_UART_PARITY_T {
57 HAL_UART_PARITY_NONE,
58 HAL_UART_PARITY_ODD,
59 HAL_UART_PARITY_EVEN,
60 HAL_UART_PARITY_FORCE1,
61 HAL_UART_PARITY_FORCE0,
62 };
63
64 enum HAL_UART_STOP_BITS_T {
65 HAL_UART_STOP_BITS_1,
66 HAL_UART_STOP_BITS_2,
67 };
68
69 enum HAL_UART_DATA_BITS_T {
70 HAL_UART_DATA_BITS_5,
71 HAL_UART_DATA_BITS_6,
72 HAL_UART_DATA_BITS_7,
73 HAL_UART_DATA_BITS_8,
74 };
75
76 enum HAL_UART_FLOW_CONTROL_T {
77 HAL_UART_FLOW_CONTROL_NONE,
78 HAL_UART_FLOW_CONTROL_RTS,
79 HAL_UART_FLOW_CONTROL_CTS,
80 HAL_UART_FLOW_CONTROL_RTSCTS,
81 };
82
83 enum HAL_UART_FIFO_LEVEL_T {
84 HAL_UART_FIFO_LEVEL_1_8,
85 HAL_UART_FIFO_LEVEL_1_4,
86 HAL_UART_FIFO_LEVEL_1_2,
87 HAL_UART_FIFO_LEVEL_3_4,
88 HAL_UART_FIFO_LEVEL_7_8,
89 };
90
91 enum HAL_UART_XFER_TYPE_T {
92 HAL_UART_XFER_TYPE_TX = (1 << 0),
93 HAL_UART_XFER_TYPE_RX = (1 << 1),
94 };
95
96 struct HAL_UART_CFG_T {
97 enum HAL_UART_PARITY_T parity;
98 enum HAL_UART_STOP_BITS_T stop;
99 enum HAL_UART_DATA_BITS_T data;
100 enum HAL_UART_FLOW_CONTROL_T flow;
101 enum HAL_UART_FIFO_LEVEL_T rx_level;
102 enum HAL_UART_FIFO_LEVEL_T tx_level;
103 uint32_t baud;
104 bool dma_rx : 1;
105 bool dma_tx : 1;
106 bool dma_rx_stop_on_err : 1;
107 };
108
109 struct HAL_UART_BUF_T {
110 uint8_t *buf;
111 uint32_t len;
112 bool irq;
113 bool loop_hdr;
114 };
115
116 union HAL_UART_STATUS_T {
117 struct {
118 uint32_t FE :1; // frame error
119 uint32_t PE :1; // parity error
120 uint32_t BE :1; // break error
121 uint32_t OE :1; // overrun error
122 };
123 uint32_t reg;
124 };
125
126 union HAL_UART_FLAG_T {
127 struct {
128 uint32_t CTS :1;
129 uint32_t DSR :1;
130 uint32_t DCD :1;
131 uint32_t BUSY :1;
132 uint32_t RXFE :1; // rx fifo empty
133 uint32_t TXFF :1; // tx fifo full
134 uint32_t RXFF :1; // rx fifo full
135 uint32_t TXFE :1; // tx fifo empty
136 uint32_t RI :1; // ring indicator
137 };
138 uint32_t reg;
139 };
140
141 union HAL_UART_IRQ_T {
142 struct {
143 uint32_t RIM :1; // ri
144 uint32_t CTSM :1; // cts
145 uint32_t DCDM :1; // dcd
146 uint32_t DSRM :1; // dsr
147 uint32_t RX :1; // rx
148 uint32_t TX :1; // tx
149 uint32_t RT :1; // receive timeout
150 uint32_t FE :1; // framing error
151 uint32_t PE :1; // parity error
152 uint32_t BE :1; // break error
153 uint32_t OE :1; // overrun
154 };
155 uint32_t reg;
156 };
157
158 typedef void (*HAL_UART_IRQ_HANDLER_T)(enum HAL_UART_ID_T id, union HAL_UART_IRQ_T status);
159
160 typedef void (*HAL_UART_IRQ_RXDMA_HANDLER_T)(uint32_t xfer_size, int dma_error, union HAL_UART_IRQ_T status);
161
162 typedef void (*HAL_UART_IRQ_TXDMA_HANDLER_T)(uint32_t xfer_size, int dma_error);
163
164 int hal_uart_open(enum HAL_UART_ID_T id, const struct HAL_UART_CFG_T *cfg);
165
166 int hal_uart_reopen(enum HAL_UART_ID_T id, const struct HAL_UART_CFG_T *cfg);
167
168 int hal_uart_close(enum HAL_UART_ID_T id);
169
170 int hal_uart_opened(enum HAL_UART_ID_T id);
171
172 void hal_uart_sleep(void);
173
174 void hal_uart_wakeup(void);
175
176 int hal_uart_change_baud_rate(enum HAL_UART_ID_T id, uint32_t rate);
177
178 int hal_uart_pause(enum HAL_UART_ID_T id, enum HAL_UART_XFER_TYPE_T type);
179
180 int hal_uart_continue(enum HAL_UART_ID_T id, enum HAL_UART_XFER_TYPE_T type);
181
182 int hal_uart_readable(enum HAL_UART_ID_T id);
183
184 int hal_uart_writable(enum HAL_UART_ID_T id);
185
186 uint8_t hal_uart_getc(enum HAL_UART_ID_T id);
187
188 int hal_uart_putc(enum HAL_UART_ID_T id, uint8_t c);
189
190 uint8_t hal_uart_blocked_getc(enum HAL_UART_ID_T id);
191
192 int hal_uart_blocked_putc(enum HAL_UART_ID_T id, uint8_t c);
193
194 union HAL_UART_FLAG_T hal_uart_get_flag(enum HAL_UART_ID_T id);
195
196 union HAL_UART_STATUS_T hal_uart_get_status(enum HAL_UART_ID_T id);
197
198 void hal_uart_clear_status(enum HAL_UART_ID_T id);
199
200 void hal_uart_break_set(enum HAL_UART_ID_T id);
201
202 void hal_uart_break_clear(enum HAL_UART_ID_T id);
203
204 void hal_uart_flush(enum HAL_UART_ID_T id, uint32_t ticks);
205
206 union HAL_UART_IRQ_T hal_uart_get_raw_irq(enum HAL_UART_ID_T id);
207
208 void hal_uart_clear_irq(enum HAL_UART_ID_T id, union HAL_UART_IRQ_T irq);
209
210 union HAL_UART_IRQ_T hal_uart_irq_get_mask(enum HAL_UART_ID_T id);
211
212 union HAL_UART_IRQ_T hal_uart_irq_set_mask(enum HAL_UART_ID_T id, union HAL_UART_IRQ_T mask);
213
214 HAL_UART_IRQ_HANDLER_T hal_uart_irq_set_handler(enum HAL_UART_ID_T id, HAL_UART_IRQ_HANDLER_T handler);
215
216 void hal_uart_irq_set_dma_handler(enum HAL_UART_ID_T id, HAL_UART_IRQ_RXDMA_HANDLER_T rxdma, HAL_UART_IRQ_TXDMA_HANDLER_T txdma);
217
218 int hal_uart_dma_recv(enum HAL_UART_ID_T id, uint8_t *buf, uint32_t len,
219 struct HAL_DMA_DESC_T *desc, uint32_t *desc_cnt);
220
221 int hal_uart_dma_recv_pingpang(enum HAL_UART_ID_T id, uint8_t *buf, uint32_t len,
222 struct HAL_DMA_DESC_T *desc, uint32_t *desc_cnt);
223
224
225 int hal_uart_dma_recv_mask(enum HAL_UART_ID_T id, uint8_t *buf, uint32_t len,
226 struct HAL_DMA_DESC_T *desc, uint32_t *desc_cnt,
227 const union HAL_UART_IRQ_T *mask);
228
229 int hal_uart_dma_recv_mask_pingpang(enum HAL_UART_ID_T id, uint8_t *buf, uint32_t len,
230 struct HAL_DMA_DESC_T *desc, uint32_t *desc_cnt,
231 const union HAL_UART_IRQ_T *mask, uint32_t step);
232
233 int hal_uart_dma_recv_mask_stream(enum HAL_UART_ID_T id, uint8_t *buf, uint32_t len,
234 struct HAL_DMA_DESC_T *desc, uint32_t *desc_cnt,
235 const union HAL_UART_IRQ_T *mask, uint32_t step);
236
237 int hal_uart_dma_recv_mask_buf_list(enum HAL_UART_ID_T id, const struct HAL_UART_BUF_T *ubuf, uint32_t ucnt,
238 struct HAL_DMA_DESC_T *desc, uint32_t *desc_cnt, const union HAL_UART_IRQ_T *mask);
239
240 uint32_t hal_uart_get_dma_recv_addr(enum HAL_UART_ID_T id);
241
242 uint32_t hal_uart_stop_dma_recv(enum HAL_UART_ID_T id);
243
244 int hal_uart_dma_send(enum HAL_UART_ID_T id, const uint8_t *buf, uint32_t len,
245 struct HAL_DMA_DESC_T *desc, uint32_t *desc_cnt);
246
247 uint32_t hal_uart_stop_dma_send(enum HAL_UART_ID_T id);
248
249
250 // ========================================================================
251 // Test function
252
253 int hal_uart_printf_init(void);
254
255 void hal_uart_printf_output(const uint8_t *buf, uint32_t len);
256
hal_uart_output(const uint8_t * buf,uint32_t len)257 static inline void hal_uart_output(const uint8_t *buf, uint32_t len)
258 {
259 return hal_uart_printf_output(buf, len);
260 }
261
262 void hal_uart_printf(const char *fmt, ...);
263
264 #endif // CHIP_HAS_UART
265
266 #ifdef __cplusplus
267 }
268 #endif
269
270 #endif
271
272