1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Amlogic Meson Video Processing Unit driver
4 *
5 * Copyright (c) 2018 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 */
8
9 #include <edid.h>
10 #include "meson_vpu.h"
11
12 enum {
13 MESON_VENC_MODE_NONE = 0,
14 MESON_VENC_MODE_CVBS_PAL,
15 MESON_VENC_MODE_CVBS_NTSC,
16 MESON_VENC_MODE_HDMI,
17 };
18
19 enum meson_venc_source {
20 MESON_VENC_SOURCE_NONE = 0,
21 MESON_VENC_SOURCE_ENCI = 1,
22 MESON_VENC_SOURCE_ENCP = 2,
23 };
24
25 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
26 #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbb offset in data sheet */
27 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
28 #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */
29
30 struct meson_cvbs_enci_mode {
31 unsigned int mode_tag;
32 unsigned int hso_begin; /* HSO begin position */
33 unsigned int hso_end; /* HSO end position */
34 unsigned int vso_even; /* VSO even line */
35 unsigned int vso_odd; /* VSO odd line */
36 unsigned int macv_max_amp; /* Macrovision max amplitude */
37 unsigned int video_prog_mode;
38 unsigned int video_mode;
39 unsigned int sch_adjust;
40 unsigned int yc_delay;
41 unsigned int pixel_start;
42 unsigned int pixel_end;
43 unsigned int top_field_line_start;
44 unsigned int top_field_line_end;
45 unsigned int bottom_field_line_start;
46 unsigned int bottom_field_line_end;
47 unsigned int video_saturation;
48 unsigned int video_contrast;
49 unsigned int video_brightness;
50 unsigned int video_hue;
51 unsigned int analog_sync_adj;
52 };
53
54 struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
55 .mode_tag = MESON_VENC_MODE_CVBS_PAL,
56 .hso_begin = 3,
57 .hso_end = 129,
58 .vso_even = 3,
59 .vso_odd = 260,
60 .macv_max_amp = 7,
61 .video_prog_mode = 0xff,
62 .video_mode = 0x13,
63 .sch_adjust = 0x28,
64 .yc_delay = 0x343,
65 .pixel_start = 251,
66 .pixel_end = 1691,
67 .top_field_line_start = 22,
68 .top_field_line_end = 310,
69 .bottom_field_line_start = 23,
70 .bottom_field_line_end = 311,
71 .video_saturation = 9,
72 .video_contrast = 0,
73 .video_brightness = 0,
74 .video_hue = 0,
75 .analog_sync_adj = 0x8080,
76 };
77
78 struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
79 .mode_tag = MESON_VENC_MODE_CVBS_NTSC,
80 .hso_begin = 5,
81 .hso_end = 129,
82 .vso_even = 3,
83 .vso_odd = 260,
84 .macv_max_amp = 0xb,
85 .video_prog_mode = 0xf0,
86 .video_mode = 0x8,
87 .sch_adjust = 0x20,
88 .yc_delay = 0x333,
89 .pixel_start = 227,
90 .pixel_end = 1667,
91 .top_field_line_start = 18,
92 .top_field_line_end = 258,
93 .bottom_field_line_start = 19,
94 .bottom_field_line_end = 259,
95 .video_saturation = 18,
96 .video_contrast = 3,
97 .video_brightness = 0,
98 .video_hue = 0,
99 .analog_sync_adj = 0x9c00,
100 };
101
102 union meson_hdmi_venc_mode {
103 struct {
104 unsigned int mode_tag;
105 unsigned int hso_begin;
106 unsigned int hso_end;
107 unsigned int vso_even;
108 unsigned int vso_odd;
109 unsigned int macv_max_amp;
110 unsigned int video_prog_mode;
111 unsigned int video_mode;
112 unsigned int sch_adjust;
113 unsigned int yc_delay;
114 unsigned int pixel_start;
115 unsigned int pixel_end;
116 unsigned int top_field_line_start;
117 unsigned int top_field_line_end;
118 unsigned int bottom_field_line_start;
119 unsigned int bottom_field_line_end;
120 } enci;
121 struct {
122 unsigned int dvi_settings;
123 unsigned int video_mode;
124 unsigned int video_mode_adv;
125 unsigned int video_prog_mode;
126 bool video_prog_mode_present;
127 unsigned int video_sync_mode;
128 bool video_sync_mode_present;
129 unsigned int video_yc_dly;
130 bool video_yc_dly_present;
131 unsigned int video_rgb_ctrl;
132 bool video_rgb_ctrl_present;
133 unsigned int video_filt_ctrl;
134 bool video_filt_ctrl_present;
135 unsigned int video_ofld_voav_ofst;
136 bool video_ofld_voav_ofst_present;
137 unsigned int yfp1_htime;
138 unsigned int yfp2_htime;
139 unsigned int max_pxcnt;
140 unsigned int hspuls_begin;
141 unsigned int hspuls_end;
142 unsigned int hspuls_switch;
143 unsigned int vspuls_begin;
144 unsigned int vspuls_end;
145 unsigned int vspuls_bline;
146 unsigned int vspuls_eline;
147 unsigned int eqpuls_begin;
148 bool eqpuls_begin_present;
149 unsigned int eqpuls_end;
150 bool eqpuls_end_present;
151 unsigned int eqpuls_bline;
152 bool eqpuls_bline_present;
153 unsigned int eqpuls_eline;
154 bool eqpuls_eline_present;
155 unsigned int havon_begin;
156 unsigned int havon_end;
157 unsigned int vavon_bline;
158 unsigned int vavon_eline;
159 unsigned int hso_begin;
160 unsigned int hso_end;
161 unsigned int vso_begin;
162 unsigned int vso_end;
163 unsigned int vso_bline;
164 unsigned int vso_eline;
165 bool vso_eline_present;
166 unsigned int sy_val;
167 bool sy_val_present;
168 unsigned int sy2_val;
169 bool sy2_val_present;
170 unsigned int max_lncnt;
171 } encp;
172 };
173
174 union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
175 .enci = {
176 .hso_begin = 5,
177 .hso_end = 129,
178 .vso_even = 3,
179 .vso_odd = 260,
180 .macv_max_amp = 0xb,
181 .video_prog_mode = 0xf0,
182 .video_mode = 0x8,
183 .sch_adjust = 0x20,
184 .yc_delay = 0,
185 .pixel_start = 227,
186 .pixel_end = 1667,
187 .top_field_line_start = 18,
188 .top_field_line_end = 258,
189 .bottom_field_line_start = 19,
190 .bottom_field_line_end = 259,
191 },
192 };
193
194 union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
195 .enci = {
196 .hso_begin = 3,
197 .hso_end = 129,
198 .vso_even = 3,
199 .vso_odd = 260,
200 .macv_max_amp = 0x7,
201 .video_prog_mode = 0xff,
202 .video_mode = 0x13,
203 .sch_adjust = 0x28,
204 .yc_delay = 0x333,
205 .pixel_start = 251,
206 .pixel_end = 1691,
207 .top_field_line_start = 22,
208 .top_field_line_end = 310,
209 .bottom_field_line_start = 23,
210 .bottom_field_line_end = 311,
211 },
212 };
213
214 union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
215 .encp = {
216 .dvi_settings = 0x21,
217 .video_mode = 0x4000,
218 .video_mode_adv = 0x9,
219 .video_prog_mode = 0,
220 .video_prog_mode_present = true,
221 .video_sync_mode = 7,
222 .video_sync_mode_present = true,
223 /* video_yc_dly */
224 /* video_rgb_ctrl */
225 .video_filt_ctrl = 0x2052,
226 .video_filt_ctrl_present = true,
227 /* video_ofld_voav_ofst */
228 .yfp1_htime = 244,
229 .yfp2_htime = 1630,
230 .max_pxcnt = 1715,
231 .hspuls_begin = 0x22,
232 .hspuls_end = 0xa0,
233 .hspuls_switch = 88,
234 .vspuls_begin = 0,
235 .vspuls_end = 1589,
236 .vspuls_bline = 0,
237 .vspuls_eline = 5,
238 .havon_begin = 249,
239 .havon_end = 1689,
240 .vavon_bline = 42,
241 .vavon_eline = 521,
242 /* eqpuls_begin */
243 /* eqpuls_end */
244 /* eqpuls_bline */
245 /* eqpuls_eline */
246 .hso_begin = 3,
247 .hso_end = 5,
248 .vso_begin = 3,
249 .vso_end = 5,
250 .vso_bline = 0,
251 /* vso_eline */
252 .sy_val = 8,
253 .sy_val_present = true,
254 .sy2_val = 0x1d8,
255 .sy2_val_present = true,
256 .max_lncnt = 524,
257 },
258 };
259
260 union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
261 .encp = {
262 .dvi_settings = 0x21,
263 .video_mode = 0x4000,
264 .video_mode_adv = 0x9,
265 .video_prog_mode = 0,
266 .video_prog_mode_present = true,
267 .video_sync_mode = 7,
268 .video_sync_mode_present = true,
269 /* video_yc_dly */
270 /* video_rgb_ctrl */
271 .video_filt_ctrl = 0x52,
272 .video_filt_ctrl_present = true,
273 /* video_ofld_voav_ofst */
274 .yfp1_htime = 235,
275 .yfp2_htime = 1674,
276 .max_pxcnt = 1727,
277 .hspuls_begin = 0,
278 .hspuls_end = 0x80,
279 .hspuls_switch = 88,
280 .vspuls_begin = 0,
281 .vspuls_end = 1599,
282 .vspuls_bline = 0,
283 .vspuls_eline = 4,
284 .havon_begin = 235,
285 .havon_end = 1674,
286 .vavon_bline = 44,
287 .vavon_eline = 619,
288 /* eqpuls_begin */
289 /* eqpuls_end */
290 /* eqpuls_bline */
291 /* eqpuls_eline */
292 .hso_begin = 0x80,
293 .hso_end = 0,
294 .vso_begin = 0,
295 .vso_end = 5,
296 .vso_bline = 0,
297 /* vso_eline */
298 .sy_val = 8,
299 .sy_val_present = true,
300 .sy2_val = 0x1d8,
301 .sy2_val_present = true,
302 .max_lncnt = 624,
303 },
304 };
305
306 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
307 .encp = {
308 .dvi_settings = 0x2029,
309 .video_mode = 0x4040,
310 .video_mode_adv = 0x19,
311 /* video_prog_mode */
312 /* video_sync_mode */
313 /* video_yc_dly */
314 /* video_rgb_ctrl */
315 /* video_filt_ctrl */
316 /* video_ofld_voav_ofst */
317 .yfp1_htime = 648,
318 .yfp2_htime = 3207,
319 .max_pxcnt = 3299,
320 .hspuls_begin = 80,
321 .hspuls_end = 240,
322 .hspuls_switch = 80,
323 .vspuls_begin = 688,
324 .vspuls_end = 3248,
325 .vspuls_bline = 4,
326 .vspuls_eline = 8,
327 .havon_begin = 648,
328 .havon_end = 3207,
329 .vavon_bline = 29,
330 .vavon_eline = 748,
331 /* eqpuls_begin */
332 /* eqpuls_end */
333 /* eqpuls_bline */
334 /* eqpuls_eline */
335 .hso_begin = 256,
336 .hso_end = 168,
337 .vso_begin = 168,
338 .vso_end = 256,
339 .vso_bline = 0,
340 .vso_eline = 5,
341 .vso_eline_present = true,
342 /* sy_val */
343 /* sy2_val */
344 .max_lncnt = 749,
345 },
346 };
347
348 union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
349 .encp = {
350 .dvi_settings = 0x202d,
351 .video_mode = 0x4040,
352 .video_mode_adv = 0x19,
353 .video_prog_mode = 0x100,
354 .video_prog_mode_present = true,
355 .video_sync_mode = 0x407,
356 .video_sync_mode_present = true,
357 .video_yc_dly = 0,
358 .video_yc_dly_present = true,
359 /* video_rgb_ctrl */
360 /* video_filt_ctrl */
361 /* video_ofld_voav_ofst */
362 .yfp1_htime = 648,
363 .yfp2_htime = 3207,
364 .max_pxcnt = 3959,
365 .hspuls_begin = 80,
366 .hspuls_end = 240,
367 .hspuls_switch = 80,
368 .vspuls_begin = 688,
369 .vspuls_end = 3248,
370 .vspuls_bline = 4,
371 .vspuls_eline = 8,
372 .havon_begin = 648,
373 .havon_end = 3207,
374 .vavon_bline = 29,
375 .vavon_eline = 748,
376 /* eqpuls_begin */
377 /* eqpuls_end */
378 /* eqpuls_bline */
379 /* eqpuls_eline */
380 .hso_begin = 128,
381 .hso_end = 208,
382 .vso_begin = 128,
383 .vso_end = 128,
384 .vso_bline = 0,
385 .vso_eline = 5,
386 .vso_eline_present = true,
387 /* sy_val */
388 /* sy2_val */
389 .max_lncnt = 749,
390 },
391 };
392
393 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
394 .encp = {
395 .dvi_settings = 0x2029,
396 .video_mode = 0x5ffc,
397 .video_mode_adv = 0x19,
398 .video_prog_mode = 0x100,
399 .video_prog_mode_present = true,
400 .video_sync_mode = 0x207,
401 .video_sync_mode_present = true,
402 /* video_yc_dly */
403 /* video_rgb_ctrl */
404 /* video_filt_ctrl */
405 .video_ofld_voav_ofst = 0x11,
406 .video_ofld_voav_ofst_present = true,
407 .yfp1_htime = 516,
408 .yfp2_htime = 4355,
409 .max_pxcnt = 4399,
410 .hspuls_begin = 88,
411 .hspuls_end = 264,
412 .hspuls_switch = 88,
413 .vspuls_begin = 440,
414 .vspuls_end = 2200,
415 .vspuls_bline = 0,
416 .vspuls_eline = 4,
417 .havon_begin = 516,
418 .havon_end = 4355,
419 .vavon_bline = 20,
420 .vavon_eline = 559,
421 .eqpuls_begin = 2288,
422 .eqpuls_begin_present = true,
423 .eqpuls_end = 2464,
424 .eqpuls_end_present = true,
425 .eqpuls_bline = 0,
426 .eqpuls_bline_present = true,
427 .eqpuls_eline = 4,
428 .eqpuls_eline_present = true,
429 .hso_begin = 264,
430 .hso_end = 176,
431 .vso_begin = 88,
432 .vso_end = 88,
433 .vso_bline = 0,
434 .vso_eline = 5,
435 .vso_eline_present = true,
436 /* sy_val */
437 /* sy2_val */
438 .max_lncnt = 1124,
439 },
440 };
441
442 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
443 .encp = {
444 .dvi_settings = 0x202d,
445 .video_mode = 0x5ffc,
446 .video_mode_adv = 0x19,
447 .video_prog_mode = 0x100,
448 .video_prog_mode_present = true,
449 .video_sync_mode = 0x7,
450 .video_sync_mode_present = true,
451 /* video_yc_dly */
452 /* video_rgb_ctrl */
453 /* video_filt_ctrl */
454 .video_ofld_voav_ofst = 0x11,
455 .video_ofld_voav_ofst_present = true,
456 .yfp1_htime = 526,
457 .yfp2_htime = 4365,
458 .max_pxcnt = 5279,
459 .hspuls_begin = 88,
460 .hspuls_end = 264,
461 .hspuls_switch = 88,
462 .vspuls_begin = 440,
463 .vspuls_end = 2200,
464 .vspuls_bline = 0,
465 .vspuls_eline = 4,
466 .havon_begin = 526,
467 .havon_end = 4365,
468 .vavon_bline = 20,
469 .vavon_eline = 559,
470 .eqpuls_begin = 2288,
471 .eqpuls_begin_present = true,
472 .eqpuls_end = 2464,
473 .eqpuls_end_present = true,
474 .eqpuls_bline = 0,
475 .eqpuls_bline_present = true,
476 .eqpuls_eline = 4,
477 .eqpuls_eline_present = true,
478 .hso_begin = 142,
479 .hso_end = 230,
480 .vso_begin = 142,
481 .vso_end = 142,
482 .vso_bline = 0,
483 .vso_eline = 5,
484 .vso_eline_present = true,
485 /* sy_val */
486 /* sy2_val */
487 .max_lncnt = 1124,
488 },
489 };
490
491 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
492 .encp = {
493 .dvi_settings = 0xd,
494 .video_mode = 0x4040,
495 .video_mode_adv = 0x18,
496 .video_prog_mode = 0x100,
497 .video_prog_mode_present = true,
498 .video_sync_mode = 0x7,
499 .video_sync_mode_present = true,
500 .video_yc_dly = 0,
501 .video_yc_dly_present = true,
502 .video_rgb_ctrl = 2,
503 .video_rgb_ctrl_present = true,
504 .video_filt_ctrl = 0x1052,
505 .video_filt_ctrl_present = true,
506 /* video_ofld_voav_ofst */
507 .yfp1_htime = 271,
508 .yfp2_htime = 2190,
509 .max_pxcnt = 2749,
510 .hspuls_begin = 44,
511 .hspuls_end = 132,
512 .hspuls_switch = 44,
513 .vspuls_begin = 220,
514 .vspuls_end = 2140,
515 .vspuls_bline = 0,
516 .vspuls_eline = 4,
517 .havon_begin = 271,
518 .havon_end = 2190,
519 .vavon_bline = 41,
520 .vavon_eline = 1120,
521 /* eqpuls_begin */
522 /* eqpuls_end */
523 .eqpuls_bline = 0,
524 .eqpuls_bline_present = true,
525 .eqpuls_eline = 4,
526 .eqpuls_eline_present = true,
527 .hso_begin = 79,
528 .hso_end = 123,
529 .vso_begin = 79,
530 .vso_end = 79,
531 .vso_bline = 0,
532 .vso_eline = 5,
533 .vso_eline_present = true,
534 /* sy_val */
535 /* sy2_val */
536 .max_lncnt = 1124,
537 },
538 };
539
540 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
541 .encp = {
542 .dvi_settings = 0x1,
543 .video_mode = 0x4040,
544 .video_mode_adv = 0x18,
545 .video_prog_mode = 0x100,
546 .video_prog_mode_present = true,
547 /* video_sync_mode */
548 /* video_yc_dly */
549 /* video_rgb_ctrl */
550 .video_filt_ctrl = 0x1052,
551 .video_filt_ctrl_present = true,
552 /* video_ofld_voav_ofst */
553 .yfp1_htime = 140,
554 .yfp2_htime = 2060,
555 .max_pxcnt = 2199,
556 .hspuls_begin = 2156,
557 .hspuls_end = 44,
558 .hspuls_switch = 44,
559 .vspuls_begin = 140,
560 .vspuls_end = 2059,
561 .vspuls_bline = 0,
562 .vspuls_eline = 4,
563 .havon_begin = 148,
564 .havon_end = 2067,
565 .vavon_bline = 41,
566 .vavon_eline = 1120,
567 /* eqpuls_begin */
568 /* eqpuls_end */
569 /* eqpuls_bline */
570 /* eqpuls_eline */
571 .hso_begin = 44,
572 .hso_end = 2156,
573 .vso_begin = 2100,
574 .vso_end = 2164,
575 .vso_bline = 0,
576 .vso_eline = 5,
577 .vso_eline_present = true,
578 /* sy_val */
579 /* sy2_val */
580 .max_lncnt = 1124,
581 },
582 };
583
584 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
585 .encp = {
586 .dvi_settings = 0xd,
587 .video_mode = 0x4040,
588 .video_mode_adv = 0x18,
589 .video_prog_mode = 0x100,
590 .video_prog_mode_present = true,
591 .video_sync_mode = 0x7,
592 .video_sync_mode_present = true,
593 .video_yc_dly = 0,
594 .video_yc_dly_present = true,
595 .video_rgb_ctrl = 2,
596 .video_rgb_ctrl_present = true,
597 /* video_filt_ctrl */
598 /* video_ofld_voav_ofst */
599 .yfp1_htime = 271,
600 .yfp2_htime = 2190,
601 .max_pxcnt = 2639,
602 .hspuls_begin = 44,
603 .hspuls_end = 132,
604 .hspuls_switch = 44,
605 .vspuls_begin = 220,
606 .vspuls_end = 2140,
607 .vspuls_bline = 0,
608 .vspuls_eline = 4,
609 .havon_begin = 271,
610 .havon_end = 2190,
611 .vavon_bline = 41,
612 .vavon_eline = 1120,
613 /* eqpuls_begin */
614 /* eqpuls_end */
615 .eqpuls_bline = 0,
616 .eqpuls_bline_present = true,
617 .eqpuls_eline = 4,
618 .eqpuls_eline_present = true,
619 .hso_begin = 79,
620 .hso_end = 123,
621 .vso_begin = 79,
622 .vso_end = 79,
623 .vso_bline = 0,
624 .vso_eline = 5,
625 .vso_eline_present = true,
626 /* sy_val */
627 /* sy2_val */
628 .max_lncnt = 1124,
629 },
630 };
631
632 union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
633 .encp = {
634 .dvi_settings = 0x1,
635 .video_mode = 0x4040,
636 .video_mode_adv = 0x18,
637 .video_prog_mode = 0x100,
638 .video_prog_mode_present = true,
639 /* video_sync_mode */
640 /* video_yc_dly */
641 /* video_rgb_ctrl */
642 .video_filt_ctrl = 0x1052,
643 .video_filt_ctrl_present = true,
644 /* video_ofld_voav_ofst */
645 .yfp1_htime = 140,
646 .yfp2_htime = 2060,
647 .max_pxcnt = 2199,
648 .hspuls_begin = 2156,
649 .hspuls_end = 44,
650 .hspuls_switch = 44,
651 .vspuls_begin = 140,
652 .vspuls_end = 2059,
653 .vspuls_bline = 0,
654 .vspuls_eline = 4,
655 .havon_begin = 148,
656 .havon_end = 2067,
657 .vavon_bline = 41,
658 .vavon_eline = 1120,
659 /* eqpuls_begin */
660 /* eqpuls_end */
661 /* eqpuls_bline */
662 /* eqpuls_eline */
663 .hso_begin = 44,
664 .hso_end = 2156,
665 .vso_begin = 2100,
666 .vso_end = 2164,
667 .vso_bline = 0,
668 .vso_eline = 5,
669 .vso_eline_present = true,
670 /* sy_val */
671 /* sy2_val */
672 .max_lncnt = 1124,
673 },
674 };
675
to_signed(unsigned int a)676 static signed int to_signed(unsigned int a)
677 {
678 if (a <= 7)
679 return a;
680 else
681 return a - 16;
682 }
683
modulo(unsigned long a,unsigned long b)684 static unsigned long modulo(unsigned long a, unsigned long b)
685 {
686 if (a >= b)
687 return a - b;
688 else
689 return a;
690 }
691
meson_venc_hdmi_supported_mode(const struct display_timing * mode)692 bool meson_venc_hdmi_supported_mode(const struct display_timing *mode)
693 {
694 if (mode->flags & ~(DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_HSYNC_HIGH |
695 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH))
696 return false;
697
698 if (mode->hactive.typ < 640 || mode->hactive.typ > 1920)
699 return false;
700
701 if (mode->vactive.typ < 480 || mode->vactive.typ > 1200)
702 return false;
703
704 return true;
705 }
706
meson_venc_hdmi_get_dmt_vmode(const struct display_timing * mode,union meson_hdmi_venc_mode * dmt_mode)707 static void meson_venc_hdmi_get_dmt_vmode(const struct display_timing *mode,
708 union meson_hdmi_venc_mode *dmt_mode)
709 {
710 memset(dmt_mode, 0, sizeof(*dmt_mode));
711
712 dmt_mode->encp.dvi_settings = 0x21;
713 dmt_mode->encp.video_mode = 0x4040;
714 dmt_mode->encp.video_mode_adv = 0x18;
715
716 dmt_mode->encp.max_pxcnt = mode->hactive.typ +
717 mode->hfront_porch.typ +
718 mode->hback_porch.typ +
719 mode->hsync_len.typ - 1;
720
721 dmt_mode->encp.havon_begin = mode->hback_porch.typ +
722 mode->hsync_len.typ;
723
724 dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin +
725 mode->hactive.typ - 1;
726
727 dmt_mode->encp.vavon_bline = mode->vback_porch.typ +
728 mode->vsync_len.typ;
729 dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline +
730 mode->vactive.typ - 1;
731
732 /* to investigate */
733 dmt_mode->encp.hso_begin = 0;
734 dmt_mode->encp.hso_end = mode->hsync_len.typ;
735 dmt_mode->encp.vso_begin = 30;
736 dmt_mode->encp.vso_end = 50;
737
738 dmt_mode->encp.vso_bline = 0;
739 dmt_mode->encp.vso_eline = mode->vsync_len.typ;
740 dmt_mode->encp.vso_eline_present = true;
741
742 dmt_mode->encp.max_lncnt = mode->vactive.typ +
743 mode->vfront_porch.typ +
744 mode->vback_porch.typ +
745 mode->vsync_len.typ - 1;
746 }
747
meson_venc_hdmi_mode_set(struct meson_vpu_priv * priv,const struct display_timing * mode)748 static void meson_venc_hdmi_mode_set(struct meson_vpu_priv *priv,
749 const struct display_timing *mode)
750 {
751 union meson_hdmi_venc_mode *vmode = NULL;
752 union meson_hdmi_venc_mode vmode_dmt;
753 bool use_enci = false;
754 bool venc_repeat = false;
755 bool hdmi_repeat = false;
756 unsigned int venc_hdmi_latency = 2;
757 unsigned long total_pixels_venc = 0;
758 unsigned long active_pixels_venc = 0;
759 unsigned long front_porch_venc = 0;
760 unsigned long hsync_pixels_venc = 0;
761 unsigned long de_h_begin = 0;
762 unsigned long de_h_end = 0;
763 unsigned long de_v_begin_even = 0;
764 unsigned long de_v_end_even = 0;
765 unsigned long de_v_begin_odd = 0;
766 unsigned long de_v_end_odd = 0;
767 unsigned long hs_begin = 0;
768 unsigned long hs_end = 0;
769 unsigned long vs_adjust = 0;
770 unsigned long vs_bline_evn = 0;
771 unsigned long vs_eline_evn = 0;
772 unsigned long vs_bline_odd = 0;
773 unsigned long vs_eline_odd = 0;
774 unsigned long vso_begin_evn = 0;
775 unsigned long vso_begin_odd = 0;
776 unsigned int eof_lines;
777 unsigned int sof_lines;
778 unsigned int vsync_lines;
779 u32 reg;
780
781 /* Use VENCI for 480i and 576i and double HDMI pixels */
782 if (mode->flags & DISPLAY_FLAGS_DOUBLECLK) {
783 hdmi_repeat = true;
784 use_enci = true;
785 venc_hdmi_latency = 1;
786 }
787
788 meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
789 vmode = &vmode_dmt;
790 use_enci = false;
791
792 debug(" max_pxcnt %04d, max_lncnt %04d\n"
793 " havon_begin %04d, havon_end %04d\n"
794 " vavon_bline %04d, vavon_eline %04d\n"
795 " hso_begin %04d, hso_end %04d\n"
796 " vso_begin %04d, vso_end %04d\n"
797 " vso_bline %04d, vso_eline %04d\n",
798 vmode->encp.max_pxcnt, vmode->encp.max_lncnt,
799 vmode->encp.havon_begin, vmode->encp.havon_end,
800 vmode->encp.vavon_bline, vmode->encp.vavon_eline,
801 vmode->encp.hso_begin, vmode->encp.hso_end,
802 vmode->encp.vso_begin, vmode->encp.vso_end,
803 vmode->encp.vso_bline, vmode->encp.vso_eline);
804
805 eof_lines = mode->vfront_porch.typ;
806 if (mode->flags & DISPLAY_FLAGS_INTERLACED)
807 eof_lines /= 2;
808
809 sof_lines = mode->vback_porch.typ;
810 if (mode->flags & DISPLAY_FLAGS_INTERLACED)
811 sof_lines /= 2;
812
813 vsync_lines = mode->vsync_len.typ;
814 if (mode->flags & DISPLAY_FLAGS_INTERLACED)
815 vsync_lines /= 2;
816
817 total_pixels_venc = mode->hback_porch.typ + mode->hactive.typ +
818 mode->hfront_porch.typ + mode->hsync_len.typ;
819 if (hdmi_repeat)
820 total_pixels_venc /= 2;
821 if (venc_repeat)
822 total_pixels_venc *= 2;
823
824 active_pixels_venc = mode->hactive.typ;
825 if (hdmi_repeat)
826 active_pixels_venc /= 2;
827 if (venc_repeat)
828 active_pixels_venc *= 2;
829
830 front_porch_venc = mode->hfront_porch.typ;
831 if (hdmi_repeat)
832 front_porch_venc /= 2;
833 if (venc_repeat)
834 front_porch_venc *= 2;
835
836 hsync_pixels_venc = mode->hsync_len.typ;
837 if (hdmi_repeat)
838 hsync_pixels_venc /= 2;
839 if (venc_repeat)
840 hsync_pixels_venc *= 2;
841
842 /* Disable VDACs */
843 writel_bits(0xff, 0xff,
844 priv->io_base + _REG(VENC_VDAC_SETTING));
845
846 writel(0, priv->io_base + _REG(ENCI_VIDEO_EN));
847 writel(0, priv->io_base + _REG(ENCP_VIDEO_EN));
848
849 debug("use_enci: %d, hdmi_repeat: %d\n", use_enci, hdmi_repeat);
850
851 if (use_enci) {
852 unsigned int lines_f0;
853 unsigned int lines_f1;
854
855 /* CVBS Filter settings */
856 writel(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
857 priv->io_base + _REG(ENCI_CFILT_CTRL));
858 writel(ENCI_CFILT_CMPT_CR_DLY(2) |
859 ENCI_CFILT_CMPT_CB_DLY(1),
860 priv->io_base + _REG(ENCI_CFILT_CTRL2));
861
862 /* Digital Video Select : Interlace, clk27 clk, external */
863 writel(0, priv->io_base + _REG(VENC_DVI_SETTING));
864
865 /* Reset Video Mode */
866 writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
867 writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
868
869 /* Horizontal sync signal output */
870 writel(vmode->enci.hso_begin,
871 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
872 writel(vmode->enci.hso_end,
873 priv->io_base + _REG(ENCI_SYNC_HSO_END));
874
875 /* Vertical Sync lines */
876 writel(vmode->enci.vso_even,
877 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
878 writel(vmode->enci.vso_odd,
879 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
880
881 /* Macrovision max amplitude change */
882 writel(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
883 ENCI_MACV_MAX_AMP_VAL(vmode->enci.macv_max_amp),
884 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
885
886 /* Video mode */
887 writel(vmode->enci.video_prog_mode,
888 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
889 writel(vmode->enci.video_mode,
890 priv->io_base + _REG(ENCI_VIDEO_MODE));
891
892 /*
893 * Advanced Video Mode :
894 * Demux shifting 0x2
895 * Blank line end at line17/22
896 * High bandwidth Luma Filter
897 * Low bandwidth Chroma Filter
898 * Bypass luma low pass filter
899 * No macrovision on CSYNC
900 */
901 writel(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
902 ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
903 ENCI_VIDEO_MODE_ADV_YBW_HIGH,
904 priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
905
906 writel(vmode->enci.sch_adjust,
907 priv->io_base + _REG(ENCI_VIDEO_SCH));
908
909 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
910 writel(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
911
912 if (vmode->enci.yc_delay)
913 writel(vmode->enci.yc_delay,
914 priv->io_base + _REG(ENCI_YC_DELAY));
915
916 /* UNreset Interlaced TV Encoder */
917 writel(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
918
919 /*
920 * Enable Vfifo2vd and set Y_Cb_Y_Cr:
921 * Corresponding value:
922 * Y => 00 or 10
923 * Cb => 01
924 * Cr => 11
925 * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
926 */
927 writel(ENCI_VFIFO2VD_CTL_ENABLE |
928 ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
929 priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
930
931 /* Timings */
932 writel(vmode->enci.pixel_start,
933 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
934 writel(vmode->enci.pixel_end,
935 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
936
937 writel(vmode->enci.top_field_line_start,
938 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
939 writel(vmode->enci.top_field_line_end,
940 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
941
942 writel(vmode->enci.bottom_field_line_start,
943 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
944 writel(vmode->enci.bottom_field_line_end,
945 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
946
947 /* Select ENCI for VIU */
948 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
949
950 /* Interlace video enable */
951 writel(ENCI_VIDEO_EN_ENABLE,
952 priv->io_base + _REG(ENCI_VIDEO_EN));
953
954 lines_f0 = mode->vback_porch.typ + mode->vactive.typ +
955 mode->vback_porch.typ + mode->vsync_len.typ;
956 lines_f0 = lines_f0 >> 1;
957 lines_f1 = lines_f0 + 1;
958
959 de_h_begin = modulo(readl(priv->io_base +
960 _REG(ENCI_VFIFO2VD_PIXEL_START))
961 + venc_hdmi_latency,
962 total_pixels_venc);
963 de_h_end = modulo(de_h_begin + active_pixels_venc,
964 total_pixels_venc);
965
966 writel(de_h_begin,
967 priv->io_base + _REG(ENCI_DE_H_BEGIN));
968 writel(de_h_end,
969 priv->io_base + _REG(ENCI_DE_H_END));
970
971 de_v_begin_even = readl(priv->io_base +
972 _REG(ENCI_VFIFO2VD_LINE_TOP_START));
973 de_v_end_even = de_v_begin_even + mode->vactive.typ;
974 de_v_begin_odd = readl(priv->io_base +
975 _REG(ENCI_VFIFO2VD_LINE_BOT_START));
976 de_v_end_odd = de_v_begin_odd + mode->vactive.typ;
977
978 writel(de_v_begin_even,
979 priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
980 writel(de_v_end_even,
981 priv->io_base + _REG(ENCI_DE_V_END_EVEN));
982 writel(de_v_begin_odd,
983 priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
984 writel(de_v_end_odd,
985 priv->io_base + _REG(ENCI_DE_V_END_ODD));
986
987 /* Program Hsync timing */
988 hs_begin = de_h_end + front_porch_venc;
989 if (de_h_end + front_porch_venc >= total_pixels_venc) {
990 hs_begin -= total_pixels_venc;
991 vs_adjust = 1;
992 } else {
993 hs_begin = de_h_end + front_porch_venc;
994 vs_adjust = 0;
995 }
996
997 hs_end = modulo(hs_begin + hsync_pixels_venc,
998 total_pixels_venc);
999 writel(hs_begin,
1000 priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
1001 writel(hs_end,
1002 priv->io_base + _REG(ENCI_DVI_HSO_END));
1003
1004 /* Program Vsync timing for even field */
1005 if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) {
1006 vs_bline_evn = (de_v_end_odd - 1)
1007 + eof_lines
1008 + vs_adjust
1009 - lines_f1;
1010 vs_eline_evn = vs_bline_evn + vsync_lines;
1011
1012 writel(vs_bline_evn,
1013 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1014
1015 writel(vs_eline_evn,
1016 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
1017
1018 writel(hs_begin,
1019 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1020 writel(hs_begin,
1021 priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
1022 } else {
1023 vs_bline_odd = (de_v_end_odd - 1)
1024 + eof_lines
1025 + vs_adjust;
1026
1027 writel(vs_bline_odd,
1028 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1029
1030 writel(hs_begin,
1031 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1032
1033 if ((vs_bline_odd + vsync_lines) >= lines_f1) {
1034 vs_eline_evn = vs_bline_odd
1035 + vsync_lines
1036 - lines_f1;
1037
1038 writel(vs_eline_evn, priv->io_base
1039 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1040
1041 writel(hs_begin, priv->io_base
1042 + _REG(ENCI_DVI_VSO_END_EVN));
1043 } else {
1044 vs_eline_odd = vs_bline_odd
1045 + vsync_lines;
1046
1047 writel(vs_eline_odd, priv->io_base
1048 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1049
1050 writel(hs_begin, priv->io_base
1051 + _REG(ENCI_DVI_VSO_END_ODD));
1052 }
1053 }
1054
1055 /* Program Vsync timing for odd field */
1056 if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) {
1057 vs_bline_odd = (de_v_end_even - 1)
1058 + (eof_lines + 1)
1059 - lines_f0;
1060 vs_eline_odd = vs_bline_odd + vsync_lines;
1061
1062 writel(vs_bline_odd,
1063 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
1064
1065 writel(vs_eline_odd,
1066 priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
1067
1068 vso_begin_odd = modulo(hs_begin
1069 + (total_pixels_venc >> 1),
1070 total_pixels_venc);
1071
1072 writel(vso_begin_odd,
1073 priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
1074 writel(vso_begin_odd,
1075 priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
1076 } else {
1077 vs_bline_evn = (de_v_end_even - 1)
1078 + (eof_lines + 1);
1079
1080 writel(vs_bline_evn,
1081 priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
1082
1083 vso_begin_evn = modulo(hs_begin
1084 + (total_pixels_venc >> 1),
1085 total_pixels_venc);
1086
1087 writel(vso_begin_evn, priv->io_base
1088 + _REG(ENCI_DVI_VSO_BEGIN_EVN));
1089
1090 if (vs_bline_evn + vsync_lines >= lines_f0) {
1091 vs_eline_odd = vs_bline_evn
1092 + vsync_lines
1093 - lines_f0;
1094
1095 writel(vs_eline_odd, priv->io_base
1096 + _REG(ENCI_DVI_VSO_ELINE_ODD));
1097
1098 writel(vso_begin_evn, priv->io_base
1099 + _REG(ENCI_DVI_VSO_END_ODD));
1100 } else {
1101 vs_eline_evn = vs_bline_evn + vsync_lines;
1102
1103 writel(vs_eline_evn, priv->io_base
1104 + _REG(ENCI_DVI_VSO_ELINE_EVN));
1105
1106 writel(vso_begin_evn, priv->io_base
1107 + _REG(ENCI_DVI_VSO_END_EVN));
1108 }
1109 }
1110 } else {
1111 writel(vmode->encp.dvi_settings,
1112 priv->io_base + _REG(VENC_DVI_SETTING));
1113 writel(vmode->encp.video_mode,
1114 priv->io_base + _REG(ENCP_VIDEO_MODE));
1115 writel(vmode->encp.video_mode_adv,
1116 priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
1117 if (vmode->encp.video_prog_mode_present)
1118 writel(vmode->encp.video_prog_mode,
1119 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1120 if (vmode->encp.video_sync_mode_present)
1121 writel(vmode->encp.video_sync_mode,
1122 priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
1123 if (vmode->encp.video_yc_dly_present)
1124 writel(vmode->encp.video_yc_dly,
1125 priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
1126 if (vmode->encp.video_rgb_ctrl_present)
1127 writel(vmode->encp.video_rgb_ctrl,
1128 priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
1129 if (vmode->encp.video_filt_ctrl_present)
1130 writel(vmode->encp.video_filt_ctrl,
1131 priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
1132 if (vmode->encp.video_ofld_voav_ofst_present)
1133 writel(vmode->encp.video_ofld_voav_ofst,
1134 priv->io_base
1135 + _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1136 writel(vmode->encp.yfp1_htime,
1137 priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
1138 writel(vmode->encp.yfp2_htime,
1139 priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
1140 writel(vmode->encp.max_pxcnt,
1141 priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
1142 writel(vmode->encp.hspuls_begin,
1143 priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
1144 writel(vmode->encp.hspuls_end,
1145 priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
1146 writel(vmode->encp.hspuls_switch,
1147 priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
1148 writel(vmode->encp.vspuls_begin,
1149 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
1150 writel(vmode->encp.vspuls_end,
1151 priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
1152 writel(vmode->encp.vspuls_bline,
1153 priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
1154 writel(vmode->encp.vspuls_eline,
1155 priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
1156 if (vmode->encp.eqpuls_begin_present)
1157 writel(vmode->encp.eqpuls_begin,
1158 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
1159 if (vmode->encp.eqpuls_end_present)
1160 writel(vmode->encp.eqpuls_end,
1161 priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
1162 if (vmode->encp.eqpuls_bline_present)
1163 writel(vmode->encp.eqpuls_bline,
1164 priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
1165 if (vmode->encp.eqpuls_eline_present)
1166 writel(vmode->encp.eqpuls_eline,
1167 priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
1168 writel(vmode->encp.havon_begin,
1169 priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
1170 writel(vmode->encp.havon_end,
1171 priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
1172 writel(vmode->encp.vavon_bline,
1173 priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
1174 writel(vmode->encp.vavon_eline,
1175 priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
1176 writel(vmode->encp.hso_begin,
1177 priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
1178 writel(vmode->encp.hso_end,
1179 priv->io_base + _REG(ENCP_VIDEO_HSO_END));
1180 writel(vmode->encp.vso_begin,
1181 priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
1182 writel(vmode->encp.vso_end,
1183 priv->io_base + _REG(ENCP_VIDEO_VSO_END));
1184 writel(vmode->encp.vso_bline,
1185 priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
1186 if (vmode->encp.vso_eline_present)
1187 writel(vmode->encp.vso_eline,
1188 priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
1189 if (vmode->encp.sy_val_present)
1190 writel(vmode->encp.sy_val,
1191 priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
1192 if (vmode->encp.sy2_val_present)
1193 writel(vmode->encp.sy2_val,
1194 priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
1195 writel(vmode->encp.max_lncnt,
1196 priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
1197
1198 writel(1, priv->io_base + _REG(ENCP_VIDEO_EN));
1199
1200 /* Set DE signal's polarity is active high */
1201 writel_bits(ENCP_VIDEO_MODE_DE_V_HIGH,
1202 ENCP_VIDEO_MODE_DE_V_HIGH,
1203 priv->io_base + _REG(ENCP_VIDEO_MODE));
1204
1205 /* Program DE timing */
1206 de_h_begin = modulo(readl(priv->io_base +
1207 _REG(ENCP_VIDEO_HAVON_BEGIN))
1208 + venc_hdmi_latency,
1209 total_pixels_venc);
1210 de_h_end = modulo(de_h_begin + active_pixels_venc,
1211 total_pixels_venc);
1212
1213 writel(de_h_begin,
1214 priv->io_base + _REG(ENCP_DE_H_BEGIN));
1215 writel(de_h_end,
1216 priv->io_base + _REG(ENCP_DE_H_END));
1217
1218 /* Program DE timing for even field */
1219 de_v_begin_even = readl(priv->io_base
1220 + _REG(ENCP_VIDEO_VAVON_BLINE));
1221 if (mode->flags & DISPLAY_FLAGS_INTERLACED)
1222 de_v_end_even = de_v_begin_even +
1223 (mode->vactive.typ / 2);
1224 else
1225 de_v_end_even = de_v_begin_even + mode->vactive.typ;
1226
1227 writel(de_v_begin_even,
1228 priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
1229 writel(de_v_end_even,
1230 priv->io_base + _REG(ENCP_DE_V_END_EVEN));
1231
1232 /* Program DE timing for odd field if needed */
1233 if (mode->flags & DISPLAY_FLAGS_INTERLACED) {
1234 unsigned int ofld_voav_ofst =
1235 readl(priv->io_base +
1236 _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
1237 de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)
1238 + de_v_begin_even
1239 + ((mode->vfront_porch.typ +
1240 mode->vactive.typ +
1241 mode->vsync_len.typ - 1) / 2);
1242 de_v_end_odd = de_v_begin_odd + (mode->vactive.typ / 2);
1243
1244 writel(de_v_begin_odd,
1245 priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
1246 writel(de_v_end_odd,
1247 priv->io_base + _REG(ENCP_DE_V_END_ODD));
1248 }
1249
1250 /* Program Hsync timing */
1251 if ((de_h_end + front_porch_venc) >= total_pixels_venc) {
1252 hs_begin = de_h_end
1253 + front_porch_venc
1254 - total_pixels_venc;
1255 vs_adjust = 1;
1256 } else {
1257 hs_begin = de_h_end
1258 + front_porch_venc;
1259 vs_adjust = 0;
1260 }
1261
1262 hs_end = modulo(hs_begin + hsync_pixels_venc,
1263 total_pixels_venc);
1264
1265 writel(hs_begin,
1266 priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
1267 writel(hs_end,
1268 priv->io_base + _REG(ENCP_DVI_HSO_END));
1269
1270 /* Program Vsync timing for even field */
1271 if (de_v_begin_even >=
1272 (sof_lines + vsync_lines + (1 - vs_adjust)))
1273 vs_bline_evn = de_v_begin_even
1274 - sof_lines
1275 - vsync_lines
1276 - (1 - vs_adjust);
1277 else
1278 vs_bline_evn = (mode->vfront_porch.typ +
1279 mode->vactive.typ +
1280 mode->vsync_len.typ) +
1281 + de_v_begin_even
1282 - sof_lines
1283 - vsync_lines
1284 - (1 - vs_adjust);
1285
1286 vs_eline_evn = modulo(vs_bline_evn + vsync_lines,
1287 mode->hfront_porch.typ +
1288 mode->hactive.typ +
1289 mode->hsync_len.typ);
1290
1291 writel(vs_bline_evn,
1292 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
1293 writel(vs_eline_evn,
1294 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
1295
1296 vso_begin_evn = hs_begin;
1297 writel(vso_begin_evn,
1298 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
1299 writel(vso_begin_evn,
1300 priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
1301
1302 /* Program Vsync timing for odd field if needed */
1303 if (mode->flags & DISPLAY_FLAGS_INTERLACED) {
1304 vs_bline_odd = (de_v_begin_odd - 1)
1305 - sof_lines
1306 - vsync_lines;
1307 vs_eline_odd = (de_v_begin_odd - 1)
1308 - vsync_lines;
1309 vso_begin_odd = modulo(hs_begin
1310 + (total_pixels_venc >> 1),
1311 total_pixels_venc);
1312
1313 writel(vs_bline_odd,
1314 priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
1315 writel(vs_eline_odd,
1316 priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
1317 writel(vso_begin_odd,
1318 priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
1319 writel(vso_begin_odd,
1320 priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
1321 }
1322
1323 /* Select ENCP for VIU */
1324 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
1325 }
1326
1327 /* Set VPU HDMI setting */
1328 /* Select ENCP or ENCI data to HDMI */
1329 if (use_enci)
1330 reg = VPU_HDMI_ENCI_DATA_TO_HDMI;
1331 else
1332 reg = VPU_HDMI_ENCP_DATA_TO_HDMI;
1333
1334 /* Invert polarity of HSYNC from VENC */
1335 if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
1336 reg |= VPU_HDMI_INV_HSYNC;
1337
1338 /* Invert polarity of VSYNC from VENC */
1339 if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
1340 reg |= VPU_HDMI_INV_VSYNC;
1341
1342 /* Output data format: CbYCr */
1343 reg |= VPU_HDMI_OUTPUT_CBYCR;
1344
1345 /*
1346 * Write rate to the async FIFO between VENC and HDMI.
1347 * One write every 2 wr_clk.
1348 */
1349 if (venc_repeat)
1350 reg |= VPU_HDMI_WR_RATE(2);
1351
1352 /*
1353 * Read rate to the async FIFO between VENC and HDMI.
1354 * One read every 2 wr_clk.
1355 */
1356 if (hdmi_repeat)
1357 reg |= VPU_HDMI_RD_RATE(2);
1358
1359 writel(reg, priv->io_base + _REG(VPU_HDMI_SETTING));
1360 }
1361
meson_venci_cvbs_mode_set(struct meson_vpu_priv * priv,struct meson_cvbs_enci_mode * mode)1362 static void meson_venci_cvbs_mode_set(struct meson_vpu_priv *priv,
1363 struct meson_cvbs_enci_mode *mode)
1364 {
1365 u32 reg;
1366
1367 /* CVBS Filter settings */
1368 writel(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
1369 priv->io_base + _REG(ENCI_CFILT_CTRL));
1370 writel(ENCI_CFILT_CMPT_CR_DLY(2) |
1371 ENCI_CFILT_CMPT_CB_DLY(1),
1372 priv->io_base + _REG(ENCI_CFILT_CTRL2));
1373
1374 /* Digital Video Select : Interlace, clk27 clk, external */
1375 writel(0, priv->io_base + _REG(VENC_DVI_SETTING));
1376
1377 /* Reset Video Mode */
1378 writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1379 writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1380
1381 /* Horizontal sync signal output */
1382 writel(mode->hso_begin,
1383 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
1384 writel(mode->hso_end,
1385 priv->io_base + _REG(ENCI_SYNC_HSO_END));
1386
1387 /* Vertical Sync lines */
1388 writel(mode->vso_even,
1389 priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
1390 writel(mode->vso_odd,
1391 priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
1392
1393 /* Macrovision max amplitude change */
1394 writel(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
1395 ENCI_MACV_MAX_AMP_VAL(mode->macv_max_amp),
1396 priv->io_base + _REG(ENCI_MACV_MAX_AMP));
1397
1398 /* Video mode */
1399 writel(mode->video_prog_mode,
1400 priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
1401 writel(mode->video_mode,
1402 priv->io_base + _REG(ENCI_VIDEO_MODE));
1403
1404 /*
1405 * Advanced Video Mode :
1406 * Demux shifting 0x2
1407 * Blank line end at line17/22
1408 * High bandwidth Luma Filter
1409 * Low bandwidth Chroma Filter
1410 * Bypass luma low pass filter
1411 * No macrovision on CSYNC
1412 */
1413 writel(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
1414 ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
1415 ENCI_VIDEO_MODE_ADV_YBW_HIGH,
1416 priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1417
1418 writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
1419
1420 /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
1421 writel(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
1422
1423 /* 0x3 Y, C, and Component Y delay */
1424 writel(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
1425
1426 /* Timings */
1427 writel(mode->pixel_start,
1428 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
1429 writel(mode->pixel_end,
1430 priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
1431
1432 writel(mode->top_field_line_start,
1433 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
1434 writel(mode->top_field_line_end,
1435 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
1436
1437 writel(mode->bottom_field_line_start,
1438 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
1439 writel(mode->bottom_field_line_end,
1440 priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
1441
1442 /* Internal Venc, Internal VIU Sync, Internal Vencoder */
1443 writel(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
1444
1445 /* UNreset Interlaced TV Encoder */
1446 writel(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
1447
1448 /*
1449 * Enable Vfifo2vd and set Y_Cb_Y_Cr:
1450 * Corresponding value:
1451 * Y => 00 or 10
1452 * Cb => 01
1453 * Cr => 11
1454 * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
1455 */
1456 writel(ENCI_VFIFO2VD_CTL_ENABLE |
1457 ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
1458 priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
1459
1460 /* Power UP Dacs */
1461 writel(0, priv->io_base + _REG(VENC_VDAC_SETTING));
1462
1463 /* Video Upsampling */
1464 /*
1465 * CTRL0, CTRL1 and CTRL2:
1466 * Filter0: input data sample every 2 cloks
1467 * Filter1: filtering and upsample enable
1468 */
1469 reg = VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO | VENC_UPSAMPLE_CTRL_F1_EN |
1470 VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN;
1471
1472 /*
1473 * Upsample CTRL0:
1474 * Interlace High Bandwidth Luma
1475 */
1476 writel(VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA | reg,
1477 priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
1478
1479 /*
1480 * Upsample CTRL1:
1481 * Interlace Pb
1482 */
1483 writel(VENC_UPSAMPLE_CTRL_INTERLACE_PB | reg,
1484 priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
1485
1486 /*
1487 * Upsample CTRL2:
1488 * Interlace R
1489 */
1490 writel(VENC_UPSAMPLE_CTRL_INTERLACE_PR | reg,
1491 priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
1492
1493 /* Select Interlace Y DACs */
1494 writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
1495 writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
1496 writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
1497 writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
1498 writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
1499 writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
1500
1501 /* Select ENCI for VIU */
1502 meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
1503
1504 /* Enable ENCI FIFO */
1505 writel(VENC_VDAC_FIFO_EN_ENCI_ENABLE,
1506 priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
1507
1508 /* Select ENCI DACs 0, 1, 4, and 5 */
1509 writel(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
1510 writel(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
1511
1512 /* Interlace video enable */
1513 writel(ENCI_VIDEO_EN_ENABLE,
1514 priv->io_base + _REG(ENCI_VIDEO_EN));
1515
1516 /* Configure Video Saturation / Contrast / Brightness / Hue */
1517 writel(mode->video_saturation,
1518 priv->io_base + _REG(ENCI_VIDEO_SAT));
1519 writel(mode->video_contrast,
1520 priv->io_base + _REG(ENCI_VIDEO_CONT));
1521 writel(mode->video_brightness,
1522 priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
1523 writel(mode->video_hue,
1524 priv->io_base + _REG(ENCI_VIDEO_HUE));
1525
1526 /* Enable DAC0 Filter */
1527 writel(VENC_VDAC_DAC0_FILT_CTRL0_EN,
1528 priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
1529 writel(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
1530
1531 /* 0 in Macrovision register 0 */
1532 writel(0, priv->io_base + _REG(ENCI_MACV_N0));
1533
1534 /* Analog Synchronization and color burst value adjust */
1535 writel(mode->analog_sync_adj,
1536 priv->io_base + _REG(ENCI_SYNC_ADJ));
1537
1538 /* enable VDAC */
1539 writel_bits(VENC_VDAC_SEL_ATV_DMD, 0,
1540 priv->io_base + _REG(VENC_VDAC_DACSEL0));
1541
1542 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
1543 hhi_write(HHI_VDAC_CNTL0, 1);
1544 else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
1545 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
1546 hhi_write(HHI_VDAC_CNTL0, 0xf0001);
1547 else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
1548 hhi_write(HHI_VDAC_CNTL0_G12A, 0x906001);
1549
1550 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
1551 hhi_write(HHI_VDAC_CNTL1_G12A, 0);
1552 else
1553 hhi_write(HHI_VDAC_CNTL1, 0);
1554 }
1555
meson_vpu_setup_venc(struct udevice * dev,const struct display_timing * mode,bool is_cvbs)1556 void meson_vpu_setup_venc(struct udevice *dev,
1557 const struct display_timing *mode, bool is_cvbs)
1558 {
1559 struct meson_vpu_priv *priv = dev_get_priv(dev);
1560
1561 if (is_cvbs)
1562 return meson_venci_cvbs_mode_set(priv, &meson_cvbs_enci_pal);
1563
1564 meson_venc_hdmi_mode_set(priv, mode);
1565 }
1566