1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_IB_H
34 #define MLX5_IB_H
35
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 #include <linux/mlx5/transobj.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/mlx5-abi.h>
48 #include <rdma/uverbs_ioctl.h>
49 #include <rdma/mlx5_user_ioctl_cmds.h>
50
51 #define mlx5_ib_dbg(dev, format, arg...) \
52 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
53 __LINE__, current->pid, ##arg)
54
55 #define mlx5_ib_err(dev, format, arg...) \
56 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
57 __LINE__, current->pid, ##arg)
58
59 #define mlx5_ib_warn(dev, format, arg...) \
60 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
61 __LINE__, current->pid, ##arg)
62
63 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
64 sizeof(((type *)0)->fld) <= (sz))
65 #define MLX5_IB_DEFAULT_UIDX 0xffffff
66 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
67
68 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
69
70 enum {
71 MLX5_IB_MMAP_CMD_SHIFT = 8,
72 MLX5_IB_MMAP_CMD_MASK = 0xff,
73 };
74
75 enum {
76 MLX5_RES_SCAT_DATA32_CQE = 0x1,
77 MLX5_RES_SCAT_DATA64_CQE = 0x2,
78 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
79 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
80 };
81
82 enum mlx5_ib_mad_ifc_flags {
83 MLX5_MAD_IFC_IGNORE_MKEY = 1,
84 MLX5_MAD_IFC_IGNORE_BKEY = 2,
85 MLX5_MAD_IFC_NET_VIEW = 4,
86 };
87
88 enum {
89 MLX5_CROSS_CHANNEL_BFREG = 0,
90 };
91
92 enum {
93 MLX5_CQE_VERSION_V0,
94 MLX5_CQE_VERSION_V1,
95 };
96
97 enum {
98 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
99 MLX5_TM_MAX_SGE = 1,
100 };
101
102 enum {
103 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
104 MLX5_IB_INVALID_BFREG = BIT(31),
105 };
106
107 enum {
108 MLX5_MAX_MEMIC_PAGES = 0x100,
109 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
110 };
111
112 enum {
113 MLX5_MEMIC_BASE_ALIGN = 6,
114 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
115 };
116
117 struct mlx5_ib_vma_private_data {
118 struct list_head list;
119 struct vm_area_struct *vma;
120 /* protect vma_private_list add/del */
121 struct mutex *vma_private_list_mutex;
122 };
123
124 struct mlx5_ib_ucontext {
125 struct ib_ucontext ibucontext;
126 struct list_head db_page_list;
127
128 /* protect doorbell record alloc/free
129 */
130 struct mutex db_page_mutex;
131 struct mlx5_bfreg_info bfregi;
132 u8 cqe_version;
133 /* Transport Domain number */
134 u32 tdn;
135 struct list_head vma_private_list;
136 /* protect vma_private_list add/del */
137 struct mutex vma_private_list_mutex;
138
139 u64 lib_caps;
140 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES);
141 u16 devx_uid;
142 /* For RoCE LAG TX affinity */
143 atomic_t tx_port_affinity;
144 };
145
to_mucontext(struct ib_ucontext * ibucontext)146 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
147 {
148 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
149 }
150
151 struct mlx5_ib_pd {
152 struct ib_pd ibpd;
153 u32 pdn;
154 };
155
156 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
157 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
158 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
159 #error "Invalid number of bypass priorities"
160 #endif
161 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
162
163 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
164 #define MLX5_IB_NUM_SNIFFER_FTS 2
165 #define MLX5_IB_NUM_EGRESS_FTS 1
166 struct mlx5_ib_flow_prio {
167 struct mlx5_flow_table *flow_table;
168 unsigned int refcount;
169 };
170
171 struct mlx5_ib_flow_handler {
172 struct list_head list;
173 struct ib_flow ibflow;
174 struct mlx5_ib_flow_prio *prio;
175 struct mlx5_flow_handle *rule;
176 struct ib_counters *ibcounters;
177 struct mlx5_ib_dev *dev;
178 struct mlx5_ib_flow_matcher *flow_matcher;
179 };
180
181 struct mlx5_ib_flow_matcher {
182 struct mlx5_ib_match_params matcher_mask;
183 int mask_len;
184 enum mlx5_ib_flow_type flow_type;
185 u16 priority;
186 struct mlx5_core_dev *mdev;
187 atomic_t usecnt;
188 u8 match_criteria_enable;
189 };
190
191 struct mlx5_ib_flow_db {
192 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
193 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
194 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
195 struct mlx5_flow_table *lag_demux_ft;
196 /* Protect flow steering bypass flow tables
197 * when add/del flow rules.
198 * only single add/removal of flow steering rule could be done
199 * simultaneously.
200 */
201 struct mutex lock;
202 };
203
204 /* Use macros here so that don't have to duplicate
205 * enum ib_send_flags and enum ib_qp_type for low-level driver
206 */
207
208 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
209 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
210 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
211 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
212 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
213 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
214
215 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
216 /*
217 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
218 * creates the actual hardware QP.
219 */
220 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
221 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
222 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
223 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
224
225 #define MLX5_IB_UMR_OCTOWORD 16
226 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
227
228 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
229 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
230 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
231 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
232 #define MLX5_IB_UPD_XLT_PD BIT(4)
233 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
234 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
235
236 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
237 *
238 * These flags are intended for internal use by the mlx5_ib driver, and they
239 * rely on the range reserved for that use in the ib_qp_create_flags enum.
240 */
241
242 /* Create a UD QP whose source QP number is 1 */
mlx5_ib_create_qp_sqpn_qp1(void)243 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
244 {
245 return IB_QP_CREATE_RESERVED_START;
246 }
247
248 struct wr_list {
249 u16 opcode;
250 u16 next;
251 };
252
253 enum mlx5_ib_rq_flags {
254 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
255 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
256 };
257
258 struct mlx5_ib_wq {
259 u64 *wrid;
260 u32 *wr_data;
261 struct wr_list *w_list;
262 unsigned *wqe_head;
263 u16 unsig_count;
264
265 /* serialize post to the work queue
266 */
267 spinlock_t lock;
268 int wqe_cnt;
269 int max_post;
270 int max_gs;
271 int offset;
272 int wqe_shift;
273 unsigned head;
274 unsigned tail;
275 u16 cur_post;
276 u16 last_poll;
277 void *qend;
278 };
279
280 enum mlx5_ib_wq_flags {
281 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
282 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
283 };
284
285 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
286 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
287 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
288 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
289
290 struct mlx5_ib_rwq {
291 struct ib_wq ibwq;
292 struct mlx5_core_qp core_qp;
293 u32 rq_num_pas;
294 u32 log_rq_stride;
295 u32 log_rq_size;
296 u32 rq_page_offset;
297 u32 log_page_size;
298 u32 log_num_strides;
299 u32 two_byte_shift_en;
300 u32 single_stride_log_num_of_bytes;
301 struct ib_umem *umem;
302 size_t buf_size;
303 unsigned int page_shift;
304 int create_type;
305 struct mlx5_db db;
306 u32 user_index;
307 u32 wqe_count;
308 u32 wqe_shift;
309 int wq_sig;
310 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
311 };
312
313 enum {
314 MLX5_QP_USER,
315 MLX5_QP_KERNEL,
316 MLX5_QP_EMPTY
317 };
318
319 enum {
320 MLX5_WQ_USER,
321 MLX5_WQ_KERNEL
322 };
323
324 struct mlx5_ib_rwq_ind_table {
325 struct ib_rwq_ind_table ib_rwq_ind_tbl;
326 u32 rqtn;
327 };
328
329 struct mlx5_ib_ubuffer {
330 struct ib_umem *umem;
331 int buf_size;
332 u64 buf_addr;
333 };
334
335 struct mlx5_ib_qp_base {
336 struct mlx5_ib_qp *container_mibqp;
337 struct mlx5_core_qp mqp;
338 struct mlx5_ib_ubuffer ubuffer;
339 };
340
341 struct mlx5_ib_qp_trans {
342 struct mlx5_ib_qp_base base;
343 u16 xrcdn;
344 u8 alt_port;
345 u8 atomic_rd_en;
346 u8 resp_depth;
347 };
348
349 struct mlx5_ib_rss_qp {
350 u32 tirn;
351 };
352
353 struct mlx5_ib_rq {
354 struct mlx5_ib_qp_base base;
355 struct mlx5_ib_wq *rq;
356 struct mlx5_ib_ubuffer ubuffer;
357 struct mlx5_db *doorbell;
358 u32 tirn;
359 u8 state;
360 u32 flags;
361 };
362
363 struct mlx5_ib_sq {
364 struct mlx5_ib_qp_base base;
365 struct mlx5_ib_wq *sq;
366 struct mlx5_ib_ubuffer ubuffer;
367 struct mlx5_db *doorbell;
368 struct mlx5_flow_handle *flow_rule;
369 u32 tisn;
370 u8 state;
371 };
372
373 struct mlx5_ib_raw_packet_qp {
374 struct mlx5_ib_sq sq;
375 struct mlx5_ib_rq rq;
376 };
377
378 struct mlx5_bf {
379 int buf_size;
380 unsigned long offset;
381 struct mlx5_sq_bfreg *bfreg;
382 };
383
384 struct mlx5_ib_dct {
385 struct mlx5_core_dct mdct;
386 u32 *in;
387 };
388
389 struct mlx5_ib_qp {
390 struct ib_qp ibqp;
391 union {
392 struct mlx5_ib_qp_trans trans_qp;
393 struct mlx5_ib_raw_packet_qp raw_packet_qp;
394 struct mlx5_ib_rss_qp rss_qp;
395 struct mlx5_ib_dct dct;
396 };
397 struct mlx5_frag_buf buf;
398
399 struct mlx5_db db;
400 struct mlx5_ib_wq rq;
401
402 u8 sq_signal_bits;
403 u8 next_fence;
404 struct mlx5_ib_wq sq;
405
406 /* serialize qp state modifications
407 */
408 struct mutex mutex;
409 u32 flags;
410 u8 port;
411 u8 state;
412 int wq_sig;
413 int scat_cqe;
414 int max_inline_data;
415 struct mlx5_bf bf;
416 int has_rq;
417
418 /* only for user space QPs. For kernel
419 * we have it from the bf object
420 */
421 int bfregn;
422
423 int create_type;
424
425 /* Store signature errors */
426 bool signature_en;
427
428 struct list_head qps_list;
429 struct list_head cq_recv_list;
430 struct list_head cq_send_list;
431 struct mlx5_rate_limit rl;
432 u32 underlay_qpn;
433 bool tunnel_offload_en;
434 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */
435 enum ib_qp_type qp_sub_type;
436 };
437
438 struct mlx5_ib_cq_buf {
439 struct mlx5_frag_buf_ctrl fbc;
440 struct ib_umem *umem;
441 int cqe_size;
442 int nent;
443 };
444
445 enum mlx5_ib_qp_flags {
446 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
447 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
448 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
449 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
450 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
451 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
452 /* QP uses 1 as its source QP number */
453 MLX5_IB_QP_SQPN_QP1 = 1 << 6,
454 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
455 MLX5_IB_QP_RSS = 1 << 8,
456 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9,
457 MLX5_IB_QP_UNDERLAY = 1 << 10,
458 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11,
459 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12,
460 };
461
462 struct mlx5_umr_wr {
463 struct ib_send_wr wr;
464 u64 virt_addr;
465 u64 offset;
466 struct ib_pd *pd;
467 unsigned int page_shift;
468 unsigned int xlt_size;
469 u64 length;
470 int access_flags;
471 u32 mkey;
472 u8 ignore_free_state:1;
473 };
474
umr_wr(const struct ib_send_wr * wr)475 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
476 {
477 return container_of(wr, struct mlx5_umr_wr, wr);
478 }
479
480 struct mlx5_shared_mr_info {
481 int mr_id;
482 struct ib_umem *umem;
483 };
484
485 enum mlx5_ib_cq_pr_flags {
486 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
487 };
488
489 struct mlx5_ib_cq {
490 struct ib_cq ibcq;
491 struct mlx5_core_cq mcq;
492 struct mlx5_ib_cq_buf buf;
493 struct mlx5_db db;
494
495 /* serialize access to the CQ
496 */
497 spinlock_t lock;
498
499 /* protect resize cq
500 */
501 struct mutex resize_mutex;
502 struct mlx5_ib_cq_buf *resize_buf;
503 struct ib_umem *resize_umem;
504 int cqe_size;
505 struct list_head list_send_qp;
506 struct list_head list_recv_qp;
507 u32 create_flags;
508 struct list_head wc_list;
509 enum ib_cq_notify_flags notify_flags;
510 struct work_struct notify_work;
511 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
512 };
513
514 struct mlx5_ib_wc {
515 struct ib_wc wc;
516 struct list_head list;
517 };
518
519 struct mlx5_ib_srq {
520 struct ib_srq ibsrq;
521 struct mlx5_core_srq msrq;
522 struct mlx5_frag_buf buf;
523 struct mlx5_db db;
524 u64 *wrid;
525 /* protect SRQ hanlding
526 */
527 spinlock_t lock;
528 int head;
529 int tail;
530 u16 wqe_ctr;
531 struct ib_umem *umem;
532 /* serialize arming a SRQ
533 */
534 struct mutex mutex;
535 int wq_sig;
536 };
537
538 struct mlx5_ib_xrcd {
539 struct ib_xrcd ibxrcd;
540 u32 xrcdn;
541 };
542
543 enum mlx5_ib_mtt_access_flags {
544 MLX5_IB_MTT_READ = (1 << 0),
545 MLX5_IB_MTT_WRITE = (1 << 1),
546 };
547
548 struct mlx5_ib_dm {
549 struct ib_dm ibdm;
550 phys_addr_t dev_addr;
551 };
552
553 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
554
555 #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
556 IB_ACCESS_REMOTE_WRITE |\
557 IB_ACCESS_REMOTE_READ |\
558 IB_ACCESS_REMOTE_ATOMIC |\
559 IB_ZERO_BASED)
560
561 struct mlx5_ib_mr {
562 struct ib_mr ibmr;
563 void *descs;
564 dma_addr_t desc_map;
565 int ndescs;
566 int max_descs;
567 int desc_size;
568 int access_mode;
569 struct mlx5_core_mkey mmkey;
570 struct ib_umem *umem;
571 struct mlx5_shared_mr_info *smr_info;
572 struct list_head list;
573 int order;
574 bool allocated_from_cache;
575 int npages;
576 struct mlx5_ib_dev *dev;
577 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
578 struct mlx5_core_sig_ctx *sig;
579 int live;
580 void *descs_alloc;
581 int access_flags; /* Needed for rereg MR */
582
583 struct mlx5_ib_mr *parent;
584 atomic_t num_leaf_free;
585 wait_queue_head_t q_leaf_free;
586 };
587
588 struct mlx5_ib_mw {
589 struct ib_mw ibmw;
590 struct mlx5_core_mkey mmkey;
591 int ndescs;
592 };
593
594 struct mlx5_ib_umr_context {
595 struct ib_cqe cqe;
596 enum ib_wc_status status;
597 struct completion done;
598 };
599
600 struct umr_common {
601 struct ib_pd *pd;
602 struct ib_cq *cq;
603 struct ib_qp *qp;
604 /* control access to UMR QP
605 */
606 struct semaphore sem;
607 };
608
609 enum {
610 MLX5_FMR_INVALID,
611 MLX5_FMR_VALID,
612 MLX5_FMR_BUSY,
613 };
614
615 struct mlx5_cache_ent {
616 struct list_head head;
617 /* sync access to the cahce entry
618 */
619 spinlock_t lock;
620
621
622 struct dentry *dir;
623 char name[4];
624 u32 order;
625 u32 xlt;
626 u32 access_mode;
627 u32 page;
628
629 u32 size;
630 u32 cur;
631 u32 miss;
632 u32 limit;
633
634 struct dentry *fsize;
635 struct dentry *fcur;
636 struct dentry *fmiss;
637 struct dentry *flimit;
638
639 struct mlx5_ib_dev *dev;
640 struct work_struct work;
641 struct delayed_work dwork;
642 int pending;
643 struct completion compl;
644 };
645
646 struct mlx5_mr_cache {
647 struct workqueue_struct *wq;
648 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
649 int stopped;
650 struct dentry *root;
651 unsigned long last_add;
652 };
653
654 struct mlx5_ib_gsi_qp;
655
656 struct mlx5_ib_port_resources {
657 struct mlx5_ib_resources *devr;
658 struct mlx5_ib_gsi_qp *gsi;
659 struct work_struct pkey_change_work;
660 };
661
662 struct mlx5_ib_resources {
663 struct ib_cq *c0;
664 struct ib_xrcd *x0;
665 struct ib_xrcd *x1;
666 struct ib_pd *p0;
667 struct ib_srq *s0;
668 struct ib_srq *s1;
669 struct mlx5_ib_port_resources ports[2];
670 /* Protects changes to the port resources */
671 struct mutex mutex;
672 };
673
674 struct mlx5_ib_counters {
675 const char **names;
676 size_t *offsets;
677 u32 num_q_counters;
678 u32 num_cong_counters;
679 u32 num_ext_ppcnt_counters;
680 u16 set_id;
681 bool set_id_valid;
682 };
683
684 struct mlx5_ib_multiport_info;
685
686 struct mlx5_ib_multiport {
687 struct mlx5_ib_multiport_info *mpi;
688 /* To be held when accessing the multiport info */
689 spinlock_t mpi_lock;
690 };
691
692 struct mlx5_ib_port {
693 struct mlx5_ib_counters cnts;
694 struct mlx5_ib_multiport mp;
695 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
696 };
697
698 struct mlx5_roce {
699 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
700 * netdev pointer
701 */
702 rwlock_t netdev_lock;
703 struct net_device *netdev;
704 struct notifier_block nb;
705 atomic_t tx_port_affinity;
706 enum ib_port_state last_port_state;
707 struct mlx5_ib_dev *dev;
708 u8 native_port_num;
709 };
710
711 struct mlx5_ib_dbg_param {
712 int offset;
713 struct mlx5_ib_dev *dev;
714 struct dentry *dentry;
715 u8 port_num;
716 };
717
718 enum mlx5_ib_dbg_cc_types {
719 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
720 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
721 MLX5_IB_DBG_CC_RP_TIME_RESET,
722 MLX5_IB_DBG_CC_RP_BYTE_RESET,
723 MLX5_IB_DBG_CC_RP_THRESHOLD,
724 MLX5_IB_DBG_CC_RP_AI_RATE,
725 MLX5_IB_DBG_CC_RP_HAI_RATE,
726 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
727 MLX5_IB_DBG_CC_RP_MIN_RATE,
728 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
729 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
730 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
731 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
732 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
733 MLX5_IB_DBG_CC_RP_GD,
734 MLX5_IB_DBG_CC_NP_CNP_DSCP,
735 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
736 MLX5_IB_DBG_CC_NP_CNP_PRIO,
737 MLX5_IB_DBG_CC_MAX,
738 };
739
740 struct mlx5_ib_dbg_cc_params {
741 struct dentry *root;
742 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
743 };
744
745 enum {
746 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
747 };
748
749 struct mlx5_ib_dbg_delay_drop {
750 struct dentry *dir_debugfs;
751 struct dentry *rqs_cnt_debugfs;
752 struct dentry *events_cnt_debugfs;
753 struct dentry *timeout_debugfs;
754 };
755
756 struct mlx5_ib_delay_drop {
757 struct mlx5_ib_dev *dev;
758 struct work_struct delay_drop_work;
759 /* serialize setting of delay drop */
760 struct mutex lock;
761 u32 timeout;
762 bool activate;
763 atomic_t events_cnt;
764 atomic_t rqs_cnt;
765 struct mlx5_ib_dbg_delay_drop *dbg;
766 };
767
768 enum mlx5_ib_stages {
769 MLX5_IB_STAGE_INIT,
770 MLX5_IB_STAGE_FLOW_DB,
771 MLX5_IB_STAGE_CAPS,
772 MLX5_IB_STAGE_NON_DEFAULT_CB,
773 MLX5_IB_STAGE_ROCE,
774 MLX5_IB_STAGE_DEVICE_RESOURCES,
775 MLX5_IB_STAGE_ODP,
776 MLX5_IB_STAGE_COUNTERS,
777 MLX5_IB_STAGE_CONG_DEBUGFS,
778 MLX5_IB_STAGE_UAR,
779 MLX5_IB_STAGE_BFREG,
780 MLX5_IB_STAGE_PRE_IB_REG_UMR,
781 MLX5_IB_STAGE_SPECS,
782 MLX5_IB_STAGE_IB_REG,
783 MLX5_IB_STAGE_POST_IB_REG_UMR,
784 MLX5_IB_STAGE_DELAY_DROP,
785 MLX5_IB_STAGE_CLASS_ATTR,
786 MLX5_IB_STAGE_REP_REG,
787 MLX5_IB_STAGE_MAX,
788 };
789
790 struct mlx5_ib_stage {
791 int (*init)(struct mlx5_ib_dev *dev);
792 void (*cleanup)(struct mlx5_ib_dev *dev);
793 };
794
795 #define STAGE_CREATE(_stage, _init, _cleanup) \
796 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
797
798 struct mlx5_ib_profile {
799 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
800 };
801
802 struct mlx5_ib_multiport_info {
803 struct list_head list;
804 struct mlx5_ib_dev *ibdev;
805 struct mlx5_core_dev *mdev;
806 struct completion unref_comp;
807 u64 sys_image_guid;
808 u32 mdev_refcnt;
809 bool is_master;
810 bool unaffiliate;
811 };
812
813 struct mlx5_ib_flow_action {
814 struct ib_flow_action ib_action;
815 union {
816 struct {
817 u64 ib_flags;
818 struct mlx5_accel_esp_xfrm *ctx;
819 } esp_aes_gcm;
820 };
821 };
822
823 struct mlx5_memic {
824 struct mlx5_core_dev *dev;
825 spinlock_t memic_lock;
826 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
827 };
828
829 struct mlx5_read_counters_attr {
830 struct mlx5_fc *hw_cntrs_hndl;
831 u64 *out;
832 u32 flags;
833 };
834
835 enum mlx5_ib_counters_type {
836 MLX5_IB_COUNTERS_FLOW,
837 };
838
839 struct mlx5_ib_mcounters {
840 struct ib_counters ibcntrs;
841 enum mlx5_ib_counters_type type;
842 /* number of counters supported for this counters type */
843 u32 counters_num;
844 struct mlx5_fc *hw_cntrs_hndl;
845 /* read function for this counters type */
846 int (*read_counters)(struct ib_device *ibdev,
847 struct mlx5_read_counters_attr *read_attr);
848 /* max index set as part of create_flow */
849 u32 cntrs_max_index;
850 /* number of counters data entries (<description,index> pair) */
851 u32 ncounters;
852 /* counters data array for descriptions and indexes */
853 struct mlx5_ib_flow_counters_desc *counters_data;
854 /* protects access to mcounters internal data */
855 struct mutex mcntrs_mutex;
856 };
857
858 static inline struct mlx5_ib_mcounters *
to_mcounters(struct ib_counters * ibcntrs)859 to_mcounters(struct ib_counters *ibcntrs)
860 {
861 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
862 }
863
864 struct mlx5_ib_dev {
865 struct ib_device ib_dev;
866 const struct uverbs_object_tree_def *driver_trees[6];
867 struct mlx5_core_dev *mdev;
868 struct mlx5_roce roce[MLX5_MAX_PORTS];
869 int num_ports;
870 /* serialize update of capability mask
871 */
872 struct mutex cap_mask_mutex;
873 bool ib_active;
874 struct umr_common umrc;
875 /* sync used page count stats
876 */
877 struct mlx5_ib_resources devr;
878 struct mlx5_mr_cache cache;
879 struct timer_list delay_timer;
880 /* Prevents soft lock on massive reg MRs */
881 struct mutex slow_path_mutex;
882 int fill_delay;
883 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
884 struct ib_odp_caps odp_caps;
885 u64 odp_max_size;
886 /*
887 * Sleepable RCU that prevents destruction of MRs while they are still
888 * being used by a page fault handler.
889 */
890 struct srcu_struct mr_srcu;
891 u32 null_mkey;
892 #endif
893 struct mlx5_ib_flow_db *flow_db;
894 /* protect resources needed as part of reset flow */
895 spinlock_t reset_flow_resource_lock;
896 struct list_head qp_list;
897 /* Array with num_ports elements */
898 struct mlx5_ib_port *port;
899 struct mlx5_sq_bfreg bfreg;
900 struct mlx5_sq_bfreg fp_bfreg;
901 struct mlx5_ib_delay_drop delay_drop;
902 const struct mlx5_ib_profile *profile;
903 struct mlx5_eswitch_rep *rep;
904
905 /* protect the user_td */
906 struct mutex lb_mutex;
907 u32 user_td;
908 u8 umr_fence;
909 struct list_head ib_dev_list;
910 u64 sys_image_guid;
911 struct mlx5_memic memic;
912 };
913
to_mibcq(struct mlx5_core_cq * mcq)914 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
915 {
916 return container_of(mcq, struct mlx5_ib_cq, mcq);
917 }
918
to_mxrcd(struct ib_xrcd * ibxrcd)919 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
920 {
921 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
922 }
923
to_mdev(struct ib_device * ibdev)924 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
925 {
926 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
927 }
928
to_mcq(struct ib_cq * ibcq)929 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
930 {
931 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
932 }
933
to_mibqp(struct mlx5_core_qp * mqp)934 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
935 {
936 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
937 }
938
to_mibrwq(struct mlx5_core_qp * core_qp)939 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
940 {
941 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
942 }
943
to_mibmr(struct mlx5_core_mkey * mmkey)944 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
945 {
946 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
947 }
948
to_mpd(struct ib_pd * ibpd)949 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
950 {
951 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
952 }
953
to_msrq(struct ib_srq * ibsrq)954 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
955 {
956 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
957 }
958
to_mqp(struct ib_qp * ibqp)959 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
960 {
961 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
962 }
963
to_mrwq(struct ib_wq * ibwq)964 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
965 {
966 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
967 }
968
to_mrwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)969 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
970 {
971 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
972 }
973
to_mibsrq(struct mlx5_core_srq * msrq)974 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
975 {
976 return container_of(msrq, struct mlx5_ib_srq, msrq);
977 }
978
to_mdm(struct ib_dm * ibdm)979 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
980 {
981 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
982 }
983
to_mmr(struct ib_mr * ibmr)984 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
985 {
986 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
987 }
988
to_mmw(struct ib_mw * ibmw)989 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
990 {
991 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
992 }
993
994 static inline struct mlx5_ib_flow_action *
to_mflow_act(struct ib_flow_action * ibact)995 to_mflow_act(struct ib_flow_action *ibact)
996 {
997 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
998 }
999
1000 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
1001 struct mlx5_db *db);
1002 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1003 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1004 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1005 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1006 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
1007 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1008 const void *in_mad, void *response_mad);
1009 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr,
1010 struct ib_udata *udata);
1011 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1012 int mlx5_ib_destroy_ah(struct ib_ah *ah);
1013 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
1014 struct ib_srq_init_attr *init_attr,
1015 struct ib_udata *udata);
1016 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1017 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1018 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1019 int mlx5_ib_destroy_srq(struct ib_srq *srq);
1020 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1021 const struct ib_recv_wr **bad_wr);
1022 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1023 struct ib_qp_init_attr *init_attr,
1024 struct ib_udata *udata);
1025 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1026 int attr_mask, struct ib_udata *udata);
1027 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1028 struct ib_qp_init_attr *qp_init_attr);
1029 int mlx5_ib_destroy_qp(struct ib_qp *qp);
1030 void mlx5_ib_drain_sq(struct ib_qp *qp);
1031 void mlx5_ib_drain_rq(struct ib_qp *qp);
1032 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1033 const struct ib_send_wr **bad_wr);
1034 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1035 const struct ib_recv_wr **bad_wr);
1036 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
1037 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
1038 void *buffer, u32 length,
1039 struct mlx5_ib_qp_base *base);
1040 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
1041 const struct ib_cq_init_attr *attr,
1042 struct ib_ucontext *context,
1043 struct ib_udata *udata);
1044 int mlx5_ib_destroy_cq(struct ib_cq *cq);
1045 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1046 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1047 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1048 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1049 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1050 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1051 u64 virt_addr, int access_flags,
1052 struct ib_udata *udata);
1053 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1054 struct ib_udata *udata);
1055 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1056 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1057 int page_shift, int flags);
1058 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1059 int access_flags);
1060 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1061 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1062 u64 length, u64 virt_addr, int access_flags,
1063 struct ib_pd *pd, struct ib_udata *udata);
1064 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
1065 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
1066 enum ib_mr_type mr_type,
1067 u32 max_num_sg);
1068 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1069 unsigned int *sg_offset);
1070 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1071 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1072 const struct ib_mad_hdr *in, size_t in_mad_size,
1073 struct ib_mad_hdr *out, size_t *out_mad_size,
1074 u16 *out_mad_pkey_index);
1075 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1076 struct ib_ucontext *context,
1077 struct ib_udata *udata);
1078 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
1079 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1080 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1081 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1082 struct ib_smp *out_mad);
1083 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1084 __be64 *sys_image_guid);
1085 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1086 u16 *max_pkeys);
1087 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1088 u32 *vendor_id);
1089 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1090 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1091 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1092 u16 *pkey);
1093 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1094 union ib_gid *gid);
1095 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1096 struct ib_port_attr *props);
1097 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1098 struct ib_port_attr *props);
1099 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
1100 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
1101 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1102 unsigned long max_page_shift,
1103 int *count, int *shift,
1104 int *ncont, int *order);
1105 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1106 int page_shift, size_t offset, size_t num_pages,
1107 __be64 *pas, int access_flags);
1108 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1109 int page_shift, __be64 *pas, int access_flags);
1110 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1111 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
1112 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1113 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1114
1115 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry);
1116 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1117 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1118 struct ib_mr_status *mr_status);
1119 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1120 struct ib_wq_init_attr *init_attr,
1121 struct ib_udata *udata);
1122 int mlx5_ib_destroy_wq(struct ib_wq *wq);
1123 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1124 u32 wq_attr_mask, struct ib_udata *udata);
1125 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1126 struct ib_rwq_ind_table_init_attr *init_attr,
1127 struct ib_udata *udata);
1128 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1129 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev);
1130 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1131 struct ib_ucontext *context,
1132 struct ib_dm_alloc_attr *attr,
1133 struct uverbs_attr_bundle *attrs);
1134 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm);
1135 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1136 struct ib_dm_mr_attr *attr,
1137 struct uverbs_attr_bundle *attrs);
1138
1139 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1140 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1141 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context,
1142 struct mlx5_pagefault *pfault);
1143 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1144 int __init mlx5_ib_odp_init(void);
1145 void mlx5_ib_odp_cleanup(void);
1146 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
1147 unsigned long end);
1148 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1149 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1150 size_t nentries, struct mlx5_ib_mr *mr, int flags);
1151 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev * dev)1152 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1153 {
1154 return;
1155 }
1156
mlx5_ib_odp_init_one(struct mlx5_ib_dev * ibdev)1157 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
mlx5_ib_odp_init(void)1158 static inline int mlx5_ib_odp_init(void) { return 0; }
mlx5_ib_odp_cleanup(void)1159 static inline void mlx5_ib_odp_cleanup(void) {}
mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent * ent)1160 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
mlx5_odp_populate_klm(struct mlx5_klm * pklm,size_t offset,size_t nentries,struct mlx5_ib_mr * mr,int flags)1161 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1162 size_t nentries, struct mlx5_ib_mr *mr,
1163 int flags) {}
1164
1165 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1166
1167 /* Needed for rep profile */
1168 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev);
1169 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev);
1170 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev);
1171 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev);
1172 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev);
1173 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev);
1174 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev);
1175 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev);
1176 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev);
1177 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev);
1178 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev);
1179 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev);
1180 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev);
1181 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev);
1182 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev);
1183 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev);
1184 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev);
1185 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev);
1186 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1187 const struct mlx5_ib_profile *profile,
1188 int stage);
1189 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1190 const struct mlx5_ib_profile *profile);
1191
1192 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1193 u8 port, struct ifla_vf_info *info);
1194 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1195 u8 port, int state);
1196 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1197 u8 port, struct ifla_vf_stats *stats);
1198 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1199 u64 guid, int type);
1200
1201 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
1202 const struct ib_gid_attr *attr);
1203
1204 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1205 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1206
1207 /* GSI QP helper functions */
1208 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1209 struct ib_qp_init_attr *init_attr);
1210 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1211 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1212 int attr_mask);
1213 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1214 int qp_attr_mask,
1215 struct ib_qp_init_attr *qp_init_attr);
1216 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1217 const struct ib_send_wr **bad_wr);
1218 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1219 const struct ib_recv_wr **bad_wr);
1220 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1221
1222 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1223
1224 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1225 int bfregn);
1226 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1227 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1228 u8 ib_port_num,
1229 u8 *native_port_num);
1230 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1231 u8 port_num);
1232
1233 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
1234 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1235 struct mlx5_ib_ucontext *context);
1236 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev,
1237 struct mlx5_ib_ucontext *context);
1238 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void);
1239 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1240 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1241 void *cmd_in, int inlen, int dest_id, int dest_type);
1242 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type);
1243 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root);
1244 #else
1245 static inline int
mlx5_ib_devx_create(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1246 mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1247 struct mlx5_ib_ucontext *context) { return -EOPNOTSUPP; };
mlx5_ib_devx_destroy(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1248 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev,
1249 struct mlx5_ib_ucontext *context) {}
1250 static inline const struct uverbs_object_tree_def *
mlx5_ib_get_devx_tree(void)1251 mlx5_ib_get_devx_tree(void) { return NULL; }
mlx5_ib_devx_is_flow_dest(void * obj,int * dest_id,int * dest_type)1252 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id,
1253 int *dest_type)
1254 {
1255 return false;
1256 }
1257 static inline int
mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def ** root)1258 mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root)
1259 {
1260 return 0;
1261 }
1262 #endif
init_query_mad(struct ib_smp * mad)1263 static inline void init_query_mad(struct ib_smp *mad)
1264 {
1265 mad->base_version = 1;
1266 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1267 mad->class_version = 1;
1268 mad->method = IB_MGMT_METHOD_GET;
1269 }
1270
convert_access(int acc)1271 static inline u8 convert_access(int acc)
1272 {
1273 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1274 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1275 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1276 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1277 MLX5_PERM_LOCAL_READ;
1278 }
1279
is_qp1(enum ib_qp_type qp_type)1280 static inline int is_qp1(enum ib_qp_type qp_type)
1281 {
1282 return qp_type == MLX5_IB_QPT_HW_GSI;
1283 }
1284
1285 #define MLX5_MAX_UMR_SHIFT 16
1286 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1287
check_cq_create_flags(u32 flags)1288 static inline u32 check_cq_create_flags(u32 flags)
1289 {
1290 /*
1291 * It returns non-zero value for unsupported CQ
1292 * create flags, otherwise it returns zero.
1293 */
1294 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1295 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1296 }
1297
verify_assign_uidx(u8 cqe_version,u32 cmd_uidx,u32 * user_index)1298 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1299 u32 *user_index)
1300 {
1301 if (cqe_version) {
1302 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1303 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1304 return -EINVAL;
1305 *user_index = cmd_uidx;
1306 } else {
1307 *user_index = MLX5_IB_DEFAULT_UIDX;
1308 }
1309
1310 return 0;
1311 }
1312
get_qp_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_qp * ucmd,int inlen,u32 * user_index)1313 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1314 struct mlx5_ib_create_qp *ucmd,
1315 int inlen,
1316 u32 *user_index)
1317 {
1318 u8 cqe_version = ucontext->cqe_version;
1319
1320 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
1321 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1322 return 0;
1323
1324 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
1325 !!cqe_version))
1326 return -EINVAL;
1327
1328 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1329 }
1330
get_srq_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_srq * ucmd,int inlen,u32 * user_index)1331 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1332 struct mlx5_ib_create_srq *ucmd,
1333 int inlen,
1334 u32 *user_index)
1335 {
1336 u8 cqe_version = ucontext->cqe_version;
1337
1338 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
1339 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1340 return 0;
1341
1342 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
1343 !!cqe_version))
1344 return -EINVAL;
1345
1346 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1347 }
1348
get_uars_per_sys_page(struct mlx5_ib_dev * dev,bool lib_support)1349 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1350 {
1351 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1352 MLX5_UARS_IN_PAGE : 1;
1353 }
1354
get_num_static_uars(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)1355 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1356 struct mlx5_bfreg_info *bfregi)
1357 {
1358 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1359 }
1360
1361 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1362 void mlx5_ib_put_xlt_emergency_page(void);
1363
1364 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1365 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1366 bool dyn_bfreg);
1367 #endif /* MLX5_IB_H */
1368