1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCI autoconfiguration library (legacy version, do not change)
4 *
5 * Author: Matt Porter <mporter@mvista.com>
6 *
7 * Copyright 2000 MontaVista Software Inc.
8 */
9
10 #include <common.h>
11 #include <errno.h>
12 #include <pci.h>
13
14 /*
15 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
16 * and change pci_auto.c.
17 */
18
19 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
20 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
21 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
22 #endif
23
24 /*
25 *
26 */
27
pciauto_setup_device(struct pci_controller * hose,pci_dev_t dev,int bars_num,struct pci_region * mem,struct pci_region * prefetch,struct pci_region * io)28 void pciauto_setup_device(struct pci_controller *hose,
29 pci_dev_t dev, int bars_num,
30 struct pci_region *mem,
31 struct pci_region *prefetch,
32 struct pci_region *io)
33 {
34 u32 bar_response;
35 pci_size_t bar_size;
36 u16 cmdstat = 0;
37 int bar, bar_nr = 0;
38 #ifndef CONFIG_PCI_ENUM_ONLY
39 u8 header_type;
40 int rom_addr;
41 pci_addr_t bar_value;
42 struct pci_region *bar_res;
43 int found_mem64 = 0;
44 #endif
45 u16 class;
46
47 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
48 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
49
50 for (bar = PCI_BASE_ADDRESS_0;
51 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
52 /* Tickle the BAR and get the response */
53 #ifndef CONFIG_PCI_ENUM_ONLY
54 #ifdef CONFIG_PCIE_BVT
55 pci_hose_write_config_dword(hose, dev, bar, 0xfffffff0);
56
57 #else
58 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
59 #endif
60 #endif
61 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
62
63 /* If BAR is not implemented go to the next BAR */
64 if (!bar_response)
65 continue;
66
67 #ifndef CONFIG_PCI_ENUM_ONLY
68 found_mem64 = 0;
69 #endif
70
71 /* Check the BAR type and set our address mask */
72 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
73 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
74 & 0xffff) + 1;
75 #ifndef CONFIG_PCI_ENUM_ONLY
76 bar_res = io;
77 #endif
78
79 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
80 bar_nr, (unsigned long long)bar_size);
81 } else {
82 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
83 PCI_BASE_ADDRESS_MEM_TYPE_64) {
84 u32 bar_response_upper;
85 u64 bar64;
86
87 #ifndef CONFIG_PCI_ENUM_ONLY
88 pci_hose_write_config_dword(hose, dev, bar + 4,
89 0xffffffff);
90 #endif
91 pci_hose_read_config_dword(hose, dev, bar + 4,
92 &bar_response_upper);
93
94 bar64 = ((u64)bar_response_upper << 32) | bar_response;
95
96 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
97 #ifndef CONFIG_PCI_ENUM_ONLY
98 found_mem64 = 1;
99 #endif
100 } else {
101 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
102 }
103 #ifndef CONFIG_PCI_ENUM_ONLY
104 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
105 bar_res = prefetch;
106 else
107 bar_res = mem;
108
109 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
110 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
111 (unsigned long long)bar_size);
112 #endif
113 }
114
115 #ifndef CONFIG_PCI_ENUM_ONLY
116 if (pciauto_region_allocate(bar_res, bar_size,
117 &bar_value, found_mem64) == 0) {
118 /* Write it out and update our limit */
119 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
120
121 if (found_mem64) {
122 bar += 4;
123 #ifdef CONFIG_SYS_PCI_64BIT
124 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
125 #else
126 /*
127 * If we are a 64-bit decoder then increment to the
128 * upper 32 bits of the bar and force it to locate
129 * in the lower 4GB of memory.
130 */
131 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
132 #endif
133 }
134
135 }
136 #endif
137 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
138 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
139
140 debug("\n");
141
142 bar_nr++;
143 }
144
145 #ifndef CONFIG_PCI_ENUM_ONLY
146 /* Configure the expansion ROM address */
147 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
148 header_type &= 0x7f;
149 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
150 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
151 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
152 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
153 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
154 if (bar_response) {
155 bar_size = -(bar_response & ~1);
156 debug("PCI Autoconfig: ROM, size=%#x, ",
157 (unsigned int)bar_size);
158 if (pciauto_region_allocate(mem, bar_size,
159 &bar_value, false) == 0) {
160 pci_hose_write_config_dword(hose, dev, rom_addr,
161 bar_value);
162 }
163 cmdstat |= PCI_COMMAND_MEMORY;
164 debug("\n");
165 }
166 }
167 #endif
168
169 /* PCI_COMMAND_IO must be set for VGA device */
170 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
171 if (class == PCI_CLASS_DISPLAY_VGA)
172 cmdstat |= PCI_COMMAND_IO;
173
174 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
175 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
176 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
177 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
178 }
179
pciauto_prescan_setup_bridge(struct pci_controller * hose,pci_dev_t dev,int sub_bus)180 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
181 pci_dev_t dev, int sub_bus)
182 {
183 struct pci_region *pci_mem;
184 struct pci_region *pci_prefetch;
185 struct pci_region *pci_io;
186 u16 cmdstat, prefechable_64;
187
188 pci_mem = hose->pci_mem;
189 pci_prefetch = hose->pci_prefetch;
190 pci_io = hose->pci_io;
191
192 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
193 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
194 &prefechable_64);
195 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
196
197 /* Configure bus number registers */
198 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
199 PCI_BUS(dev) - hose->first_busno);
200 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
201 sub_bus - hose->first_busno);
202 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
203
204 if (pci_mem) {
205 /* Round memory allocator to 1MB boundary */
206 pciauto_region_align(pci_mem, 0x100000);
207
208 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
209 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
210 (pci_mem->bus_lower & 0xfff00000) >> 16);
211
212 cmdstat |= PCI_COMMAND_MEMORY;
213 }
214
215 if (pci_prefetch) {
216 /* Round memory allocator to 1MB boundary */
217 pciauto_region_align(pci_prefetch, 0x100000);
218
219 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
220 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
221 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
222 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
223 #ifdef CONFIG_SYS_PCI_64BIT
224 pci_hose_write_config_dword(hose, dev,
225 PCI_PREF_BASE_UPPER32,
226 pci_prefetch->bus_lower >> 32);
227 #else
228 pci_hose_write_config_dword(hose, dev,
229 PCI_PREF_BASE_UPPER32,
230 0x0);
231 #endif
232
233 cmdstat |= PCI_COMMAND_MEMORY;
234 } else {
235 /* We don't support prefetchable memory for now, so disable */
236 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
237 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
238 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
239 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
240 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
241 }
242 }
243
244 if (pci_io) {
245 /* Round I/O allocator to 4KB boundary */
246 pciauto_region_align(pci_io, 0x1000);
247
248 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
249 (pci_io->bus_lower & 0x0000f000) >> 8);
250 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
251 (pci_io->bus_lower & 0xffff0000) >> 16);
252
253 cmdstat |= PCI_COMMAND_IO;
254 }
255
256 /* Enable memory and I/O accesses, enable bus master */
257 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
258 cmdstat | PCI_COMMAND_MASTER);
259 }
260
pciauto_postscan_setup_bridge(struct pci_controller * hose,pci_dev_t dev,int sub_bus)261 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
262 pci_dev_t dev, int sub_bus)
263 {
264 struct pci_region *pci_mem;
265 struct pci_region *pci_prefetch;
266 struct pci_region *pci_io;
267
268 pci_mem = hose->pci_mem;
269 pci_prefetch = hose->pci_prefetch;
270 pci_io = hose->pci_io;
271
272 /* Configure bus number registers */
273 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
274 sub_bus - hose->first_busno);
275
276 if (pci_mem) {
277 /* Round memory allocator to 1MB boundary */
278 pciauto_region_align(pci_mem, 0x100000);
279
280 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
281 (pci_mem->bus_lower - 1) >> 16);
282 }
283
284 if (pci_prefetch) {
285 u16 prefechable_64;
286
287 pci_hose_read_config_word(hose, dev,
288 PCI_PREF_MEMORY_LIMIT,
289 &prefechable_64);
290 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
291
292 /* Round memory allocator to 1MB boundary */
293 pciauto_region_align(pci_prefetch, 0x100000);
294
295 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
296 (pci_prefetch->bus_lower - 1) >> 16);
297 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
298 #ifdef CONFIG_SYS_PCI_64BIT
299 pci_hose_write_config_dword(hose, dev,
300 PCI_PREF_LIMIT_UPPER32,
301 (pci_prefetch->bus_lower - 1) >> 32);
302 #else
303 pci_hose_write_config_dword(hose, dev,
304 PCI_PREF_LIMIT_UPPER32,
305 0x0);
306 #endif
307 }
308
309 if (pci_io) {
310 /* Round I/O allocator to 4KB boundary */
311 pciauto_region_align(pci_io, 0x1000);
312
313 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
314 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
315 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
316 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
317 }
318 }
319
320
321 /*
322 * HJF: Changed this to return int. I think this is required
323 * to get the correct result when scanning bridges
324 */
pciauto_config_device(struct pci_controller * hose,pci_dev_t dev)325 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
326 {
327 struct pci_region *pci_mem;
328 struct pci_region *pci_prefetch;
329 struct pci_region *pci_io;
330 unsigned int sub_bus = PCI_BUS(dev);
331 unsigned short class;
332 int n;
333
334 pci_mem = hose->pci_mem;
335 pci_prefetch = hose->pci_prefetch;
336 pci_io = hose->pci_io;
337
338 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
339
340 switch (class) {
341 case PCI_CLASS_BRIDGE_PCI:
342 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
343 PCI_DEV(dev));
344
345 pciauto_setup_device(hose, dev, 2, pci_mem,
346 pci_prefetch, pci_io);
347
348 /* Passing in current_busno allows for sibling P2P bridges */
349 hose->current_busno++;
350 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
351 /*
352 * need to figure out if this is a subordinate bridge on the bus
353 * to be able to properly set the pri/sec/sub bridge registers.
354 */
355 n = pci_hose_scan_bus(hose, hose->current_busno);
356
357 /* figure out the deepest we've gone for this leg */
358 sub_bus = max((unsigned int)n, sub_bus);
359 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
360
361 sub_bus = hose->current_busno;
362 break;
363
364 case PCI_CLASS_BRIDGE_CARDBUS:
365 /*
366 * just do a minimal setup of the bridge,
367 * let the OS take care of the rest
368 */
369 pciauto_setup_device(hose, dev, 0, pci_mem,
370 pci_prefetch, pci_io);
371
372 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
373 PCI_DEV(dev));
374
375 hose->current_busno++;
376 break;
377
378 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
379 case PCI_CLASS_BRIDGE_OTHER:
380 debug("PCI Autoconfig: Skipping bridge device %d\n",
381 PCI_DEV(dev));
382 break;
383 #endif
384 #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
385 !defined(CONFIG_TARGET_CADDY2)
386 case PCI_CLASS_BRIDGE_OTHER:
387 /*
388 * The host/PCI bridge 1 seems broken in 8349 - it presents
389 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
390 * device claiming resources io/mem/irq.. we only allow for
391 * the PIMMR window to be allocated (BAR0 - 1MB size)
392 */
393 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
394 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
395 hose->pci_prefetch, hose->pci_io);
396 break;
397 #endif
398
399 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
400 debug("PCI AutoConfig: Found PowerPC device\n");
401
402 default:
403 pciauto_setup_device(hose, dev, 6, pci_mem,
404 pci_prefetch, pci_io);
405 break;
406 }
407
408 return sub_bus;
409 }
410