1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> 4 * All rights reserved. 5 */ 6 7 #include <asm/cache.h> 8 #include <altera.h> 9 #include <image.h> 10 11 #ifndef _FPGA_MANAGER_ARRIA10_H_ 12 #define _FPGA_MANAGER_ARRIA10_H_ 13 14 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) 15 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) 16 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) 17 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) 18 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) 19 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) 20 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) 21 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) 22 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) 23 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) 24 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) 25 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) 26 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) 27 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) 28 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) 29 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) 30 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) 31 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ 32 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ 33 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ 34 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) 35 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) 36 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) 37 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) 38 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) 39 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 40 41 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) 42 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) 43 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) 44 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) 45 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) 46 #define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) 47 48 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) 49 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) 50 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) 51 52 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) 53 #define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) 54 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 55 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) 56 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 57 58 #define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c 59 #define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d 60 #define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001 61 #define FPGA_SOCFPGA_A10_RBF_CORE 0x8001 62 #ifndef __ASSEMBLY__ 63 64 struct socfpga_fpga_manager { 65 u32 _pad_0x0_0x7[2]; 66 u32 dclkcnt; 67 u32 dclkstat; 68 u32 gpo; 69 u32 gpi; 70 u32 misci; 71 u32 _pad_0x1c_0x2f[5]; 72 u32 emr_data0; 73 u32 emr_data1; 74 u32 emr_data2; 75 u32 emr_data3; 76 u32 emr_data4; 77 u32 emr_data5; 78 u32 emr_valid; 79 u32 emr_en; 80 u32 jtag_config; 81 u32 jtag_status; 82 u32 jtag_kick; 83 u32 _pad_0x5c_0x5f; 84 u32 jtag_data_w; 85 u32 jtag_data_r; 86 u32 _pad_0x68_0x6f[2]; 87 u32 imgcfg_ctrl_00; 88 u32 imgcfg_ctrl_01; 89 u32 imgcfg_ctrl_02; 90 u32 _pad_0x7c_0x7f; 91 u32 imgcfg_stat; 92 u32 intr_masked_status; 93 u32 intr_mask; 94 u32 intr_polarity; 95 u32 dma_config; 96 u32 imgcfg_fifo_status; 97 }; 98 99 enum rbf_type { 100 unknown, 101 periph_section, 102 core_section 103 }; 104 105 enum rbf_security { 106 invalid, 107 unencrypted, 108 encrypted 109 }; 110 111 struct rbf_info { 112 enum rbf_type section; 113 enum rbf_security security; 114 }; 115 116 struct fpga_loadfs_info { 117 fpga_fs_info *fpga_fsinfo; 118 u32 remaining; 119 u32 offset; 120 struct rbf_info rbfinfo; 121 }; 122 123 /* Functions */ 124 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); 125 int fpgamgr_program_finish(void); 126 int is_fpgamgr_user_mode(void); 127 int fpgamgr_wait_early_user_mode(void); 128 const char *get_fpga_filename(void); 129 int is_fpgamgr_early_user_mode(void); 130 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, 131 u32 offset); 132 void fpgamgr_program(const void *buf, size_t bsize, u32 offset); 133 #endif /* __ASSEMBLY__ */ 134 135 #endif /* _FPGA_MANAGER_ARRIA10_H_ */ 136