| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/hal/phy/hisiv200/regs/ |
| D | hdmi_reg_dphy.c | 43 static hi_void hdmi21_txreg_write(hi_u32 *reg_addr, hi_u32 value) in hdmi21_txreg_write()
49 static hi_u32 hdmi21_txreg_read(hi_u32 *reg_addr) in hdmi21_txreg_read()
56 hi_u32 *reg_addr = NULL; in hdmi_phy_csen_stb_cs_en_set() local
69 hi_u32 *reg_addr = NULL; in hdmi_phy_wr_stb_wen_set() local
82 hi_u32 *reg_addr = NULL; in hdmi_resetn_resetn_set() local
95 hi_u32 *reg_addr = NULL; in hdmi_resetn_resetn_get() local
105 hi_u32 *reg_addr = NULL; in hdmi_fdsrcparam_src_enable_set() local
118 hi_u32 *reg_addr = NULL; in hdmi_phy_wdata_stb_wdata_set() local
131 hi_u32 *reg_addr = NULL; in hdmi_fcgset_p_fcg_lock_en_set() local
144 hi_u32 *reg_addr = NULL; in hdmi_phy_addr_stb_addr_set() local
[all …]
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/hal/phy/hisiv100/regs/ |
| D | hdmi_reg_dphy.c | 40 hi_u32 *reg_addr = NULL; in hdmi_hdmitx_inssc_set_reg_sscin_bypass_en_set() local
53 hi_u32 *reg_addr = NULL; in hdmi_hdmitx_inssc_set_reg_pllfbmash111_en_set() local
66 hi_u32 *reg_addr = NULL; in hdmi_hdmitx_dphy_rst_reg_rstset() local
79 hi_u32 *reg_addr = NULL; in hdmi_hdmitx_afifo_data_sel_reg_aphy_data_clk_h_set() local
92 hi_u32 *reg_addr = NULL; in hdmi_hdmitx_afifo_clk_reg_aphy_data_clk_l_set() local
105 hi_u32 *reg_addr = NULL; in hdmi_aphy_top_pd_reg_divsel_set() local
118 hi_u32 *reg_addr = NULL; in hdmi_aphy_top_pd_reg_gc_txpll_pd_set() local
131 hi_u32 *reg_addr = NULL; in hdmi_aphy_top_pd_reg_gc_txpll_pd_get() local
141 hi_u32 *reg_addr = NULL; in hdmi_aphy_top_pd_reg_gc_pd_rxsense_set() local
154 hi_u32 *reg_addr = NULL; in hdmi_aphy_top_pd_reg_gc_pd_rxsense_get() local
[all …]
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3519av100/regs/ |
| D | hdmi_reg_crg.c | 52 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_osc_24m_cken_set() local
65 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_osc_24m_cken_get() local
75 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_cec_cken_set() local
88 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_cec_cken_get() local
98 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_os_cken_set() local
111 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_os_cken_get() local
121 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_as_cken_set() local
134 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_as_cken_get() local
144 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_bus_srst_req_set() local
157 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_bus_srst_req_get() local
[all …]
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3559av100/regs/ |
| D | hdmi_reg_crg.c | 52 hi_u32 *reg_addr = NULL; in reg_mpll_crg_mpll_postdiv1_set() local
65 hi_u32 *reg_addr = NULL; in reg_mpll_crg_mpll_postdiv2_set() local
78 hi_u32 *reg_addr = NULL; in reg_mpll_crg_mpll_dsmpd_set() local
91 hi_u32 *reg_addr = NULL; in reg_mpll_crg_mpll_refdiv_set() local
104 hi_u32 *reg_addr = NULL; in reg_mpll_crg_mpll_fbdiv_set() local
117 hi_u32 *reg_addr = NULL; in reg_mpll_crg_mpll_pd_set() local
130 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_osc_24m_cken_set() local
143 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_cec_cken_set() local
156 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_os_cken_set() local
169 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_as_cken_set() local
[all …]
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/hal/ctrl/hisiv200/regs/ |
| D | hdmi_reg_video_path.c | 42 hi_u32 *reg_addr = NULL; in hdmi_data_align_ctrl_reg_vert_cbcr_sel_set() local
55 hi_u32 *reg_addr = NULL; in hdmi_tx_pack_fifo_ctrl_reg_fifo_manu_rst_set() local
68 hi_u32 *reg_addr = NULL; in hdmi_multi_csc_ctrl_reg_csc_mode_get() local
78 hi_u32 *reg_addr = NULL; in hdmi_dither_config_mode_set() local
91 hi_u32 *reg_addr = NULL; in hdmi_dither_config_rnd_byp_set() local
104 hi_u32 *reg_addr = NULL; in hdmi_multi_csc_ctrl_reg_csc_mode_set() local
117 hi_u32 *reg_addr = NULL; in hdmi_multi_csc_ctrl_reg_csc_saturate_en_set() local
130 hi_u32 *reg_addr = NULL; in hdmi_multi_csc_ctrl_reg_csc_en_set() local
143 hi_u32 *reg_addr = NULL; in hdmi_video_dwsm_ctrl_reg_dwsm_vert_en_set() local
156 hi_u32 *reg_addr = NULL; in hdmi_video_dwsm_ctrl_reg_dwsm_hori_en_set() local
[all …]
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| D | hdmi_reg_tx.c | 42 hi_u32 *reg_addr = NULL; in hdmi_avi_pkt_header_hb_set() local
57 hi_u32 *reg_addr = NULL; in hdmi_avi_sub_pkt0_l_pb_set() local
73 hi_u32 *reg_addr = NULL; in hdmi_avi_sub_pkt0_h_pb_set() local
89 hi_u32 *reg_addr = NULL; in hdmi_avi_sub_pkt1_l_pb_set() local
105 hi_u32 *reg_addr = NULL; in hdmi_avi_sub_pkt1_h_pb_set() local
121 hi_u32 *reg_addr = NULL; in hdmi_avi_sub_pkt2_l_pb_set() local
137 hi_u32 *reg_addr = NULL; in hdmi_avi_sub_pkt2_h_pb_set() local
153 hi_u32 *reg_addr = NULL; in hdmi_avi_sub_pkt3_l_pb_set() local
169 hi_u32 *reg_addr = NULL; in hdmi_avi_sub_pkt3_h_pb_set() local
184 hi_u32 *reg_addr = NULL; in hdmi_vsif_pkt_header_hb_set() local
[all …]
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| D | hdmi_reg_ctrl.c | 40 hi_u32 *reg_addr = NULL; in hdmi_tx_channel_reg_vid_bypass_sel_set() local
53 hi_u32 *reg_addr = NULL; in hdmi_tx_channel_reg_vid_bypass_sel_get() local
63 hi_u32 *reg_addr = NULL; in hdmi_tx_hdmi_srst_req_set() local
76 hi_u32 *reg_addr = NULL; in hdmi_tx_pwd_srst_req_set() local
89 hi_u32 *reg_addr = NULL; in hdmi_vidpath_dout_clk_sel_set() local
102 hi_u32 *reg_addr = NULL; in hdmi_yuv_rgb_cfg_reg_set() local
115 hi_u32 *reg_addr = NULL; in hdmi_pwd_fifo_wdata_set() local
128 hi_u32 *reg_addr = NULL; in hdmi_pwd_data_out_cnt_set() local
141 hi_u32 *reg_addr = NULL; in hdmi_pwd_slave_seg_set() local
154 hi_u32 *reg_addr = NULL; in hdmi_pwd_slave_offset_set() local
[all …]
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| D | hdmi_reg_aon.c | 39 hi_u32 *reg_addr = NULL; in hdmi_dcc_man_en_set() local
52 hi_u32 *reg_addr = NULL; in hdmi_ddc_sda_oen_set() local
65 hi_u32 *reg_addr = NULL; in hdmi_ddc_scl_oen_set() local
78 hi_u32 *reg_addr = NULL; in hdmi_ddc_i2c_no_ack_get() local
88 hi_u32 *reg_addr = NULL; in hdmi_ddc_i2c_bus_low_get() local
98 hi_u32 *reg_addr = NULL; in hdmi_ddc_sda_st_get() local
108 hi_u32 *reg_addr = NULL; in hdmi_ddc_scl_st_get() local
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3531dv200/regs/ |
| D | hdmi_reg_crg.c | 52 hi_u32 *reg_addr = NULL; in hdmi_reg_ssc_in_cken_set() local
65 hi_u32 *reg_addr = NULL; in hdmi_reg_ssc_bypass_cken_set() local
78 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_osc_24m_cken_set() local
91 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_cec_cken_set() local
104 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_os_cken_set() local
117 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_as_cken_set() local
129 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_bus_srst_req_set() local
142 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_srst_req_set() local
155 hi_u32 *reg_addr = NULL; in hdmi_reg_cec_srst_req_set() local
168 hi_u32 *reg_addr = NULL; in hdmi_reg_ssc_srst_req_set() local
[all …]
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3516cv500/regs/ |
| D | hdmi_reg_crg.c | 51 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_ssc_in_cken_set() local
64 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_ssc_bypass_cken_set() local
77 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_osc_24m_cken_set() local
90 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_cec_cken_set() local
103 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_os_cken_set() local
116 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_as_cken_set() local
128 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_bus_srst_req_set() local
141 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_srst_req_set() local
154 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ctrl_cec_srst_req_set() local
167 hi_u32 *reg_addr = NULL; in reg_hdmi_crg_hdmitx_ssc_srst_req_set() local
[all …]
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3521dv200/regs/ |
| D | hdmi_reg_crg.c | 52 hi_u32 *reg_addr = NULL; in hdmi_reg_ssc_in_cken_set() local
65 hi_u32 *reg_addr = NULL; in hdmi_reg_ssc_bypass_cken_set() local
78 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_osc_24m_cken_set() local
91 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_cec_cken_set() local
104 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_os_cken_set() local
117 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_as_cken_set() local
129 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_bus_srst_req_set() local
142 hi_u32 *reg_addr = NULL; in hdmi_reg_ctrl_srst_req_set() local
155 hi_u32 *reg_addr = NULL; in hdmi_reg_cec_srst_req_set() local
168 hi_u32 *reg_addr = NULL; in hdmi_reg_ssc_srst_req_set() local
[all …]
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/hal/ctrl/hisiv100/regs/ |
| D | hdmi_reg_tx.c | 40 hi_u32 *reg_addr = NULL; in hdmi_tx_tmds_pack_mode_set() local
53 hi_u32 *reg_addr = NULL; in hdmi_avi_pkt_header_hb_set() local
68 hi_u32 *reg_addr = NULL; in hdmi_l_avi_pkt0_pb_set() local
85 hi_u32 *reg_addr = NULL; in hdmi_h_avi_pkt0_pb_set() local
101 hi_u32 *reg_addr = NULL; in hdmi_l_avi_pkt1_pb_set() local
118 hi_u32 *reg_addr = NULL; in hdmi_h_avi_pkt1_pb_set() local
134 hi_u32 *reg_addr = NULL; in hdmi_l_avi_pkt2_pb_set() local
151 hi_u32 *reg_addr = NULL; in hdmi_h_avi_pkt2_pb_set() local
167 hi_u32 *reg_addr = NULL; in hdmi_l_avi_pkt3_pb_set() local
184 hi_u32 *reg_addr = NULL; in hdmi_h_avi_pkt3_pb_set() local
[all …]
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| D | hdmi_reg_video_path.c | 40 hi_u32 *reg_addr = NULL; in hdmi_reg_csc_mode_get() local
50 hi_u32 *reg_addr = NULL; in hdmi_dither_mode_set() local
63 hi_u32 *reg_addr = NULL; in hdmi_dither_rnd_byp_set() local
76 hi_u32 *reg_addr = NULL; in hdmi_reg_csc_mode_set() local
89 hi_u32 *reg_addr = NULL; in hdmi_reg_csc_saturate_en_set() local
102 hi_u32 *reg_addr = NULL; in hdmi_reg_csc_en_set() local
115 hi_u32 *reg_addr = NULL; in hdmi_reg_dwsm_vert_byp_set() local
128 hi_u32 *reg_addr = NULL; in hdmi_reg_dwsm_vert_en_set() local
141 hi_u32 *reg_addr = NULL; in hdmi_reg_hori_filter_en_set() local
154 hi_u32 *reg_addr = NULL; in hdmi_reg_dwsm_hori_en_set() local
[all …]
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| D | hdmi_reg_ctrl.c | 40 hi_u32 *reg_addr = NULL; in hdmi_pwd_tx_afifo_srst_req_set() local
53 hi_u32 *reg_addr = NULL; in hdmi_pwd_tx_acr_srst_req_set() local
66 hi_u32 *reg_addr = NULL; in hdmi_pwd_tx_aud_srst_req_set() local
79 hi_u32 *reg_addr = NULL; in hdmi_pwd_tx_hdmi_srst_req_set() local
92 hi_u32 *reg_addr = NULL; in hdmi_pwd_fifo_data_in_set() local
105 hi_u32 *reg_addr = NULL; in hdmi_pwd_data_out_cnt_set() local
118 hi_u32 *reg_addr = NULL; in hdmi_pwd_slave_seg_set() local
131 hi_u32 *reg_addr = NULL; in hdmi_pwd_slave_offset_set() local
144 hi_u32 *reg_addr = NULL; in hdmi_pwd_slave_addr_set() local
157 hi_u32 *reg_addr = NULL; in hdmi_pwd_mst_cmd_set() local
[all …]
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| D | hdmi_reg_aon.c | 39 hi_u32 *reg_addr = NULL; in hdmi_dcc_man_en_set() local
52 hi_u32 *reg_addr = NULL; in hdmi_ddc_sda_oen_set() local
65 hi_u32 *reg_addr = NULL; in hdmi_ddc_scl_oen_set() local
78 hi_u32 *reg_addr = NULL; in hdmi_ddc_i2c_no_ack_get() local
88 hi_u32 *reg_addr = NULL; in hdmi_ddc_i2c_bus_low_get() local
98 hi_u32 *reg_addr = NULL; in hdmi_ddc_sda_st_get() local
108 hi_u32 *reg_addr = NULL; in hdmi_ddc_scl_st_get() local
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3559av100/ |
| D | hdmi_product_define.c | 40 hi_s32 hdmi_tx_reg_write (hi_u32 *reg_addr, hi_u32 value) in hdmi_tx_reg_write()
47 hi_u32 hdmi_tx_reg_read(hi_u32 *reg_addr) in hdmi_tx_reg_read()
53 hi_s32 hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value) in hdmi_reg_write_u32()
68 hi_u32 hdmi_reg_read_u32 (hi_u32 reg_addr) in hdmi_reg_read_u32()
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3521dv200/ |
| D | hdmi_product_define.c | 25 hi_s32 hdmi_tx_reg_write(hi_u32 *reg_addr, hi_u32 value) in hdmi_tx_reg_write()
32 hi_u32 hdmi_tx_reg_read(hi_u32 *reg_addr) in hdmi_tx_reg_read()
38 hi_s32 hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value) in hdmi_reg_write_u32()
53 hi_u32 hdmi_reg_read_u32 (hi_u32 reg_addr) in hdmi_reg_read_u32()
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3531dv200/ |
| D | hdmi_product_define.c | 25 hi_s32 hdmi_tx_reg_write(hi_u32 *reg_addr, hi_u32 value) in hdmi_tx_reg_write()
32 hi_u32 hdmi_tx_reg_read(hi_u32 *reg_addr) in hdmi_tx_reg_read()
38 hi_s32 hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value) in hdmi_reg_write_u32()
53 hi_u32 hdmi_reg_read_u32 (hi_u32 reg_addr) in hdmi_reg_read_u32()
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3516cv500/ |
| D | hdmi_product_define.c | 41 hi_s32 hdmi_tx_reg_write (hi_u32 *reg_addr, hi_u32 value) in hdmi_tx_reg_write()
48 hi_u32 hdmi_tx_reg_read(hi_u32 *reg_addr) in hdmi_tx_reg_read()
54 hi_s32 hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value) in hdmi_reg_write_u32()
69 hi_u32 hdmi_reg_read_u32 (hi_u32 reg_addr) in hdmi_reg_read_u32()
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/product/hi3519av100/ |
| D | hdmi_product_define.c | 40 hi_s32 hdmi_tx_reg_write (hi_u32 *reg_addr, hi_u32 value) in hdmi_tx_reg_write()
47 hi_u32 hdmi_tx_reg_read(hi_u32 *reg_addr) in hdmi_tx_reg_read()
53 hi_s32 hdmi_reg_write_u32(hi_u32 reg_addr, hi_u32 value) in hdmi_reg_write_u32()
68 hi_u32 hdmi_reg_read_u32 (hi_u32 reg_addr) in hdmi_reg_read_u32()
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| /third_party/uboot/u-boot-2020.01/drivers/video/bridge/ |
| D | anx6345.c | 23 unsigned char reg_addr, unsigned char value) in anx6345_write()
46 unsigned char reg_addr, unsigned char *value) in anx6345_read()
72 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr, in anx6345_write_r0()
80 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr, in anx6345_read_r0()
88 static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr, in anx6345_write_r1()
96 static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr, in anx6345_read_r1()
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| /third_party/uboot/u-boot-2020.01/product/hiosd/hdmi/hdmi_2_0/drv/ |
| D | drv_hdmi_common.c | 237 hi_void hdmi_reg_write(volatile hi_void *reg_addr, hi_u32 value) in hdmi_reg_write()
244 hi_u32 hdmi_reg_read(volatile hi_void *reg_addr) in hdmi_reg_read()
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| /third_party/uboot/u-boot-2020.01/drivers/net/pfe_eth/ |
| D | pfe_mdio.c | 17 int reg_addr) in pfe_write_addr()
51 int reg_addr) in pfe_phy_read()
106 int reg_addr, u16 data) in pfe_phy_write()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/marvell/a38x/ |
| D | ddr3_training_pbs.c | 49 u32 reg_addr = 0; in ddr3_tip_pbs() local
943 u32 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_print_pbs_result() local
993 u32 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_clean_pbs_result() local
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-sunxi/ |
| D | rsb.c | 145 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) in rsb_write()
158 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) in rsb_read()
|