1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 *
5 * Based on CAAM driver in drivers/crypto/caam in Linux
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <malloc.h>
11 #include "fsl_sec.h"
12 #include "jr.h"
13 #include "jobdesc.h"
14 #include "desc_constr.h"
15 #include <time.h>
16 #ifdef CONFIG_FSL_CORENET
17 #include <asm/fsl_pamu.h>
18 #endif
19
20 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
21 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
22
23 uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
24 0,
25 #if defined(CONFIG_ARCH_C29X)
26 CONFIG_SYS_FSL_SEC_IDX_OFFSET,
27 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
28 #endif
29 };
30
31 #define SEC_ADDR(idx) \
32 ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
33
34 #define SEC_JR0_ADDR(idx) \
35 (SEC_ADDR(idx) + \
36 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
37
38 struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
39
start_jr0(uint8_t sec_idx)40 static inline void start_jr0(uint8_t sec_idx)
41 {
42 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
43 u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
44 u32 scfgr = sec_in32(&sec->scfgr);
45
46 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
47 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
48 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
49 */
50 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
51 (scfgr & SEC_SCFGR_VIRT_EN))
52 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
53 } else {
54 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
55 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
56 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
57 }
58 }
59
jr_reset_liodn(uint8_t sec_idx)60 static inline void jr_reset_liodn(uint8_t sec_idx)
61 {
62 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
63 sec_out32(&sec->jrliodnr[0].ls, 0);
64 }
65
jr_disable_irq(uint8_t sec_idx)66 static inline void jr_disable_irq(uint8_t sec_idx)
67 {
68 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
69 uint32_t jrcfg = sec_in32(®s->jrcfg1);
70
71 jrcfg = jrcfg | JR_INTMASK;
72
73 sec_out32(®s->jrcfg1, jrcfg);
74 }
75
jr_initregs(uint8_t sec_idx)76 static void jr_initregs(uint8_t sec_idx)
77 {
78 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
79 struct jobring *jr = &jr0[sec_idx];
80 phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
81 phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
82
83 #ifdef CONFIG_PHYS_64BIT
84 sec_out32(®s->irba_h, ip_base >> 32);
85 #else
86 sec_out32(®s->irba_h, 0x0);
87 #endif
88 sec_out32(®s->irba_l, (uint32_t)ip_base);
89 #ifdef CONFIG_PHYS_64BIT
90 sec_out32(®s->orba_h, op_base >> 32);
91 #else
92 sec_out32(®s->orba_h, 0x0);
93 #endif
94 sec_out32(®s->orba_l, (uint32_t)op_base);
95 sec_out32(®s->ors, JR_SIZE);
96 sec_out32(®s->irs, JR_SIZE);
97
98 if (!jr->irq)
99 jr_disable_irq(sec_idx);
100 }
101
jr_init(uint8_t sec_idx)102 static int jr_init(uint8_t sec_idx)
103 {
104 struct jobring *jr = &jr0[sec_idx];
105
106 memset(jr, 0, sizeof(struct jobring));
107
108 jr->jq_id = DEFAULT_JR_ID;
109 jr->irq = DEFAULT_IRQ;
110
111 #ifdef CONFIG_FSL_CORENET
112 jr->liodn = DEFAULT_JR_LIODN;
113 #endif
114 jr->size = JR_SIZE;
115 jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
116 JR_SIZE * sizeof(dma_addr_t));
117 if (!jr->input_ring)
118 return -1;
119
120 jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
121 ARCH_DMA_MINALIGN);
122 jr->output_ring =
123 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
124 if (!jr->output_ring)
125 return -1;
126
127 memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
128 memset(jr->output_ring, 0, jr->op_size);
129
130 start_jr0(sec_idx);
131
132 jr_initregs(sec_idx);
133
134 return 0;
135 }
136
jr_sw_cleanup(uint8_t sec_idx)137 static int jr_sw_cleanup(uint8_t sec_idx)
138 {
139 struct jobring *jr = &jr0[sec_idx];
140
141 jr->head = 0;
142 jr->tail = 0;
143 jr->read_idx = 0;
144 jr->write_idx = 0;
145 memset(jr->info, 0, sizeof(jr->info));
146 memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
147 memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
148
149 return 0;
150 }
151
jr_hw_reset(uint8_t sec_idx)152 static int jr_hw_reset(uint8_t sec_idx)
153 {
154 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
155 uint32_t timeout = 100000;
156 uint32_t jrint, jrcr;
157
158 sec_out32(®s->jrcr, JRCR_RESET);
159 do {
160 jrint = sec_in32(®s->jrint);
161 } while (((jrint & JRINT_ERR_HALT_MASK) ==
162 JRINT_ERR_HALT_INPROGRESS) && --timeout);
163
164 jrint = sec_in32(®s->jrint);
165 if (((jrint & JRINT_ERR_HALT_MASK) !=
166 JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
167 return -1;
168
169 timeout = 100000;
170 sec_out32(®s->jrcr, JRCR_RESET);
171 do {
172 jrcr = sec_in32(®s->jrcr);
173 } while ((jrcr & JRCR_RESET) && --timeout);
174
175 if (timeout == 0)
176 return -1;
177
178 return 0;
179 }
180
181 /* -1 --- error, can't enqueue -- no space available */
jr_enqueue(uint32_t * desc_addr,void (* callback)(uint32_t status,void * arg),void * arg,uint8_t sec_idx)182 static int jr_enqueue(uint32_t *desc_addr,
183 void (*callback)(uint32_t status, void *arg),
184 void *arg, uint8_t sec_idx)
185 {
186 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
187 struct jobring *jr = &jr0[sec_idx];
188 int head = jr->head;
189 uint32_t desc_word;
190 int length = desc_len(desc_addr);
191 int i;
192 #ifdef CONFIG_PHYS_64BIT
193 uint32_t *addr_hi, *addr_lo;
194 #endif
195
196 /* The descriptor must be submitted to SEC block as per endianness
197 * of the SEC Block.
198 * So, if the endianness of Core and SEC block is different, each word
199 * of the descriptor will be byte-swapped.
200 */
201 for (i = 0; i < length; i++) {
202 desc_word = desc_addr[i];
203 sec_out32((uint32_t *)&desc_addr[i], desc_word);
204 }
205
206 phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
207
208 jr->info[head].desc_phys_addr = desc_phys_addr;
209 jr->info[head].callback = (void *)callback;
210 jr->info[head].arg = arg;
211 jr->info[head].op_done = 0;
212
213 unsigned long start = (unsigned long)&jr->info[head] &
214 ~(ARCH_DMA_MINALIGN - 1);
215 unsigned long end = ALIGN((unsigned long)&jr->info[head] +
216 sizeof(struct jr_info), ARCH_DMA_MINALIGN);
217 flush_dcache_range(start, end);
218
219 #ifdef CONFIG_PHYS_64BIT
220 /* Write the 64 bit Descriptor address on Input Ring.
221 * The 32 bit hign and low part of the address will
222 * depend on endianness of SEC block.
223 */
224 #ifdef CONFIG_SYS_FSL_SEC_LE
225 addr_lo = (uint32_t *)(&jr->input_ring[head]);
226 addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
227 #elif defined(CONFIG_SYS_FSL_SEC_BE)
228 addr_hi = (uint32_t *)(&jr->input_ring[head]);
229 addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
230 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
231
232 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
233 sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
234
235 #else
236 /* Write the 32 bit Descriptor address on Input Ring. */
237 sec_out32(&jr->input_ring[head], desc_phys_addr);
238 #endif /* ifdef CONFIG_PHYS_64BIT */
239
240 start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
241 end = ALIGN((unsigned long)&jr->input_ring[head] +
242 sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
243 flush_dcache_range(start, end);
244
245 jr->head = (head + 1) & (jr->size - 1);
246
247 /* Invalidate output ring */
248 start = (unsigned long)jr->output_ring &
249 ~(ARCH_DMA_MINALIGN - 1);
250 end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
251 ARCH_DMA_MINALIGN);
252 invalidate_dcache_range(start, end);
253
254 sec_out32(®s->irja, 1);
255
256 return 0;
257 }
258
jr_dequeue(int sec_idx)259 static int jr_dequeue(int sec_idx)
260 {
261 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
262 struct jobring *jr = &jr0[sec_idx];
263 int head = jr->head;
264 int tail = jr->tail;
265 int idx, i, found;
266 void (*callback)(uint32_t status, void *arg);
267 void *arg = NULL;
268 #ifdef CONFIG_PHYS_64BIT
269 uint32_t *addr_hi, *addr_lo;
270 #else
271 uint32_t *addr;
272 #endif
273
274 while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail,
275 jr->size)) {
276
277 found = 0;
278
279 phys_addr_t op_desc;
280 #ifdef CONFIG_PHYS_64BIT
281 /* Read the 64 bit Descriptor address from Output Ring.
282 * The 32 bit hign and low part of the address will
283 * depend on endianness of SEC block.
284 */
285 #ifdef CONFIG_SYS_FSL_SEC_LE
286 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
287 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
288 #elif defined(CONFIG_SYS_FSL_SEC_BE)
289 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
290 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
291 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
292
293 op_desc = ((u64)sec_in32(addr_hi) << 32) |
294 ((u64)sec_in32(addr_lo));
295
296 #else
297 /* Read the 32 bit Descriptor address from Output Ring. */
298 addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
299 op_desc = sec_in32(addr);
300 #endif /* ifdef CONFIG_PHYS_64BIT */
301
302 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
303
304 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
305 idx = (tail + i) & (jr->size - 1);
306 if (op_desc == jr->info[idx].desc_phys_addr) {
307 found = 1;
308 break;
309 }
310 }
311
312 /* Error condition if match not found */
313 if (!found)
314 return -1;
315
316 jr->info[idx].op_done = 1;
317 callback = (void *)jr->info[idx].callback;
318 arg = jr->info[idx].arg;
319
320 /* When the job on tail idx gets done, increment
321 * tail till the point where job completed out of oredr has
322 * been taken into account
323 */
324 if (idx == tail)
325 do {
326 tail = (tail + 1) & (jr->size - 1);
327 } while (jr->info[tail].op_done);
328
329 jr->tail = tail;
330 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
331
332 sec_out32(®s->orjr, 1);
333 jr->info[idx].op_done = 0;
334
335 callback(status, arg);
336 }
337
338 return 0;
339 }
340
desc_done(uint32_t status,void * arg)341 static void desc_done(uint32_t status, void *arg)
342 {
343 struct result *x = arg;
344 x->status = status;
345 #ifndef CONFIG_SPL_BUILD
346 caam_jr_strstatus(status);
347 #endif
348 x->done = 1;
349 }
350
run_descriptor_jr_idx(uint32_t * desc,uint8_t sec_idx)351 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
352 {
353 unsigned long long timeval = get_ticks();
354 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
355 struct result op;
356 int ret = 0;
357
358 memset(&op, 0, sizeof(op));
359
360 ret = jr_enqueue(desc, desc_done, &op, sec_idx);
361 if (ret) {
362 debug("Error in SEC enq\n");
363 ret = JQ_ENQ_ERR;
364 goto out;
365 }
366
367 timeval = get_ticks();
368 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
369 while (op.done != 1) {
370 ret = jr_dequeue(sec_idx);
371 if (ret) {
372 debug("Error in SEC deq\n");
373 ret = JQ_DEQ_ERR;
374 goto out;
375 }
376
377 if ((get_ticks() - timeval) > timeout) {
378 debug("SEC Dequeue timed out\n");
379 ret = JQ_DEQ_TO_ERR;
380 goto out;
381 }
382 }
383
384 if (op.status) {
385 debug("Error %x\n", op.status);
386 ret = op.status;
387 }
388 out:
389 return ret;
390 }
391
run_descriptor_jr(uint32_t * desc)392 int run_descriptor_jr(uint32_t *desc)
393 {
394 return run_descriptor_jr_idx(desc, 0);
395 }
396
jr_reset_sec(uint8_t sec_idx)397 static inline int jr_reset_sec(uint8_t sec_idx)
398 {
399 if (jr_hw_reset(sec_idx) < 0)
400 return -1;
401
402 /* Clean up the jobring structure maintained by software */
403 jr_sw_cleanup(sec_idx);
404
405 return 0;
406 }
407
jr_reset(void)408 int jr_reset(void)
409 {
410 return jr_reset_sec(0);
411 }
412
sec_reset_idx(uint8_t sec_idx)413 static inline int sec_reset_idx(uint8_t sec_idx)
414 {
415 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
416 uint32_t mcfgr = sec_in32(&sec->mcfgr);
417 uint32_t timeout = 100000;
418
419 mcfgr |= MCFGR_SWRST;
420 sec_out32(&sec->mcfgr, mcfgr);
421
422 mcfgr |= MCFGR_DMA_RST;
423 sec_out32(&sec->mcfgr, mcfgr);
424 do {
425 mcfgr = sec_in32(&sec->mcfgr);
426 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
427
428 if (timeout == 0)
429 return -1;
430
431 timeout = 100000;
432 do {
433 mcfgr = sec_in32(&sec->mcfgr);
434 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
435
436 if (timeout == 0)
437 return -1;
438
439 return 0;
440 }
sec_reset(void)441 int sec_reset(void)
442 {
443 return sec_reset_idx(0);
444 }
445 #ifndef CONFIG_SPL_BUILD
instantiate_rng(uint8_t sec_idx)446 static int instantiate_rng(uint8_t sec_idx)
447 {
448 u32 *desc;
449 u32 rdsta_val;
450 int ret = 0, sh_idx, size;
451 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
452 struct rng4tst __iomem *rng =
453 (struct rng4tst __iomem *)&sec->rng;
454
455 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
456 if (!desc) {
457 printf("cannot allocate RNG init descriptor memory\n");
458 return -1;
459 }
460
461 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
462 /*
463 * If the corresponding bit is set, this state handle
464 * was initialized by somebody else, so it's left alone.
465 */
466 rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
467 if (rdsta_val & (1 << sh_idx))
468 continue;
469
470 inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx);
471 size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
472 flush_dcache_range((unsigned long)desc,
473 (unsigned long)desc + size);
474
475 ret = run_descriptor_jr_idx(desc, sec_idx);
476
477 if (ret)
478 printf("RNG: Instantiation failed with error 0x%x\n",
479 ret);
480
481 rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
482 if (!(rdsta_val & (1 << sh_idx))) {
483 free(desc);
484 return -1;
485 }
486
487 memset(desc, 0, sizeof(uint32_t) * 6);
488 }
489
490 free(desc);
491
492 return ret;
493 }
494
get_rng_vid(uint8_t sec_idx)495 static u8 get_rng_vid(uint8_t sec_idx)
496 {
497 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
498 u32 cha_vid = sec_in32(&sec->chavid_ls);
499
500 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
501 }
502
503 /*
504 * By default, the TRNG runs for 200 clocks per sample;
505 * 1200 clocks per sample generates better entropy.
506 */
kick_trng(int ent_delay,uint8_t sec_idx)507 static void kick_trng(int ent_delay, uint8_t sec_idx)
508 {
509 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
510 struct rng4tst __iomem *rng =
511 (struct rng4tst __iomem *)&sec->rng;
512 u32 val;
513
514 /* put RNG4 into program mode */
515 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
516 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
517 * length (in system clocks) of each Entropy sample taken
518 * */
519 val = sec_in32(&rng->rtsdctl);
520 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
521 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
522 sec_out32(&rng->rtsdctl, val);
523 /* min. freq. count, equal to 1/4 of the entropy sample length */
524 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
525 /* disable maximum frequency count */
526 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
527 /*
528 * select raw sampling in both entropy shifter
529 * and statistical checker
530 */
531 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
532 /* put RNG4 into run mode */
533 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
534 }
535
rng_init(uint8_t sec_idx)536 static int rng_init(uint8_t sec_idx)
537 {
538 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
539 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
540 struct rng4tst __iomem *rng =
541 (struct rng4tst __iomem *)&sec->rng;
542 u32 inst_handles;
543
544 do {
545 inst_handles = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
546
547 /*
548 * If either of the SH's were instantiated by somebody else
549 * then it is assumed that the entropy
550 * parameters are properly set and thus the function
551 * setting these (kick_trng(...)) is skipped.
552 * Also, if a handle was instantiated, do not change
553 * the TRNG parameters.
554 */
555 if (!inst_handles) {
556 kick_trng(ent_delay, sec_idx);
557 ent_delay += 400;
558 }
559 /*
560 * if instantiate_rng(...) fails, the loop will rerun
561 * and the kick_trng(...) function will modfiy the
562 * upper and lower limits of the entropy sampling
563 * interval, leading to a sucessful initialization of
564 * the RNG.
565 */
566 ret = instantiate_rng(sec_idx);
567 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
568 if (ret) {
569 printf("RNG: Failed to instantiate RNG\n");
570 return ret;
571 }
572
573 /* Enable RDB bit so that RNG works faster */
574 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
575
576 return ret;
577 }
578 #endif
sec_init_idx(uint8_t sec_idx)579 int sec_init_idx(uint8_t sec_idx)
580 {
581 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
582 uint32_t mcr = sec_in32(&sec->mcfgr);
583 int ret = 0;
584
585 #ifdef CONFIG_FSL_CORENET
586 uint32_t liodnr;
587 uint32_t liodn_ns;
588 uint32_t liodn_s;
589 #endif
590
591 if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
592 printf("SEC initialization failed\n");
593 return -1;
594 }
595
596 /*
597 * Modifying CAAM Read/Write Attributes
598 * For LS2080A
599 * For AXI Write - Cacheable, Write Back, Write allocate
600 * For AXI Read - Cacheable, Read allocate
601 * Only For LS2080a, to solve CAAM coherency issues
602 */
603 #ifdef CONFIG_ARCH_LS2080A
604 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
605 mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
606 #else
607 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
608 #endif
609
610 #ifdef CONFIG_PHYS_64BIT
611 mcr |= (1 << MCFGR_PS_SHIFT);
612 #endif
613 sec_out32(&sec->mcfgr, mcr);
614
615 #ifdef CONFIG_FSL_CORENET
616 #ifdef CONFIG_SPL_BUILD
617 /*
618 * For SPL Build, Set the Liodns in SEC JR0 for
619 * creating PAMU entries corresponding to these.
620 * For normal build, these are set in set_liodns().
621 */
622 liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
623 liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
624
625 liodnr = sec_in32(&sec->jrliodnr[0].ls) &
626 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
627 liodnr = liodnr |
628 (liodn_ns << JRNSLIODN_SHIFT) |
629 (liodn_s << JRSLIODN_SHIFT);
630 sec_out32(&sec->jrliodnr[0].ls, liodnr);
631 #else
632 liodnr = sec_in32(&sec->jrliodnr[0].ls);
633 liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
634 liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
635 #endif
636 #endif
637
638 ret = jr_init(sec_idx);
639 if (ret < 0) {
640 printf("SEC initialization failed\n");
641 return -1;
642 }
643
644 #ifdef CONFIG_FSL_CORENET
645 ret = sec_config_pamu_table(liodn_ns, liodn_s);
646 if (ret < 0)
647 return -1;
648
649 pamu_enable();
650 #endif
651 #ifndef CONFIG_SPL_BUILD
652 if (get_rng_vid(sec_idx) >= 4) {
653 if (rng_init(sec_idx) < 0) {
654 printf("SEC%u: RNG instantiation failed\n", sec_idx);
655 return -1;
656 }
657 printf("SEC%u: RNG instantiated\n", sec_idx);
658 }
659 #endif
660 return ret;
661 }
662
sec_init(void)663 int sec_init(void)
664 {
665 return sec_init_idx(0);
666 }
667