1 /*
2 * Intel SMP support routines.
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * (c) 2002,2003 Andi Kleen, SuSE Labs.
7 *
8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
9 *
10 * This code is released under the GNU General Public License version 2 or
11 * later.
12 */
13
14 #include <linux/init.h>
15
16 #include <linux/mm.h>
17 #include <linux/delay.h>
18 #include <linux/spinlock.h>
19 #include <linux/export.h>
20 #include <linux/kernel_stat.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/cache.h>
23 #include <linux/interrupt.h>
24 #include <linux/cpu.h>
25 #include <linux/gfp.h>
26
27 #include <asm/mtrr.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/proto.h>
31 #include <asm/apic.h>
32 #include <asm/nmi.h>
33 #include <asm/mce.h>
34 #include <asm/trace/irq_vectors.h>
35 #include <asm/kexec.h>
36 #include <asm/virtext.h>
37
38 /*
39 * Some notes on x86 processor bugs affecting SMP operation:
40 *
41 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
42 * The Linux implications for SMP are handled as follows:
43 *
44 * Pentium III / [Xeon]
45 * None of the E1AP-E3AP errata are visible to the user.
46 *
47 * E1AP. see PII A1AP
48 * E2AP. see PII A2AP
49 * E3AP. see PII A3AP
50 *
51 * Pentium II / [Xeon]
52 * None of the A1AP-A3AP errata are visible to the user.
53 *
54 * A1AP. see PPro 1AP
55 * A2AP. see PPro 2AP
56 * A3AP. see PPro 7AP
57 *
58 * Pentium Pro
59 * None of 1AP-9AP errata are visible to the normal user,
60 * except occasional delivery of 'spurious interrupt' as trap #15.
61 * This is very rare and a non-problem.
62 *
63 * 1AP. Linux maps APIC as non-cacheable
64 * 2AP. worked around in hardware
65 * 3AP. fixed in C0 and above steppings microcode update.
66 * Linux does not use excessive STARTUP_IPIs.
67 * 4AP. worked around in hardware
68 * 5AP. symmetric IO mode (normal Linux operation) not affected.
69 * 'noapic' mode has vector 0xf filled out properly.
70 * 6AP. 'noapic' mode might be affected - fixed in later steppings
71 * 7AP. We do not assume writes to the LVT deassering IRQs
72 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
73 * 9AP. We do not use mixed mode
74 *
75 * Pentium
76 * There is a marginal case where REP MOVS on 100MHz SMP
77 * machines with B stepping processors can fail. XXX should provide
78 * an L1cache=Writethrough or L1cache=off option.
79 *
80 * B stepping CPUs may hang. There are hardware work arounds
81 * for this. We warn about it in case your board doesn't have the work
82 * arounds. Basically that's so I can tell anyone with a B stepping
83 * CPU and SMP problems "tough".
84 *
85 * Specific items [From Pentium Processor Specification Update]
86 *
87 * 1AP. Linux doesn't use remote read
88 * 2AP. Linux doesn't trust APIC errors
89 * 3AP. We work around this
90 * 4AP. Linux never generated 3 interrupts of the same priority
91 * to cause a lost local interrupt.
92 * 5AP. Remote read is never used
93 * 6AP. not affected - worked around in hardware
94 * 7AP. not affected - worked around in hardware
95 * 8AP. worked around in hardware - we get explicit CS errors if not
96 * 9AP. only 'noapic' mode affected. Might generate spurious
97 * interrupts, we log only the first one and count the
98 * rest silently.
99 * 10AP. not affected - worked around in hardware
100 * 11AP. Linux reads the APIC between writes to avoid this, as per
101 * the documentation. Make sure you preserve this as it affects
102 * the C stepping chips too.
103 * 12AP. not affected - worked around in hardware
104 * 13AP. not affected - worked around in hardware
105 * 14AP. we always deassert INIT during bootup
106 * 15AP. not affected - worked around in hardware
107 * 16AP. not affected - worked around in hardware
108 * 17AP. not affected - worked around in hardware
109 * 18AP. not affected - worked around in hardware
110 * 19AP. not affected - worked around in BIOS
111 *
112 * If this sounds worrying believe me these bugs are either ___RARE___,
113 * or are signal timing bugs worked around in hardware and there's
114 * about nothing of note with C stepping upwards.
115 */
116
117 static atomic_t stopping_cpu = ATOMIC_INIT(-1);
118 static bool smp_no_nmi_ipi = false;
119
120 /*
121 * this function sends a 'reschedule' IPI to another CPU.
122 * it goes straight through and wastes no time serializing
123 * anything. Worst case is that we lose a reschedule ...
124 */
native_smp_send_reschedule(int cpu)125 static void native_smp_send_reschedule(int cpu)
126 {
127 if (unlikely(cpu_is_offline(cpu))) {
128 WARN(1, "sched: Unexpected reschedule of offline CPU#%d!\n", cpu);
129 return;
130 }
131 apic->send_IPI(cpu, RESCHEDULE_VECTOR);
132 }
133
native_send_call_func_single_ipi(int cpu)134 void native_send_call_func_single_ipi(int cpu)
135 {
136 apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR);
137 }
138
native_send_call_func_ipi(const struct cpumask * mask)139 void native_send_call_func_ipi(const struct cpumask *mask)
140 {
141 cpumask_var_t allbutself;
142
143 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
144 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
145 return;
146 }
147
148 cpumask_copy(allbutself, cpu_online_mask);
149 cpumask_clear_cpu(smp_processor_id(), allbutself);
150
151 if (cpumask_equal(mask, allbutself) &&
152 cpumask_equal(cpu_online_mask, cpu_callout_mask))
153 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
154 else
155 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
156
157 free_cpumask_var(allbutself);
158 }
159
smp_stop_nmi_callback(unsigned int val,struct pt_regs * regs)160 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
161 {
162 /* We are registered on stopping cpu too, avoid spurious NMI */
163 if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
164 return NMI_HANDLED;
165
166 cpu_emergency_vmxoff();
167 stop_this_cpu(NULL);
168
169 return NMI_HANDLED;
170 }
171
172 /*
173 * this function calls the 'stop' function on all other CPUs in the system.
174 */
175
smp_reboot_interrupt(void)176 asmlinkage __visible void smp_reboot_interrupt(void)
177 {
178 ipi_entering_ack_irq();
179 cpu_emergency_vmxoff();
180 stop_this_cpu(NULL);
181 irq_exit();
182 }
183
register_stop_handler(void)184 static int register_stop_handler(void)
185 {
186 return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
187 NMI_FLAG_FIRST, "smp_stop");
188 }
189
native_stop_other_cpus(int wait)190 static void native_stop_other_cpus(int wait)
191 {
192 unsigned long flags;
193 unsigned long timeout;
194
195 if (reboot_force)
196 return;
197
198 /*
199 * Use an own vector here because smp_call_function
200 * does lots of things not suitable in a panic situation.
201 */
202
203 /*
204 * We start by using the REBOOT_VECTOR irq.
205 * The irq is treated as a sync point to allow critical
206 * regions of code on other cpus to release their spin locks
207 * and re-enable irqs. Jumping straight to an NMI might
208 * accidentally cause deadlocks with further shutdown/panic
209 * code. By syncing, we give the cpus up to one second to
210 * finish their work before we force them off with the NMI.
211 */
212 if (num_online_cpus() > 1) {
213 /* did someone beat us here? */
214 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
215 return;
216
217 /* sync above data before sending IRQ */
218 wmb();
219
220 apic->send_IPI_allbutself(REBOOT_VECTOR);
221
222 /*
223 * Don't wait longer than a second for IPI completion. The
224 * wait request is not checked here because that would
225 * prevent an NMI shutdown attempt in case that not all
226 * CPUs reach shutdown state.
227 */
228 timeout = USEC_PER_SEC;
229 while (num_online_cpus() > 1 && timeout--)
230 udelay(1);
231 }
232
233 /* if the REBOOT_VECTOR didn't work, try with the NMI */
234 if (num_online_cpus() > 1) {
235 /*
236 * If NMI IPI is enabled, try to register the stop handler
237 * and send the IPI. In any case try to wait for the other
238 * CPUs to stop.
239 */
240 if (!smp_no_nmi_ipi && !register_stop_handler()) {
241 /* Sync above data before sending IRQ */
242 wmb();
243
244 pr_emerg("Shutting down cpus with NMI\n");
245
246 apic->send_IPI_allbutself(NMI_VECTOR);
247 }
248 /*
249 * Don't wait longer than 10 ms if the caller didn't
250 * reqeust it. If wait is true, the machine hangs here if
251 * one or more CPUs do not reach shutdown state.
252 */
253 timeout = USEC_PER_MSEC * 10;
254 while (num_online_cpus() > 1 && (wait || timeout--))
255 udelay(1);
256 }
257
258 local_irq_save(flags);
259 disable_local_APIC();
260 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
261 local_irq_restore(flags);
262 }
263
264 /*
265 * Reschedule call back. KVM uses this interrupt to force a cpu out of
266 * guest mode
267 */
smp_reschedule_interrupt(struct pt_regs * regs)268 __visible void __irq_entry smp_reschedule_interrupt(struct pt_regs *regs)
269 {
270 ack_APIC_irq();
271 inc_irq_stat(irq_resched_count);
272 kvm_set_cpu_l1tf_flush_l1d();
273
274 if (trace_resched_ipi_enabled()) {
275 /*
276 * scheduler_ipi() might call irq_enter() as well, but
277 * nested calls are fine.
278 */
279 irq_enter();
280 trace_reschedule_entry(RESCHEDULE_VECTOR);
281 scheduler_ipi();
282 trace_reschedule_exit(RESCHEDULE_VECTOR);
283 irq_exit();
284 return;
285 }
286 scheduler_ipi();
287 }
288
smp_call_function_interrupt(struct pt_regs * regs)289 __visible void __irq_entry smp_call_function_interrupt(struct pt_regs *regs)
290 {
291 ipi_entering_ack_irq();
292 trace_call_function_entry(CALL_FUNCTION_VECTOR);
293 inc_irq_stat(irq_call_count);
294 generic_smp_call_function_interrupt();
295 trace_call_function_exit(CALL_FUNCTION_VECTOR);
296 exiting_irq();
297 }
298
smp_call_function_single_interrupt(struct pt_regs * r)299 __visible void __irq_entry smp_call_function_single_interrupt(struct pt_regs *r)
300 {
301 ipi_entering_ack_irq();
302 trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
303 inc_irq_stat(irq_call_count);
304 generic_smp_call_function_single_interrupt();
305 trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
306 exiting_irq();
307 }
308
nonmi_ipi_setup(char * str)309 static int __init nonmi_ipi_setup(char *str)
310 {
311 smp_no_nmi_ipi = true;
312 return 1;
313 }
314
315 __setup("nonmi_ipi", nonmi_ipi_setup);
316
317 struct smp_ops smp_ops = {
318 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
319 .smp_prepare_cpus = native_smp_prepare_cpus,
320 .smp_cpus_done = native_smp_cpus_done,
321
322 .stop_other_cpus = native_stop_other_cpus,
323 #if defined(CONFIG_KEXEC_CORE)
324 .crash_stop_other_cpus = kdump_nmi_shootdown_cpus,
325 #endif
326 .smp_send_reschedule = native_smp_send_reschedule,
327
328 .cpu_up = native_cpu_up,
329 .cpu_die = native_cpu_die,
330 .cpu_disable = native_cpu_disable,
331 .play_dead = native_play_dead,
332
333 .send_call_func_ipi = native_send_call_func_ipi,
334 .send_call_func_single_ipi = native_send_call_func_single_ipi,
335 };
336 EXPORT_SYMBOL_GPL(smp_ops);
337