1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
4 */
5 #include <asm/io.h>
6 #include <asm/arch/fpga_manager.h>
7 #include <asm/arch/reset_manager.h>
8 #include <asm/arch/system_manager.h>
9 #include <asm/arch/sdram.h>
10 #include <asm/arch/misc.h>
11 #include <altera.h>
12 #include <asm/arch/pinmux.h>
13 #include <common.h>
14 #include <dm/ofnode.h>
15 #include <errno.h>
16 #include <fs_loader.h>
17 #include <wait_bit.h>
18 #include <watchdog.h>
19
20 #define CFGWDTH_32 1
21 #define MIN_BITSTREAM_SIZECHECK 230
22 #define ENCRYPTION_OFFSET 69
23 #define COMPRESSION_OFFSET 229
24 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
25 #define FPGA_TIMEOUT_CNT 0x1000000
26 #define DEFAULT_DDR_LOAD_ADDRESS 0x400
27
28 DECLARE_GLOBAL_DATA_PTR;
29
30 static const struct socfpga_fpga_manager *fpga_manager_base =
31 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
32
33 static const struct socfpga_system_manager *system_manager_base =
34 (void *)SOCFPGA_SYSMGR_ADDRESS;
35
36 static void fpgamgr_set_cd_ratio(unsigned long ratio);
37
fpgamgr_get_msel(void)38 static uint32_t fpgamgr_get_msel(void)
39 {
40 u32 reg;
41
42 reg = readl(&fpga_manager_base->imgcfg_stat);
43 reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
44 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
45
46 return reg;
47 }
48
fpgamgr_set_cfgwdth(int width)49 static void fpgamgr_set_cfgwdth(int width)
50 {
51 if (width)
52 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
53 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
54 else
55 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
56 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
57 }
58
is_fpgamgr_user_mode(void)59 int is_fpgamgr_user_mode(void)
60 {
61 return (readl(&fpga_manager_base->imgcfg_stat) &
62 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
63 }
64
wait_for_user_mode(void)65 static int wait_for_user_mode(void)
66 {
67 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
68 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
69 1, FPGA_TIMEOUT_MSEC, false);
70 }
71
is_fpgamgr_early_user_mode(void)72 int is_fpgamgr_early_user_mode(void)
73 {
74 return (readl(&fpga_manager_base->imgcfg_stat) &
75 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
76 }
77
fpgamgr_wait_early_user_mode(void)78 int fpgamgr_wait_early_user_mode(void)
79 {
80 u32 sync_data = 0xffffffff;
81 u32 i = 0;
82 unsigned start = get_timer(0);
83 unsigned long cd_ratio;
84
85 /* Getting existing CDRATIO */
86 cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
87 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
88 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
89
90 /* Using CDRATIO_X1 for better compatibility */
91 fpgamgr_set_cd_ratio(CDRATIO_x1);
92
93 while (!is_fpgamgr_early_user_mode()) {
94 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
95 return -ETIMEDOUT;
96 fpgamgr_program_write((const long unsigned int *)&sync_data,
97 sizeof(sync_data));
98 udelay(FPGA_TIMEOUT_MSEC);
99 i++;
100 }
101
102 debug("FPGA: Additional %i sync word needed\n", i);
103
104 /* restoring original CDRATIO */
105 fpgamgr_set_cd_ratio(cd_ratio);
106
107 return 0;
108 }
109
110 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
wait_for_nconfig_pin_and_nstatus_pin(void)111 static int wait_for_nconfig_pin_and_nstatus_pin(void)
112 {
113 unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
114 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
115
116 /*
117 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
118 * de-asserted, timeout at 1000ms
119 */
120 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
121 true, FPGA_TIMEOUT_MSEC, false);
122 }
123
wait_for_f2s_nstatus_pin(unsigned long value)124 static int wait_for_f2s_nstatus_pin(unsigned long value)
125 {
126 /* Poll until f2s to specific value, timeout at 1000ms */
127 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
128 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
129 value, FPGA_TIMEOUT_MSEC, false);
130 }
131
132 /* set CD ratio */
fpgamgr_set_cd_ratio(unsigned long ratio)133 static void fpgamgr_set_cd_ratio(unsigned long ratio)
134 {
135 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
136 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
137
138 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
139 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
140 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
141 }
142
143 /* get the MSEL value, verify we are set for FPP configuration mode */
fpgamgr_verify_msel(void)144 static int fpgamgr_verify_msel(void)
145 {
146 u32 msel = fpgamgr_get_msel();
147
148 if (msel & ~BIT(0)) {
149 printf("Fail: read msel=%d\n", msel);
150 return -EPERM;
151 }
152
153 return 0;
154 }
155
156 /*
157 * Write cdratio and cdwidth based on whether the bitstream is compressed
158 * and/or encoded
159 */
fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width,u32 * rbf_data,size_t rbf_size)160 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
161 size_t rbf_size)
162 {
163 unsigned int cd_ratio;
164 bool encrypt, compress;
165
166 /*
167 * According to the bitstream specification,
168 * both encryption and compression status are
169 * in location before offset 230 of the buffer.
170 */
171 if (rbf_size < MIN_BITSTREAM_SIZECHECK)
172 return -EINVAL;
173
174 encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
175 encrypt = encrypt != 0;
176
177 compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
178 compress = !compress;
179
180 debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
181 debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
182 debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
183 compress);
184
185 /*
186 * from the register map description of cdratio in imgcfg_ctrl_02:
187 * Normal Configuration : 32bit Passive Parallel
188 * Partial Reconfiguration : 16bit Passive Parallel
189 */
190
191 /*
192 * cd ratio is dependent on cfg width and whether the bitstream
193 * is encrypted and/or compressed.
194 *
195 * | width | encr. | compr. | cd ratio |
196 * | 16 | 0 | 0 | 1 |
197 * | 16 | 0 | 1 | 4 |
198 * | 16 | 1 | 0 | 2 |
199 * | 16 | 1 | 1 | 4 |
200 * | 32 | 0 | 0 | 1 |
201 * | 32 | 0 | 1 | 8 |
202 * | 32 | 1 | 0 | 4 |
203 * | 32 | 1 | 1 | 8 |
204 */
205 if (!compress && !encrypt) {
206 cd_ratio = CDRATIO_x1;
207 } else {
208 if (compress)
209 cd_ratio = CDRATIO_x4;
210 else
211 cd_ratio = CDRATIO_x2;
212
213 /* if 32 bit, double the cd ratio (so register
214 field setting is incremented) */
215 if (cfg_width == CFGWDTH_32)
216 cd_ratio += 1;
217 }
218
219 fpgamgr_set_cfgwdth(cfg_width);
220 fpgamgr_set_cd_ratio(cd_ratio);
221
222 return 0;
223 }
224
fpgamgr_reset(void)225 static int fpgamgr_reset(void)
226 {
227 unsigned long reg;
228
229 /* S2F_NCONFIG = 0 */
230 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
231 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
232
233 /* Wait for f2s_nstatus == 0 */
234 if (wait_for_f2s_nstatus_pin(0))
235 return -ETIME;
236
237 /* S2F_NCONFIG = 1 */
238 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
239 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
240
241 /* Wait for f2s_nstatus == 1 */
242 if (wait_for_f2s_nstatus_pin(1))
243 return -ETIME;
244
245 /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
246 reg = readl(&fpga_manager_base->imgcfg_stat);
247 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
248 return -EPERM;
249
250 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
251 return -EPERM;
252
253 return 0;
254 }
255
256 /* Start the FPGA programming by initialize the FPGA Manager */
fpgamgr_program_init(u32 * rbf_data,size_t rbf_size)257 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
258 {
259 int ret;
260
261 /* Step 1 */
262 if (fpgamgr_verify_msel())
263 return -EPERM;
264
265 /* Step 2 */
266 if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
267 return -EPERM;
268
269 /*
270 * Step 3:
271 * Make sure no other external devices are trying to interfere with
272 * programming:
273 */
274 if (wait_for_nconfig_pin_and_nstatus_pin())
275 return -ETIME;
276
277 /*
278 * Step 4:
279 * Deassert the signal drives from HPS
280 *
281 * S2F_NCE = 1
282 * S2F_PR_REQUEST = 0
283 * EN_CFG_CTRL = 0
284 * EN_CFG_DATA = 0
285 * S2F_NCONFIG = 1
286 * S2F_NSTATUS_OE = 0
287 * S2F_CONDONE_OE = 0
288 */
289 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
290 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
291
292 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
293 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
294
295 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
296 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
297 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
298
299 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
300 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
301
302 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
303 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
304 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
305
306 /*
307 * Step 5:
308 * Enable overrides
309 * S2F_NENABLE_CONFIG = 0
310 * S2F_NENABLE_NCONFIG = 0
311 */
312 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
313 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
314 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
315 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
316
317 /*
318 * Disable driving signals that HPS doesn't need to drive.
319 * S2F_NENABLE_NSTATUS = 1
320 * S2F_NENABLE_CONDONE = 1
321 */
322 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
323 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
324 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
325
326 /*
327 * Step 6:
328 * Drive chip select S2F_NCE = 0
329 */
330 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
331 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
332
333 /* Step 7 */
334 if (wait_for_nconfig_pin_and_nstatus_pin())
335 return -ETIME;
336
337 /* Step 8 */
338 ret = fpgamgr_reset();
339
340 if (ret)
341 return ret;
342
343 /*
344 * Step 9:
345 * EN_CFG_CTRL and EN_CFG_DATA = 1
346 */
347 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
348 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
349 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
350
351 return 0;
352 }
353
354 /* Ensure the FPGA entering config done */
fpgamgr_program_poll_cd(void)355 static int fpgamgr_program_poll_cd(void)
356 {
357 unsigned long reg, i;
358
359 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
360 reg = readl(&fpga_manager_base->imgcfg_stat);
361 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
362 return 0;
363
364 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
365 printf("nstatus == 0 while waiting for condone\n");
366 return -EPERM;
367 }
368 WATCHDOG_RESET();
369 }
370
371 if (i == FPGA_TIMEOUT_CNT)
372 return -ETIME;
373
374 return 0;
375 }
376
377 /* Ensure the FPGA entering user mode */
fpgamgr_program_poll_usermode(void)378 static int fpgamgr_program_poll_usermode(void)
379 {
380 unsigned long reg;
381 int ret = 0;
382
383 if (fpgamgr_dclkcnt_set(0xf))
384 return -ETIME;
385
386 ret = wait_for_user_mode();
387 if (ret < 0) {
388 printf("%s: Failed to enter user mode with ", __func__);
389 printf("error code %d\n", ret);
390 return ret;
391 }
392
393 /*
394 * Step 14:
395 * Stop DATA path and Dclk
396 * EN_CFG_CTRL and EN_CFG_DATA = 0
397 */
398 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
399 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
400 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
401
402 /*
403 * Step 15:
404 * Disable overrides
405 * S2F_NENABLE_CONFIG = 1
406 * S2F_NENABLE_NCONFIG = 1
407 */
408 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
409 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
410 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
411 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
412
413 /* Disable chip select S2F_NCE = 1 */
414 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
415 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
416
417 /*
418 * Step 16:
419 * Final check
420 */
421 reg = readl(&fpga_manager_base->imgcfg_stat);
422 if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
423 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
424 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
425 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
426 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
427 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
428 return -EPERM;
429
430 return 0;
431 }
432
fpgamgr_program_finish(void)433 int fpgamgr_program_finish(void)
434 {
435 /* Ensure the FPGA entering config done */
436 int status = fpgamgr_program_poll_cd();
437
438 if (status) {
439 printf("FPGA: Poll CD failed with error code %d\n", status);
440 return -EPERM;
441 }
442
443 /* Ensure the FPGA entering user mode */
444 status = fpgamgr_program_poll_usermode();
445 if (status) {
446 printf("FPGA: Poll usermode failed with error code %d\n",
447 status);
448 return -EPERM;
449 }
450
451 printf("Full Configuration Succeeded.\n");
452
453 return 0;
454 }
455
get_fpga_mgr_ofnode(ofnode from)456 ofnode get_fpga_mgr_ofnode(ofnode from)
457 {
458 return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
459 }
460
get_fpga_filename(void)461 const char *get_fpga_filename(void)
462 {
463 const char *fpga_filename = NULL;
464
465 ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
466
467 if (ofnode_valid(fpgamgr_node))
468 fpga_filename = ofnode_read_string(fpgamgr_node,
469 "altr,bitstream");
470
471 return fpga_filename;
472 }
473
get_rbf_image_info(struct rbf_info * rbf,u16 * buffer)474 static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
475 {
476 /*
477 * Magic ID starting at:
478 * -> 1st dword[15:0] in periph.rbf
479 * -> 2nd dword[15:0] in core.rbf
480 * Note: dword == 32 bits
481 */
482 u32 word_reading_max = 2;
483 u32 i;
484
485 for (i = 0; i < word_reading_max; i++) {
486 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
487 rbf->security = unencrypted;
488 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
489 rbf->security = encrypted;
490 } else if (*(buffer + i + 1) ==
491 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
492 rbf->security = unencrypted;
493 } else if (*(buffer + i + 1) ==
494 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
495 rbf->security = encrypted;
496 } else {
497 rbf->security = invalid;
498 continue;
499 }
500
501 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
502 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
503 rbf->section = periph_section;
504 break;
505 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
506 rbf->section = core_section;
507 break;
508 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
509 rbf->section = periph_section;
510 break;
511 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
512 rbf->section = core_section;
513 break;
514 }
515
516 rbf->section = unknown;
517 break;
518
519 WATCHDOG_RESET();
520 }
521 }
522
523 #ifdef CONFIG_FS_LOADER
first_loading_rbf_to_buffer(struct udevice * dev,struct fpga_loadfs_info * fpga_loadfs,u32 * buffer,size_t * buffer_bsize)524 static int first_loading_rbf_to_buffer(struct udevice *dev,
525 struct fpga_loadfs_info *fpga_loadfs,
526 u32 *buffer, size_t *buffer_bsize)
527 {
528 u32 *buffer_p = (u32 *)*buffer;
529 u32 *loadable = buffer_p;
530 size_t buffer_size = *buffer_bsize;
531 size_t fit_size;
532 int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
533 const char *fpga_node_name = NULL;
534 const char *uname = NULL;
535
536 /* Load image header into buffer */
537 ret = request_firmware_into_buf(dev,
538 fpga_loadfs->fpga_fsinfo->filename,
539 buffer_p, sizeof(struct image_header),
540 0);
541 if (ret < 0) {
542 debug("FPGA: Failed to read image header from flash.\n");
543 return -ENOENT;
544 }
545
546 if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
547 debug("FPGA: No FDT magic was found.\n");
548 return -EBADF;
549 }
550
551 fit_size = fdt_totalsize(buffer_p);
552
553 if (fit_size > buffer_size) {
554 debug("FPGA: FIT image is larger than available buffer.\n");
555 debug("Please use FIT external data or increasing buffer.\n");
556 return -ENOMEM;
557 }
558
559 /* Load entire FIT into buffer */
560 ret = request_firmware_into_buf(dev,
561 fpga_loadfs->fpga_fsinfo->filename,
562 buffer_p, fit_size, 0);
563 if (ret < 0)
564 return ret;
565
566 ret = fit_check_format(buffer_p, IMAGE_SIZE_INVAL);
567 if (ret) {
568 debug("FPGA: No valid FIT image was found.\n");
569 return ret;
570 }
571
572 confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
573 images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
574 if (confs_noffset < 0 || images_noffset < 0) {
575 debug("FPGA: No Configurations or images nodes were found.\n");
576 return -ENOENT;
577 }
578
579 /* Get default configuration unit name from default property */
580 confs_noffset = fit_conf_get_node(buffer_p, NULL);
581 if (confs_noffset < 0) {
582 debug("FPGA: No default configuration was found in config.\n");
583 return -ENOENT;
584 }
585
586 count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
587 FIT_FPGA_PROP);
588 if (count < 0) {
589 debug("FPGA: Invalid configuration format for FPGA node.\n");
590 return count;
591 }
592 debug("FPGA: FPGA node count: %d\n", count);
593
594 for (i = 0; i < count; i++) {
595 images_noffset = fit_conf_get_prop_node_index(buffer_p,
596 confs_noffset,
597 FIT_FPGA_PROP, i);
598 uname = fit_get_name(buffer_p, images_noffset, NULL);
599 if (uname) {
600 debug("FPGA: %s\n", uname);
601
602 if (strstr(uname, "fpga-periph") &&
603 (!is_fpgamgr_early_user_mode() ||
604 is_fpgamgr_user_mode())) {
605 fpga_node_name = uname;
606 printf("FPGA: Start to program ");
607 printf("peripheral/full bitstream ...\n");
608 break;
609 } else if (strstr(uname, "fpga-core") &&
610 (is_fpgamgr_early_user_mode() &&
611 !is_fpgamgr_user_mode())) {
612 fpga_node_name = uname;
613 printf("FPGA: Start to program core ");
614 printf("bitstream ...\n");
615 break;
616 }
617 }
618 WATCHDOG_RESET();
619 }
620
621 if (!fpga_node_name) {
622 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
623 return 1;
624 }
625
626 images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
627 if (images_noffset < 0) {
628 debug("FPGA: No node '%s' was found in FIT.\n",
629 fpga_node_name);
630 return -ENOENT;
631 }
632
633 if (!fit_image_get_data_position(buffer_p, images_noffset,
634 &rbf_offset)) {
635 debug("FPGA: Data position was found.\n");
636 } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
637 &rbf_offset)) {
638 /*
639 * For FIT with external data, figure out where
640 * the external images start. This is the base
641 * for the data-offset properties in each image.
642 */
643 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
644 debug("FPGA: Data offset was found.\n");
645 } else {
646 debug("FPGA: No data position/offset was found.\n");
647 return -ENOENT;
648 }
649
650 ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
651 if (ret < 0) {
652 debug("FPGA: No data size was found (err=%d).\n", ret);
653 return -ENOENT;
654 }
655
656 if (gd->ram_size < rbf_size) {
657 debug("FPGA: Using default OCRAM buffer and size.\n");
658 } else {
659 ret = fit_image_get_load(buffer_p, images_noffset,
660 (ulong *)loadable);
661 if (ret < 0) {
662 buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
663 debug("FPGA: No loadable was found.\n");
664 debug("FPGA: Using default DDR load address: 0x%x .\n",
665 DEFAULT_DDR_LOAD_ADDRESS);
666 } else {
667 buffer_p = (u32 *)*loadable;
668 debug("FPGA: Found loadable address = 0x%x.\n",
669 *loadable);
670 }
671
672 buffer_size = rbf_size;
673 }
674
675 debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
676 rbf_offset, rbf_size);
677
678 fpga_loadfs->remaining = rbf_size;
679
680 /*
681 * Determine buffer size vs bitstream size, and calculating number of
682 * chunk by chunk transfer is required due to smaller buffer size
683 * compare to bitstream
684 */
685 if (rbf_size <= buffer_size) {
686 /* Loading whole bitstream into buffer */
687 buffer_size = rbf_size;
688 fpga_loadfs->remaining = 0;
689 } else {
690 fpga_loadfs->remaining -= buffer_size;
691 }
692
693 fpga_loadfs->offset = rbf_offset;
694 /* Loading bitstream into buffer */
695 ret = request_firmware_into_buf(dev,
696 fpga_loadfs->fpga_fsinfo->filename,
697 buffer_p, buffer_size,
698 fpga_loadfs->offset);
699 if (ret < 0) {
700 debug("FPGA: Failed to read bitstream from flash.\n");
701 return -ENOENT;
702 }
703
704 /* Getting info about bitstream types */
705 get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
706
707 /* Update next reading bitstream offset */
708 fpga_loadfs->offset += buffer_size;
709
710 /* Update the final addr for bitstream */
711 *buffer = (u32)buffer_p;
712
713 /* Update the size of bitstream to be programmed into FPGA */
714 *buffer_bsize = buffer_size;
715
716 return 0;
717 }
718
subsequent_loading_rbf_to_buffer(struct udevice * dev,struct fpga_loadfs_info * fpga_loadfs,u32 * buffer,size_t * buffer_bsize)719 static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
720 struct fpga_loadfs_info *fpga_loadfs,
721 u32 *buffer, size_t *buffer_bsize)
722 {
723 int ret = 0;
724 u32 *buffer_p = (u32 *)*buffer;
725
726 /* Read the bitstream chunk by chunk. */
727 if (fpga_loadfs->remaining > *buffer_bsize) {
728 fpga_loadfs->remaining -= *buffer_bsize;
729 } else {
730 *buffer_bsize = fpga_loadfs->remaining;
731 fpga_loadfs->remaining = 0;
732 }
733
734 ret = request_firmware_into_buf(dev,
735 fpga_loadfs->fpga_fsinfo->filename,
736 buffer_p, *buffer_bsize,
737 fpga_loadfs->offset);
738 if (ret < 0) {
739 debug("FPGA: Failed to read bitstream from flash.\n");
740 return -ENOENT;
741 }
742
743 /* Update next reading bitstream offset */
744 fpga_loadfs->offset += *buffer_bsize;
745
746 return 0;
747 }
748
socfpga_loadfs(fpga_fs_info * fpga_fsinfo,const void * buf,size_t bsize,u32 offset)749 int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
750 u32 offset)
751 {
752 struct fpga_loadfs_info fpga_loadfs;
753 struct udevice *dev;
754 int status, ret, size;
755 u32 buffer = (uintptr_t)buf;
756 size_t buffer_sizebytes = bsize;
757 size_t buffer_sizebytes_ori = bsize;
758 size_t total_sizeof_image = 0;
759 ofnode node;
760 const fdt32_t *phandle_p;
761 u32 phandle;
762
763 node = get_fpga_mgr_ofnode(ofnode_null());
764
765 if (ofnode_valid(node)) {
766 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
767 if (!phandle_p) {
768 node = ofnode_path("/chosen");
769 if (!ofnode_valid(node)) {
770 debug("FPGA: /chosen node was not found.\n");
771 return -ENOENT;
772 }
773
774 phandle_p = ofnode_get_property(node, "firmware-loader",
775 &size);
776 if (!phandle_p) {
777 debug("FPGA: firmware-loader property was not");
778 debug(" found.\n");
779 return -ENOENT;
780 }
781 }
782 } else {
783 debug("FPGA: FPGA manager node was not found.\n");
784 return -ENOENT;
785 }
786
787 phandle = fdt32_to_cpu(*phandle_p);
788 ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
789 phandle, &dev);
790 if (ret)
791 return ret;
792
793 memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
794
795 fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
796 fpga_loadfs.offset = offset;
797
798 printf("FPGA: Checking FPGA configuration setting ...\n");
799
800 /*
801 * Note: Both buffer and buffer_sizebytes values can be altered by
802 * function below.
803 */
804 ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
805 &buffer_sizebytes);
806 if (ret == 1) {
807 printf("FPGA: Skipping configuration ...\n");
808 return 0;
809 } else if (ret) {
810 return ret;
811 }
812
813 if (fpga_loadfs.rbfinfo.section == core_section &&
814 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
815 debug("FPGA : Must be in Early Release mode to program ");
816 debug("core bitstream.\n");
817 return -EPERM;
818 }
819
820 /* Disable all signals from HPS peripheral controller to FPGA */
821 writel(0, &system_manager_base->fpgaintf_en_global);
822
823 /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
824 socfpga_bridges_reset();
825
826 if (fpga_loadfs.rbfinfo.section == periph_section) {
827 /* Initialize the FPGA Manager */
828 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
829 if (status) {
830 debug("FPGA: Init with peripheral bitstream failed.\n");
831 return -EPERM;
832 }
833 }
834
835 /* Transfer bitstream to FPGA Manager */
836 fpgamgr_program_write((void *)buffer, buffer_sizebytes);
837
838 total_sizeof_image += buffer_sizebytes;
839
840 while (fpga_loadfs.remaining) {
841 ret = subsequent_loading_rbf_to_buffer(dev,
842 &fpga_loadfs,
843 &buffer,
844 &buffer_sizebytes_ori);
845
846 if (ret)
847 return ret;
848
849 /* Transfer data to FPGA Manager */
850 fpgamgr_program_write((void *)buffer,
851 buffer_sizebytes_ori);
852
853 total_sizeof_image += buffer_sizebytes_ori;
854
855 WATCHDOG_RESET();
856 }
857
858 if (fpga_loadfs.rbfinfo.section == periph_section) {
859 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
860 config_pins(gd->fdt_blob, "shared");
861 puts("FPGA: Early Release Succeeded.\n");
862 } else {
863 debug("FPGA: Failed to see Early Release.\n");
864 return -EIO;
865 }
866
867 /* For monolithic bitstream */
868 if (is_fpgamgr_user_mode()) {
869 /* Ensure the FPGA entering config done */
870 status = fpgamgr_program_finish();
871 if (status)
872 return status;
873
874 config_pins(gd->fdt_blob, "fpga");
875 puts("FPGA: Enter user mode.\n");
876 }
877 } else if (fpga_loadfs.rbfinfo.section == core_section) {
878 /* Ensure the FPGA entering config done */
879 status = fpgamgr_program_finish();
880 if (status)
881 return status;
882
883 config_pins(gd->fdt_blob, "fpga");
884 puts("FPGA: Enter user mode.\n");
885 } else {
886 debug("FPGA: Config Error: Unsupported bitstream type.\n");
887 return -ENOEXEC;
888 }
889
890 return (int)total_sizeof_image;
891 }
892
fpgamgr_program(const void * buf,size_t bsize,u32 offset)893 void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
894 {
895 fpga_fs_info fpga_fsinfo;
896
897 fpga_fsinfo.filename = get_fpga_filename();
898
899 if (fpga_fsinfo.filename)
900 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
901 }
902 #endif
903
904 /* This function is used to load the core bitstream from the OCRAM. */
socfpga_load(Altera_desc * desc,const void * rbf_data,size_t rbf_size)905 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
906 {
907 unsigned long status;
908 struct rbf_info rbfinfo;
909
910 memset(&rbfinfo, 0, sizeof(rbfinfo));
911
912 /* Disable all signals from hps peripheral controller to fpga */
913 writel(0, &system_manager_base->fpgaintf_en_global);
914
915 /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
916 socfpga_bridges_reset();
917
918 /* Getting info about bitstream types */
919 get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
920
921 if (rbfinfo.section == periph_section) {
922 /* Initialize the FPGA Manager */
923 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
924 if (status)
925 return status;
926 }
927
928 if (rbfinfo.section == core_section &&
929 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
930 debug("FPGA : Must be in early release mode to program ");
931 debug("core bitstream.\n");
932 return -EPERM;
933 }
934
935 /* Write the bitstream to FPGA Manager */
936 fpgamgr_program_write(rbf_data, rbf_size);
937
938 status = fpgamgr_program_finish();
939 if (status)
940 return status;
941
942 config_pins(gd->fdt_blob, "fpga");
943 puts("FPGA: Enter user mode.\n");
944
945 return status;
946 }
947