1 /**
2 ****************************************************************************************
3 *
4 * @file gr55xx_hal_dma.h
5 * @author BLE Driver Team
6 * @brief Header file containing functions prototypes of DMA HAL library.
7 *
8 ****************************************************************************************
9 * @attention
10 #####Copyright (c) 2019 GOODIX
11 All rights reserved.
12
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 * Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 * Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 * Neither the name of GOODIX nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ****************************************************************************************
36 */
37
38 /** @addtogroup PERIPHERAL Peripheral Driver
39 * @{
40 */
41
42 /** @addtogroup HAL_DRIVER HAL Driver
43 * @{
44 */
45
46 /** @defgroup HAL_DMA DMA
47 * @brief DMA HAL module driver.
48 * @{
49 */
50
51 /* Define to prevent recursive inclusion -------------------------------------*/
52 #ifndef __GR55xx_HAL_DMA_H__
53 #define __GR55xx_HAL_DMA_H__
54
55 /* Includes ------------------------------------------------------------------*/
56 #include <stdbool.h>
57 #include "gr55xx_ll_dma.h"
58 #include "gr55xx_hal_def.h"
59
60 #ifdef __cplusplus
61 extern "C" {
62 #endif
63
64 /* Exported types ------------------------------------------------------------*/
65 /** @addtogroup HAL_DMA_ENUMERATIONS Enumerations
66 * @{
67 */
68
69 /** @defgroup HAL_DMA_state HAL DMA state
70 * @{
71 */
72
73 /**
74 * @brief HAL DMA State Enumerations definition
75 */
76 typedef enum {
77 HAL_DMA_STATE_RESET = 0x00U, /**< DMA not yet initialized or disabled */
78 HAL_DMA_STATE_READY = 0x01U, /**< DMA process success and ready for use */
79 HAL_DMA_STATE_BUSY = 0x02U, /**< DMA process is ongoing */
80 HAL_DMA_STATE_TIMEOUT = 0x03U, /**< DMA timeout state */
81 HAL_DMA_STATE_ERROR = 0x04U, /**< DMA error state */
82 } hal_dma_state_t;
83 /** @} */
84
85 /** @defgroup HAL_DMA_channel HAL DMA channel
86 * @{
87 */
88
89 /**
90 * @brief HAL DMA Channel Enumerations definition
91 */
92 typedef enum {
93 DMA_Channel0 = 0U, /**< Channel 0 */
94 DMA_Channel1 = 1U, /**< Channel 1 */
95 DMA_Channel2 = 2U, /**< Channel 2 */
96 DMA_Channel3 = 3U, /**< Channel 3 */
97 DMA_Channel4 = 4U, /**< Channel 4 */
98 DMA_Channel5 = 5U, /**< Channel 5 */
99 DMA_Channel6 = 6U, /**< Channel 6 */
100 DMA_Channel7 = 7U, /**< Channel 7 */
101 } dma_channel_t;
102 /** @} */
103
104 /** @defgroup HAL_DMA_callback_ID HAL DMA callback ID
105 * @{
106 */
107
108 /**
109 * @brief HAL DMA Callback ID Enumerations definition
110 */
111 typedef enum {
112 HAL_DMA_XFER_TFR_CB_ID = 0x00, /**< Full transfer */
113 HAL_DMA_XFER_BLK_CB_ID = 0x01, /**< Block transfer */
114 HAL_DMA_XFER_ERROR_CB_ID = 0x02, /**< Error */
115 HAL_DMA_XFER_ABORT_CB_ID = 0x03, /**< Abort */
116 HAL_DMA_XFER_ALL_CB_ID = 0x04 /**< All */
117 } hal_dma_callback_id_t;
118 /** @} */
119
120 /** @} */
121
122
123 /** @addtogroup HAL_DMA_STRUCTURES Structures
124 * @{
125 */
126
127 /** @defgroup DMA_Configuration DMA Configuration
128 * @{
129 */
130
131 /**
132 * @brief DMA Configuration Structure definition
133 */
134 typedef struct _dma_init {
135 uint32_t src_request; /**< Specifies the source request selected for the specified channel.
136 This parameter can be a value of @ref DMA_request */
137
138 uint32_t dst_request; /**< Specifies the destination request selected for the specified channel.
139 This parameter can be a value of @ref DMA_request */
140
141 uint32_t direction; /**< Specifies if the data will be transferred from memory to peripheral,
142 from memory to memory or from peripheral to memory.
143 This parameter can be a value of @ref DMA_Data_transfer_direction */
144
145 uint32_t src_increment; /**< Specifies whether the srouce address register should be incremented
146 or decrement or not.
147 This parameter can be a value of @ref DMA_Source_incremented_mode */
148
149 uint32_t dst_increment; /**< Specifies whether the destination address register should be incremented
150 or decrement or not.
151 This parameter can be a
152 value of @ref
153 DMA_Destination_incremented_mode
154 */
155
156 uint32_t src_data_alignment; /**< Specifies the source data width.
157 This parameter can be a value of @ref DMA_Source_data_size */
158
159 uint32_t dst_data_alignment; /**< Specifies the destination data width.
160 This parameter can be a value of @ref DMA_Destination_data_size */
161
162 uint32_t mode; /**< Specifies the operation mode of the DMA Channel(Normal or Circular).
163 This parameter can be a value of @ref DMA_mode
164 @note The circular buffer
165 mode cannot be used if
166 the memory-to-memory
167 data transfer is configured on the selected Channel */
168
169 uint32_t priority; /**< Specifies the software priority for the DMA Channel.
170 This parameter can be a value of @ref DMA_Priority_level */
171 } dma_init_t;
172
173 /** @} */
174
175 /** @defgroup DMA_handle DMA handle
176 * @{
177 */
178
179 /**
180 * @brief DMA handle Structure definition
181 */
182 typedef struct _dma_handle {
183 dma_channel_t channel; /**< DMA Channel Number */
184
185 dma_init_t init; /**< DMA communication parameters */
186
187 hal_lock_t lock; /**< DMA locking object */
188
189 __IO hal_dma_state_t state; /**< DMA transfer state */
190
191 void *p_parent; /**< Parent object state */
192
193 void (* xfer_tfr_callback)(struct _dma_handle *p_dma); /**< DMA transfer complete callback */
194
195 void (* xfer_blk_callback)(struct _dma_handle *p_dma); /**< DMA block complete callback */
196
197 void (* xfer_error_callback)(struct _dma_handle *p_dma); /**< DMA transfer error callback */
198
199 void (* xfer_abort_callback)(struct _dma_handle *p_dma); /**< DMA transfer abort callback */
200
201 __IO uint32_t error_code; /**< DMA Error code */
202
203 uint32_t retention[5]; /**< DMA important register
204 information. */
205 } dma_handle_t;
206
207 /** @} */
208
209 /** @} */
210
211
212 /**
213 * @defgroup HAL_DMA_MACRO Defines
214 * @{
215 */
216
217 /* Exported constants --------------------------------------------------------*/
218 /** @defgroup DMA_Exported_Constants DMA Exported Constants
219 * @{
220 */
221
222 /** @defgroup DMA_Error_Code DMA Error Code
223 * @{
224 */
225 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /**< No error */
226 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /**< Transfer error */
227 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /**< no ongoing transfer */
228 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /**< Timeout error */
229 /** @} */
230
231 /** @defgroup DMA_request DMA request definitions
232 * @{
233 */
234 #define DMA_REQUEST_SPIM_TX LL_DMA_PERIPH_SPIM_TX /**< DMA SPIM transmit request */
235 #define DMA_REQUEST_SPIM_RX LL_DMA_PERIPH_SPIM_RX /**< DMA SPIM receive request */
236 #define DMA_REQUEST_SPIS_TX LL_DMA_PERIPH_SPIS_TX /**< DMA SPIS transmit request */
237 #define DMA_REQUEST_SPIS_RX LL_DMA_PERIPH_SPIS_RX /**< DMA SPIS receive request */
238 #define DMA_REQUEST_QSPI0_TX LL_DMA_PERIPH_QSPI0_TX /**< DMA QSPI0 transmit request */
239 #define DMA_REQUEST_QSPI0_RX LL_DMA_PERIPH_QSPI0_RX /**< DMA QSPI0 receive request */
240 #define DMA_REQUEST_I2C0_TX LL_DMA_PERIPH_I2C0_TX /**< DMA I2C0 transmit request */
241 #define DMA_REQUEST_I2C0_RX LL_DMA_PERIPH_I2C0_RX /**< DMA I2C0 receive request */
242 #define DMA_REQUEST_I2C1_TX LL_DMA_PERIPH_I2C1_TX /**< DMA I2C1 transmit request */
243 #define DMA_REQUEST_I2C1_RX LL_DMA_PERIPH_I2C1_RX /**< DMA I2C1 receive request */
244 #define DMA_REQUEST_I2S_S_TX LL_DMA_PERIPH_I2S_S_TX /**< DMA I2S_S transmit request */
245 #define DMA_REQUEST_I2S_S_RX LL_DMA_PERIPH_I2S_S_RX /**< DMA I2S_S receive request */
246 #define DMA_REQUEST_UART0_TX LL_DMA_PERIPH_UART0_TX /**< DMA UART0 transmit request */
247 #define DMA_REQUEST_UART0_RX LL_DMA_PERIPH_UART0_RX /**< DMA UART0 receive request */
248 #define DMA_REQUEST_QSPI1_TX LL_DMA_PERIPH_QSPI1_TX /**< DMA QSPI1 transmit request */
249 #define DMA_REQUEST_QSPI1_RX LL_DMA_PERIPH_QSPI1_RX /**< DMA QSPI1 receive request */
250 #define DMA_REQUEST_I2S_M_TX LL_DMA_PERIPH_I2S_M_TX /**< DMA I2S_M transmit request */
251 #define DMA_REQUEST_I2S_M_RX LL_DMA_PERIPH_I2S_M_RX /**< DMA I2S_M receive request */
252 #define DMA_REQUEST_SNSADC LL_DMA_PERIPH_SNSADC /**< DMA SenseADC request */
253 #define DMA_REQUEST_MEM LL_DMA_PERIPH_MEM /**< DMA Memory request */
254 /** @} */
255
256 /** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions
257 * @{
258 */
259 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /**< Memory to memory direction */
260 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /**< Memory to peripheral direction */
261 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /**< Peripheral to memory direction */
262 #define DMA_PERIPH_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_PERIPH /**< Peripheral to
263 Peripheral direction */
264 /** @} */
265
266 /** @defgroup DMA_Source_incremented_mode DMA Source Incremented Mode
267 * @{
268 */
269 #define DMA_SRC_INCREMENT LL_DMA_SRC_INCREMENT /**< Source increment mode */
270 #define DMA_SRC_DECREMENT LL_DMA_SRC_DECREMENT /**< Source decrement mode */
271 #define DMA_SRC_NO_CHANGE LL_DMA_SRC_NO_CHANGE /**< Source no change mode */
272 /** @} */
273
274 /** @defgroup DMA_Destination_incremented_mode DMA Destination Incremented Mode
275 * @{
276 */
277 #define DMA_DST_INCREMENT LL_DMA_DST_INCREMENT /**< Destination increment mode */
278 #define DMA_DST_DECREMENT LL_DMA_DST_DECREMENT /**< Destination decrement mode */
279 #define DMA_DST_NO_CHANGE LL_DMA_DST_NO_CHANGE /**< Destination no change mode */
280 /** @} */
281
282 /** @defgroup DMA_Source_data_size DMA Source Data Size Alignment
283 * @{
284 */
285 #define DMA_SDATAALIGN_BYTE LL_DMA_SDATAALIGN_BYTE /**< Source data alignment : Byte */
286 #define DMA_SDATAALIGN_HALFWORD LL_DMA_SDATAALIGN_HALFWORD /**< Source data alignment : HalfWord */
287 #define DMA_SDATAALIGN_WORD LL_DMA_SDATAALIGN_WORD /**< Source data alignment : Word */
288 /** @} */
289
290 /** @defgroup DMA_Destination_data_size DMA Destination Data Size Alignment
291 * @{
292 */
293 #define DMA_DDATAALIGN_BYTE LL_DMA_DDATAALIGN_BYTE /**< Destination data alignment : Byte */
294 #define DMA_DDATAALIGN_HALFWORD LL_DMA_DDATAALIGN_HALFWORD /**< Destination data alignment : HalfWord */
295 #define DMA_DDATAALIGN_WORD LL_DMA_DDATAALIGN_WORD /**< Destination data alignment : Word */
296 /** @} */
297
298 /** @defgroup DMA_mode DMA Mode
299 * @{
300 */
301 #define DMA_NORMAL LL_DMA_MODE_SINGLE_BLOCK /**< Normal Mode */
302 #define DMA_CIRCULAR LL_DMA_MODE_MULTI_BLOCK_ALL_RELOAD /**< Circular Mode */
303
304 /** @} */
305
306 /** @defgroup DMA_Priority_level DMA Priority Level
307 * @{
308 */
309 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_0 /**< Priority level : Low */
310 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_2 /**< Priority level : Medium */
311 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_5 /**< Priority level : High */
312 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_7 /**< Priority level : Very High */
313 /** @} */
314
315 /** @} */
316
317 /* Private macros ------------------------------------------------------------*/
318 /** @defgroup DMA_Private_Macro DMA Private Macros
319 * @{
320 */
321
322 /** @brief Check if DMA channel instance is valid.
323 * @param __instance__ DMA channel instance.
324 * @retval SET (__instance__ is valid) or RESET (__instance__ is invalid)
325 */
IS_DMA_ALL_INSTANCE(dma_channel_t __instance__)326 __STATIC_INLINE bool IS_DMA_ALL_INSTANCE(dma_channel_t __instance__)
327 {
328 return (((__instance__) == DMA_Channel0) || ((__instance__) == DMA_Channel1) || \
329 ((__instance__) == DMA_Channel2) || ((__instance__) == DMA_Channel3) || \
330 ((__instance__) == DMA_Channel4) || ((__instance__) == DMA_Channel5) || \
331 ((__instance__) == DMA_Channel6) || ((__instance__) == DMA_Channel7));
332 }
333
334 /** @brief Check if DMA request is valid.
335 * @param __REQUEST__ DMA request.
336 * @retval SET (__REQUEST__ is valid) or RESET (__REQUEST__ is invalid)
337 */
IS_DMA_ALL_REQUEST(uint32_t __REQUEST__)338 __STATIC_INLINE bool IS_DMA_ALL_REQUEST(uint32_t __REQUEST__)
339 {
340 return (((__REQUEST__) == DMA_REQUEST_SPIM_TX) || \
341 ((__REQUEST__) == DMA_REQUEST_SPIM_RX) || \
342 ((__REQUEST__) == DMA_REQUEST_SPIS_TX) || \
343 ((__REQUEST__) == DMA_REQUEST_SPIS_RX) || \
344 ((__REQUEST__) == DMA_REQUEST_QSPI0_TX) || \
345 ((__REQUEST__) == DMA_REQUEST_QSPI0_RX) || \
346 ((__REQUEST__) == DMA_REQUEST_I2C0_TX) || \
347 ((__REQUEST__) == DMA_REQUEST_I2C0_RX) || \
348 ((__REQUEST__) == DMA_REQUEST_I2C1_TX) || \
349 ((__REQUEST__) == DMA_REQUEST_I2C1_RX) || \
350 ((__REQUEST__) == DMA_REQUEST_I2S_S_TX) || \
351 ((__REQUEST__) == DMA_REQUEST_I2S_S_RX) || \
352 ((__REQUEST__) == DMA_REQUEST_UART0_TX) || \
353 ((__REQUEST__) == DMA_REQUEST_UART0_RX) || \
354 ((__REQUEST__) == DMA_REQUEST_QSPI1_TX) || \
355 ((__REQUEST__) == DMA_REQUEST_QSPI1_RX) || \
356 ((__REQUEST__) == DMA_REQUEST_I2S_M_TX) || \
357 ((__REQUEST__) == DMA_REQUEST_I2S_M_RX) || \
358 ((__REQUEST__) == DMA_REQUEST_SNSADC) || \
359 ((__REQUEST__) == DMA_REQUEST_MEM));
360 }
361
362 /** @brief Check if DMA direction is valid.
363 * @param __DIRECTION__ DMA direction.
364 * @retval SET (__DIRECTION__ is valid) or RESET (__DIRECTION__ is invalid)
365 */
IS_DMA_DIRECTION(uint32_t __DIRECTION__)366 __STATIC_INLINE bool IS_DMA_DIRECTION(uint32_t __DIRECTION__)
367 {
368 return (((__DIRECTION__) == DMA_MEMORY_TO_MEMORY) || \
369 ((__DIRECTION__) == DMA_MEMORY_TO_PERIPH) || \
370 ((__DIRECTION__) == DMA_PERIPH_TO_MEMORY) || \
371 ((__DIRECTION__) == DMA_PERIPH_TO_PERIPH));
372 }
373
374 /** @brief Check if DMA buffer size is valid.
375 * @param __SIZE__ DMA buffer size.
376 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
377 */
IS_DMA_BUFFER_SIZE(uint32_t __SIZE__)378 __STATIC_INLINE bool IS_DMA_BUFFER_SIZE(uint32_t __SIZE__)
379 {
380 return (((__SIZE__) >= 0x1) && ((__SIZE__) < 0xFFF));
381 }
382
383 /** @brief Check if DMA source address increment state is valid.
384 * @param __STATE__ DMA source address increment state.
385 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
386 */
IS_DMA_SOURCE_INC_STATE(uint32_t __STATE__)387 __STATIC_INLINE bool IS_DMA_SOURCE_INC_STATE(uint32_t __STATE__)
388 {
389 return (((__STATE__) == DMA_SRC_INCREMENT) || \
390 ((__STATE__) == DMA_SRC_DECREMENT) || \
391 ((__STATE__) == DMA_SRC_NO_CHANGE));
392 }
393
394 /** @brief Check if DMA destination address increment state is valid.
395 * @param __STATE__ DMA destination address increment state.
396 * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
397 */
IS_DMA_DESTINATION_INC_STATE(uint32_t __STATE__)398 __STATIC_INLINE bool IS_DMA_DESTINATION_INC_STATE(uint32_t __STATE__)
399 {
400 return (((__STATE__) == DMA_DST_INCREMENT) || \
401 ((__STATE__) == DMA_DST_DECREMENT) || \
402 ((__STATE__) == DMA_DST_NO_CHANGE));
403 }
404
405 /** @brief Check if DMA source data size is valid.
406 * @param __SIZE__ DMA source data size.
407 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
408 */
IS_DMA_SOURCE_DATA_SIZE(uint32_t __SIZE__)409 __STATIC_INLINE bool IS_DMA_SOURCE_DATA_SIZE(uint32_t __SIZE__)
410 {
411 return (((__SIZE__) == DMA_SDATAALIGN_BYTE) || \
412 ((__SIZE__) == DMA_SDATAALIGN_HALFWORD) || \
413 ((__SIZE__) == DMA_SDATAALIGN_WORD));
414 }
415
416 /** @brief Check if DMA destination data size is valid.
417 * @param __SIZE__ DMA destination data size.
418 * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
419 */
IS_DMA_DESTINATION_DATA_SIZE(uint32_t __SIZE__)420 __STATIC_INLINE bool IS_DMA_DESTINATION_DATA_SIZE(uint32_t __SIZE__)
421 {
422 return (((__SIZE__) == DMA_DDATAALIGN_BYTE) || \
423 ((__SIZE__) == DMA_DDATAALIGN_HALFWORD) || \
424 ((__SIZE__) == DMA_DDATAALIGN_WORD));
425 }
426
427 /** @brief Check if DMA mode is valid.
428 * @param __MODE__ DMA mode.
429 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
430 */
IS_DMA_MODE(uint32_t __MODE__)431 __STATIC_INLINE bool IS_DMA_MODE(uint32_t __MODE__)
432 {
433 return (((__MODE__) == DMA_NORMAL) || ((__MODE__) == DMA_CIRCULAR));
434 }
435
436 /** @brief Check if DMA priority is valid.
437 * @param __PRIORITY__ DMA priority.
438 * @retval SET (__PRIORITY__ is valid) or RESET (__PRIORITY__ is invalid)
439 */
IS_DMA_PRIORITY(uint32_t __PRIORITY__)440 __STATIC_INLINE bool IS_DMA_PRIORITY(uint32_t __PRIORITY__)
441 {
442 return (((__PRIORITY__) == DMA_PRIORITY_LOW ) || ((__PRIORITY__) == DMA_PRIORITY_MEDIUM) || \
443 ((__PRIORITY__) == DMA_PRIORITY_HIGH) || ((__PRIORITY__) == DMA_PRIORITY_VERY_HIGH));
444 }
445 /** @} */
446
447 /** @} */
448
449
450 /* Exported functions --------------------------------------------------------*/
451 /** @addtogroup HAL_DMA_DRIVER_FUNCTIONS Functions
452 * @{
453 */
454
455 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
456 * @brief Initialization and de-initialization functions
457 *
458 @verbatim
459 ===============================================================================
460 ##### Initialization and de-initialization functions #####
461 ===============================================================================
462 [..]
463 This section provides functions allowing to initialize the DMA Channel source
464 and destination addresses, incrementation and data sizes, transfer direction,
465 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
466 [..]
467 The hal_dma_init() function follows the DMA configuration procedures as described in
468 reference manual.
469
470 @endverbatim
471 * @{
472 */
473
474 /**
475 ****************************************************************************************
476 * @brief Initialize the DMA according to the specified
477 * parameters in the dma_init_t and initialize the associated handle.
478 *
479 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
480 * information for the specified DMA Channel.
481 *
482 * @retval ::HAL_OK: Operation is OK.
483 * @retval ::HAL_ERROR: Parameter error or operation not supported.
484 * @retval ::HAL_BUSY: Driver is busy.
485 * @retval ::HAL_TIMEOUT: Timeout occurred.
486 ****************************************************************************************
487 */
488 hal_status_t hal_dma_init(dma_handle_t *p_dma);
489
490 /**
491 ****************************************************************************************
492 * @brief De-initialize the DMA peripheral.
493 *
494 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
495 * information for the specified DMA Channel.
496 *
497 * @retval ::HAL_OK: Operation is OK.
498 * @retval ::HAL_ERROR: Parameter error or operation not supported.
499 * @retval ::HAL_BUSY: Driver is busy.
500 * @retval ::HAL_TIMEOUT: Timeout occurred.
501 ****************************************************************************************
502 */
503 hal_status_t hal_dma_deinit (dma_handle_t *p_dma);
504
505 /** @} */
506
507
508 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
509 * @brief Input and Output operation functions
510 *
511 @verbatim
512 ===============================================================================
513 ##### IO operation functions #####
514 ===============================================================================
515 [..] This section provides functions allowing to:
516 (+) Configure the source, destination address and data length and Start DMA transfer
517 (+) Configure the source, destination address and data length and
518 Start DMA transfer with interrupt
519 (+) Abort DMA transfer
520 (+) Poll for transfer complete
521 (+) Handle DMA interrupt request
522
523 @endverbatim
524 * @{
525 */
526
527 /**
528 ****************************************************************************************
529 * @brief Start the DMA Transfer.
530 *
531 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
532 * information for the specified DMA Channel.
533 * @param[in] src_address: The source memory Buffer address
534 * @param[in] dst_address: The destination memory Buffer address
535 * @param[in] data_length: The length of data to be transferred from
536 * source to destination, ranging between 0 and
537 * 4095.
538 *
539 * @retval ::HAL_OK: Operation is OK.
540 * @retval ::HAL_ERROR: Parameter error or operation not supported.
541 * @retval ::HAL_BUSY: Driver is busy.
542 * @retval ::HAL_TIMEOUT: Timeout occurred.
543 ****************************************************************************************
544 */
545 hal_status_t hal_dma_start (dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
546
547 /**
548 ****************************************************************************************
549 * @brief Start the DMA Transfer with interrupt enabled.
550 *
551 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
552 * information for the specified DMA Channel.
553 * @param[in] src_address: The source memory Buffer address
554 * @param[in] dst_address: The destination memory Buffer address
555 * @param[in] data_length: The length of data to be transferred from
556 * source to destination, ranging between 0 and
557 * 4095.
558 *
559 * @retval ::HAL_OK: Operation is OK.
560 * @retval ::HAL_ERROR: Parameter error or operation not supported.
561 * @retval ::HAL_BUSY: Driver is busy.
562 * @retval ::HAL_TIMEOUT: Timeout occurred.
563 ****************************************************************************************
564 */
565 hal_status_t hal_dma_start_it(dma_handle_t *p_dma, uint32_t src_address, uint32_t dst_address, uint32_t data_length);
566
567 /**
568 ****************************************************************************************
569 * @brief Abort the DMA Transfer.
570 *
571 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
572 * information for the specified DMA Channel.
573 *
574 * @retval ::HAL_OK: Operation is OK.
575 * @retval ::HAL_ERROR: Parameter error or operation not supported.
576 * @retval ::HAL_BUSY: Driver is busy.
577 * @retval ::HAL_TIMEOUT: Timeout occurred.
578 ****************************************************************************************
579 */
580 hal_status_t hal_dma_abort(dma_handle_t *p_dma);
581
582 /**
583 ****************************************************************************************
584 * @brief Aborts the DMA Transfer in Interrupt mode.
585 *
586 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
587 * information for the specified DMA Channel.
588 *
589 * @retval ::HAL_OK: Operation is OK.
590 * @retval ::HAL_ERROR: Parameter error or operation not supported.
591 * @retval ::HAL_BUSY: Driver is busy.
592 * @retval ::HAL_TIMEOUT: Timeout occurred.
593 ****************************************************************************************
594 */
595 hal_status_t hal_dma_abort_it(dma_handle_t *p_dma);
596
597 /**
598 ****************************************************************************************
599 * @brief Polling for transfer complete.
600 *
601 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
602 * information for the specified DMA Channel.
603 * @param[in] timeout: Timeout duration.
604 *
605 * @retval ::HAL_OK: Operation is OK.
606 * @retval ::HAL_ERROR: Parameter error or operation not supported.
607 * @retval ::HAL_BUSY: Driver is busy.
608 * @retval ::HAL_TIMEOUT: Timeout occurred.
609 ****************************************************************************************
610 */
611 hal_status_t hal_dma_poll_for_transfer(dma_handle_t *p_dma, uint32_t timeout);
612
613 /** @} */
614
615 /** @addtogroup DMA_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
616 * @brief IRQ Handler and Callbacks functions
617 * @{
618 */
619
620 /**
621 ****************************************************************************************
622 * @brief Handle DMA interrupt request.
623 *
624 * @param[in] p_dma: Pointer to a DMA handle which contains the
625 * configuration information for the specified DMA Channel.
626 ****************************************************************************************
627 */
628 void hal_dma_irq_handler(dma_handle_t *p_dma);
629
630 /**
631 ****************************************************************************************
632 * @brief Register callbacks
633 *
634 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
635 * information for the specified DMA Channel.
636 * @param[in] id: User Callback identifer. This parameter can be one of the following values:
637 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
638 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
639 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
640 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
641 * @param[in] callback: Pointer to private callback function which
642 * has pointer to dma_handle_t structure as
643 * parameter.
644 *
645 * @retval ::HAL_OK: Operation is OK.
646 * @retval ::HAL_ERROR: Parameter error or operation not supported.
647 * @retval ::HAL_BUSY: Driver is busy.
648 * @retval ::HAL_TIMEOUT: Timeout occurred.
649 ****************************************************************************************
650 */
651 hal_status_t hal_dma_register_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id,
652 void (* callback)(dma_handle_t *p_dma));
653
654 /**
655 ****************************************************************************************
656 * @brief UnRegister callbacks
657 *
658 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
659 * information for the specified DMA Channel.
660 * @param[in] id: User Callback identifer. This parameter can be a combiantion of the following values:
661 * @arg @ref HAL_DMA_XFER_TFR_CB_ID
662 * @arg @ref HAL_DMA_XFER_BLK_CB_ID
663 * @arg @ref HAL_DMA_XFER_ERROR_CB_ID
664 * @arg @ref HAL_DMA_XFER_ABORT_CB_ID
665 * @arg @ref HAL_DMA_XFER_ALL_CB_ID
666 *
667 * @retval ::HAL_OK: Operation is OK.
668 * @retval ::HAL_ERROR: Parameter error or operation not supported.
669 * @retval ::HAL_BUSY: Driver is busy.
670 * @retval ::HAL_TIMEOUT: Timeout occurred.
671 ****************************************************************************************
672 */
673 hal_status_t hal_dma_unregister_callback(dma_handle_t *p_dma, hal_dma_callback_id_t id);
674
675 /** @} */
676
677 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
678 * @brief Peripheral State and Errors functions
679 *
680 @verbatim
681 ===============================================================================
682 ##### Peripheral State and Errors functions #####
683 ===============================================================================
684 [..]
685 This subsection provides functions allowing to
686 (+) Check the DMA state
687 (+) Get error code
688
689 @endverbatim
690 * @{
691 */
692
693 /**
694 ****************************************************************************************
695 * @brief Return the DMA hande state.
696 *
697 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
698 * information for the specified DMA Channel.
699 *
700 * @retval ::HAL_DMA_STATE_RESET: DMA not yet initialized or disabled.
701 * @retval ::HAL_DMA_STATE_READY: DMA process succeeded and ready for use.
702 * @retval ::HAL_DMA_STATE_BUSY: DMA process is ongoing.
703 * @retval ::HAL_DMA_STATE_TIMEOUT: DMA timeout state.
704 * @retval ::HAL_DMA_STATE_ERROR: DMA error state.
705 ****************************************************************************************
706 */
707 hal_dma_state_t hal_dma_get_state(dma_handle_t *p_dma);
708
709 /**
710 ****************************************************************************************
711 * @brief Return the DMA error code.
712 *
713 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
714 * information for the specified DMA Channel.
715 *
716 * @return DMA Error Code
717 ****************************************************************************************
718 */
719 uint32_t hal_dma_get_error(dma_handle_t *p_dma);
720
721 /**
722 ****************************************************************************************
723 * @brief Suspend some registers related to DMA configuration before sleep.
724 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
725 * information for the specified DMA Channel.
726 * @retval ::HAL_OK: Operation is OK.
727 * @retval ::HAL_ERROR: Parameter error or operation not supported.
728 * @retval ::HAL_BUSY: Driver is busy.
729 * @retval ::HAL_TIMEOUT: Timeout occurred.
730 ****************************************************************************************
731 */
732 hal_status_t hal_dma_suspend_reg(dma_handle_t *p_dma);
733
734 /**
735 ****************************************************************************************
736 * @brief Restore some registers related to DMA configuration after sleep.
737 * This function must be used in conjunction with the hal_dma_resume_reg().
738 * @param[in] p_dma: Pointer to a DMA handle which contains the configuration
739 * information for the specified DMA Channel.
740 * @retval ::HAL_OK: Operation is OK.
741 * @retval ::HAL_ERROR: Parameter error or operation not supported.
742 * @retval ::HAL_BUSY: Driver is busy.
743 * @retval ::HAL_TIMEOUT: Timeout occurred.
744 ****************************************************************************************
745 */
746 hal_status_t hal_dma_resume_reg(dma_handle_t *p_dma);
747
748 /** @} */
749
750 /** @} */
751
752 #ifdef __cplusplus
753 }
754 #endif
755
756 #endif /* __GR55xx_HAL_DMA_H__ */
757
758 /** @} */
759
760 /** @} */
761
762 /** @} */
763