1 /*
2 * Copyright (C) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #include <linux/version.h>
20 #include "securec.h"
21 #include "hi_log.h"
22
23 #include "drv_i2c.h"
24 #include "drv_i2c_ioctl.h"
25 #include "hi_sys_reg.h"
26 #include "hi_common.h"
27 #include "hi_drv_i2c.h"
28 #include "hi_module.h"
29 #include "hi_error_mpi.h"
30 #include "hi_osal.h"
31 #include "hi_drv_gpioi2c.h"
32 #include "drv_base_ext.h"
33
34 #ifdef CFG_HI_USER_DRV
35 volatile hi_reg_crg *g_pst_reg_crg = NULL;
36 #endif
37
38 #define SONY_I2C_START_EN 0x01 /* < Output START (S) */
39 #define SONY_I2C_STOP_EN 0x02 /* < Output STOP (P) */
40
41 // Wait time will change with cpu running freq
42 #define I2C_WAIT_TIME_OUT 0x10000
43 #define RESTART_TIME 3
44
45 #define i2c_write_reg(Addr, Value) ((*(volatile hi_u32 *)(Addr)) = (Value))
46 #define i2c_read_reg(Addr) (*(volatile hi_u32 *)(Addr))
47 #define i2c_scl_clk(a, b) (((a) / ((b) * 2)) / 2 - 1)
48
49 #define I2C_CLEAR_ALL_MASK 0x100
50 #define I2C_SET_IRQ_MASK 0x181 /* bit 0 & bit 7 */
51 #define HI_I2C0_IRQ_NO (38 + 32) /* I2C0 Irq No */
52 #define HI_I2C1_IRQ_NO (39 + 32) /* I2C1 Irq No */
53 #define I2C1_IRQ_NAME "hi_i2c1_irq"
54 #define I2C0_IRQ_NAME "hi_i2c0_irq"
55
56 typedef struct i2c_drv_irq_info_s {
57 hi_u32 irq_send_count;
58 hi_u32 irq_recv_count;
59 hi_u32 irq_ack_err;
60 hi_bool irq_wakeup_flag;
61 hi_bool irq_is_send_data;
62 } i2c_drv_irq_info;
63
64 typedef struct i2c_drv_info_s {
65 hi_u32 i2c_num;
66 hi_u8 i2c_dev_addr;
67 hi_u32 i2c_reg_addr;
68 hi_u32 i2c_reg_addr_byte_num;
69 hi_u8 *data;
70 hi_u32 data_len;
71 i2c_drv_irq_info irq_info;
72 } i2c_drv_info;
73
74 i2c_drv_info g_i2c_info[HI_STD_I2C_NUM] = {0};
75 osal_wait g_i2c_wait_queue[HI_STD_I2C_NUM];
76
77 osal_semaphore g_i2c_sem;
78 osal_semaphore g_i2c_sem_rw[HI_STD_I2C_NUM];
79
80 static hi_void *g_i2c_kernel_addr[HI_STD_I2C_NUM];
81 static hi_u32 g_reg_i2c_store[HI_STD_I2C_NUM] = {0};
82 hi_u32 g_a_i2c_rate[HI_STD_I2C_NUM] = {0};
83
84 static i2c_ext_func g_st_i2c_ext_funcs = {
85 .pfn_i2c_write_config = hi_drv_i2c_write_config,
86 .pfn_i2c_write = hi_drv_i2c_write,
87 .pfn_i2c_read = hi_drv_i2c_read,
88 .pfn_i2c_write_nostop = hi_drv_i2c_write_no_stop,
89 .pfn_i2c_read_directly = hi_drv_i2c_read_directly,
90 .pfn_i2c_read_si_labs = hi_drv_i2c_read_si_labs,
91 };
92
i2c_drv_get_i2c_ext_func(i2c_ext_func ** st_i2c_export_funcs)93 hi_void i2c_drv_get_i2c_ext_func(i2c_ext_func **st_i2c_export_funcs)
94 {
95 *st_i2c_export_funcs = &g_st_i2c_ext_funcs;
96 }
97 EXPORT_SYMBOL(i2c_drv_get_i2c_ext_func);
98
i2c_drv_get_rate(hi_u32 i2c_num)99 hi_s32 i2c_drv_get_rate(hi_u32 i2c_num)
100 {
101 if (i2c_num >= HI_STD_I2C_NUM) {
102 return HI_FAILURE;
103 }
104 return g_a_i2c_rate[i2c_num];
105 }
106
i2c_drv_set_rate(hi_u32 i2c_num,hi_u32 i2c_rate)107 hi_void i2c_drv_set_rate(hi_u32 i2c_num, hi_u32 i2c_rate)
108 {
109 hi_u32 value, sclh, scll, chip;
110 const hi_u32 sys_clock = I2C_DFT_SYSCLK;
111
112 /* 400*1000 HZ : max i2c rate */
113 if (i2c_num >= HI_STD_I2C_NUM || i2c_rate > 400 * 1000 || i2c_rate == 0) {
114 return;
115 }
116
117 chip = hi_drv_i2c_get_chip_version();
118 g_a_i2c_rate[i2c_num] = i2c_rate;
119
120 /* read i2c I2C_CTRL register */
121 value = i2c_read_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG));
122
123 /* close all i2c interrupt */
124 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG), (value & (~I2C_UNMASK_TOTAL)));
125
126 sclh = i2c_scl_clk(sys_clock, i2c_rate); // (sys_clock / (i2c_rate * 2)) / 2 - 1
127 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_SCL_H_REG), sclh);
128
129 scll = i2c_scl_clk(sys_clock, i2c_rate); // (sys_clock / (i2c_rate * 2)) / 2 - 1
130 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_SCL_L_REG), scll);
131
132 /* enable i2c interrupt, resume original interrupt */
133 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG), value);
134
135 return;
136 }
137
i2c_drv_wait_write_end(hi_u32 i2c_num)138 static hi_s32 i2c_drv_wait_write_end(hi_u32 i2c_num)
139 {
140 hi_u32 i2c_sr_reg = 0;
141 hi_u32 i = 0;
142
143 do {
144 i2c_sr_reg = i2c_read_reg((g_i2c_kernel_addr[i2c_num] + I2C_SR_REG));
145 HI_LOG_DBG("i2c_sr_reg = 0x%x!\n", i2c_sr_reg);
146
147 if (i > I2C_WAIT_TIME_OUT) {
148 HI_LOG_INFO("i2c_sr_reg = 0x%x!\n", i2c_sr_reg);
149 HI_LOG_INFO("wait write data timeout!\n");
150 goto reset;
151 }
152
153 i++;
154 } while ((i2c_sr_reg & I2C_OVER_INTR) != I2C_OVER_INTR);
155
156 if (i2c_sr_reg & I2C_ACK_INTR) {
157 HI_LOG_INFO("i2c_sr_reg = 0x%x!\n", i2c_sr_reg);
158 HI_LOG_INFO("wait write data timeout!\n");
159 goto reset;
160 }
161
162 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
163
164 return HI_SUCCESS;
165
166 reset:
167 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG), 0x0);
168 /* enable relative interrupt */
169 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG),
170 (I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL));
171 /* clear all i2c interrupt */
172 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
173 /* set stop */
174 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
175
176 return HI_FAILURE;
177 }
178
i2c_wait_condition(const hi_void * param)179 static hi_s32 i2c_wait_condition(const hi_void *param)
180 {
181 hi_s32 ret = HI_FALSE;
182 hi_u32 i2c_num = *((hi_u32 *)(param));
183 if (g_i2c_info[i2c_num].irq_info.irq_wakeup_flag == HI_TRUE || g_i2c_info[i2c_num].irq_info.irq_ack_err > 0) {
184 ret = HI_TRUE;
185 }
186 return ret;
187 }
188
i2c_drv_wait_interrupt(hi_u32 i2c_num)189 static hi_s32 i2c_drv_wait_interrupt(hi_u32 i2c_num)
190 {
191 hi_s32 ret;
192 ret = osal_wait_timeout_interruptible(&g_i2c_wait_queue[i2c_num],
193 i2c_wait_condition, (const void *)(&i2c_num), 200); /* 200ms */
194
195 if (g_i2c_info[i2c_num].irq_info.irq_ack_err > 0) {
196 g_i2c_info[i2c_num].irq_info.irq_ack_err = 0;
197 HI_LOG_INFO("wait ack err.\n");
198 ret = HI_ERR_I2C_ACK_ERR;
199 goto reset;
200 }
201
202 if (g_i2c_info[i2c_num].irq_info.irq_wakeup_flag == HI_FALSE) {
203 HI_LOG_INFO("i2c timeout, current send count is %d\n", g_i2c_info[i2c_num].irq_info.irq_send_count);
204 ret = HI_ERR_I2C_WRITE_TIMEOUT;
205 goto reset;
206 }
207 g_i2c_info[i2c_num].irq_info.irq_wakeup_flag = HI_FALSE;
208
209 return HI_SUCCESS;
210
211 reset:
212 HI_LOG_ERR("I2C_DRV_Write I2cNum %d I2cDevAddr 0x%x I2cRegAddr 0x%x I2cRegAddrByteNum %d failed!\n",
213 g_i2c_info[i2c_num].i2c_num, g_i2c_info[i2c_num].i2c_dev_addr,
214 g_i2c_info[i2c_num].i2c_reg_addr, g_i2c_info[i2c_num].i2c_reg_addr_byte_num);
215 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG), 0x0);
216 /* enable relative interrupt */
217 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG),
218 (I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL));
219 /* clear all i2c interrupt */
220 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
221 /* set stop */
222 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
223
224 return ret;
225 }
226
227
i2c_drv_wait_read(hi_u32 i2c_num)228 static hi_s32 i2c_drv_wait_read(hi_u32 i2c_num)
229 {
230 hi_u32 i2c_sr_reg = 0;
231 hi_u32 i = 0;
232
233 do {
234 i2c_sr_reg = i2c_read_reg((g_i2c_kernel_addr[i2c_num] + I2C_SR_REG));
235
236 if (i > I2C_WAIT_TIME_OUT) {
237 HI_LOG_INFO("i2c_sr_reg = 0x%x !\n", i2c_sr_reg);
238 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG), 0x0);
239 /* enable relative interrupt */
240 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG),
241 (I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL));
242 /* clear all i2c interrupt */
243 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
244 /* set stop */
245 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
246 HI_LOG_INFO("wait Read data timeout!\n");
247 return HI_FAILURE;
248 }
249
250 i++;
251 } while ((i2c_sr_reg & I2C_RECEIVE_INTR) != I2C_RECEIVE_INTR);
252
253 return HI_SUCCESS;
254 }
255
256 /*
257 * I2C write finished acknowledgment function
258 * it use to e2prom device ,make sure it finished write operation.
259 * i2c master start next write operation must waiting when it acknowledge e2prom write cycle finished.
260 */
i2c_drv_write_config(hi_u32 i2c_num,hi_u8 i2c_dev_addr)261 static hi_s32 i2c_drv_write_config(hi_u32 i2c_num, hi_u8 i2c_dev_addr)
262 {
263 hi_u32 i = 0;
264 hi_u32 j = 0;
265 hi_u32 i2c_sr_reg = 0;
266
267 do {
268 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (i2c_dev_addr & WRITE_OPERATION));
269 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), (I2C_WRITE | I2C_START));
270
271 j = 0;
272 do {
273 i2c_sr_reg = i2c_read_reg((g_i2c_kernel_addr[i2c_num] + I2C_SR_REG));
274
275 if (j > I2C_WAIT_TIME_OUT) {
276 HI_LOG_ERR("wait write data timeout!\n");
277 return HI_FAILURE;
278 }
279
280 j++;
281 } while ((i2c_sr_reg & I2C_OVER_INTR) != I2C_OVER_INTR);
282
283 i2c_sr_reg = i2c_read_reg((g_i2c_kernel_addr[i2c_num] + I2C_SR_REG));
284 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
285
286 i++;
287
288 if (i > 0x200000) { // I2C_WAIT_TIME_OUT)
289 HI_LOG_ERR("wait write ack ok timeout!\n");
290 return HI_FAILURE;
291 }
292 } while ((i2c_sr_reg & I2C_ACK_INTR));
293
294 return HI_SUCCESS;
295 }
296
i2c_drv_reset(hi_u32 i2c_num)297 static hi_s32 i2c_drv_reset(hi_u32 i2c_num)
298 {
299 /* soft reset */
300 switch (i2c_num) {
301 case I2C0: {
302 g_pst_reg_crg->peri_crg27.u32 = 0x2023F;
303 break;
304 }
305 case I2C1: {
306 g_pst_reg_crg->peri_crg27.u32 = 0x4023F;
307 break;
308 }
309 case I2C2: {
310 g_pst_reg_crg->peri_crg27.u32 = 0x8023F;
311 break;
312 }
313 case I2C3: {
314 g_pst_reg_crg->peri_crg27.u32 = 0x10023F;
315 break;
316 }
317 default: {
318 return HI_ERR_I2C_INVALID_PARA;
319 }
320 }
321 /* close soft reset */
322 g_pst_reg_crg->peri_crg27.u32 = 0x23F;
323 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG), 0x0);
324 /* clear all i2c interrupt */
325 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
326 /* enable relative interrupt */
327 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_CTRL_REG), (I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL));
328
329 /* reset i2c rate */
330 i2c_drv_set_rate(i2c_num, g_a_i2c_rate[i2c_num]);
331
332 /* set stop */
333 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
334
335 return HI_SUCCESS;
336 }
337
i2c_drv_set_write_mode(hi_u32 i2c_num,hi_u8 i2c_dev_addr)338 static hi_s32 i2c_drv_set_write_mode(hi_u32 i2c_num, hi_u8 i2c_dev_addr)
339 {
340 hi_s32 i = 0;
341 hi_s32 ret = 0;
342
343 if (i2c_num >= HI_STD_I2C_NUM) {
344 HI_LOG_ERR("i2c_num = %d, over ", i2c_num);
345 return HI_FAILURE;
346 }
347
348 for (i = 0 ; i < RESTART_TIME; i++) {
349 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
350
351 /* send divide address */
352 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (i2c_dev_addr & WRITE_OPERATION));
353 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), (I2C_WRITE | I2C_START));
354
355 ret = i2c_drv_wait_write_end(i2c_num);
356 if (ret == HI_SUCCESS) {
357 break;
358 }
359 }
360
361 if (i > RESTART_TIME) {
362 HI_LOG_ERR("i2c_drv_set_write_mode i2c_num %d i2c_dev_addr 0x%x RestartTime %d timeout!\n",
363 i2c_num, i2c_dev_addr, i);
364 i2c_drv_reset(i2c_num);
365 return HI_ERR_I2C_WRITE_TIMEOUT;
366 }
367
368 return HI_SUCCESS;
369 }
370
i2c_drv_set_read_mode(hi_u32 i2c_num,hi_u8 i2c_dev_addr)371 static hi_s32 i2c_drv_set_read_mode(hi_u32 i2c_num, hi_u8 i2c_dev_addr)
372 {
373 if (i2c_num >= HI_STD_I2C_NUM) {
374 HI_LOG_ERR("i2c_num = %d, over ", i2c_num);
375 return HI_FAILURE;
376 }
377
378 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (i2c_dev_addr | READ_OPERATION));
379 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_START | I2C_WRITE);
380
381 if (i2c_drv_wait_write_end(i2c_num)) {
382 HI_LOG_ERR("i2c_drv_set_read_mode i2c_num %u i2c_dev_addr 0x%x timeout!\n",
383 i2c_num, i2c_dev_addr);
384 return HI_ERR_I2C_WRITE_TIMEOUT;
385 }
386
387 return HI_SUCCESS;
388 }
389
390 /* I2C1 Irq server */
i2c_read_write_data_by_irq(hi_u32 i2c_num)391 static hi_s32 i2c_read_write_data_by_irq(hi_u32 i2c_num)
392 {
393 hi_u32 int_value;
394 volatile hi_void *i2c_usr_addr = HI_NULL;
395
396 i2c_usr_addr = g_i2c_kernel_addr[i2c_num];
397 int_value = i2c_read_reg(i2c_usr_addr + I2C_SR_REG);
398
399 /* check interrupt bit */
400 if (int_value & 0x1) { /* Transfer completion interrupt flag */
401 if (int_value & (1 << 6)) { /* bit 6 Host start conditional transmission end interrupt flag */
402 g_i2c_info[i2c_num].irq_info.irq_wakeup_flag = HI_TRUE;
403 } else if (int_value & (1 << 5)) { /* bit 5 Host stop condition transmission end interrupt flag */
404 g_i2c_info[i2c_num].irq_info.irq_send_count = 0;
405 g_i2c_info[i2c_num].irq_info.irq_recv_count = 0;
406 g_i2c_info[i2c_num].irq_info.irq_wakeup_flag = HI_TRUE;
407 }
408 if (int_value & (1 << 4)) { /* bit 4 Host send interrupt flag */
409 g_i2c_info[i2c_num].irq_info.irq_wakeup_flag = HI_TRUE;
410 if (g_i2c_info[i2c_num].irq_info.irq_is_send_data == HI_TRUE) {
411 g_i2c_info[i2c_num].irq_info.irq_send_count++;
412 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
413 if (g_i2c_info[i2c_num].irq_info.irq_send_count < g_i2c_info[i2c_num].data_len) {
414 g_i2c_info[i2c_num].irq_info.irq_wakeup_flag = HI_FALSE;
415 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG),
416 (*(g_i2c_info[i2c_num].data + g_i2c_info[i2c_num].irq_info.irq_send_count)));
417 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE);
418 return OSAL_IRQ_HANDLED;
419 }
420 }
421 } else if (int_value & (1 << 3)) { /* bit 3 Host recv interrupt flag */
422 g_i2c_info[i2c_num].irq_info.irq_wakeup_flag = HI_TRUE;
423 g_i2c_info[i2c_num].irq_info.irq_recv_count++;
424 }
425
426 if (int_value & (1 << 2)) { /* bit 2 ack err interrupt flag */
427 g_i2c_info[i2c_num].irq_info.irq_ack_err++;
428 }
429
430 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
431 } else {
432 g_i2c_info[i2c_num].irq_info.irq_wakeup_flag = HI_FALSE;
433 }
434
435 osal_wait_wakeup(&(g_i2c_wait_queue[i2c_num]));
436 return OSAL_IRQ_HANDLED;
437 }
438
439
i2c0_read_write_data_isr(hi_s32 irq,hi_void * i2c_info)440 hi_s32 i2c0_read_write_data_isr(hi_s32 irq, hi_void *i2c_info)
441 {
442 return i2c_read_write_data_by_irq(I2C0);
443 }
444
i2c1_read_write_data_isr(hi_s32 irq,hi_void * i2c_info)445 hi_s32 i2c1_read_write_data_isr(hi_s32 irq, hi_void *i2c_info)
446 {
447 return i2c_read_write_data_by_irq(I2C1);
448 }
449
450
i2c_drv_write_byte(hi_u32 i2c_num,hi_u8 byte)451 static hi_s32 i2c_drv_write_byte(hi_u32 i2c_num, hi_u8 byte)
452 {
453 if (i2c_num >= HI_STD_I2C_NUM) {
454 HI_LOG_ERR("i2c_num = %u, over ", i2c_num);
455 return HI_FAILURE;
456 }
457
458 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), byte);
459
460 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE);
461
462 if (i2c_drv_wait_write_end(i2c_num)) {
463 HI_LOG_ERR("i2c_set_mode i2c_num %d byte 0x%x !\n", i2c_num, byte);
464 return HI_ERR_I2C_WRITE_TIMEOUT;
465 }
466
467 return HI_SUCCESS;
468 }
469
i2c_drv_write(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len,HI_BOOL b_with_stop)470 static hi_s32 i2c_drv_write(hi_u32 i2c_num, hi_u8 i2c_dev_addr,
471 hi_u32 i2c_reg_addr, hi_u32 i2c_reg_addr_byte_num,
472 hi_u8 *p_data, hi_u32 data_len,
473 HI_BOOL b_with_stop)
474 {
475 hi_u32 i = 0;
476 hi_u32 reg_addr = 0;
477
478 if (i2c_num >= HI_STD_I2C_NUM) {
479 HI_LOG_ERR("i2c_num(%u) is wrong, STD_I2C_NUM is %d\n", i2c_num, HI_STD_I2C_NUM);
480 return HI_ERR_I2C_INVALID_PARA;
481 }
482
483 if (i2c_reg_addr_byte_num < 0 || i2c_reg_addr_byte_num > 4) { // reg addr max 4 byte
484 HI_LOG_ERR("i2c_reg_addr_byte_num is invalid\n");
485 return HI_ERR_I2C_INVALID_PARA;
486 }
487
488 do {
489 /* clear interrupt flag */
490 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
491
492 /* send divide address */
493 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (i2c_dev_addr & WRITE_OPERATION));
494 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), (I2C_WRITE | I2C_START));
495 i++;
496 } while (i2c_drv_wait_write_end(i2c_num) && (i < RESTART_TIME));
497
498 if (i >= RESTART_TIME) {
499 HI_LOG_ERR("i2c_drv_write i2c_num %u i2c_dev_addr 0x%x i2c_reg_addr 0x%x i2c_reg_addr_byte_num %u\
500 RestartTime %u timeout!\n", i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num, i);
501 i2c_drv_reset(i2c_num);
502 return HI_ERR_I2C_WRITE_TIMEOUT;
503 }
504
505 /* send register address which will need to write */
506 for (i = 0; i < i2c_reg_addr_byte_num; i++) {
507 reg_addr = i2c_reg_addr >> ((i2c_reg_addr_byte_num - i - 1) * 8); /* 8bit */
508 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), reg_addr);
509
510 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE);
511
512 if (i2c_drv_wait_write_end(i2c_num)) {
513 HI_LOG_ERR("i2c_drv_write i2c_num %d i2c_dev_addr 0x%x i2c_reg_addr 0x%x\
514 i2c_reg_addr_byte_num %d timeout!\n", i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num);
515 return HI_ERR_I2C_WRITE_TIMEOUT;
516 }
517 }
518
519 /* send data */
520 for (i = 0; i < data_len; i++) {
521 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (*(p_data + i)));
522 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE);
523
524 if (i2c_drv_wait_write_end(i2c_num)) {
525 HI_LOG_ERR("i2c_drv_write i2c_num % i2c_dev_addr 0x%x i2c_reg_addr 0x%x\
526 i2c_reg_addr_byte_num %d timeout!\n", i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num);
527 return HI_ERR_I2C_WRITE_TIMEOUT;
528 }
529 }
530
531 if (b_with_stop) {
532 /* send stop flag bit */
533 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
534 if (i2c_drv_wait_write_end(i2c_num)) {
535 HI_LOG_ERR("i2c_drv_write i2c_num %u i2c_dev_addr 0x%x i2c_reg_addr 0x%x\
536 i2c_reg_addr_byte_num %u timeout!\n", i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num);
537 return HI_ERR_I2C_WRITE_TIMEOUT;
538 }
539 }
540
541 return HI_SUCCESS;
542 }
543
i2c_drv_send_slave_by_int(i2c_drv_info * i2c_info)544 int i2c_drv_send_slave_by_int(i2c_drv_info *i2c_info)
545 {
546 hi_u32 i;
547 hi_u32 reg_addr = 0;
548 hi_s32 ret;
549
550 /* send divide address */
551 i2c_write_reg((g_i2c_kernel_addr[i2c_info->i2c_num] + I2C_TXR_REG), (i2c_info->i2c_dev_addr & WRITE_OPERATION));
552 i2c_write_reg((g_i2c_kernel_addr[i2c_info->i2c_num] + I2C_COM_REB), (I2C_WRITE | I2C_START));
553 ret = i2c_drv_wait_interrupt(i2c_info->i2c_num);
554 if (ret != HI_SUCCESS) {
555 return ret;
556 }
557
558 /* send register address which will need to write */
559 for (i = 0; i < i2c_info->i2c_reg_addr_byte_num; i++) {
560 reg_addr = i2c_info->i2c_reg_addr >> ((i2c_info->i2c_reg_addr_byte_num - i - 1) * 8); /* 8 bit */
561 i2c_write_reg((g_i2c_kernel_addr[i2c_info->i2c_num] + I2C_TXR_REG), reg_addr);
562 i2c_write_reg((g_i2c_kernel_addr[i2c_info->i2c_num] + I2C_COM_REB), I2C_WRITE);
563 ret = i2c_drv_wait_interrupt(i2c_info->i2c_num);
564 if (ret != HI_SUCCESS) {
565 return ret;
566 }
567 i2c_info->irq_info.irq_send_count = 0;
568 }
569 return HI_SUCCESS;
570 }
571
572
i2c_drv_read(hi_u32 i2c_num,hi_u8 i2c_dev_addr,HI_BOOL b_send_slave,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len)573 static int i2c_drv_read(hi_u32 i2c_num, hi_u8 i2c_dev_addr, HI_BOOL b_send_slave, hi_u32 i2c_reg_addr,\
574 hi_u32 i2c_reg_addr_byte_num, hi_u8 *p_data, hi_u32 data_len)
575 {
576 hi_u32 data_tmp = 0xff;
577 hi_u32 i = 0;
578 hi_u32 reg_addr = 0;
579 hi_s32 ret = 0;
580
581 if (i2c_num >= HI_STD_I2C_NUM || i2c_reg_addr_byte_num > 4) { /* max reg address len is 4 byte */
582 HI_LOG_ERR("i2c param is invalid\n");
583 return HI_ERR_I2C_INVALID_PARA;
584 }
585
586 if (b_send_slave) {
587 ret = i2c_drv_set_write_mode(i2c_num, i2c_dev_addr);
588 if (ret != HI_SUCCESS) {
589 return HI_ERR_I2C_WRITE_TIMEOUT;
590 }
591 /* send register address which will need to write */
592 for (i = 0; i < i2c_reg_addr_byte_num; i++) {
593 reg_addr = i2c_reg_addr >> ((i2c_reg_addr_byte_num - i - 1) * 8); /* 8 bit */
594 i2c_drv_write_byte(i2c_num, reg_addr);
595 }
596 }
597
598 /* send register address which will need to read */
599 ret = i2c_drv_set_read_mode(i2c_num, i2c_dev_addr);
600 if (ret != HI_SUCCESS) {
601 return HI_ERR_I2C_WRITE_TIMEOUT;
602 }
603 /* repetitivily read data */
604 for (i = 0; i < data_len; i++) {
605 /* the last byte don't need send ACK */
606 if (i == (data_len - 1)) {
607 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), (I2C_READ | (~I2C_SEND_ACK)));
608 } else { /* if i2c master receive data will send ACK */
609 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_READ);
610 }
611
612 if (i2c_drv_wait_read(i2c_num)) {
613 goto TIMEOUT;
614 }
615
616 data_tmp = i2c_read_reg((g_i2c_kernel_addr[i2c_num] + I2C_RXR_REG));
617 *(p_data + i) = data_tmp & 0xff;
618
619 if (i2c_drv_wait_write_end(i2c_num)) {
620 goto TIMEOUT;
621 }
622 }
623
624 /* send stop flag bit */
625 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
626 if (i2c_drv_wait_write_end(i2c_num)) {
627 goto TIMEOUT;
628 }
629
630 return HI_SUCCESS;
631 TIMEOUT:
632 HI_LOG_ERR("i2c_drv_read i2c_num %u i2c_dev_addr 0x%x i2c_reg_addr 0x%x i2c_reg_addr_byte_num %u timeout!\n",
633 i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num);
634 return HI_ERR_I2C_WRITE_TIMEOUT;
635 }
636
i2c_drv_read_si_labs(hi_u32 i2c_num,hi_u8 i2c_dev_addr,HI_BOOL b_send_slave,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len)637 static int i2c_drv_read_si_labs(hi_u32 i2c_num, hi_u8 i2c_dev_addr, HI_BOOL b_send_slave, hi_u32 i2c_reg_addr,\
638 hi_u32 i2c_reg_addr_byte_num, hi_u8 *p_data, hi_u32 data_len)
639 {
640 hi_u32 data_tmp = 0xff;
641 hi_u32 i = 0;
642
643 if (i2c_num >= HI_STD_I2C_NUM) {
644 HI_LOG_ERR("i2c_num(%u) is wrong, STD_I2C_NUM is %d\n", i2c_num, HI_STD_I2C_NUM);
645 return HI_ERR_I2C_INVALID_PARA;
646 }
647
648 /* clear interrupt flag */
649 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
650
651 /* send register address which will need to read */
652 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (i2c_dev_addr | READ_OPERATION));
653 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE | I2C_START);
654
655 if (i2c_drv_wait_write_end(i2c_num)) {
656 HI_LOG_ERR("i2c_drv_read i2c_num %d i2c_dev_addr 0x%x i2c_reg_addr 0x%x i2c_reg_addr_byte_num %d timeout!\n",
657 i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num);
658 return HI_ERR_I2C_WRITE_TIMEOUT;
659 }
660
661 /* repetitivily read data */
662 for (i = 0; i < data_len; i++) {
663 /* the last byte don't need send ACK */
664 if (i == (data_len - 1)) {
665 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), (I2C_READ | (~I2C_SEND_ACK)));
666 } else { /* if i2c master receive data will send ACK */
667 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_READ);
668 }
669
670 if (i2c_drv_wait_read(i2c_num)) {
671 HI_LOG_ERR("i2c_drv_read i2c_num %d i2c_dev_addr 0x%x i2c_reg_addr 0x%x\
672 i2c_reg_addr_byte_num %d timeout!\n", i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num);
673 return HI_ERR_I2C_READ_TIMEOUT;
674 }
675
676 data_tmp = i2c_read_reg((g_i2c_kernel_addr[i2c_num] + I2C_RXR_REG));
677 *(p_data + i) = data_tmp & 0xff;
678
679 if (i2c_drv_wait_write_end(i2c_num)) {
680 HI_LOG_ERR("i2c_drv_read i2c_num %d i2c_dev_addr 0x%x i2c_reg_addr 0x%x\
681 i2c_reg_addr_byte_num %d timeout!\n", i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num);
682 return HI_ERR_I2C_WRITE_TIMEOUT;
683 }
684 }
685
686 /* send stop flag bit */
687 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
688 if (i2c_drv_wait_write_end(i2c_num)) {
689 HI_LOG_ERR("i2c_drv_read i2c_num %u i2c_dev_addr 0x%x i2c_reg_addr 0x%x i2c_reg_addr_byte_num %u timeout!\n",
690 i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num);
691 return HI_ERR_I2C_WRITE_TIMEOUT;
692 }
693
694 return HI_SUCCESS;
695 }
696
i2c_drv_write_sony(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len,hi_u8 mode)697 static hi_s32 i2c_drv_write_sony(hi_u32 i2c_num, hi_u8 i2c_dev_addr, hi_u32 i2c_reg_addr, hi_u32 i2c_reg_addr_byte_num,
698 hi_u8 *p_data, hi_u32 data_len, hi_u8 mode)
699 {
700 hi_u32 i = 0;
701 hi_u32 reg_addr = 0;
702
703 /* clear interrupt flag */
704 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_ICR_REG), I2C_CLEAR_ALL);
705
706 /* send divide address */
707 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (i2c_dev_addr & WRITE_OPERATION));
708
709 if (mode & SONY_I2C_START_EN) {
710 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), (I2C_WRITE | I2C_START));
711 } else {
712 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE);
713 }
714
715 if (i2c_drv_wait_write_end(i2c_num)) {
716 HI_LOG_ERR("wait write data timeout!%s, %d\n", __func__, __LINE__);
717 return HI_ERR_I2C_WRITE_TIMEOUT;
718 }
719
720 /* send register address which will need to write */
721 for (i = 0; i < i2c_reg_addr_byte_num; i++) {
722 reg_addr = i2c_reg_addr >> ((i2c_reg_addr_byte_num - i - 1) * 8); /* 8 bit */
723 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), reg_addr);
724
725 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE);
726
727 if (i2c_drv_wait_write_end(i2c_num)) {
728 HI_LOG_ERR("wait write data timeout!%s, %d\n", __func__, __LINE__);
729 return HI_ERR_I2C_WRITE_TIMEOUT;
730 }
731 }
732
733 /* send data */
734 for (i = 0; i < data_len; i++) {
735 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (*(p_data + i)));
736 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE);
737
738 if (i2c_drv_wait_write_end(i2c_num)) {
739 HI_LOG_ERR("wait write data timeout!%s, %d\n", __func__, __LINE__);
740 return HI_ERR_I2C_WRITE_TIMEOUT;
741 }
742 }
743
744 /* send stop flag bit */
745 if (mode & SONY_I2C_STOP_EN) {
746 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
747 if (i2c_drv_wait_write_end(i2c_num)) {
748 HI_LOG_ERR("wait write data timeout!%s, %d\n", __func__, __LINE__);
749 return HI_ERR_I2C_WRITE_TIMEOUT;
750 }
751 }
752
753 return HI_SUCCESS;
754 }
755
i2c_drv_read_sony(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len,hi_u8 mode)756 static int i2c_drv_read_sony(hi_u32 i2c_num, hi_u8 i2c_dev_addr,
757 hi_u32 i2c_reg_addr, hi_u32 i2c_reg_addr_byte_num,
758 hi_u8 *p_data, hi_u32 data_len, hi_u8 mode)
759 {
760 hi_u32 data_tmp = 0xff;
761 hi_u32 i = 0;
762
763 if (mode & SONY_I2C_START_EN) {
764 /* send register address which will need to read */
765 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_TXR_REG), (i2c_dev_addr | READ_OPERATION));
766 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_WRITE | I2C_START);
767
768 if (i2c_drv_wait_write_end(i2c_num)) {
769 return HI_ERR_I2C_WRITE_TIMEOUT;
770 }
771 }
772
773 /* repetitivily read data */
774 for (i = 0; i < data_len; i++) {
775 /* the last byte don't need send ACK */
776 if (i == (data_len - 1)) {
777 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), (I2C_READ | (~I2C_SEND_ACK)));
778 } else { /* if i2c master receive data will send ACK */
779 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_READ);
780 }
781
782 if (i2c_drv_wait_read(i2c_num)) {
783 HI_LOG_ERR("wait read data timeout!\n");
784 return HI_ERR_I2C_READ_TIMEOUT;
785 }
786
787 data_tmp = i2c_read_reg((g_i2c_kernel_addr[i2c_num] + I2C_RXR_REG));
788 *(p_data + i) = data_tmp & 0xff;
789
790 if (i2c_drv_wait_write_end(i2c_num)) {
791 HI_LOG_ERR("wait write data timeout!\n");
792 return HI_ERR_I2C_WRITE_TIMEOUT;
793 }
794 }
795
796 if (mode & SONY_I2C_STOP_EN) {
797 /* send stop flag bit */
798 i2c_write_reg((g_i2c_kernel_addr[i2c_num] + I2C_COM_REB), I2C_STOP);
799 if (i2c_drv_wait_write_end(i2c_num)) {
800 HI_LOG_ERR("wait write data timeout!\n");
801 return HI_ERR_I2C_WRITE_TIMEOUT;
802 }
803 }
804
805 return HI_SUCCESS;
806 }
807
808 /*****************************************************************************
809 Prototype :
810 Description : I2C mudole suspend function
811 Input : None
812 Output : None
813 return value : None
814 *****************************************************************************/
815 struct i2c_pm_info {
816 unsigned int rsclh;
817 unsigned int rscll;
818 };
819 static int g_i2c_state = 0;
820 static struct i2c_pm_info g_pm_status[HI_I2C_MAX_NUM];
821
822 /*
823 because this module have opened in tuner/e2prom ModeuleInit,
824 so relational opened operation register need to store
825 */
i2c_pm_suspend(hi_void * private_data)826 int i2c_pm_suspend(hi_void *private_data)
827 {
828 #if !defined(CFG_HI_USER_DRV)
829 int i = 0;
830 int ret ;
831
832 ret = osal_sem_trydown(&g_i2c_sem);
833 if (ret) {
834 HI_LOG_ERR("lock err!\n");
835 return -1;
836 }
837
838 for (i = 0; i < HI_STD_I2C_NUM; i++) {
839 /* disable all i2c interrupt */
840 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_CTRL_REG), 0x0);
841
842 /* clear all i2c interrupt */
843 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_ICR_REG), I2C_CLEAR_ALL);
844
845 /* store I2C_SCL_H and I2C_SCL_L register */
846 g_pm_status[i].rsclh = i2c_read_reg(g_i2c_kernel_addr[i] + I2C_SCL_H_REG);
847 g_pm_status[i].rscll = i2c_read_reg(g_i2c_kernel_addr[i] + I2C_SCL_L_REG);
848 }
849
850 g_reg_i2c_store[0] = g_pst_reg_crg->peri_crg27.u32;
851
852 osal_sem_up(&g_i2c_sem);
853 HI_PRINT("I2C suspend OK\n");
854 #endif
855 return 0;
856 }
857
i2c_pm_resume(hi_void * private_data)858 int i2c_pm_resume(hi_void *private_data)
859 {
860 int i = 0;
861 int ret;
862
863 ret = osal_sem_trydown(&g_i2c_sem);
864 if (ret) {
865 HI_LOG_ERR("lock err!\n");
866 return -1;
867 }
868
869 g_pst_reg_crg->peri_crg27.u32 = g_reg_i2c_store[0];
870
871 for (i = 0; i < HI_STD_I2C_NUM; i++) {
872 /* disable all i2c interrupt */
873 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_CTRL_REG), 0x0);
874
875 /* resume previous store register before suspend */
876 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_SCL_H_REG), g_pm_status[i].rsclh);
877 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_SCL_L_REG), g_pm_status[i].rscll);
878
879 /* config scl clk rate */
880 g_a_i2c_rate[i] = I2C_DFT_RATE;
881 i2c_drv_set_rate(i, I2C_DFT_RATE);
882
883 /* clear all i2c interrupt */
884 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_ICR_REG), I2C_CLEAR_ALL);
885
886 /* enable relative interrupt */
887 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_CTRL_REG), (I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL));
888 }
889
890 osal_sem_up(&g_i2c_sem);
891 HI_PRINT("I2C resume OK\n");
892 return 0;
893 }
894
i2c_drv_lowpower_enter(hi_void * private_data)895 hi_s32 i2c_drv_lowpower_enter(hi_void *private_data)
896 {
897 HI_LOG_NOTICE("I2C lowpower enter OK\n");
898 return HI_SUCCESS;
899 }
900
i2c_drv_lowpower_exit(hi_void * private_data)901 hi_s32 i2c_drv_lowpower_exit(hi_void *private_data)
902 {
903 HI_LOG_NOTICE("I2C lowpower exit OK\n");
904 return HI_SUCCESS;
905 }
906
907
hi_drv_i2c_open(hi_void)908 static hi_void hi_drv_i2c_open(hi_void)
909 {
910 hi_s32 ret;
911 hi_u32 i = 0;
912
913 if (g_i2c_state == 1) {
914 return;
915 }
916
917 ret = osal_sem_down_interruptible(&g_i2c_sem);
918 if (ret) {
919 HI_LOG_INFO("lock g_i2c_sem error.\n");
920 return;
921 }
922
923 for (i = 0; i < HI_STD_I2C_NUM; i++) {
924 /* disable all i2c interrupt */
925 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_CTRL_REG), 0x0);
926
927 /* enable relative interrupt */
928 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_CTRL_REG), (I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL));
929
930 /* clear all i2c interrupt */
931 i2c_write_reg((g_i2c_kernel_addr[i] + I2C_ICR_REG), I2C_CLEAR_ALL);
932
933 /* config scl clk rate */
934 g_a_i2c_rate[i] = I2C_DFT_RATE;
935 i2c_drv_set_rate(i, I2C_DFT_RATE);
936 }
937 #ifdef HI_UNIFIED_IMAGE_SUPPORT
938 ret = hi_get_dts_config_u32_byname("i2c", "i2c_rw_use_interrupt", &g_i2c_rw_irq_enable);
939 if (ret != HI_SUCCESS) {
940 g_i2c_rw_irq_enable = 0;
941 HI_LOG_ERR("ERR: call hi_get_dts_config_u32_byname i2c_rw_use_interrupt fail\n");
942 }
943 #endif
944 g_i2c_state = 1;
945
946 osal_sem_up(&g_i2c_sem);
947 return;
948 }
949
950
hi_drv_std_i2c_write(i2c_data * i2c_data_ptr)951 static hi_s32 hi_drv_std_i2c_write(i2c_data *i2c_data_ptr)
952 {
953 hi_u8 *p_data = NULL;
954 errno_t err_ret;
955 hi_s32 ret;
956 hi_u32 chip;
957
958 hi_dbg_func_enter();
959
960 if (i2c_data_ptr == NULL || i2c_data_ptr->data_len == 0 || i2c_data_ptr->data_len > HI_I2C_MAX_LENGTH) {
961 HI_LOG_ERR("i2c param is invalid.\n");
962 return HI_ERR_I2C_INVALID_PARA;
963 }
964
965 p_data = osal_kmalloc(HI_ID_I2C, i2c_data_ptr->data_len, OSAL_GFP_KERNEL);
966 if (p_data == NULL) {
967 HI_LOG_ERR("i2c kmalloc fail!\n");
968 return HI_ERR_I2C_MALLOC_ERR;
969 }
970
971 err_ret = memset_s(p_data, i2c_data_ptr->data_len, 0, i2c_data_ptr->data_len);
972 if (err_ret != EOK) {
973 osal_kfree(HI_ID_I2C, p_data);
974 HI_LOG_ERR("secure func call error\n");
975 return HI_FAILURE;
976 }
977
978 if (osal_copy_from_user(p_data, (hi_void *)(uintptr_t)(i2c_data_ptr->p_data),
979 i2c_data_ptr->data_len)) {
980 osal_kfree(HI_ID_I2C, p_data);
981 p_data = HI_NULL;
982 return HI_ERR_I2C_COPY_DATA_ERR;
983 }
984 chip = hi_drv_i2c_get_chip_version();
985 ret = i2c_drv_write(i2c_data_ptr->i2c_num, i2c_data_ptr->i2c_dev_addr, i2c_data_ptr->i2c_reg_addr,
986 i2c_data_ptr->i2c_reg_count, p_data, i2c_data_ptr->data_len, HI_TRUE);
987 osal_kfree(HI_ID_I2C, p_data);
988 p_data = HI_NULL;
989
990 hi_dbg_func_exit();
991
992 return ret;
993 }
994
hi_drv_i2c_cmd_write(unsigned int cmd,hi_void * arg,hi_void * private_data)995 hi_s32 hi_drv_i2c_cmd_write(unsigned int cmd, hi_void *arg, hi_void *private_data)
996 {
997 hi_s32 ret;
998 i2c_data *i2c_data_ptr = NULL;
999 hi_dbg_func_enter();
1000
1001 i2c_data_ptr = (i2c_data *)arg;
1002
1003 if (i2c_data_ptr->i2c_num >= HI_I2C_MAX_NUM) {
1004 HI_LOG_INFO("i2c chanenl (NO:%d) is invalid !\n", i2c_data_ptr->i2c_num);
1005 return HI_ERR_I2C_INVALID_PARA;
1006 }
1007
1008 if (HI_STD_I2C_NUM <= i2c_data_ptr->i2c_num) {
1009 ret = hi_drv_gpioi2c_cmd_write(cmd, arg, private_data);
1010 return ret;
1011 }
1012
1013 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_data_ptr->i2c_num]);
1014 if (ret) {
1015 HI_LOG_INFO("lock g_i2c_sem error.\n");
1016 return HI_FAILURE;
1017 }
1018
1019 ret = hi_drv_std_i2c_write(i2c_data_ptr);
1020
1021 osal_sem_up(&g_i2c_sem_rw[i2c_data_ptr->i2c_num]);
1022
1023 hi_dbg_func_exit();
1024
1025 return ret;
1026 }
1027
hi_drv_std_i2c_read(unsigned int cmd,i2c_data * i2c_data_ptr)1028 static hi_s32 hi_drv_std_i2c_read(unsigned int cmd, i2c_data *i2c_data_ptr)
1029 {
1030 hi_s32 ret;
1031 hi_u32 chip;
1032 hi_u8 *p_data = NULL;
1033 errno_t err_ret;
1034 hi_bool send_slave = HI_TRUE;
1035
1036 if (i2c_data_ptr == NULL) {
1037 HI_LOG_ERR("i2c_data_ptr is null pointer.\n");
1038 return HI_ERR_I2C_INVALID_PARA;
1039 }
1040 if (i2c_data_ptr->data_len > HI_I2C_MAX_LENGTH || i2c_data_ptr->data_len == 0) {
1041 HI_LOG_ERR("para i2c_data.data_len[%d] is invalid.\n", i2c_data_ptr->data_len);
1042 return HI_ERR_I2C_INVALID_PARA;
1043 }
1044
1045 p_data = osal_kmalloc(HI_ID_I2C, i2c_data_ptr->data_len, OSAL_GFP_KERNEL);
1046 if (p_data == NULL) {
1047 HI_LOG_ERR("i2c kmalloc fail!\n");
1048 return HI_ERR_I2C_MALLOC_ERR;
1049 }
1050
1051 err_ret = memset_s(p_data, i2c_data_ptr->data_len, 0, i2c_data_ptr->data_len);
1052 if (err_ret != EOK) {
1053 osal_kfree(HI_ID_I2C, p_data);
1054 HI_LOG_ERR("secure func call error\n");
1055 return HI_FAILURE;
1056 }
1057
1058 if (cmd == CMD_I2C_READ_DIRECT) {
1059 send_slave = HI_FALSE;
1060 }
1061
1062 chip = hi_drv_i2c_get_chip_version();
1063 if (i2c_data_ptr->i2c_reg_count != 0) {
1064 ret = i2c_drv_read(i2c_data_ptr->i2c_num, i2c_data_ptr->i2c_dev_addr, send_slave,
1065 i2c_data_ptr->i2c_reg_addr, i2c_data_ptr->i2c_reg_count,
1066 p_data, i2c_data_ptr->data_len);
1067 } else {
1068 ret = i2c_drv_read_si_labs(i2c_data_ptr->i2c_num, i2c_data_ptr->i2c_dev_addr, \
1069 HI_TRUE, i2c_data_ptr->i2c_reg_addr, i2c_data_ptr->i2c_reg_count,
1070 p_data, i2c_data_ptr->data_len);
1071 }
1072
1073 if (ret == HI_SUCCESS) {
1074 if (osal_copy_to_user((hi_void *)((uintptr_t)(i2c_data_ptr->p_data)), p_data, i2c_data_ptr->data_len)) {
1075 HI_LOG_INFO("copy data to user fail!\n");
1076 ret = HI_ERR_I2C_COPY_DATA_ERR;
1077 }
1078 }
1079
1080 osal_kfree(HI_ID_I2C, p_data);
1081 p_data = HI_NULL;
1082
1083 hi_dbg_func_exit();
1084
1085 return ret;
1086 }
1087
hi_drv_i2c_cmd_read(unsigned int cmd,hi_void * arg,hi_void * private_data)1088 hi_s32 hi_drv_i2c_cmd_read(unsigned int cmd, hi_void *arg, hi_void *private_data)
1089 {
1090 hi_s32 ret;
1091 i2c_data *i2c_data_ptr = NULL;
1092
1093 hi_dbg_func_enter();
1094
1095 i2c_data_ptr = (i2c_data *)arg;
1096 if (i2c_data_ptr->i2c_num >= HI_I2C_MAX_NUM) {
1097 HI_LOG_INFO("i2c chanenl (NO:%d) is invalid !\n", i2c_data_ptr->i2c_num);
1098 return HI_ERR_I2C_INVALID_PARA;
1099 }
1100
1101 if (HI_STD_I2C_NUM <= i2c_data_ptr->i2c_num) {
1102 ret = hi_drv_gpioi2c_cmd_read(cmd, arg, private_data);
1103 return ret;
1104 }
1105
1106 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_data_ptr->i2c_num]);
1107 if (ret) {
1108 HI_LOG_INFO("lock g_i2c_sem error.\n");
1109 return HI_FAILURE;
1110 }
1111 ret = hi_drv_std_i2c_read(cmd, i2c_data_ptr);
1112
1113 osal_sem_up(&g_i2c_sem_rw[i2c_data_ptr->i2c_num]);
1114
1115 hi_dbg_func_exit();
1116
1117 return ret;
1118 }
1119
hi_drv_i2c_cmd_set_rate(unsigned int cmd,hi_void * arg,hi_void * private_data)1120 hi_s32 hi_drv_i2c_cmd_set_rate(unsigned int cmd, hi_void *arg, hi_void *private_data)
1121 {
1122 hi_s32 ret;
1123 i2c_rate *i2c_rate_ptr = NULL;
1124
1125 hi_dbg_func_enter();
1126
1127 i2c_rate_ptr = (i2c_rate *)arg;
1128 if (i2c_rate_ptr->i2c_num >= HI_STD_I2C_NUM) {
1129 HI_LOG_INFO("i2c chanenl (NO:%d) is invalid !\n", i2c_rate_ptr->i2c_num);
1130 return HI_ERR_I2C_INVALID_PARA;
1131 }
1132
1133 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_rate_ptr->i2c_num]);
1134 if (ret) {
1135 HI_LOG_INFO("lock g_i2c_sem error.\n");
1136 return HI_FAILURE;
1137 }
1138
1139 i2c_drv_set_rate(i2c_rate_ptr->i2c_num, i2c_rate_ptr->i2c_rate);
1140 ret = HI_SUCCESS;
1141
1142 osal_sem_up(&g_i2c_sem_rw[i2c_rate_ptr->i2c_num]);
1143
1144 hi_dbg_func_exit();
1145
1146 return ret;
1147 }
1148
init_reg_crg(hi_void)1149 static hi_void init_reg_crg(hi_void)
1150 {
1151 #ifdef CFG_HI_USER_DRV
1152 #define V350_REG_BASE 0xF8A22000
1153 #define V350_REG_REMAP_SIZE 4096
1154 if (g_pst_reg_crg != NULL) {
1155 return;
1156 }
1157 g_pst_reg_crg = (hi_reg_crg *)osal_ioremap_nocache(V350_REG_BASE, V350_REG_REMAP_SIZE);
1158 if (g_pst_reg_crg == NULL) {
1159 HI_LOG_FATAL("g_pst_reg_crg osal_ioremap_nocache failure!\n");
1160 return;
1161 }
1162 #endif
1163 return;
1164 }
1165
hi_drv_i2c_init(hi_void)1166 hi_s32 hi_drv_i2c_init(hi_void)
1167 {
1168 hi_u32 reg_val;
1169 hi_s32 ret;
1170 hi_u32 i = 0;
1171
1172 hi_dbg_func_enter();
1173
1174 if (g_i2c_state == 1) {
1175 return HI_SUCCESS;
1176 }
1177
1178 init_reg_crg();
1179
1180 ret = osal_exportfunc_register(HI_ID_I2C, "HI_I2C", (hi_void *)&g_st_i2c_ext_funcs);
1181 if (ret != HI_SUCCESS) {
1182 HI_LOG_INFO(" I2C Module register failed 0x%x.\n", ret);
1183 return HI_FAILURE;
1184 }
1185
1186 ret = osal_sem_init(&g_i2c_sem, 1);
1187 if (ret != HI_SUCCESS) {
1188 HI_LOG_FATAL(" I2C semaphore init failed.\n");
1189 return HI_FAILURE;
1190 }
1191
1192 for (i = 0; i < HI_STD_I2C_NUM; i++) {
1193 /* init semaphore for each bus */
1194 ret = osal_sem_init(&g_i2c_sem_rw[i], 1);
1195 if (ret != HI_SUCCESS) {
1196 HI_LOG_FATAL(" I2C rw semaphore init failed.\n");
1197 return HI_FAILURE;
1198 }
1199 /* init wait queue for each bus */
1200 osal_wait_init(&g_i2c_wait_queue[i]);
1201 /* clean i2c's reg base address */
1202 g_i2c_kernel_addr[i] = NULL;
1203 }
1204
1205 HI_I2C_REG_REMAP(g_i2c_kernel_addr[0], I2C0_PHY_ADDR); // I2C0 base addr
1206 HI_I2C_REG_REMAP(g_i2c_kernel_addr[1], I2C1_PHY_ADDR); // I2C1 base addr
1207 HI_I2C_REG_REMAP(g_i2c_kernel_addr[2], I2C2_PHY_ADDR); // I2C2 base addr
1208 HI_I2C_REG_REMAP(g_i2c_kernel_addr[3], I2C3_PHY_ADDR); // I2C3 base addr
1209 HI_I2C_REG_REMAP(g_i2c_kernel_addr[4], I2C_TUNER_ADDR); // 4 I2C_TUNER base addr
1210 HI_I2C_REG_REMAP(g_i2c_kernel_addr[5], I2C_DTMB_ADDR); // 5 I2C_DTMB base addr
1211 HI_I2C_REG_REMAP(g_i2c_kernel_addr[6], I2C_ADC_ADDR); // 6 I2C_ADC base addr
1212
1213 reg_val = g_pst_reg_crg->peri_crg27.u32;
1214 reg_val &= ~0x27E023F;
1215 reg_val |= 0x23F;
1216 g_pst_reg_crg->peri_crg27.u32 = reg_val;
1217
1218 hi_drv_i2c_open();
1219 hi_dbg_func_exit();
1220
1221 return 0;
1222 }
1223
hi_drv_i2c_de_init(hi_void)1224 hi_void hi_drv_i2c_de_init(hi_void)
1225 {
1226 hi_u32 reg_val;
1227 hi_u32 i = 0;
1228 i2c_drv_chip chip;
1229 hi_s32 ret;
1230
1231 hi_dbg_func_enter();
1232
1233 chip = hi_drv_i2c_get_chip_version();
1234
1235 osal_sem_destory(&g_i2c_sem);
1236 for (i = 0; i < HI_STD_I2C_NUM; i++) {
1237 osal_sem_destory(&g_i2c_sem_rw[i]);
1238 osal_wait_destroy(&g_i2c_wait_queue[i]);
1239 }
1240
1241 ret = osal_exportfunc_unregister(HI_ID_I2C);
1242 if (ret != HI_SUCCESS) {
1243 HI_LOG_INFO(" GPIO Module unregister failed 0x%x.\n", ret);
1244 }
1245
1246 reg_val = g_pst_reg_crg->peri_crg27.u32;
1247 reg_val &= ~0x27E023F;
1248 reg_val |= 0x27E0000;
1249 g_pst_reg_crg->peri_crg27.u32 = reg_val;
1250
1251 /* unmap i2c's reg address */
1252 for (i = 0; i < HI_STD_I2C_NUM; i++) {
1253 HI_I2C_REG_UNMAP(g_i2c_kernel_addr[i]);
1254 g_i2c_kernel_addr[i] = NULL;
1255 }
1256 g_i2c_state = 0;
1257
1258 hi_dbg_func_exit();
1259
1260 return;
1261 }
1262
hi_drv_i2c_write_config(hi_u32 i2c_num,hi_u8 i2c_dev_addr)1263 hi_s32 hi_drv_i2c_write_config(hi_u32 i2c_num, hi_u8 i2c_dev_addr)
1264 {
1265 hi_s32 ret;
1266
1267 hi_dbg_func_enter();
1268
1269 if (i2c_num >= HI_STD_I2C_NUM) {
1270 HI_LOG_ERR("i2c_num(%u) is wrong, STD_I2C_NUM is %d\n", i2c_num, HI_STD_I2C_NUM);
1271 return HI_FAILURE;
1272 }
1273
1274 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_num]);
1275 if (ret) {
1276 HI_LOG_INFO("lock g_i2c_sem error.\n");
1277 return HI_FAILURE;
1278 }
1279
1280 ret = i2c_drv_write_config(i2c_num, i2c_dev_addr);
1281
1282 osal_sem_up(&g_i2c_sem_rw[i2c_num]);
1283
1284 hi_dbg_func_exit();
1285
1286 return ret;
1287 }
1288
hi_drv_i2c_parm_check(hi_u32 i2c_num,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len)1289 static hi_s32 hi_drv_i2c_parm_check(hi_u32 i2c_num, hi_u32 i2c_reg_addr_byte_num, hi_u8 *p_data, hi_u32 data_len)
1290 {
1291 if (i2c_num >= HI_STD_I2C_NUM) {
1292 HI_LOG_ERR("i2c_num(%d) is wrong, STD_I2C_NUM is %d\n", i2c_num, HI_STD_I2C_NUM);
1293 return HI_FAILURE;
1294 }
1295
1296 if (i2c_reg_addr_byte_num > 4) { /* max reg address len is 4 byte */
1297 HI_LOG_ERR("para i2c_reg_addr_byte_num is invalid.\n");
1298 return HI_FAILURE;
1299 }
1300
1301 if (p_data == NULL) {
1302 HI_LOG_ERR("para p_data is null.\n");
1303 return HI_FAILURE;
1304 }
1305
1306 if ((data_len > HI_I2C_MAX_LENGTH) || (data_len == 0)) {
1307 HI_LOG_ERR("para data_len is invalid.\n");
1308 return HI_FAILURE;
1309 }
1310 return HI_SUCCESS;
1311 }
1312
hi_drv_i2c_write(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len)1313 hi_s32 hi_drv_i2c_write(hi_u32 i2c_num, hi_u8 i2c_dev_addr, hi_u32 i2c_reg_addr,
1314 hi_u32 i2c_reg_addr_byte_num, hi_u8 *p_data, hi_u32 data_len)
1315 {
1316 hi_s32 ret;
1317 hi_u32 chip;
1318
1319 hi_dbg_func_enter();
1320
1321 if (i2c_num >= HI_STD_I2C_NUM) {
1322 HI_LOG_ERR("i2c_num(%d) is wrong, STD_I2C_NUM is %d\n", i2c_num, HI_STD_I2C_NUM);
1323 return HI_FAILURE;
1324 }
1325
1326 if (i2c_reg_addr_byte_num > 4) { /* max reg address len is 4 byte */
1327 HI_LOG_ERR("para i2c_reg_addr_byte_num is invalid.\n");
1328 return HI_FAILURE;
1329 }
1330
1331 if (p_data == NULL) {
1332 HI_LOG_ERR("para p_data is null.\n");
1333 return HI_FAILURE;
1334 }
1335
1336 if (data_len > HI_I2C_MAX_LENGTH) {
1337 HI_LOG_ERR("para data_len is invalid.\n");
1338 return HI_FAILURE;
1339 }
1340
1341 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_num]);
1342 if (ret) {
1343 HI_LOG_INFO("lock g_i2c_sem error.\n");
1344 return HI_FAILURE;
1345 }
1346
1347 chip = hi_drv_i2c_get_chip_version();
1348 ret = i2c_drv_write(i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num, p_data, data_len, HI_TRUE);
1349 HI_LOG_INFO("ret=0x%x, i2c_num=%u, DevAddr=0x%x, reg_addr=0x%x, Num=%u, Len=%u\n", ret, i2c_num,
1350 i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num, data_len);
1351
1352 osal_sem_up(&g_i2c_sem_rw[i2c_num]);
1353
1354 hi_dbg_func_exit();
1355
1356 return ret;
1357 }
1358
hi_drv_i2c_write_no_stop(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len)1359 hi_s32 hi_drv_i2c_write_no_stop(hi_u32 i2c_num, hi_u8 i2c_dev_addr, hi_u32 i2c_reg_addr,
1360 hi_u32 i2c_reg_addr_byte_num, hi_u8 *p_data, hi_u32 data_len)
1361 {
1362 hi_s32 ret;
1363
1364 hi_dbg_func_enter();
1365
1366 if (i2c_num >= HI_STD_I2C_NUM) {
1367 HI_LOG_ERR("i2c_num(%d) is wrong, STD_I2C_NUM is %d\n", i2c_num, HI_STD_I2C_NUM);
1368 return HI_FAILURE;
1369 }
1370
1371 if (i2c_reg_addr_byte_num > 4) { /* max reg address len is 4 byte */
1372 HI_LOG_ERR("para i2c_reg_addr_byte_num is invalid.\n");
1373 return HI_FAILURE;
1374 }
1375
1376 if (p_data == NULL) {
1377 HI_LOG_ERR("para p_data is null.\n");
1378 return HI_FAILURE;
1379 }
1380
1381 if ((data_len > HI_I2C_MAX_LENGTH)) {
1382 HI_LOG_ERR("para data_len is invalid.\n");
1383 return HI_FAILURE;
1384 }
1385
1386 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_num]);
1387 if (ret) {
1388 HI_LOG_INFO("lock g_i2c_sem error.\n");
1389 return HI_FAILURE;
1390 }
1391
1392 ret = i2c_drv_write(i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num, p_data, data_len, HI_FALSE);
1393 HI_LOG_INFO("ret=0x%x, i2c_num=%d, DevAddr=0x%x, reg_addr=0x%x, Num=%d, Len=%d\n", ret, i2c_num,
1394 i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num, data_len);
1395
1396 osal_sem_up(&g_i2c_sem_rw[i2c_num]);
1397
1398 hi_dbg_func_exit();
1399
1400 return ret;
1401 }
1402
hi_drv_i2c_read(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len)1403 hi_s32 hi_drv_i2c_read(hi_u32 i2c_num, hi_u8 i2c_dev_addr, hi_u32 i2c_reg_addr,
1404 hi_u32 i2c_reg_addr_byte_num, hi_u8 *p_data, hi_u32 data_len)
1405 {
1406 hi_s32 ret;
1407 hi_u32 chip;
1408
1409 hi_dbg_func_enter();
1410
1411 ret = hi_drv_i2c_parm_check(i2c_num, i2c_reg_addr_byte_num, p_data, data_len);
1412 if (ret != HI_SUCCESS) {
1413 HI_LOG_INFO("hi_drv_i2c_parm_check error.\n");
1414 return HI_FAILURE;
1415 }
1416
1417 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_num]);
1418 if (ret) {
1419 HI_LOG_INFO("lock g_i2c_sem error.\n");
1420 return HI_FAILURE;
1421 }
1422
1423 chip = hi_drv_i2c_get_chip_version();
1424 ret = i2c_drv_read(i2c_num, i2c_dev_addr, HI_TRUE, i2c_reg_addr, i2c_reg_addr_byte_num, p_data, data_len);
1425 hi_dbg_print_h32(ret);
1426 hi_dbg_print_s32(i2c_num);
1427 hi_dbg_print_h32(i2c_dev_addr);
1428 hi_dbg_print_h32(i2c_reg_addr);
1429 hi_dbg_print_s32(i2c_reg_addr_byte_num);
1430 hi_dbg_print_s32(data_len);
1431
1432 osal_sem_up(&g_i2c_sem_rw[i2c_num]);
1433
1434 hi_dbg_func_exit();
1435
1436 return ret;
1437 }
1438
hi_drv_i2c_read_si_labs(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len)1439 hi_s32 hi_drv_i2c_read_si_labs(hi_u32 i2c_num, hi_u8 i2c_dev_addr, hi_u32 i2c_reg_addr, hi_u32 i2c_reg_addr_byte_num,
1440 hi_u8 *p_data, hi_u32 data_len)
1441 {
1442 hi_s32 ret;
1443
1444 hi_dbg_func_enter();
1445
1446 ret = hi_drv_i2c_parm_check(i2c_num, i2c_reg_addr_byte_num, p_data, data_len);
1447 if (ret != HI_SUCCESS) {
1448 HI_LOG_INFO("hi_drv_i2c_parm_check error.\n");
1449 return HI_FAILURE;
1450 }
1451
1452 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_num]);
1453 if (ret) {
1454 HI_LOG_INFO("lock g_i2c_sem error.\n");
1455 return HI_FAILURE;
1456 }
1457
1458 ret = i2c_drv_read_si_labs(i2c_num, i2c_dev_addr, HI_TRUE, i2c_reg_addr, i2c_reg_addr_byte_num, p_data, data_len);
1459
1460 osal_sem_up(&g_i2c_sem_rw[i2c_num]);
1461
1462 hi_dbg_func_exit();
1463
1464 return ret;
1465 }
1466
hi_drv_i2c_write_sony(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len,hi_u8 mode)1467 hi_s32 hi_drv_i2c_write_sony(hi_u32 i2c_num, hi_u8 i2c_dev_addr, hi_u32 i2c_reg_addr, hi_u32 i2c_reg_addr_byte_num,\
1468 hi_u8 *p_data, hi_u32 data_len, hi_u8 mode)
1469 {
1470 hi_s32 ret;
1471
1472 hi_dbg_func_enter();
1473
1474 if (i2c_num >= HI_STD_I2C_NUM) {
1475 HI_LOG_ERR("i2c_num(%d) is wrong, STD_I2C_NUM is %d\n", i2c_num, HI_STD_I2C_NUM);
1476 return HI_FAILURE;
1477 }
1478
1479 if (i2c_reg_addr_byte_num > 4) { /* max reg address len is 4 byte */
1480 HI_LOG_ERR("para i2c_reg_addr_byte_num is invalid.\n");
1481 return HI_FAILURE;
1482 }
1483
1484 if (p_data == NULL) {
1485 HI_LOG_ERR("para p_data is null.\n");
1486 return HI_FAILURE;
1487 }
1488
1489 if ((data_len > HI_I2C_MAX_LENGTH)) {
1490 HI_LOG_ERR("para data_len is invalid.\n");
1491 return HI_FAILURE;
1492 }
1493
1494 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_num]);
1495 if (ret) {
1496 HI_LOG_ERR("lock g_i2c_sem error.\n");
1497 return HI_FAILURE;
1498 }
1499
1500 ret = i2c_drv_write_sony(i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num, p_data, data_len, mode);
1501 HI_LOG_INFO("ret=0x%x, i2c_num=%d, DevAddr=0x%x, reg_addr=0x%x, Num=%d, Len=%d, data0=0x%x\n", ret, i2c_num,
1502 i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num, data_len, p_data[0]);
1503
1504 osal_sem_up(&g_i2c_sem_rw[i2c_num]);
1505
1506 hi_dbg_func_exit();
1507
1508 return ret;
1509 }
1510
hi_drv_i2c_read_sony(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len,hi_u8 mode)1511 hi_s32 hi_drv_i2c_read_sony(hi_u32 i2c_num, hi_u8 i2c_dev_addr, hi_u32 i2c_reg_addr,
1512 hi_u32 i2c_reg_addr_byte_num, hi_u8 *p_data, hi_u32 data_len, hi_u8 mode)
1513 {
1514 hi_s32 ret;
1515
1516 hi_dbg_func_enter();
1517
1518 ret = hi_drv_i2c_parm_check(i2c_num, i2c_reg_addr_byte_num, p_data, data_len);
1519 if (ret != HI_SUCCESS) {
1520 HI_LOG_INFO("hi_drv_i2c_parm_check error.\n");
1521 return HI_FAILURE;
1522 }
1523
1524 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_num]);
1525 if (ret) {
1526 HI_LOG_ERR("lock g_i2c_sem error.\n");
1527 return HI_FAILURE;
1528 }
1529
1530 ret = i2c_drv_read_sony(i2c_num, i2c_dev_addr, i2c_reg_addr, i2c_reg_addr_byte_num, p_data, data_len, mode);
1531 HI_LOG_INFO("ret=0x%x, i2c_num=%d, DevAddr=0x%x, reg_addr=0x%x, Num=%d, Len=%d\n", ret, i2c_num, i2c_dev_addr,
1532 i2c_reg_addr, i2c_reg_addr_byte_num, data_len);
1533
1534 osal_sem_up(&g_i2c_sem_rw[i2c_num]);
1535
1536 hi_dbg_func_exit();
1537
1538 return ret;
1539 }
1540
1541 /* Some I2C needn't send slave address before read */
hi_drv_i2c_read_directly(hi_u32 i2c_num,hi_u8 i2c_dev_addr,hi_u32 i2c_reg_addr,hi_u32 i2c_reg_addr_byte_num,hi_u8 * p_data,hi_u32 data_len)1542 hi_s32 hi_drv_i2c_read_directly(hi_u32 i2c_num, hi_u8 i2c_dev_addr, hi_u32 i2c_reg_addr, \
1543 hi_u32 i2c_reg_addr_byte_num, hi_u8 *p_data, hi_u32 data_len)
1544 {
1545 hi_s32 ret;
1546
1547 hi_dbg_func_enter();
1548
1549 ret = hi_drv_i2c_parm_check(i2c_num, i2c_reg_addr_byte_num, p_data, data_len);
1550 if (ret != HI_SUCCESS) {
1551 HI_LOG_INFO("hi_drv_i2c_parm_check error.\n");
1552 return HI_FAILURE;
1553 }
1554
1555 ret = osal_sem_down_interruptible(&g_i2c_sem_rw[i2c_num]);
1556 if (ret) {
1557 HI_LOG_INFO("lock g_i2c_sem error.\n");
1558 return HI_FAILURE;
1559 }
1560
1561 ret = i2c_drv_read(i2c_num, i2c_dev_addr, HI_FALSE, i2c_reg_addr, i2c_reg_addr_byte_num, p_data, data_len);
1562 HI_LOG_INFO("ret=0x%x, i2c_num=%d, DevAddr=0x%x, reg_addr=0x%x, Num=%d, Len=%d\n", ret, i2c_num, i2c_dev_addr,
1563 i2c_reg_addr, i2c_reg_addr_byte_num, data_len);
1564
1565 osal_sem_up(&g_i2c_sem_rw[i2c_num]);
1566
1567 hi_dbg_func_exit();
1568
1569 return ret;
1570 }
1571
1572 #ifndef MODULE
1573 EXPORT_SYMBOL(i2c_pm_suspend);
1574 EXPORT_SYMBOL(i2c_pm_resume);
1575 #endif
1576 EXPORT_SYMBOL(i2c_drv_lowpower_enter);
1577 EXPORT_SYMBOL(i2c_drv_lowpower_exit);
1578
1579
1580 EXPORT_SYMBOL(hi_drv_i2c_init);
1581 EXPORT_SYMBOL(hi_drv_i2c_de_init);
1582
1583 EXPORT_SYMBOL(hi_drv_i2c_write_config);
1584 EXPORT_SYMBOL(hi_drv_i2c_write);
1585 EXPORT_SYMBOL(hi_drv_i2c_read);
1586 EXPORT_SYMBOL(hi_drv_i2c_read_sony);
1587 EXPORT_SYMBOL(hi_drv_i2c_write_sony);
1588 EXPORT_SYMBOL(hi_drv_i2c_read_directly);
1589 EXPORT_SYMBOL(hi_drv_i2c_write_no_stop);
1590 EXPORT_SYMBOL(hi_drv_i2c_read_si_labs);
1591