1 /*!
2 \file gd32vf103_timer.c
3 \brief TIMER driver
4
5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
6 */
7
8 /*
9 Copyright (c) 2019, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34 #include "gd32vf103_timer.h"
35
36 /* TIMER init parameter mask */
37 #define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */
38 #define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */
39 #define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */
40
41 /*!
42 \brief deinit a timer
43 \param[in] timer_periph: TIMERx(x=0..13)
44 \param[out] none
45 \retval none
46 */
timer_deinit(uint32_t timer_periph)47 void timer_deinit(uint32_t timer_periph)
48 {
49 switch(timer_periph){
50 case TIMER0:
51 /* reset TIMER0 */
52 rcu_periph_reset_enable(RCU_TIMER0RST);
53 rcu_periph_reset_disable(RCU_TIMER0RST);
54 break;
55 case TIMER1:
56 /* reset TIMER1 */
57 rcu_periph_reset_enable(RCU_TIMER1RST);
58 rcu_periph_reset_disable(RCU_TIMER1RST);
59 break;
60 case TIMER2:
61 /* reset TIMER2 */
62 rcu_periph_reset_enable(RCU_TIMER2RST);
63 rcu_periph_reset_disable(RCU_TIMER2RST);
64 break;
65 case TIMER3:
66 /* reset TIMER3 */
67 rcu_periph_reset_enable(RCU_TIMER3RST);
68 rcu_periph_reset_disable(RCU_TIMER3RST);
69 break;
70 case TIMER4:
71 /* reset TIMER4 */
72 rcu_periph_reset_enable(RCU_TIMER4RST);
73 rcu_periph_reset_disable(RCU_TIMER4RST);
74 break;
75 case TIMER5:
76 /* reset TIMER5 */
77 rcu_periph_reset_enable(RCU_TIMER5RST);
78 rcu_periph_reset_disable(RCU_TIMER5RST);
79 break;
80 case TIMER6:
81 /* reset TIMER6 */
82 rcu_periph_reset_enable(RCU_TIMER6RST);
83 rcu_periph_reset_disable(RCU_TIMER6RST);
84 break;
85
86 default:
87 break;
88 }
89 }
90
91 /*!
92 \brief initialize TIMER init parameter struct with a default value
93 \param[in] initpara: init parameter struct
94 \param[out] none
95 \retval none
96 */
timer_struct_para_init(timer_parameter_struct * initpara)97 void timer_struct_para_init(timer_parameter_struct* initpara)
98 {
99 /* initialize the init parameter struct member with the default value */
100 initpara->prescaler = 0U;
101 initpara->alignedmode = TIMER_COUNTER_EDGE;
102 initpara->counterdirection = TIMER_COUNTER_UP;
103 initpara->period = 65535U;
104 initpara->clockdivision = TIMER_CKDIV_DIV1;
105 initpara->repetitioncounter = 0U;
106 }
107
108 /*!
109 \brief initialize TIMER counter
110 \param[in] timer_periph: TIMERx(x=0..6)
111 \param[in] initpara: init parameter struct
112 prescaler: prescaler value of the counter clock, 0~65535
113 alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP,
114 TIMER_COUNTER_CENTER_BOTH
115 counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN
116 period: counter auto reload value, 0~65535
117 clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4
118 repetitioncounter: counter repetition value, 0~255
119 \param[out] none
120 \retval none
121 */
timer_init(uint32_t timer_periph,timer_parameter_struct * initpara)122 void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara)
123 {
124 /* configure the counter prescaler value */
125 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
126
127 /* configure the counter direction and aligned mode */
128 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)
129 || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) ){
130 TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM));
131 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK);
132 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
133 }else{
134 TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR);
135 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK);
136 }
137
138 /* configure the autoreload value */
139 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
140
141 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){
142 /* reset the CKDIV bit */
143 TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV);
144 TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK);
145 }
146
147 if (TIMER0 == timer_periph) {
148 /* configure the repetition counter value */
149 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
150 }
151
152 /* generate an update event */
153 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
154 }
155
156 /*!
157 \brief enable a timer
158 \param[in] timer_periph: TIMERx(x=0..6)
159 \param[out] none
160 \retval none
161 */
timer_enable(uint32_t timer_periph)162 void timer_enable(uint32_t timer_periph)
163 {
164 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
165 }
166
167 /*!
168 \brief disable a timer
169 \param[in] timer_periph: TIMERx(x=0..13)
170 \param[out] none
171 \retval none
172 */
timer_disable(uint32_t timer_periph)173 void timer_disable(uint32_t timer_periph)
174 {
175 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
176 }
177
178 /*!
179 \brief enable the auto reload shadow function
180 \param[in] timer_periph: TIMERx(x=0..6)
181 \param[out] none
182 \retval none
183 */
timer_auto_reload_shadow_enable(uint32_t timer_periph)184 void timer_auto_reload_shadow_enable(uint32_t timer_periph)
185 {
186 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
187 }
188
189 /*!
190 \brief disable the auto reload shadow function
191 \param[in] timer_periph: TIMERx(x=0..6)
192 \param[out] none
193 \retval none
194 */
timer_auto_reload_shadow_disable(uint32_t timer_periph)195 void timer_auto_reload_shadow_disable(uint32_t timer_periph)
196 {
197 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
198 }
199
200 /*!
201 \brief enable the update event
202 \param[in] timer_periph: TIMERx(x=0..6)
203 \param[out] none
204 \retval none
205 */
timer_update_event_enable(uint32_t timer_periph)206 void timer_update_event_enable(uint32_t timer_periph)
207 {
208 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
209 }
210
211 /*!
212 \brief disable the update event
213 \param[in] timer_periph: TIMERx(x=0..6)
214 \param[out] none
215 \retval none
216 */
timer_update_event_disable(uint32_t timer_periph)217 void timer_update_event_disable(uint32_t timer_periph)
218 {
219 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
220 }
221
222 /*!
223 \brief set TIMER counter alignment mode
224 \param[in] timer_periph: TIMERx(x=0..4)
225 \param[in] aligned:
226 only one parameter can be selected which is shown as below:
227 \arg TIMER_COUNTER_EDGE: edge-aligned mode
228 \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
229 \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
230 \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
231 \param[out] none
232 \retval none
233 */
timer_counter_alignment(uint32_t timer_periph,uint16_t aligned)234 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
235 {
236 TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM);
237 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
238 }
239
240 /*!
241 \brief set TIMER counter up direction
242 \param[in] timer_periph: TIMERx(x=0..4)
243 \param[out] none
244 \retval none
245 */
timer_counter_up_direction(uint32_t timer_periph)246 void timer_counter_up_direction(uint32_t timer_periph)
247 {
248 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
249 }
250
251 /*!
252 \brief set TIMER counter down direction
253 \param[in] timer_periph: TIMERx(x=0..4)
254 \param[out] none
255 \retval none
256 */
timer_counter_down_direction(uint32_t timer_periph)257 void timer_counter_down_direction(uint32_t timer_periph)
258 {
259 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
260 }
261
262 /*!
263 \brief configure TIMER prescaler
264 \param[in] timer_periph: TIMERx(x=0..6)
265 \param[in] prescaler: prescaler value
266 \param[in] pscreload: prescaler reload mode
267 only one parameter can be selected which is shown as below:
268 \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
269 \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
270 \param[out] none
271 \retval none
272 */
timer_prescaler_config(uint32_t timer_periph,uint16_t prescaler,uint32_t pscreload)273 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload)
274 {
275 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
276
277 if(TIMER_PSC_RELOAD_NOW == pscreload){
278 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
279 }
280 }
281
282 /*!
283 \brief configure TIMER repetition register value
284 \param[in] timer_periph: TIMERx(x=0)
285 \param[in] repetition: the counter repetition value, 0~255
286 \param[out] none
287 \retval none
288 */
timer_repetition_value_config(uint32_t timer_periph,uint16_t repetition)289 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
290 {
291 TIMER_CREP(timer_periph) = (uint32_t)repetition;
292 }
293
294 /*!
295 \brief configure TIMER autoreload register value
296 \param[in] timer_periph: TIMERx(x=0..6)
297 \param[in] autoreload: the counter auto-reload value
298 \param[out] none
299 \retval none
300 */
timer_autoreload_value_config(uint32_t timer_periph,uint16_t autoreload)301 void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload)
302 {
303 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
304 }
305
306 /*!
307 \brief configure TIMER counter register value
308 \param[in] timer_periph: TIMERx(x=0..6)
309 \param[in] counter: the counter value
310 \param[out] none
311 \retval none
312 */
timer_counter_value_config(uint32_t timer_periph,uint16_t counter)313 void timer_counter_value_config(uint32_t timer_periph, uint16_t counter)
314 {
315 TIMER_CNT(timer_periph) = (uint32_t)counter;
316 }
317
318 /*!
319 \brief read TIMER counter value
320 \param[in] timer_periph: TIMERx(x=0..6)
321 \param[out] none
322 \retval counter value
323 */
timer_counter_read(uint32_t timer_periph)324 uint32_t timer_counter_read(uint32_t timer_periph)
325 {
326 uint32_t count_value = 0U;
327 count_value = TIMER_CNT(timer_periph);
328 return (count_value);
329 }
330
331 /*!
332 \brief read TIMER prescaler value
333 \param[in] timer_periph: TIMERx(x=0..6)
334 \param[out] none
335 \retval prescaler register value
336 */
timer_prescaler_read(uint32_t timer_periph)337 uint16_t timer_prescaler_read(uint32_t timer_periph)
338 {
339 uint16_t prescaler_value = 0U;
340 prescaler_value = (uint16_t) (TIMER_PSC(timer_periph));
341 return (prescaler_value);
342 }
343
344 /*!
345 \brief configure TIMER single pulse mode
346 \param[in] timer_periph: TIMERx(x=0..6)
347 \param[in] spmode:
348 only one parameter can be selected which is shown as below:
349 \arg TIMER_SP_MODE_SINGLE: single pulse mode
350 \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
351 \param[out] none
352 \retval none
353 */
timer_single_pulse_mode_config(uint32_t timer_periph,uint32_t spmode)354 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
355 {
356 if(TIMER_SP_MODE_SINGLE == spmode){
357 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
358 }else if(TIMER_SP_MODE_REPETITIVE == spmode){
359 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
360 }else{
361 /* illegal parameters */
362 }
363 }
364
365 /*!
366 \brief configure TIMER update source
367 \param[in] timer_periph: TIMERx(x=0..6)
368 \param[in] update:
369 only one parameter can be selected which is shown as below:
370 \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,
371 or the slave mode controller trigger
372 \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
373 \param[out] none
374 \retval none
375 */
timer_update_source_config(uint32_t timer_periph,uint32_t update)376 void timer_update_source_config(uint32_t timer_periph, uint32_t update)
377 {
378 if(TIMER_UPDATE_SRC_REGULAR == update){
379 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
380 }else if(TIMER_UPDATE_SRC_GLOBAL == update){
381 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
382 }else{
383 /* illegal parameters */
384 }
385 }
386
387 /*!
388 \brief enable the TIMER DMA
389 \param[in] timer_periph: TIMERx(x=0..6)
390 \param[in] dma: specify which DMA to enable
391 one or more parameters can be selected which are shown as below:
392 \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6)
393 \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4)
394 \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4)
395 \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4)
396 \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4)
397 \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0)
398 \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4)
399 \param[out] none
400 \retval none
401 */
timer_dma_enable(uint32_t timer_periph,uint16_t dma)402 void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
403 {
404 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
405 }
406
407 /*!
408 \brief disable the TIMER DMA
409 \param[in] timer_periph: TIMERxTIMERx(x=0..6)
410 \param[in] dma: specify which DMA to disbale
411 one or more parameters can be selected which are shown as below:
412 \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6)
413 \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4)
414 \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4)
415 \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4)
416 \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4)
417 \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0)
418 \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4,7)
419 \param[out] none
420 \retval none
421 */
timer_dma_disable(uint32_t timer_periph,uint16_t dma)422 void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
423 {
424 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
425 }
426
427 /*!
428 \brief channel DMA request source selection
429 \param[in] timer_periph: TIMERx(x=0..4)
430 \param[in] dma_request: channel DMA request source selection
431 only one parameter can be selected which is shown as below:
432 \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs
433 \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs
434 \param[out] none
435 \retval none
436 */
timer_channel_dma_request_source_select(uint32_t timer_periph,uint32_t dma_request)437 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request)
438 {
439 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){
440 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
441 }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){
442 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
443 }else{
444 /* illegal parameters */
445 }
446 }
447
448 /*!
449 \brief configure the TIMER DMA transfer
450 \param[in] timer_periph: TIMERx(x=0..4)
451 \param[in] dma_baseaddr:
452 only one parameter can be selected which is shown as below:
453 \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..4)
454 \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..4)
455 \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..4)
456 \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..4)
457 \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..4)
458 \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..4)
459 \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..4)
460 \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..4)
461 \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..4)
462 \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..4)
463 \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..4)
464 \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..4)
465 \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0)
466 \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..4)
467 \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..4)
468 \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..4)
469 \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..4)
470 \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0)
471 \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..4)
472 \param[in] dma_length:
473 only one parameter can be selected which is shown as below:
474 \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..6): DMA transfer x time
475 \param[out] none
476 \retval none
477 */
timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_length)478 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_length)
479 {
480 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
481 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_length);
482 }
483
484 /*!
485 \brief software generate events
486 \param[in] timer_periph: TIMERx(x=0..4)
487 \param[in] event: the timer software event generation sources
488 one or more parameters can be selected which are shown as below:
489 \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..6)
490 \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4)
491 \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4)
492 \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4)
493 \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4)
494 \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0)
495 \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4)
496 \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0)
497 \param[out] none
498 \retval none
499 */
timer_event_software_generate(uint32_t timer_periph,uint16_t event)500 void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
501 {
502 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
503 }
504
505 /*!
506 \brief initialize TIMER break parameter struct with a default value
507 \param[in] breakpara: TIMER break parameter struct
508 \param[out] none
509 \retval none
510 */
timer_break_struct_para_init(timer_break_parameter_struct * breakpara)511 void timer_break_struct_para_init(timer_break_parameter_struct* breakpara)
512 {
513 /* initialize the break parameter struct member with the default value */
514 breakpara->runoffstate = TIMER_ROS_STATE_DISABLE;
515 breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE;
516 breakpara->deadtime = 0U;
517 breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW;
518 breakpara->outputautostate = TIMER_OUTAUTO_DISABLE;
519 breakpara->protectmode = TIMER_CCHP_PROT_OFF;
520 breakpara->breakstate = TIMER_BREAK_DISABLE;
521 }
522
523 /*!
524 \brief configure TIMER break function
525 \param[in] timer_periph: TIMERx(x=0)
526 \param[in] breakpara: TIMER break parameter struct
527 runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE
528 ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE
529 deadtime: 0~255
530 breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH
531 outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE
532 protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2
533 breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE
534 \param[out] none
535 \retval none
536 */
timer_break_config(uint32_t timer_periph,timer_break_parameter_struct * breakpara)537 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara)
538 {
539 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
540 ((uint32_t)(breakpara->ideloffstate))|
541 ((uint32_t)(breakpara->deadtime)) |
542 ((uint32_t)(breakpara->breakpolarity)) |
543 ((uint32_t)(breakpara->outputautostate)) |
544 ((uint32_t)(breakpara->protectmode)) |
545 ((uint32_t)(breakpara->breakstate)));
546 }
547
548 /*!
549 \brief enable TIMER break function
550 \param[in] timer_periph: TIMERx(x=0)
551 \param[out] none
552 \retval none
553 */
timer_break_enable(uint32_t timer_periph)554 void timer_break_enable(uint32_t timer_periph)
555 {
556 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
557 }
558
559 /*!
560 \brief disable TIMER break function
561 \param[in] timer_periph: TIMERx(x=0)
562 \param[out] none
563 \retval none
564 */
timer_break_disable(uint32_t timer_periph)565 void timer_break_disable(uint32_t timer_periph)
566 {
567 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
568 }
569
570 /*!
571 \brief enable TIMER output automatic function
572 \param[in] timer_periph: TIMERx(x=0)
573 \param[out] none
574 \retval none
575 */
timer_automatic_output_enable(uint32_t timer_periph)576 void timer_automatic_output_enable(uint32_t timer_periph)
577 {
578 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
579 }
580
581 /*!
582 \brief disable TIMER output automatic function
583 \param[in] timer_periph: TIMERx(x=0)
584 \param[out] none
585 \retval none
586 */
timer_automatic_output_disable(uint32_t timer_periph)587 void timer_automatic_output_disable(uint32_t timer_periph)
588 {
589 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
590 }
591
592 /*!
593 \brief enable or disable TIMER primary output function
594 \param[in] timer_periph: TIMERx(x=0)
595 \param[in] newvalue: ENABLE or DISABLE
596 \param[out] none
597 \retval none
598 */
timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue)599 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
600 {
601 if(ENABLE == newvalue){
602 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
603 }else{
604 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
605 }
606 }
607
608 /*!
609 \brief enable or disable channel capture/compare control shadow register
610 \param[in] timer_periph: TIMERx(x=0)
611 \param[in] newvalue: ENABLE or DISABLE
612 \param[out] none
613 \retval none
614 */
timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue)615 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
616 {
617 if(ENABLE == newvalue){
618 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
619 }else{
620 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
621 }
622 }
623
624 /*!
625 \brief configure TIMER channel control shadow register update control
626 \param[in] timer_periph: TIMERx(x=0)
627 \param[in] ccuctl: channel control shadow register update control
628 only one parameter can be selected which is shown as below:
629 \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
630 \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
631 \param[out] none
632 \retval none
633 */
timer_channel_control_shadow_update_config(uint32_t timer_periph,uint32_t ccuctl)634 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl)
635 {
636 if(TIMER_UPDATECTL_CCU == ccuctl){
637 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
638 }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){
639 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
640 }else{
641 /* illegal parameters */
642 }
643 }
644
645 /*!
646 \brief initialize TIMER channel output parameter struct with a default value
647 \param[in] ocpara: TIMER channel n output parameter struct
648 \param[out] none
649 \retval none
650 */
timer_channel_output_struct_para_init(timer_oc_parameter_struct * ocpara)651 void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara)
652 {
653 /* initialize the channel output parameter struct member with the default value */
654 ocpara->outputstate = TIMER_CCX_DISABLE;
655 ocpara->outputnstate = TIMER_CCXN_DISABLE;
656 ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH;
657 ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH;
658 ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW;
659 ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
660 }
661
662 /*!
663 \brief configure TIMER channel output function
664 \param[in] timer_periph: TIMERx(x=0..4)
665 \param[in] channel:
666 only one parameter can be selected which is shown as below:
667 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
668 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
669 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
670 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
671 \param[in] ocpara: TIMER channeln output parameter struct
672 outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE
673 outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE
674 ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW
675 ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW
676 ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH
677 ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH
678 \param[out] none
679 \retval none
680 */
timer_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_oc_parameter_struct * ocpara)681 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara)
682 {
683 switch(channel){
684 /* configure TIMER_CH_0 */
685 case TIMER_CH_0:
686 /* reset the CH0EN bit */
687 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
688 /* set the CH0EN bit */
689 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
690 /* reset the CH0P bit */
691 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
692 /* set the CH0P bit */
693 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
694
695 if (TIMER0 == timer_periph) {
696 /* reset the CH0NEN bit */
697 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
698 /* set the CH0NEN bit */
699 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
700 /* reset the CH0NP bit */
701 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
702 /* set the CH0NP bit */
703 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
704 /* reset the ISO0 bit */
705 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
706 /* set the ISO0 bit */
707 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
708 /* reset the ISO0N bit */
709 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
710 /* set the ISO0N bit */
711 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
712 }
713 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
714 break;
715 /* configure TIMER_CH_1 */
716 case TIMER_CH_1:
717 /* reset the CH1EN bit */
718 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
719 /* set the CH1EN bit */
720 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U);
721 /* reset the CH1P bit */
722 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
723 /* set the CH1P bit */
724 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
725
726 if (TIMER0 == timer_periph) {
727 /* reset the CH1NEN bit */
728 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
729 /* set the CH1NEN bit */
730 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
731 /* reset the CH1NP bit */
732 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
733 /* set the CH1NP bit */
734 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
735 /* reset the ISO1 bit */
736 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
737 /* set the ISO1 bit */
738 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
739 /* reset the ISO1N bit */
740 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
741 /* set the ISO1N bit */
742 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
743 }
744 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
745 break;
746 /* configure TIMER_CH_2 */
747 case TIMER_CH_2:
748 /* reset the CH2EN bit */
749 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
750 /* set the CH2EN bit */
751 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U);
752 /* reset the CH2P bit */
753 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
754 /* set the CH2P bit */
755 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
756
757 if (TIMER0 == timer_periph) {
758 /* reset the CH2NEN bit */
759 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
760 /* set the CH2NEN bit */
761 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
762 /* reset the CH2NP bit */
763 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
764 /* set the CH2NP bit */
765 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
766 /* reset the ISO2 bit */
767 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
768 /* set the ISO2 bit */
769 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
770 /* reset the ISO2N bit */
771 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
772 /* set the ISO2N bit */
773 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
774 }
775 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
776 break;
777 /* configure TIMER_CH_3 */
778 case TIMER_CH_3:
779 /* reset the CH3EN bit */
780 TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN);
781 /* set the CH3EN bit */
782 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U);
783 /* reset the CH3P bit */
784 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
785 /* set the CH3P bit */
786 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
787
788 if (TIMER0 == timer_periph) {
789 /* reset the ISO3 bit */
790 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
791 /* set the ISO3 bit */
792 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
793 }
794 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
795 break;
796 default:
797 break;
798 }
799 }
800
801 /*!
802 \brief configure TIMER channel output compare mode
803 \param[in] timer_periph: TIMERx(x=0..4)
804 \param[in] channel:
805 only one parameter can be selected which is shown as below:
806 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
807 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
808 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
809 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
810 \param[in] ocmode: channel output compare mode
811 only one parameter can be selected which is shown as below:
812 \arg TIMER_OC_MODE_TIMING: timing mode
813 \arg TIMER_OC_MODE_ACTIVE: active mode
814 \arg TIMER_OC_MODE_INACTIVE: inactive mode
815 \arg TIMER_OC_MODE_TOGGLE: toggle mode
816 \arg TIMER_OC_MODE_LOW: force low mode
817 \arg TIMER_OC_MODE_HIGH: force high mode
818 \arg TIMER_OC_MODE_PWM0: PWM mode 0
819 \arg TIMER_OC_MODE_PWM1: PWM mode 1
820 \param[out] none
821 \retval none
822 */
timer_channel_output_mode_config(uint32_t timer_periph,uint16_t channel,uint16_t ocmode)823 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
824 {
825 switch(channel){
826 /* configure TIMER_CH_0 */
827 case TIMER_CH_0:
828 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
829 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
830 break;
831 /* configure TIMER_CH_1 */
832 case TIMER_CH_1:
833 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
834 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
835 break;
836 /* configure TIMER_CH_2 */
837 case TIMER_CH_2:
838 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
839 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
840 break;
841 /* configure TIMER_CH_3 */
842 case TIMER_CH_3:
843 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
844 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
845 break;
846 default:
847 break;
848 }
849 }
850
851 /*!
852 \brief configure TIMER channel output pulse value
853 \param[in] timer_periph: TIMERx(x=0..4)
854 \param[in] channel:
855 only one parameter can be selected which is shown as below:
856 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
857 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
858 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
859 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
860 \param[in] pulse: channel output pulse value
861 \param[out] none
862 \retval none
863 */
timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t channel,uint32_t pulse)864 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
865 {
866 switch(channel){
867 /* configure TIMER_CH_0 */
868 case TIMER_CH_0:
869 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
870 break;
871 /* configure TIMER_CH_1 */
872 case TIMER_CH_1:
873 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
874 break;
875 /* configure TIMER_CH_2 */
876 case TIMER_CH_2:
877 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
878 break;
879 /* configure TIMER_CH_3 */
880 case TIMER_CH_3:
881 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
882 break;
883 default:
884 break;
885 }
886 }
887
888 /*!
889 \brief configure TIMER channel output shadow function
890 \param[in] timer_periph: TIMERx(x=0..4)
891 \param[in] channel:
892 only one parameter can be selected which is shown as below:
893 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
894 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
895 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
896 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
897 \param[in] ocshadow: channel output shadow state
898 only one parameter can be selected which is shown as below:
899 \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
900 \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
901 \param[out] none
902 \retval none
903 */
timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t ocshadow)904 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
905 {
906 switch(channel){
907 /* configure TIMER_CH_0 */
908 case TIMER_CH_0:
909 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
910 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
911 break;
912 /* configure TIMER_CH_1 */
913 case TIMER_CH_1:
914 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
915 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
916 break;
917 /* configure TIMER_CH_2 */
918 case TIMER_CH_2:
919 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
920 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
921 break;
922 /* configure TIMER_CH_3 */
923 case TIMER_CH_3:
924 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
925 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
926 break;
927 default:
928 break;
929 }
930 }
931
932 /*!
933 \brief configure TIMER channel output fast function
934 \param[in] timer_periph: TIMERx(x=0..4)
935 \param[in] channel:
936 only one parameter can be selected which is shown as below:
937 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
938 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
939 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
940 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
941 \param[in] ocfast: channel output fast function
942 only one parameter can be selected which is shown as below:
943 \arg TIMER_OC_FAST_ENABLE: channel output fast function enable
944 \arg TIMER_OC_FAST_DISABLE: channel output fast function disable
945 \param[out] none
946 \retval none
947 */
timer_channel_output_fast_config(uint32_t timer_periph,uint16_t channel,uint16_t ocfast)948 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
949 {
950 switch(channel){
951 /* configure TIMER_CH_0 */
952 case TIMER_CH_0:
953 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
954 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
955 break;
956 /* configure TIMER_CH_1 */
957 case TIMER_CH_1:
958 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
959 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
960 break;
961 /* configure TIMER_CH_2 */
962 case TIMER_CH_2:
963 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
964 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
965 break;
966 /* configure TIMER_CH_3 */
967 case TIMER_CH_3:
968 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
969 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
970 break;
971 default:
972 break;
973 }
974 }
975
976 /*!
977 \brief configure TIMER channel output clear function
978 \param[in] timer_periph: TIMERx(x=0..4)
979 \param[in] channel:
980 only one parameter can be selected which is shown as below:
981 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
982 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..41))
983 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
984 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
985 \param[in] occlear: channel output clear function
986 only one parameter can be selected which is shown as below:
987 \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
988 \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
989 \param[out] none
990 \retval none
991 */
timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear)992 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
993 {
994 switch(channel){
995 /* configure TIMER_CH_0 */
996 case TIMER_CH_0:
997 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
998 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
999 break;
1000 /* configure TIMER_CH_1 */
1001 case TIMER_CH_1:
1002 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1003 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1004 break;
1005 /* configure TIMER_CH_2 */
1006 case TIMER_CH_2:
1007 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1008 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1009 break;
1010 /* configure TIMER_CH_3 */
1011 case TIMER_CH_3:
1012 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1013 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1014 break;
1015 default:
1016 break;
1017 }
1018 }
1019
1020 /*!
1021 \brief configure TIMER channel output polarity
1022 \param[in] timer_periph: TIMERx(x=0..4)
1023 \param[in] channel:
1024 only one parameter can be selected which is shown as below:
1025 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1026 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1027 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1028 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1029 \param[in] ocpolarity: channel output polarity
1030 only one parameter can be selected which is shown as below:
1031 \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
1032 \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
1033 \param[out] none
1034 \retval none
1035 */
timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocpolarity)1036 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
1037 {
1038 switch(channel){
1039 /* configure TIMER_CH_0 */
1040 case TIMER_CH_0:
1041 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1042 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1043 break;
1044 /* configure TIMER_CH_1 */
1045 case TIMER_CH_1:
1046 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1047 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1048 break;
1049 /* configure TIMER_CH_2 */
1050 case TIMER_CH_2:
1051 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1052 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1053 break;
1054 /* configure TIMER_CH_3 */
1055 case TIMER_CH_3:
1056 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1057 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1058 break;
1059 default:
1060 break;
1061 }
1062 }
1063
1064 /*!
1065 \brief configure TIMER channel complementary output polarity
1066 \param[in] timer_periph: TIMERx(x=0)
1067 \param[in] channel:
1068 only one parameter can be selected which is shown as below:
1069 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0))
1070 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0))
1071 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0))
1072 \param[in] ocnpolarity: channel complementary output polarity
1073 only one parameter can be selected which is shown as below:
1074 \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
1075 \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
1076 \param[out] none
1077 \retval none
1078 */
timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnpolarity)1079 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
1080 {
1081 switch(channel){
1082 /* configure TIMER_CH_0 */
1083 case TIMER_CH_0:
1084 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1085 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1086 break;
1087 /* configure TIMER_CH_1 */
1088 case TIMER_CH_1:
1089 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1090 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1091 break;
1092 /* configure TIMER_CH_2 */
1093 case TIMER_CH_2:
1094 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1095 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1096 break;
1097 default:
1098 break;
1099 }
1100 }
1101
1102 /*!
1103 \brief configure TIMER channel enable state
1104 \param[in] timer_periph: TIMERx(x=0..4)
1105 \param[in] channel:
1106 only one parameter can be selected which is shown as below:
1107 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1108 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1109 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1110 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1111 \param[in] state: TIMER channel enable state
1112 only one parameter can be selected which is shown as below:
1113 \arg TIMER_CCX_ENABLE: channel enable
1114 \arg TIMER_CCX_DISABLE: channel disable
1115 \param[out] none
1116 \retval none
1117 */
timer_channel_output_state_config(uint32_t timer_periph,uint16_t channel,uint32_t state)1118 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
1119 {
1120 switch(channel){
1121 /* configure TIMER_CH_0 */
1122 case TIMER_CH_0:
1123 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1124 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1125 break;
1126 /* configure TIMER_CH_1 */
1127 case TIMER_CH_1:
1128 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1129 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1130 break;
1131 /* configure TIMER_CH_2 */
1132 case TIMER_CH_2:
1133 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1134 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1135 break;
1136 /* configure TIMER_CH_3 */
1137 case TIMER_CH_3:
1138 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1139 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1140 break;
1141 default:
1142 break;
1143 }
1144 }
1145
1146 /*!
1147 \brief configure TIMER channel complementary output enable state
1148 \param[in] timer_periph: TIMERx(x=0)
1149 \param[in] channel:
1150 only one parameter can be selected which is shown as below:
1151 \arg TIMER_CH_0: TIMER channel 0
1152 \arg TIMER_CH_1: TIMER channel 1
1153 \arg TIMER_CH_2: TIMER channel 2
1154 \param[in] ocnstate: TIMER channel complementary output enable state
1155 only one parameter can be selected which is shown as below:
1156 \arg TIMER_CCXN_ENABLE: channel complementary enable
1157 \arg TIMER_CCXN_DISABLE: channel complementary disable
1158 \param[out] none
1159 \retval none
1160 */
timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnstate)1161 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
1162 {
1163 switch(channel){
1164 /* configure TIMER_CH_0 */
1165 case TIMER_CH_0:
1166 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1167 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1168 break;
1169 /* configure TIMER_CH_1 */
1170 case TIMER_CH_1:
1171 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1172 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1173 break;
1174 /* configure TIMER_CH_2 */
1175 case TIMER_CH_2:
1176 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1177 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1178 break;
1179 default:
1180 break;
1181 }
1182 }
1183
1184 /*!
1185 \brief initialize TIMER channel input parameter struct with a default value
1186 \param[in] icpara: TIMER channel intput parameter struct
1187 \param[out] none
1188 \retval none
1189 */
timer_channel_input_struct_para_init(timer_ic_parameter_struct * icpara)1190 void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara)
1191 {
1192 /* initialize the channel input parameter struct member with the default value */
1193 icpara->icpolarity = TIMER_IC_POLARITY_RISING;
1194 icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
1195 icpara->icprescaler = TIMER_IC_PSC_DIV1;
1196 icpara->icfilter = 0U;
1197 }
1198
1199 /*!
1200 \brief configure TIMER input capture parameter
1201 \param[in] timer_periph: TIMERx(x=0..4)
1202 \param[in] channel:
1203 only one parameter can be selected which is shown as below:
1204 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1205 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1206 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1207 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1208 \param[in] icpara: TIMER channel intput parameter struct
1209 icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING,
1210 TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8)
1211 icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI,
1212 TIMER_IC_SELECTION_ITS
1213 icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4,
1214 TIMER_IC_PSC_DIV8
1215 icfilter: 0~15
1216 \param[out] none
1217 \retval none
1218 */
timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpara)1219 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara)
1220 {
1221 switch(channel){
1222 /* configure TIMER_CH_0 */
1223 case TIMER_CH_0:
1224 /* reset the CH0EN bit */
1225 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1226
1227 /* reset the CH0P and CH0NP bits */
1228 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1229 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1230 /* reset the CH0MS bit */
1231 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1232 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1233 /* reset the CH0CAPFLT bit */
1234 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1235 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1236
1237 /* set the CH0EN bit */
1238 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1239 break;
1240
1241 /* configure TIMER_CH_1 */
1242 case TIMER_CH_1:
1243 /* reset the CH1EN bit */
1244 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1245
1246 /* reset the CH1P and CH1NP bits */
1247 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1248 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1249 /* reset the CH1MS bit */
1250 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1251 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1252 /* reset the CH1CAPFLT bit */
1253 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1254 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1255
1256 /* set the CH1EN bit */
1257 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1258 break;
1259 /* configure TIMER_CH_2 */
1260 case TIMER_CH_2:
1261 /* reset the CH2EN bit */
1262 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1263
1264 /* reset the CH2P and CH2NP bits */
1265 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP));
1266 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1267
1268 /* reset the CH2MS bit */
1269 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1270 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1271
1272 /* reset the CH2CAPFLT bit */
1273 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1274 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1275
1276 /* set the CH2EN bit */
1277 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1278 break;
1279 /* configure TIMER_CH_3 */
1280 case TIMER_CH_3:
1281 /* reset the CH3EN bit */
1282 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1283
1284 /* reset the CH3P bits */
1285 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
1286 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1287
1288 /* reset the CH3MS bit */
1289 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1290 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1291
1292 /* reset the CH3CAPFLT bit */
1293 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1294 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1295
1296 /* set the CH3EN bit */
1297 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1298 break;
1299 default:
1300 break;
1301 }
1302 /* configure TIMER channel input capture prescaler value */
1303 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1304 }
1305
1306 /*!
1307 \brief configure TIMER channel input capture prescaler value
1308 \param[in] timer_periph: TIMERx(x=0..4)
1309 \param[in] channel:
1310 only one parameter can be selected which is shown as below:
1311 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1312 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1313 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1314 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1315 \param[in] prescaler: channel input capture prescaler value
1316 only one parameter can be selected which is shown as below:
1317 \arg TIMER_IC_PSC_DIV1: no prescaler
1318 \arg TIMER_IC_PSC_DIV2: divided by 2
1319 \arg TIMER_IC_PSC_DIV4: divided by 4
1320 \arg TIMER_IC_PSC_DIV8: divided by 8
1321 \param[out] none
1322 \retval none
1323 */
timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t channel,uint16_t prescaler)1324 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
1325 {
1326 switch(channel){
1327 /* configure TIMER_CH_0 */
1328 case TIMER_CH_0:
1329 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1330 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1331 break;
1332 /* configure TIMER_CH_1 */
1333 case TIMER_CH_1:
1334 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1335 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1336 break;
1337 /* configure TIMER_CH_2 */
1338 case TIMER_CH_2:
1339 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1340 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1341 break;
1342 /* configure TIMER_CH_3 */
1343 case TIMER_CH_3:
1344 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1345 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1346 break;
1347 default:
1348 break;
1349 }
1350 }
1351
1352 /*!
1353 \brief read TIMER channel capture compare register value
1354 \param[in] timer_periph: please refer to the following parameters
1355 \param[in] channel:
1356 only one parameter can be selected which is shown as below:
1357 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4))
1358 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4))
1359 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4))
1360 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4))
1361 \param[out] none
1362 \retval channel capture compare register value
1363 */
timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t channel)1364 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
1365 {
1366 uint32_t count_value = 0U;
1367
1368 switch(channel){
1369 case TIMER_CH_0:
1370 /* read TIMER channel 0 capture compare register value */
1371 count_value = TIMER_CH0CV(timer_periph);
1372 break;
1373 case TIMER_CH_1:
1374 /* read TIMER channel 1 capture compare register value */
1375 count_value = TIMER_CH1CV(timer_periph);
1376 break;
1377 case TIMER_CH_2:
1378 /* read TIMER channel 2 capture compare register value */
1379 count_value = TIMER_CH2CV(timer_periph);
1380 break;
1381 case TIMER_CH_3:
1382 /* read TIMER channel 3 capture compare register value */
1383 count_value = TIMER_CH3CV(timer_periph);
1384 break;
1385 default:
1386 break;
1387 }
1388 return (count_value);
1389 }
1390
1391 /*!
1392 \brief configure TIMER input pwm capture function
1393 \param[in] timer_periph: TIMERx(x=0..4)
1394 \param[in] channel:
1395 only one parameter can be selected which is shown as below:
1396 \arg TIMER_CH_0: TIMER channel 0
1397 \arg TIMER_CH_1: TIMER channel 1
1398 \param[in] icpwm: TIMER channel intput pwm parameter struct
1399 icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING
1400 icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI
1401 icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4,
1402 TIMER_IC_PSC_DIV8
1403 icfilter: 0~15
1404 \param[out] none
1405 \retval none
1406 */
timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpwm)1407 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm)
1408 {
1409 uint16_t icpolarity = 0x0U;
1410 uint16_t icselection = 0x0U;
1411
1412 /* Set channel input polarity */
1413 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){
1414 icpolarity = TIMER_IC_POLARITY_FALLING;
1415 }else{
1416 icpolarity = TIMER_IC_POLARITY_RISING;
1417 }
1418 /* Set channel input mode selection */
1419 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){
1420 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1421 }else{
1422 icselection = TIMER_IC_SELECTION_DIRECTTI;
1423 }
1424
1425 if(TIMER_CH_0 == channel){
1426 /* reset the CH0EN bit */
1427 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1428 /* reset the CH0P and CH0NP bits */
1429 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1430 /* set the CH0P and CH0NP bits */
1431 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1432 /* reset the CH0MS bit */
1433 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1434 /* set the CH0MS bit */
1435 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1436 /* reset the CH0CAPFLT bit */
1437 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1438 /* set the CH0CAPFLT bit */
1439 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1440 /* set the CH0EN bit */
1441 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1442 /* configure TIMER channel input capture prescaler value */
1443 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1444
1445 /* reset the CH1EN bit */
1446 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1447 /* reset the CH1P and CH1NP bits */
1448 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1449 /* set the CH1P and CH1NP bits */
1450 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U);
1451 /* reset the CH1MS bit */
1452 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1453 /* set the CH1MS bit */
1454 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1455 /* reset the CH1CAPFLT bit */
1456 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1457 /* set the CH1CAPFLT bit */
1458 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1459 /* set the CH1EN bit */
1460 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1461 /* configure TIMER channel input capture prescaler value */
1462 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1463 }else{
1464 /* reset the CH1EN bit */
1465 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1466 /* reset the CH1P and CH1NP bits */
1467 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1468 /* set the CH1P and CH1NP bits */
1469 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1470 /* reset the CH1MS bit */
1471 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1472 /* set the CH1MS bit */
1473 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1474 /* reset the CH1CAPFLT bit */
1475 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1476 /* set the CH1CAPFLT bit */
1477 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1478 /* set the CH1EN bit */
1479 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1480 /* configure TIMER channel input capture prescaler value */
1481 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1482
1483 /* reset the CH0EN bit */
1484 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1485 /* reset the CH0P and CH0NP bits */
1486 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1487 /* set the CH0P and CH0NP bits */
1488 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1489 /* reset the CH0MS bit */
1490 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1491 /* set the CH0MS bit */
1492 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1493 /* reset the CH0CAPFLT bit */
1494 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1495 /* set the CH0CAPFLT bit */
1496 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1497 /* set the CH0EN bit */
1498 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1499 /* configure TIMER channel input capture prescaler value */
1500 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1501 }
1502 }
1503
1504 /*!
1505 \brief configure TIMER hall sensor mode
1506 \param[in] timer_periph: TIMERx(x=0..4)
1507 \param[in] hallmode:
1508 only one parameter can be selected which is shown as below:
1509 \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
1510 \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
1511 \param[out] none
1512 \retval none
1513 */
timer_hall_mode_config(uint32_t timer_periph,uint32_t hallmode)1514 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
1515 {
1516 if(TIMER_HALLINTERFACE_ENABLE == hallmode){
1517 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1518 }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){
1519 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1520 }else{
1521 /* illegal parameters */
1522 }
1523 }
1524
1525 /*!
1526 \brief select TIMER input trigger source
1527 \param[in] timer_periph: TIMERx(x=0..4)
1528 \param[in] intrigger:
1529 only one parameter can be selected which is shown as below:
1530 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4))
1531 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4))
1532 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4))
1533 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4))
1534 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4))
1535 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4))
1536 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4))
1537 \arg TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0..4))
1538 \param[out] none
1539 \retval none
1540 */
timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger)1541 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
1542 {
1543 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1544 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1545 }
1546
1547 /*!
1548 \brief select TIMER master mode output trigger source
1549 \param[in] timer_periph: TIMERx(x=0..6)
1550 \param[in] outrigger:
1551 only one parameter can be selected which is shown as below:
1552 \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..6))
1553 \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..6))
1554 \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..6))
1555 \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4))
1556 \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4))
1557 \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4))
1558 \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4))
1559 \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4))
1560 \param[out] none
1561 \retval none
1562 */
timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t outrigger)1563 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
1564 {
1565 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1566 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1567 }
1568
1569 /*!
1570 \brief select TIMER slave mode
1571 \param[in] timer_periph: TIMERx(x=0..4)
1572 \param[in] slavemode:
1573 only one parameter can be selected which is shown as below:
1574 \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable
1575 \arg TIMER_ENCODER_MODE0: encoder mode 0
1576 \arg TIMER_ENCODER_MODE1: encoder mode 1
1577 \arg TIMER_ENCODER_MODE2: encoder mode 2
1578 \arg TIMER_SLAVE_MODE_RESTART: restart mode
1579 \arg TIMER_SLAVE_MODE_PAUSE: pause mode
1580 \arg TIMER_SLAVE_MODE_EVENT: event mode
1581 \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0
1582 \param[out] none
1583 \retval none
1584 */
1585
timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode)1586 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
1587 {
1588 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1589 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1590 }
1591
1592 /*!
1593 \brief configure TIMER master slave mode
1594 \param[in] timer_periph: TIMERx(x=0..4)
1595 \param[in] masterslave:
1596 only one parameter can be selected which is shown as below:
1597 \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
1598 \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
1599 \param[out] none
1600 \retval none
1601 */
timer_master_slave_mode_config(uint32_t timer_periph,uint32_t masterslave)1602 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
1603 {
1604 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){
1605 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1606 }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){
1607 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1608 }else{
1609 /* illegal parameters */
1610 }
1611 }
1612
1613 /*!
1614 \brief configure TIMER external trigger input
1615 \param[in] timer_periph: TIMERx(x=0..4)
1616 \param[in] extprescaler:
1617 only one parameter can be selected which is shown as below:
1618 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1619 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1620 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1621 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1622 \param[in] extpolarity:
1623 only one parameter can be selected which is shown as below:
1624 \arg TIMER_ETP_FALLING: active low or falling edge active
1625 \arg TIMER_ETP_RISING: active high or rising edge active
1626 \param[in] extfilter: a value between 0 and 15
1627 \param[out] none
1628 \retval none
1629 */
timer_external_trigger_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1630 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1631 {
1632 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
1633 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
1634 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
1635 }
1636
1637 /*!
1638 \brief configure TIMER quadrature decoder mode
1639 \param[in] timer_periph: TIMERx(x=0..4)
1640 \param[in] decomode:
1641 only one parameter can be selected which is shown as below:
1642 \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
1643 \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
1644 \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
1645 \param[in] ic0polarity:
1646 only one parameter can be selected which is shown as below:
1647 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1648 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1649 \param[in] ic1polarity:
1650 only one parameter can be selected which is shown as below:
1651 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1652 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1653 \param[out] none
1654 \retval none
1655 */
timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t decomode,uint16_t ic0polarity,uint16_t ic1polarity)1656 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity)
1657 {
1658 /* configure the quadrature decoder mode */
1659 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1660 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1661 /* configure input capture selection */
1662 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1663 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
1664 /* configure channel input capture polarity */
1665 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1666 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1667 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U));
1668 }
1669
1670 /*!
1671 \brief configure TIMER internal clock mode
1672 \param[in] timer_periph: TIMERx(x=0..4)
1673 \param[out] none
1674 \retval none
1675 */
timer_internal_clock_config(uint32_t timer_periph)1676 void timer_internal_clock_config(uint32_t timer_periph)
1677 {
1678 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1679 }
1680
1681 /*!
1682 \brief configure TIMER the internal trigger as external clock input
1683 \param[in] timer_periph: TIMERx(x=0..4)
1684 \param[in] intrigger:
1685 only one parameter can be selected which is shown as below:
1686 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
1687 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
1688 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
1689 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
1690 \param[out] none
1691 \retval none
1692 */
timer_internal_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t intrigger)1693 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
1694 {
1695 timer_input_trigger_source_select(timer_periph, intrigger);
1696 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1697 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1698 }
1699
1700 /*!
1701 \brief configure TIMER the external trigger as external clock input
1702 \param[in] timer_periph: TIMERx(x=0..4)
1703 \param[in] extrigger:
1704 only one parameter can be selected which is shown as below:
1705 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
1706 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
1707 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
1708 \param[in] extpolarity:
1709 only one parameter can be selected which is shown as below:
1710 \arg TIMER_IC_POLARITY_RISING: active low or falling edge active
1711 \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active
1712 \param[in] extfilter: a value between 0 and 15
1713 \param[out] none
1714 \retval none
1715 */
timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t extrigger,uint16_t extpolarity,uint32_t extfilter)1716 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter)
1717 {
1718 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){
1719 /* reset the CH1EN bit */
1720 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1721 /* reset the CH1NP bit */
1722 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1723 /* set the CH1NP bit */
1724 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
1725 /* reset the CH1MS bit */
1726 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1727 /* set the CH1MS bit */
1728 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
1729 /* reset the CH1CAPFLT bit */
1730 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1731 /* set the CH1CAPFLT bit */
1732 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
1733 /* set the CH1EN bit */
1734 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1735 }else{
1736 /* reset the CH0EN bit */
1737 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1738 /* reset the CH0P and CH0NP bits */
1739 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1740 /* set the CH0P and CH0NP bits */
1741 TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
1742 /* reset the CH0MS bit */
1743 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1744 /* set the CH0MS bit */
1745 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1746 /* reset the CH0CAPFLT bit */
1747 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1748 /* reset the CH0CAPFLT bit */
1749 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U);
1750 /* set the CH0EN bit */
1751 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1752 }
1753 /* select TIMER input trigger source */
1754 timer_input_trigger_source_select(timer_periph, extrigger);
1755 /* reset the SMC bit */
1756 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1757 /* set the SMC bit */
1758 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1759 }
1760
1761 /*!
1762 \brief configure TIMER the external clock mode0
1763 \param[in] timer_periph: TIMERx(x=0..4)
1764 \param[in] extprescaler:
1765 only one parameter can be selected which is shown as below:
1766 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1767 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1768 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1769 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1770 \param[in] extpolarity:
1771 only one parameter can be selected which is shown as below:
1772 \arg TIMER_ETP_FALLING: active low or falling edge active
1773 \arg TIMER_ETP_RISING: active high or rising edge active
1774 \param[in] extfilter: a value between 0 and 15
1775 \param[out] none
1776 \retval none
1777 */
timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1778 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1779 {
1780 /* configure TIMER external trigger input */
1781 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1782 /* reset the SMC bit,TRGS bit */
1783 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1784 /* set the SMC bit,TRGS bit */
1785 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1786 }
1787
1788 /*!
1789 \brief configure TIMER the external clock mode1
1790 \param[in] timer_periph: TIMERx(x=0..4)
1791 \param[in] extprescaler:
1792 only one parameter can be selected which is shown as below:
1793 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1794 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1795 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1796 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1797 \param[in] extpolarity:
1798 only one parameter can be selected which is shown as below:
1799 \arg TIMER_ETP_FALLING: active low or falling edge active
1800 \arg TIMER_ETP_RISING: active high or rising edge active
1801 \param[in] extfilter: a value between 0 and 15
1802 \param[out] none
1803 \retval none
1804 */
timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1805 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter)
1806 {
1807 /* configure TIMER external trigger input */
1808 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1809 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1810 }
1811
1812 /*!
1813 \brief disable TIMER the external clock mode1
1814 \param[in] timer_periph: TIMERx(x=0..4)
1815 \param[out] none
1816 \retval none
1817 */
timer_external_clock_mode1_disable(uint32_t timer_periph)1818 void timer_external_clock_mode1_disable(uint32_t timer_periph)
1819 {
1820 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1821 }
1822
1823 /*!
1824 \brief enable the TIMER interrupt
1825 \param[in] timer_periph: please refer to the following parameters
1826 \param[in] interrupt: specify which interrupt to enable
1827 one or more parameters can be selected which are shown as below:
1828 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6)
1829 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4)
1830 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4)
1831 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4)
1832 \arg TIMER_INT_CH3: channel 3 interrupt enable, TIMERx(x=0..4)
1833 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0)
1834 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4)
1835 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0)
1836 \param[out] none
1837 \retval none
1838 */
timer_interrupt_enable(uint32_t timer_periph,uint32_t interrupt)1839 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
1840 {
1841 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
1842 }
1843
1844 /*!
1845 \brief disable the TIMER interrupt
1846 \param[in] timer_periph: TIMERx(x=0..6)
1847 \param[in] interrupt: specify which interrupt to disbale
1848 one or more parameters can be selected which are shown as below:
1849 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6)
1850 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4)
1851 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4)
1852 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4)
1853 \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4)
1854 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0)
1855 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4)
1856 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0)
1857 \param[out] none
1858 \retval none
1859 */
timer_interrupt_disable(uint32_t timer_periph,uint32_t interrupt)1860 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
1861 {
1862 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
1863 }
1864
1865 /*!
1866 \brief get timer interrupt flag
1867 \param[in] timer_periph: TIMERx(x=0..6)
1868 \param[in] interrupt: the timer interrupt bits
1869 only one parameter can be selected which is shown as below:
1870 \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6)
1871 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4)
1872 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4)
1873 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4)
1874 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4)
1875 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0)
1876 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0)
1877 \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0)
1878 \param[out] none
1879 \retval FlagStatus: SET or RESET
1880 */
timer_interrupt_flag_get(uint32_t timer_periph,uint32_t interrupt)1881 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
1882 {
1883 uint32_t val;
1884 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
1885 if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)){
1886 return SET;
1887 }else{
1888 return RESET;
1889 }
1890 }
1891
1892 /*!
1893 \brief clear TIMER interrupt flag
1894 \param[in] timer_periph: TIMERx(x=0..6)
1895 \param[in] interrupt: the timer interrupt bits
1896 one or more parameters can be selected which are shown as below:
1897 \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6)
1898 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4)
1899 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4)
1900 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4)
1901 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4)
1902 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0)
1903 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0)
1904 \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0)
1905 \param[out] none
1906 \retval none
1907 */
timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t interrupt)1908 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
1909 {
1910 TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
1911 }
1912
1913 /*!
1914 \brief get TIMER flags
1915 \param[in] timer_periph: TIMERx(x=0..6)
1916 \param[in] flag: the timer interrupt flags
1917 only one parameter can be selected which is shown as below:
1918 \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6)
1919 \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4)
1920 \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4)
1921 \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4)
1922 \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4)
1923 \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0)
1924 \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0)
1925 \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0)
1926 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4)
1927 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4)
1928 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4)
1929 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4)
1930 \param[out] none
1931 \retval FlagStatus: SET or RESET
1932 */
timer_flag_get(uint32_t timer_periph,uint32_t flag)1933 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
1934 {
1935 if(RESET != (TIMER_INTF(timer_periph) & flag)){
1936 return SET;
1937 }else{
1938 return RESET;
1939 }
1940 }
1941
1942 /*!
1943 \brief clear TIMER flags
1944 \param[in] timer_periph: TIMERx(x=0..6)
1945 \param[in] flag: the timer interrupt flags
1946 one or more parameters can be selected which are shown as below:
1947 \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6)
1948 \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4)
1949 \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4)
1950 \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4)
1951 \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4)
1952 \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0)
1953 \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0)
1954 \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0)
1955 \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4)
1956 \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4)
1957 \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4)
1958 \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4)
1959 \param[out] none
1960 \retval none
1961 */
timer_flag_clear(uint32_t timer_periph,uint32_t flag)1962 void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
1963 {
1964 TIMER_INTF(timer_periph) = (~(uint32_t)flag);
1965 }
1966
1967
1968