1 #include "usb3.h"
2 #include "usb3_hw.h"
3 #include "usb3_drv.h"
4 #include "sys.h"
5 #include "onchiprom.h"
6 #include "common.h"
7
8 #include <cpu_func.h>
9 #include <linux/string.h>
10 #include <malloc.h>
11 #include <linux/compat.h>
12 #include "../../../phy/hibvt/usb_hisi.h"
13
14 void usb3_handle_event(usb3_device_t *dev);
15 void usb3_enable_device_interrupts(usb3_device_t *dev);
16 void usb3_dis_flush_eventbuf_intr(usb3_device_t *dev);
17 void usb3_init_eventbuf(usb3_device_t *dev, uint32_t size, phys_addr_t dma_addr);
18 #define udelay_100us udelay
19 #define msleep udelay
usb3_memset(void * buf,uint8_t value,uint32_t size)20 void usb3_memset(void *buf, uint8_t value, uint32_t size)
21 {
22 uint8_t *pbuf = (uint8_t *)buf;
23
24 while (size--) {
25 *pbuf++ = value;
26 }
27 }
28
usb3_memcpy(void * dst,void * src,uint32_t size)29 void usb3_memcpy(void *dst, void *src, uint32_t size)
30 {
31 uint8_t *pdst = (uint8_t *)dst;
32 uint8_t *psrc = (uint8_t *)src;
33
34 if (psrc > pdst) {
35 while (size--) {
36 *pdst++ = *psrc++;
37 }
38 } else {
39 pdst += size - 1;
40 psrc += size - 1;
41 while (size--) {
42 *pdst-- = *psrc--;
43 }
44 }
45 }
46
usb3_rd32(volatile uint32_t * addr)47 uint32_t usb3_rd32(volatile uint32_t *addr)
48 {
49 return *(volatile uint32_t *)(addr);
50 }
51 extern int usb_out_open;
usb3_wr32(volatile uint32_t * addr,uint32_t val)52 void usb3_wr32(volatile uint32_t *addr, uint32_t val)
53 {
54 *(volatile uint32_t *)(addr) = val;
55 udelay(200);
56 }
57
usb3_is_host_mode(usb3_device_t * dev)58 uint32_t usb3_is_host_mode(usb3_device_t *dev)
59 {
60 return usb3_rd32(&dev->core_global_regs->gsts) & 0x01;
61 }
62
pcd_epinit(usb3_pcd_t * pcd)63 void pcd_epinit(usb3_pcd_t *pcd)
64 {
65 usb3_pcd_ep_t *ep;
66
67 /* Init EP0 */
68 do {
69 ep = &pcd->ep0;
70
71 ep->pcd = pcd;
72 ep->stopped = 1;
73 ep->is_in = 0;
74 ep->active = 0;
75 ep->phys = 0;
76 ep->num = 0;
77 ep->tx_fifo_num = 0;
78 ep->out_ep_reg = &pcd->out_ep_regs[0];
79 ep->in_ep_reg = &pcd->in_ep_regs[0];
80
81 ep->type = USB3_EP_TYPE_CONTROL;
82 ep->maxburst = 0;
83 ep->maxpacket = 64;
84 ep->send_zlp = 0;
85
86 ep->req.length = 0;
87 ep->req.actual = 0;
88
89 pcd->ep0_req.length = 0;
90 pcd->ep0_req.actual = 0;
91 } while(0);
92
93 /* Init EP1-OUT */
94 do {
95 ep = &pcd->out_ep;
96
97 ep->pcd = pcd;
98 ep->stopped = 1;
99 ep->is_in = 0;
100 ep->active = 0;
101 ep->phys = USB3_BULK_OUT_EP << 1;
102 ep->num = 1;
103 ep->tx_fifo_num = 0;
104 ep->out_ep_reg = &pcd->out_ep_regs[USB3_BULK_OUT_EP];
105
106 /* Bulk EP is activated */
107 ep->type = USB3_EP_TYPE_BULK;
108 ep->maxburst = 0;
109 ep->maxpacket = USB2_FS_MAX_PACKET_SIZE;
110 ep->send_zlp = 0;
111
112 ep->req.length = 0;
113 ep->req.actual = 0;
114 } while(0);
115
116 /* Init EP1-IN */
117 do {
118 ep = &pcd->in_ep;
119
120 ep->pcd = pcd;
121 ep->stopped = 1;
122 ep->is_in = 1;
123 ep->active = 0;
124 ep->phys = (USB3_BULK_IN_EP << 1) | 1;
125 ep->num = 1;
126 ep->tx_fifo_num = USB3_BULK_IN_EP;
127 ep->in_ep_reg = &pcd->in_ep_regs[USB3_BULK_IN_EP];
128
129 /* Bulk EP is activated */
130 ep->type = USB3_EP_TYPE_BULK;
131 ep->maxburst = 0;
132 ep->maxpacket = USB2_FS_MAX_PACKET_SIZE;
133 ep->send_zlp = 0;
134
135 ep->req.length = 0;
136 ep->req.actual = 0;
137 } while(0);
138
139 pcd->ep0state = EP0_IDLE;
140 }
141
usb3_set_address(usb3_pcd_t * pcd,uint32_t addr)142 void usb3_set_address(usb3_pcd_t *pcd, uint32_t addr)
143 {
144 uint32_t dcfg;
145
146 dcfg = usb3_rd32(&pcd->dev_global_regs->dcfg);
147 dcfg &= ~USB3_DCFG_DEVADDR_BITS;
148 dcfg |= addr << USB3_DCFG_DEVADDR_SHIFT;
149 usb3_wr32(&pcd->dev_global_regs->dcfg, dcfg);
150 }
151
152 #define RAM_WIDTH 8
153 #define RAM_RX_DEPTH 4096
154 #define RAM_TX0_DEPTH 1024
155 #define RAM_TX1_DEPTH 2048
usb3_set_tx_fifo_size(usb3_device_t * dev)156 void usb3_set_tx_fifo_size(usb3_device_t *dev)
157 {
158 usb3_core_global_regs_t *global_regs =
159 dev->core_global_regs;
160 uint32_t prev_start = 0;
161 /* Set 1K for tx fifo0 */
162 usb3_wr32(&global_regs->gtxfifosiz[0],
163 ((RAM_TX0_DEPTH / RAM_WIDTH) << USB3_FIFOSZ_DEPTH_SHIFT) |
164 (prev_start << USB3_FIFOSZ_STARTADDR_SHIFT));
165
166 prev_start += RAM_TX0_DEPTH / RAM_WIDTH;
167 /* Set 2K for tx fifo1 */
168 usb3_wr32(&global_regs->gtxfifosiz[1],
169 ((RAM_TX1_DEPTH / RAM_WIDTH) << USB3_FIFOSZ_DEPTH_SHIFT) |
170 (prev_start << USB3_FIFOSZ_STARTADDR_SHIFT));
171 }
172
usb3_set_rx_fifo_size(usb3_device_t * dev)173 void usb3_set_rx_fifo_size(usb3_device_t *dev)
174 {
175 usb3_core_global_regs_t *global_regs =
176 dev->core_global_regs;
177 /* Set 4K for rx fifo */
178 usb3_wr32(&global_regs->grxfifosiz[0],
179 ((RAM_RX_DEPTH / RAM_WIDTH) << USB3_FIFOSZ_DEPTH_SHIFT));
180 }
181
usb3_resume_usb2_phy(usb3_pcd_t * pcd)182 void usb3_resume_usb2_phy(usb3_pcd_t *pcd)
183 {
184 uint32_t usb2phycfg;
185
186 usb2phycfg = usb3_rd32(&pcd->usb3_dev->core_global_regs->gusb2phycfg[0]);
187 usb2phycfg |= USB3_USB2PHYCFG_SUS_PHY_BIT;
188 usb3_wr32(&pcd->usb3_dev->core_global_regs->gusb2phycfg[0], usb2phycfg);
189 }
190
usb3_resume_usb3_phy(usb3_pcd_t * pcd)191 void usb3_resume_usb3_phy(usb3_pcd_t *pcd)
192 {
193 uint32_t pipectl;
194
195 pipectl = usb3_rd32(&pcd->usb3_dev->core_global_regs->gusb3pipectl[0]);
196 pipectl |= USB3_PIPECTL_SUS_PHY_BIT;
197 usb3_wr32(&pcd->usb3_dev->core_global_regs->gusb3pipectl[0],
198 pipectl);
199 }
200
usb3_accept_u1(usb3_pcd_t * pcd)201 void usb3_accept_u1(usb3_pcd_t *pcd)
202 {
203 uint32_t dctl;
204
205 dctl = usb3_rd32(&pcd->dev_global_regs->dctl);
206 dctl |= USB3_DCTL_ACCEPT_U1_EN_BIT;
207 usb3_wr32(&pcd->dev_global_regs->dctl, dctl);
208 }
209
usb3_accept_u2(usb3_pcd_t * pcd)210 void usb3_accept_u2(usb3_pcd_t *pcd)
211 {
212 }
213
usb3_enable_u1(usb3_pcd_t * pcd)214 void usb3_enable_u1(usb3_pcd_t *pcd)
215 {
216 uint32_t dctl;
217
218 dctl = usb3_rd32(&pcd->dev_global_regs->dctl);
219 dctl |= USB3_DCTL_INIT_U1_EN_BIT;
220 usb3_wr32(&pcd->dev_global_regs->dctl, dctl);
221 }
222
usb3_enable_u2(usb3_pcd_t * pcd)223 void usb3_enable_u2(usb3_pcd_t *pcd)
224 {
225 }
226
usb3_disable_u1(usb3_pcd_t * pcd)227 void usb3_disable_u1(usb3_pcd_t *pcd)
228 {
229 }
230
usb3_disable_u2(usb3_pcd_t * pcd)231 void usb3_disable_u2(usb3_pcd_t *pcd)
232 {
233 uint32_t dctl;
234
235 dctl = usb3_rd32(&pcd->dev_global_regs->dctl);
236 dctl &= ~USB3_DCTL_INIT_U2_EN_BIT;
237 usb3_wr32(&pcd->dev_global_regs->dctl, dctl);
238 }
239
usb3_u1_enabled(usb3_pcd_t * pcd)240 uint32_t usb3_u1_enabled(usb3_pcd_t *pcd)
241 {
242 uint32_t dctl;
243
244 dctl = usb3_rd32(&pcd->dev_global_regs->dctl);
245 return !!(dctl & USB3_DCTL_INIT_U1_EN_BIT);
246 }
247
usb3_u2_enabled(usb3_pcd_t * pcd)248 uint32_t usb3_u2_enabled(usb3_pcd_t *pcd)
249 {
250 uint32_t dctl;
251
252 dctl = usb3_rd32(&pcd->dev_global_regs->dctl);
253 return !!(dctl & USB3_DCTL_INIT_U2_EN_BIT);
254 }
255
usb3_dep_cstall(usb3_pcd_t * pcd,usb3_dev_ep_regs_t * ep_reg)256 void usb3_dep_cstall(usb3_pcd_t *pcd,
257 usb3_dev_ep_regs_t *ep_reg)
258 {
259 /* Start the command */
260 usb3_wr32(&ep_reg->depcmd,
261 USB3_EPCMD_CLR_STALL | USB3_EPCMD_ACT_BIT);
262
263 /* Wait for command completion */
264 handshake(pcd->usb3_dev, &ep_reg->depcmd, USB3_EPCMD_ACT_BIT, 0);
265 }
266
usb3_dep_sstall(usb3_pcd_t * pcd,usb3_dev_ep_regs_t * ep_reg)267 void usb3_dep_sstall(usb3_pcd_t *pcd,
268 usb3_dev_ep_regs_t *ep_reg)
269 {
270 /* Start the command */
271 usb3_wr32(&ep_reg->depcmd,
272 USB3_EPCMD_SET_STALL | USB3_EPCMD_ACT_BIT);
273
274 /* Wait for command completion */
275 handshake(pcd->usb3_dev, &ep_reg->depcmd, USB3_EPCMD_ACT_BIT, 0);
276 }
277
handshake(usb3_device_t * dev,volatile uint32_t * ptr,uint32_t mask,uint32_t done)278 uint32_t handshake(usb3_device_t *dev, volatile uint32_t *ptr,
279 uint32_t mask, uint32_t done)
280 {
281 uint32_t usec = 1000;
282 uint32_t result;
283
284 do {
285 result = usb3_rd32(ptr);
286 if ((result & mask) == done) {
287 return 1;
288 }
289
290 udelay_100us(1);
291 usec -= 1;
292 } while (usec > 0);
293
294 return 0;
295 }
296
usb3_fill_desc(usb3_dma_desc_t * desc,phys_addr_t dma_addr,uint32_t dma_len,uint32_t stream,uint32_t type,uint32_t ctrlbits,int own)297 void usb3_fill_desc(usb3_dma_desc_t *desc, phys_addr_t dma_addr,
298 uint32_t dma_len, uint32_t stream, uint32_t type,
299 uint32_t ctrlbits, int own)
300 {
301 dma_addr = map_to_dma_addr(dma_addr);
302
303 desc->bptl = (phys_addr_t)(dma_addr & 0xffffffffU);
304 desc->bpth = 0;
305 desc->status &= ~USB3_DSCSTS_XFRCNT_BITS;
306 desc->status |= ((dma_len << USB3_DSCSTS_XFRCNT_SHIFT)&USB3_DSCSTS_XFRCNT_BITS);
307 /* Note: If type is 0, leave original control bits intact (for isoc) */
308 if (type)
309 desc->control = type << USB3_DSCCTL_TRBCTL_SHIFT;
310
311 desc->control |= (stream << USB3_DSCCTL_STRMID_SOFN_SHIFT) | ctrlbits;
312
313 /* Must do this last! */
314 if (own)
315 desc->control |= USB3_DSCCTL_HWO_BIT;
316 flush_dcache_all();
317 }
318
319
usb3_dep_startnewcfg(usb3_pcd_t * pcd,usb3_dev_ep_regs_t * ep_reg,uint32_t rsrcidx)320 void usb3_dep_startnewcfg(usb3_pcd_t *pcd,
321 usb3_dev_ep_regs_t *ep_reg,
322 uint32_t rsrcidx)
323 {
324 /* Start the command */
325 usb3_wr32(&ep_reg->depcmd,
326 (rsrcidx << USB3_EPCMD_XFER_RSRC_IDX_SHIFT) |
327 USB3_EPCMD_START_NEW_CFG | USB3_EPCMD_ACT_BIT);
328
329 /* Wait for command completion */
330 handshake(pcd->usb3_dev, &ep_reg->depcmd, USB3_EPCMD_ACT_BIT, 0);
331 }
332
usb3_dep_cfg(usb3_pcd_t * pcd,usb3_dev_ep_regs_t * ep_reg,uint32_t depcfg0,uint32_t depcfg1,uint32_t depcfg2)333 void usb3_dep_cfg(usb3_pcd_t *pcd,
334 usb3_dev_ep_regs_t *ep_reg,
335 uint32_t depcfg0, uint32_t depcfg1, uint32_t depcfg2)
336 {
337 /* Set param 2 */
338 usb3_wr32(&ep_reg->depcmdpar2, depcfg2);
339
340 /* Set param 1 */
341 usb3_wr32(&ep_reg->depcmdpar1, depcfg1);
342
343 /* Set param 0 */
344 usb3_wr32(&ep_reg->depcmdpar0, depcfg0); /* himm 0x1018c808 0x200 */
345
346 /* Start the command */
347 usb3_wr32(&ep_reg->depcmd,
348 USB3_EPCMD_SET_EP_CFG | USB3_EPCMD_ACT_BIT);
349
350 /* Wait for command completion */
351 handshake(pcd->usb3_dev, &ep_reg->depcmd, USB3_EPCMD_ACT_BIT, 0);
352 }
353
usb3_dep_xfercfg(usb3_pcd_t * pcd,usb3_dev_ep_regs_t * ep_reg,uint32_t depstrmcfg)354 void usb3_dep_xfercfg(usb3_pcd_t *pcd,
355 usb3_dev_ep_regs_t *ep_reg,
356 uint32_t depstrmcfg)
357 {
358 /* Set param 0 */
359 usb3_wr32(&ep_reg->depcmdpar0, depstrmcfg);
360
361 /* Start the command */
362 usb3_wr32(&ep_reg->depcmd,
363 USB3_EPCMD_SET_XFER_CFG | USB3_EPCMD_ACT_BIT);
364
365 /* Wait for command completion */
366 handshake(pcd->usb3_dev, &ep_reg->depcmd, USB3_EPCMD_ACT_BIT, 0);
367 }
368
usb3_dep_startxfer(usb3_pcd_t * pcd,usb3_dev_ep_regs_t * ep_reg,phys_addr_t dma_addr,uint32_t stream_or_uf)369 uint8_t usb3_dep_startxfer(usb3_pcd_t *pcd,
370 usb3_dev_ep_regs_t *ep_reg,
371 phys_addr_t dma_addr, uint32_t stream_or_uf)
372 {
373 uint32_t depcmd;
374
375 dma_addr = map_to_dma_addr(dma_addr);
376
377 /* Set param 1 */
378 usb3_wr32(&ep_reg->depcmdpar1, dma_addr & 0xffffffffU);
379
380 /* Set param 0 */
381 usb3_wr32(&ep_reg->depcmdpar0, 0);
382
383 usb3_wr32(&ep_reg->depcmd,
384 (stream_or_uf << USB3_EPCMD_STR_NUM_OR_UF_SHIFT) |
385 USB3_EPCMD_START_XFER | USB3_EPCMD_ACT_BIT);
386
387 /* Wait for command completion */
388 handshake(pcd->usb3_dev, &ep_reg->depcmd, USB3_EPCMD_ACT_BIT, 0);
389
390 depcmd = usb3_rd32(&ep_reg->depcmd);
391
392 return (depcmd >> USB3_EPCMD_XFER_RSRC_IDX_SHIFT) &
393 (USB3_EPCMD_XFER_RSRC_IDX_BITS >> USB3_EPCMD_XFER_RSRC_IDX_SHIFT);
394 }
395
usb3_dep_updatexfer(usb3_pcd_t * pcd,usb3_dev_ep_regs_t * ep_reg,uint32_t tri)396 void usb3_dep_updatexfer(usb3_pcd_t *pcd,
397 usb3_dev_ep_regs_t *ep_reg,
398 uint32_t tri)
399 {
400 /* Start the command */
401 usb3_wr32(&ep_reg->depcmd,
402 (tri << USB3_EPCMD_XFER_RSRC_IDX_SHIFT) |
403 USB3_EPCMD_UPDATE_XFER | USB3_EPCMD_ACT_BIT);
404
405 /* Wait for command completion */
406 handshake(pcd->usb3_dev, &ep_reg->depcmd, USB3_EPCMD_ACT_BIT, 0);
407 }
408
usb3_enable_ep(usb3_pcd_t * pcd,usb3_pcd_ep_t * ep)409 void usb3_enable_ep(usb3_pcd_t *pcd, usb3_pcd_ep_t *ep)
410 {
411 uint32_t ep_index_num, dalepena;
412
413 ep_index_num = ep->num * 2;
414 if (ep->is_in)
415 ep_index_num += 1;
416
417 dalepena = usb3_rd32(&pcd->dev_global_regs->dalepena);
418
419 /* If we have already enabled this EP, leave it alone
420 * (shouldn't happen)
421 */
422 if (dalepena & (1 << ep_index_num))
423 return;
424
425 dalepena |= 1 << ep_index_num;
426 usb3_wr32(&pcd->dev_global_regs->dalepena, dalepena);
427 return;
428 }
429
usb3_dis_usb2_suspend(usb3_pcd_t * pcd)430 void usb3_dis_usb2_suspend(usb3_pcd_t *pcd)
431 {
432 uint32_t usb2phycfg;
433
434 if (pcd->speed == USB_SPEED_SUPER)
435 return;
436
437 usb2phycfg = usb3_rd32(&pcd->usb3_dev->core_global_regs->gusb2phycfg[0]);
438 usb2phycfg &= ~USB3_USB2PHYCFG_SUS_PHY_BIT;
439 usb2phycfg &= ~USB3_USB2PHYCFG_ENBL_SLP_M_BIT;
440 usb3_wr32(&pcd->usb3_dev->core_global_regs->gusb2phycfg[0], usb2phycfg);
441 }
442
usb3_ep0_activate(usb3_pcd_t * pcd)443 void usb3_ep0_activate(usb3_pcd_t *pcd)
444 {
445 uint32_t diepcfg0, doepcfg0, diepcfg1, doepcfg1;
446 uint32_t diepcfg2 = 0, doepcfg2 = 0;
447 usb3_dev_ep_regs_t *ep_reg;
448
449 diepcfg0 = USB3_EP_TYPE_CONTROL << USB3_EPCFG0_EPTYPE_SHIFT;
450 diepcfg1 = USB3_EPCFG1_XFER_CMPL_BIT | USB3_EPCFG1_XFER_IN_PROG_BIT | USB3_EPCFG1_XFER_NRDY_BIT | USB3_EPCFG1_EP_DIR_BIT;
451
452 doepcfg0 = USB3_EP_TYPE_CONTROL << USB3_EPCFG0_EPTYPE_SHIFT;
453 doepcfg1 = USB3_EPCFG1_XFER_CMPL_BIT | USB3_EPCFG1_XFER_IN_PROG_BIT | USB3_EPCFG1_XFER_NRDY_BIT;
454
455 /* Default to MPS of 512 (will reconfigure after ConnectDone event) */
456 diepcfg0 |= 512 << USB3_EPCFG0_MPS_SHIFT;
457 doepcfg0 |= 512 << USB3_EPCFG0_MPS_SHIFT;
458
459 diepcfg0 |= pcd->ep0.tx_fifo_num << USB3_EPCFG0_TXFNUM_SHIFT;
460
461 /* Issue "DEPCFG" command to EP0-OUT */
462
463 ep_reg = &pcd->out_ep_regs[0];
464 usb3_dis_usb2_suspend(pcd); /* himm 0x1018c200 0x102400 */
465 /* If core is version 1.09a or later */
466 /* Must issue DEPSTRTNEWCFG command first */
467 usb3_dep_startnewcfg(pcd, ep_reg, 0);
468
469 usb3_dep_cfg(pcd, ep_reg, doepcfg0, doepcfg1, doepcfg2);
470
471 /* Issue "DEPSTRMCFG" command to EP0-OUT */
472
473 /* One stream */
474 usb3_dep_xfercfg(pcd, ep_reg, 1);
475
476 /* Issue "DEPCFG" command to EP0-IN */
477
478 ep_reg = &pcd->in_ep_regs[0];
479 usb3_dep_cfg(pcd, ep_reg, diepcfg0, diepcfg1, diepcfg2);
480
481 /* Issue "DEPSTRMCFG" command to EP0-IN */
482
483 /* One stream */
484 usb3_dep_xfercfg(pcd, ep_reg, 1);
485
486 pcd->ep0.active = 1;
487 }
488
usb3_ep_activate(usb3_pcd_t * pcd,usb3_pcd_ep_t * ep)489 void usb3_ep_activate(usb3_pcd_t *pcd, usb3_pcd_ep_t *ep)
490 {
491 usb3_dev_ep_regs_t *ep_reg, *ep0_reg;
492 uint32_t depcfg0, depcfg1, depcfg2 = 0;
493
494 /*
495 * Get the appropriate EP registers
496 */
497 if (ep->is_in)
498 ep_reg = ep->in_ep_reg;
499 else
500 ep_reg = ep->out_ep_reg;
501
502 /* If this is first EP enable (ie. start of a new configuration) */
503 if (!pcd->eps_enabled) {
504 pcd->eps_enabled = 1;
505
506 /* NOTE: When setting a new configuration, we must issue a
507 * "DEPCFG" command to physical EP1 (logical EP0-IN) first.
508 * This resets the core's Tx FIFO mapping table
509 */
510 depcfg0 = USB3_EP_TYPE_CONTROL << USB3_EPCFG0_EPTYPE_SHIFT;
511 depcfg0 |= USB3_CFG_ACTION_MODIFY << USB3_EPCFG0_CFG_ACTION_SHIFT;
512 depcfg1 = USB3_EPCFG1_XFER_CMPL_BIT | USB3_EPCFG1_XFER_NRDY_BIT
513 | USB3_EPCFG1_EP_DIR_BIT;
514
515 switch (pcd->speed) {
516 case USB_SPEED_SUPER:
517 depcfg0 |= 512 << USB3_EPCFG0_MPS_SHIFT;
518 break;
519
520 case USB_SPEED_HIGH:
521 case USB_SPEED_FULL:
522 depcfg0 |= 64 << USB3_EPCFG0_MPS_SHIFT;
523 break;
524
525 case USB_SPEED_LOW:
526 depcfg0 |= 8 << USB3_EPCFG0_MPS_SHIFT;
527 break;
528 }
529
530 ep0_reg = &pcd->in_ep_regs[0];
531 usb3_dep_cfg(pcd, ep0_reg, depcfg0, depcfg1, 0);
532
533 /* If core is version 1.09a or later */
534 /* Must issue DEPSTRTNEWCFG command first */
535 ep0_reg = &pcd->out_ep_regs[0];
536 usb3_dep_startnewcfg(pcd, ep0_reg, 2);
537 }
538
539 /*
540 * Issue "DEPCFG" command to EP
541 */
542 depcfg0 = ep->type << USB3_EPCFG0_EPTYPE_SHIFT;
543 depcfg0 |= ep->maxpacket << USB3_EPCFG0_MPS_SHIFT;
544
545 if (ep->is_in) {
546 depcfg0 |= ep->tx_fifo_num << USB3_EPCFG0_TXFNUM_SHIFT;
547 }
548
549 depcfg0 |= ep->maxburst << USB3_EPCFG0_BRSTSIZ_SHIFT;
550
551 depcfg1 = ep->num << USB3_EPCFG1_EP_NUM_SHIFT;
552
553 if (ep->is_in)
554 depcfg1 |= USB3_EPCFG1_EP_DIR_BIT;
555
556 depcfg1 |= USB3_EPCFG1_XFER_CMPL_BIT;
557
558 usb3_dep_cfg(pcd, ep_reg, depcfg0, depcfg1, depcfg2);
559
560 /*
561 * Issue "DEPSTRMCFG" command to EP
562 */
563 /* Setting 1 stream resource */
564 usb3_dep_xfercfg(pcd, ep_reg, 1);
565
566 /* Enable EP in DALEPENA reg */
567 usb3_enable_ep(pcd, ep);
568
569 ep->active = 1;
570 }
571
usb3_ep0_out_start(usb3_pcd_t * pcd)572 void usb3_ep0_out_start(usb3_pcd_t *pcd)
573 {
574 usb3_dev_ep_regs_t *ep_reg;
575 usb3_dma_desc_t *desc;
576 uint32_t desc_dma;
577 uint8_t tri;
578
579 /* Get the SETUP packet DMA Descriptor (TRB) */
580 desc = pcd->ep0_setup_desc;
581 desc_dma = (phys_addr_t)pcd->ep0_setup_desc;
582
583 /* DMA Descriptor setup */
584 usb3_fill_desc(desc, (phys_addr_t)pcd->ep0_setup_pkt,
585 pcd->ep0.maxpacket,
586 0, USB3_DSCCTL_TRBCTL_SETUP, USB3_DSCCTL_IOC_BIT |
587 USB3_DSCCTL_ISP_BIT | USB3_DSCCTL_LST_BIT, 1);
588
589 ep_reg = &pcd->out_ep_regs[0];
590
591 /* Issue "DEPSTRTXFER" command to EP0-OUT */
592 tri = usb3_dep_startxfer(pcd, ep_reg, desc_dma, 0);
593 pcd->ep0.tri_out = tri;
594 }
595
usb3_core_dev_init(usb3_device_t * dev)596 void usb3_core_dev_init(usb3_device_t *dev)
597 {
598 usb3_core_global_regs_t *global_regs = dev->core_global_regs;
599 usb3_pcd_t *pcd = &dev->pcd;
600 usb3_dev_global_regs_t *dev_global_regs = pcd->dev_global_regs;
601 uint32_t temp_t;
602
603 /* Soft-reset the core */
604 do {
605 temp_t = usb3_rd32(&dev_global_regs->dctl);
606 temp_t &= ~USB3_DCTL_RUN_STOP_BIT;
607 temp_t |= USB3_DCTL_CSFT_RST_BIT;
608 usb3_wr32(&dev_global_regs->dctl, temp_t);
609 do {
610 udelay_100us(1);
611 temp_t = usb3_rd32(&dev_global_regs->dctl);
612 } while(temp_t & USB3_DCTL_CSFT_RST_BIT);
613
614 /* Wait for at least 3 PHY clocks */
615 msleep(1);
616 } while(0);
617
618 pcd->link_state = 0;
619
620 /* Set Turnaround Time = 9 (8-bit UTMI+ / ULPI) */
621 temp_t = usb3_rd32(&global_regs->gusb2phycfg[0]);
622 temp_t &= ~USB3_USB2PHYCFG_USB_TRD_TIM_BITS;
623 temp_t |= 9 << USB3_USB2PHYCFG_USB_TRD_TIM_SHIFT;
624 usb3_wr32(&global_regs->gusb2phycfg[0], temp_t);
625
626 temp_t = 0x13802004;
627 usb3_wr32(&global_regs->gctl, temp_t);
628
629 usb_info("evnt buffer addr: 0x%x\n", dev->event_buf);
630
631 usb3_init_eventbuf(dev, USB3_EVENT_BUF_SIZE, (phys_addr_t)dev->event_buf);
632 dev->event_ptr = dev->event_buf;
633
634 /* Set speed to Super */
635 temp_t = usb3_rd32(&pcd->dev_global_regs->dcfg);
636 temp_t &= ~(USB3_DCFG_DEVSPD_BITS << USB3_DCFG_DEVSPD_SHIFT);
637 temp_t |= USB3_SPEED_HS_PHY_30MHZ_OR_60MHZ
638 << USB3_DCFG_DEVSPD_SHIFT;
639 usb3_wr32(&pcd->dev_global_regs->dcfg, temp_t);
640
641 /* If LPM enable was requested */
642 temp_t = usb3_rd32(&pcd->dev_global_regs->dcfg);
643 temp_t |= USB3_DCFG_LPM_CAP_BIT;
644 usb3_wr32(&pcd->dev_global_regs->dcfg, temp_t);/*himm 0x1018c700 0x480804*/
645
646 /* Set Nump */
647 temp_t = usb3_rd32(&pcd->dev_global_regs->dcfg);
648 temp_t &= ~USB3_DCFG_NUM_RCV_BUF_BITS;
649 temp_t |= 16 << USB3_DCFG_NUM_RCV_BUF_SHIFT;
650 usb3_wr32(&pcd->dev_global_regs->dcfg, temp_t);
651
652 usb3_set_address(pcd, 0);
653
654 /* disable Phy suspend */
655 usb3_resume_usb3_phy(pcd);
656 usb3_resume_usb2_phy(pcd);/*himm 0x1018c200 0x102540*/
657 /* Enable Global and Device interrupts */
658 usb3_enable_device_interrupts(dev);
659
660 /* Activate EP0 */
661 usb3_ep0_activate(pcd);
662
663 /* Start EP0 to receive SETUP packets */
664 usb3_ep0_out_start(pcd);
665
666 /* Enable EP0-OUT/IN in DALEPENA register */
667 usb3_wr32(&pcd->dev_global_regs->dalepena, 3);
668
669 /* Set Run/Stop bit */
670 temp_t = usb3_rd32(&pcd->dev_global_regs->dctl);
671 temp_t |= USB3_DCTL_RUN_STOP_BIT;
672 usb3_wr32(&pcd->dev_global_regs->dctl, temp_t);
673 }
674
usb3_pcd_init(usb3_device_t * dev)675 void usb3_pcd_init(usb3_device_t *dev)
676 {
677 usb3_pcd_t *pcd = &dev->pcd;
678
679 pcd->usb3_dev = dev;
680 pcd->speed = USB_SPEED_UNKNOWN;
681
682 /* Initialize EP structures */
683 pcd_epinit(pcd);
684
685 /* Initialize the Core (also enables interrupts and sets Run/Stop bit) */
686 usb3_core_dev_init(dev);
687 }
688
usb3_common_init(usb3_device_t * dev,volatile uint8_t * base)689 void usb3_common_init(usb3_device_t *dev, volatile uint8_t *base)
690 {
691 usb3_pcd_t *pcd;
692
693 dev->core_global_regs = (usb3_core_global_regs_t *)(base + USB3_CORE_GLOBAL_REG_OFFSET);
694
695 pcd = &dev->pcd;
696
697 pcd->dev_global_regs = (usb3_dev_global_regs_t *)(base + USB3_DEV_GLOBAL_REG_OFFSET);
698 pcd->out_ep_regs = (usb3_dev_ep_regs_t *)(base + USB3_DEV_OUT_EP_REG_OFFSET);
699 pcd->in_ep_regs = (usb3_dev_ep_regs_t *)(base + USB3_DEV_IN_EP_REG_OFFSET);
700 }
701
usb3_init(usb3_device_t * dev)702 void usb3_init(usb3_device_t *dev)
703 {
704 /* Init the PCD (also enables interrupts and sets Run/Stop bit) */
705 usb3_pcd_init(dev);
706 }
707
708 static uint8_t string_manu[]= {'H',0,'i',0,'s',0,'l',0,'i',0,'c',0,'o',0,'n',0};
709 static uint8_t string_prod[]= {'H',0,'i',0,'U',0,'S',0,'B',0,'B',0,'u',0,'r',0,'n',0};
usb3_driver_init(void)710 int usb3_driver_init(void)
711 {
712 usb3_device_t *usb3_dev;
713 struct usb_device_descriptor *usb3_dev_desc;
714
715 usb3_dev = malloc(sizeof(usb3_device_t));
716 if (!usb3_dev) {
717 debug("usb3_dev: out of memory\n");
718 return -ENOMEM;
719 }
720 usb3_memset((void *)usb3_dev, 0, sizeof(usb3_device_t));
721 usb3_dev_desc = malloc(sizeof(struct usb_device_descriptor));
722 usb3_pcd_t *pcd = &usb3_dev->pcd;
723 usb3_pcd_ep_t *ep = &pcd->in_ep;
724 usb3_pcd_req_t *req = &ep->req;
725 req->bufdma = (uint8_t *)malloc(512);
726 usb_info("size of usb3_dev %d\n", sizeof(*usb3_dev));
727 usb3_dev->base = (volatile uint8_t *)USB3_CTRL_REG_BASE;
728 usb3_dev->string_manu_len = sizeof(string_manu);
729 usb3_dev->string_prod_len = sizeof(string_prod);
730 usb3_dev->dev_desc = usb3_dev_desc;
731 memcpy(usb3_dev->string_manu, string_manu, usb3_dev->string_manu_len);
732 memcpy(usb3_dev->string_prod, string_prod, usb3_dev->string_prod_len);
733 usb3_dev->pcd.ep0_setup_desc = (usb3_dma_desc_t *)
734 ((phys_addr_t)(usb3_dev->pcd.ep0_setup + 15) & (uint32_t)(~15));
735 usb3_dev->pcd.ep0_in_desc = (usb3_dma_desc_t *)
736 ((phys_addr_t)(usb3_dev->pcd.ep0_in + 15) & (uint32_t)(~15));
737 usb3_dev->pcd.ep0_out_desc = (usb3_dma_desc_t *)
738 ((phys_addr_t)(usb3_dev->pcd.ep0_out + 15) & (uint32_t)(~15));
739 usb3_dev->pcd.in_ep.ep_desc = (usb3_dma_desc_t *)
740 ((phys_addr_t)(usb3_dev->pcd.in_ep.epx_desc + 15) & (uint32_t)(~15));
741 usb3_dev->pcd.out_ep.ep_desc = (usb3_dma_desc_t *)
742 ((phys_addr_t)(usb3_dev->pcd.out_ep.epx_desc + 15) & (uint32_t)(~15));
743
744 /* Release usb3.0 controller */
745
746 phy_hiusb_init(0);
747
748 /* Get usb3.0 version number */
749 usb3_dev->snpsid = usb3_rd32((volatile uint32_t *)
750 (usb3_dev->base + USB3_CORE_REG_BASE + USB3_CORE_GSNPSID_REG_OFFSET));
751
752 /* Initialize usb3.0 core */
753 usb3_common_init(usb3_dev, usb3_dev->base + USB3_CORE_REG_BASE);
754
755 /* Initialize usb3.0 pcd */
756 usb3_init(usb3_dev);
757
758 usb_info("usb init done\n");
759 for (;;)
760 usb3_handle_event(usb3_dev);
761
762 }
763
764 /*
765 * Interface func for download the mirror, address from return.
766 */
udc_connect(void)767 void udc_connect(void)
768 {
769 dcache_disable();
770 usb3_driver_init();
771 dcache_enable();
772 }
773 EXPORT_SYMBOL(udc_connect);
774